if_ti.c revision 1.62
1 /* $NetBSD: if_ti.c,v 1.62 2004/09/21 21:57:30 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.62 2004/09/21 21:57:30 yamt Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((struct mbuf *, caddr_t, size_t, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 CFATTACH_DECL(ti, sizeof(struct ti_softc), 218 ti_probe, ti_attach, NULL, NULL); 219 220 /* 221 * Send an instruction or address to the EEPROM, check for ACK. 222 */ 223 static u_int32_t ti_eeprom_putbyte(sc, byte) 224 struct ti_softc *sc; 225 int byte; 226 { 227 int i, ack = 0; 228 229 /* 230 * Make sure we're in TX mode. 231 */ 232 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 233 234 /* 235 * Feed in each bit and stobe the clock. 236 */ 237 for (i = 0x80; i; i >>= 1) { 238 if (byte & i) { 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 240 } else { 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 242 } 243 DELAY(1); 244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 245 DELAY(1); 246 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 } 248 249 /* 250 * Turn off TX mode. 251 */ 252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 253 254 /* 255 * Check for ack. 256 */ 257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 258 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 259 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 260 261 return(ack); 262 } 263 264 /* 265 * Read a byte of data stored in the EEPROM at address 'addr.' 266 * We have to send two address bytes since the EEPROM can hold 267 * more than 256 bytes of data. 268 */ 269 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 270 struct ti_softc *sc; 271 int addr; 272 u_int8_t *dest; 273 { 274 int i; 275 u_int8_t byte = 0; 276 277 EEPROM_START; 278 279 /* 280 * Send write control code to EEPROM. 281 */ 282 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 283 printf("%s: failed to send write command, status: %x\n", 284 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 285 return(1); 286 } 287 288 /* 289 * Send first byte of address of byte we want to read. 290 */ 291 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 292 printf("%s: failed to send address, status: %x\n", 293 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 294 return(1); 295 } 296 /* 297 * Send second byte address of byte we want to read. 298 */ 299 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 300 printf("%s: failed to send address, status: %x\n", 301 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 302 return(1); 303 } 304 305 EEPROM_STOP; 306 EEPROM_START; 307 /* 308 * Send read control code to EEPROM. 309 */ 310 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 311 printf("%s: failed to send read command, status: %x\n", 312 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 313 return(1); 314 } 315 316 /* 317 * Start reading bits from EEPROM. 318 */ 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 320 for (i = 0x80; i; i >>= 1) { 321 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 322 DELAY(1); 323 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 324 byte |= i; 325 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 326 DELAY(1); 327 } 328 329 EEPROM_STOP; 330 331 /* 332 * No ACK generated for read, so just return byte. 333 */ 334 335 *dest = byte; 336 337 return(0); 338 } 339 340 /* 341 * Read a sequence of bytes from the EEPROM. 342 */ 343 static int ti_read_eeprom(sc, dest, off, cnt) 344 struct ti_softc *sc; 345 caddr_t dest; 346 int off; 347 int cnt; 348 { 349 int err = 0, i; 350 u_int8_t byte = 0; 351 352 for (i = 0; i < cnt; i++) { 353 err = ti_eeprom_getbyte(sc, off + i, &byte); 354 if (err) 355 break; 356 *(dest + i) = byte; 357 } 358 359 return(err ? 1 : 0); 360 } 361 362 /* 363 * NIC memory access function. Can be used to either clear a section 364 * of NIC local memory or (if buf is non-NULL) copy data into it. 365 */ 366 static void ti_mem(sc, addr, len, buf) 367 struct ti_softc *sc; 368 u_int32_t addr, len; 369 caddr_t buf; 370 { 371 int segptr, segsize, cnt; 372 caddr_t ptr; 373 374 segptr = addr; 375 cnt = len; 376 ptr = buf; 377 378 while(cnt) { 379 if (cnt < TI_WINLEN) 380 segsize = cnt; 381 else 382 segsize = TI_WINLEN - (segptr % TI_WINLEN); 383 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 384 if (buf == NULL) { 385 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 387 segsize / 4); 388 } else { 389 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 390 bus_space_write_region_stream_4(sc->ti_btag, 391 sc->ti_bhandle, 392 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 393 (u_int32_t *)ptr, segsize / 4); 394 #else 395 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 396 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 397 (u_int32_t *)ptr, segsize / 4); 398 #endif 399 ptr += segsize; 400 } 401 segptr += segsize; 402 cnt -= segsize; 403 } 404 405 return; 406 } 407 408 /* 409 * Load firmware image into the NIC. Check that the firmware revision 410 * is acceptable and see if we want the firmware for the Tigon 1 or 411 * Tigon 2. 412 */ 413 static void ti_loadfw(sc) 414 struct ti_softc *sc; 415 { 416 switch(sc->ti_hwrev) { 417 case TI_HWREV_TIGON: 418 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 419 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 420 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 421 printf("%s: firmware revision mismatch; want " 422 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 423 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 424 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 425 tigonFwReleaseMinor, tigonFwReleaseFix); 426 return; 427 } 428 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 429 (caddr_t)tigonFwText); 430 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 431 (caddr_t)tigonFwData); 432 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 433 (caddr_t)tigonFwRodata); 434 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 435 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 437 break; 438 case TI_HWREV_TIGON_II: 439 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 440 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 441 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 442 printf("%s: firmware revision mismatch; want " 443 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 444 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 445 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 446 tigon2FwReleaseMinor, tigon2FwReleaseFix); 447 return; 448 } 449 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 450 (caddr_t)tigon2FwText); 451 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 452 (caddr_t)tigon2FwData); 453 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 454 (caddr_t)tigon2FwRodata); 455 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 456 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 457 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 458 break; 459 default: 460 printf("%s: can't load firmware: unknown hardware rev\n", 461 sc->sc_dev.dv_xname); 462 break; 463 } 464 465 return; 466 } 467 468 /* 469 * Send the NIC a command via the command ring. 470 */ 471 static void ti_cmd(sc, cmd) 472 struct ti_softc *sc; 473 struct ti_cmd_desc *cmd; 474 { 475 u_int32_t index; 476 477 index = sc->ti_cmd_saved_prodidx; 478 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 479 TI_INC(index, TI_CMD_RING_CNT); 480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 481 sc->ti_cmd_saved_prodidx = index; 482 483 return; 484 } 485 486 /* 487 * Send the NIC an extended command. The 'len' parameter specifies the 488 * number of command slots to include after the initial command. 489 */ 490 static void ti_cmd_ext(sc, cmd, arg, len) 491 struct ti_softc *sc; 492 struct ti_cmd_desc *cmd; 493 caddr_t arg; 494 int len; 495 { 496 u_int32_t index; 497 int i; 498 499 index = sc->ti_cmd_saved_prodidx; 500 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 501 TI_INC(index, TI_CMD_RING_CNT); 502 for (i = 0; i < len; i++) { 503 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 504 *(u_int32_t *)(&arg[i * 4])); 505 TI_INC(index, TI_CMD_RING_CNT); 506 } 507 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 508 sc->ti_cmd_saved_prodidx = index; 509 510 return; 511 } 512 513 /* 514 * Handle events that have triggered interrupts. 515 */ 516 static void ti_handle_events(sc) 517 struct ti_softc *sc; 518 { 519 struct ti_event_desc *e; 520 521 if (sc->ti_rdata->ti_event_ring == NULL) 522 return; 523 524 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 525 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 526 switch(e->ti_event) { 527 case TI_EV_LINKSTAT_CHANGED: 528 sc->ti_linkstat = e->ti_code; 529 if (e->ti_code == TI_EV_CODE_LINK_UP) 530 printf("%s: 10/100 link up\n", 531 sc->sc_dev.dv_xname); 532 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 533 printf("%s: gigabit link up\n", 534 sc->sc_dev.dv_xname); 535 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 536 printf("%s: link down\n", 537 sc->sc_dev.dv_xname); 538 break; 539 case TI_EV_ERROR: 540 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 541 printf("%s: invalid command\n", 542 sc->sc_dev.dv_xname); 543 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 544 printf("%s: unknown command\n", 545 sc->sc_dev.dv_xname); 546 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 547 printf("%s: bad config data\n", 548 sc->sc_dev.dv_xname); 549 break; 550 case TI_EV_FIRMWARE_UP: 551 ti_init2(sc); 552 break; 553 case TI_EV_STATS_UPDATED: 554 ti_stats_update(sc); 555 break; 556 case TI_EV_RESET_JUMBO_RING: 557 case TI_EV_MCAST_UPDATED: 558 /* Who cares. */ 559 break; 560 default: 561 printf("%s: unknown event: %d\n", 562 sc->sc_dev.dv_xname, e->ti_event); 563 break; 564 } 565 /* Advance the consumer index. */ 566 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 567 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 568 } 569 570 return; 571 } 572 573 /* 574 * Memory management for the jumbo receive ring is a pain in the 575 * butt. We need to allocate at least 9018 bytes of space per frame, 576 * _and_ it has to be contiguous (unless you use the extended 577 * jumbo descriptor format). Using malloc() all the time won't 578 * work: malloc() allocates memory in powers of two, which means we 579 * would end up wasting a considerable amount of space by allocating 580 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 581 * to do our own memory management. 582 * 583 * The driver needs to allocate a contiguous chunk of memory at boot 584 * time. We then chop this up ourselves into 9K pieces and use them 585 * as external mbuf storage. 586 * 587 * One issue here is how much memory to allocate. The jumbo ring has 588 * 256 slots in it, but at 9K per slot than can consume over 2MB of 589 * RAM. This is a bit much, especially considering we also need 590 * RAM for the standard ring and mini ring (on the Tigon 2). To 591 * save space, we only actually allocate enough memory for 64 slots 592 * by default, which works out to between 500 and 600K. This can 593 * be tuned by changing a #define in if_tireg.h. 594 */ 595 596 static int ti_alloc_jumbo_mem(sc) 597 struct ti_softc *sc; 598 { 599 caddr_t ptr; 600 int i; 601 struct ti_jpool_entry *entry; 602 bus_dma_segment_t dmaseg; 603 int error, dmanseg; 604 605 /* Grab a big chunk o' storage. */ 606 if ((error = bus_dmamem_alloc(sc->sc_dmat, 607 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 608 BUS_DMA_NOWAIT)) != 0) { 609 printf("%s: can't allocate jumbo buffer, error = %d\n", 610 sc->sc_dev.dv_xname, error); 611 return (error); 612 } 613 614 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 615 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 616 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 617 printf("%s: can't map jumbo buffer, error = %d\n", 618 sc->sc_dev.dv_xname, error); 619 return (error); 620 } 621 622 if ((error = bus_dmamap_create(sc->sc_dmat, 623 TI_JMEM, 1, 624 TI_JMEM, 0, BUS_DMA_NOWAIT, 625 &sc->jumbo_dmamap)) != 0) { 626 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 627 sc->sc_dev.dv_xname, error); 628 return (error); 629 } 630 631 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 632 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 633 BUS_DMA_NOWAIT)) != 0) { 634 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 635 sc->sc_dev.dv_xname, error); 636 return (error); 637 } 638 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 639 640 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 641 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 642 643 /* 644 * Now divide it up into 9K pieces and save the addresses 645 * in an array. 646 */ 647 ptr = sc->ti_cdata.ti_jumbo_buf; 648 for (i = 0; i < TI_JSLOTS; i++) { 649 sc->ti_cdata.ti_jslots[i] = ptr; 650 ptr += TI_JLEN; 651 entry = malloc(sizeof(struct ti_jpool_entry), 652 M_DEVBUF, M_NOWAIT); 653 if (entry == NULL) { 654 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 655 sc->ti_cdata.ti_jumbo_buf = NULL; 656 printf("%s: no memory for jumbo " 657 "buffer queue!\n", sc->sc_dev.dv_xname); 658 return(ENOBUFS); 659 } 660 entry->slot = i; 661 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 662 jpool_entries); 663 } 664 665 return(0); 666 } 667 668 /* 669 * Allocate a jumbo buffer. 670 */ 671 static void *ti_jalloc(sc) 672 struct ti_softc *sc; 673 { 674 struct ti_jpool_entry *entry; 675 676 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 677 678 if (entry == NULL) { 679 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 680 return(NULL); 681 } 682 683 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 684 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 685 return(sc->ti_cdata.ti_jslots[entry->slot]); 686 } 687 688 /* 689 * Release a jumbo buffer. 690 */ 691 static void ti_jfree(m, buf, size, arg) 692 struct mbuf *m; 693 caddr_t buf; 694 size_t size; 695 void *arg; 696 { 697 struct ti_softc *sc; 698 int i, s; 699 struct ti_jpool_entry *entry; 700 701 /* Extract the softc struct pointer. */ 702 sc = (struct ti_softc *)arg; 703 704 if (sc == NULL) 705 panic("ti_jfree: didn't get softc pointer!"); 706 707 /* calculate the slot this buffer belongs to */ 708 709 i = ((caddr_t)buf 710 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 711 712 if ((i < 0) || (i >= TI_JSLOTS)) 713 panic("ti_jfree: asked to free buffer that we don't manage!"); 714 715 s = splvm(); 716 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 717 if (entry == NULL) 718 panic("ti_jfree: buffer not in use!"); 719 entry->slot = i; 720 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 721 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 722 723 if (__predict_true(m != NULL)) 724 pool_cache_put(&mbpool_cache, m); 725 splx(s); 726 } 727 728 729 /* 730 * Intialize a standard receive ring descriptor. 731 */ 732 static int ti_newbuf_std(sc, i, m, dmamap) 733 struct ti_softc *sc; 734 int i; 735 struct mbuf *m; 736 bus_dmamap_t dmamap; /* required if (m != NULL) */ 737 { 738 struct mbuf *m_new = NULL; 739 struct ti_rx_desc *r; 740 int error; 741 742 if (dmamap == NULL) { 743 /* if (m) panic() */ 744 745 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 746 MCLBYTES, 0, BUS_DMA_NOWAIT, 747 &dmamap)) != 0) { 748 printf("%s: can't create recv map, error = %d\n", 749 sc->sc_dev.dv_xname, error); 750 return(ENOMEM); 751 } 752 } 753 sc->std_dmamap[i] = dmamap; 754 755 if (m == NULL) { 756 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 757 if (m_new == NULL) { 758 printf("%s: mbuf allocation failed " 759 "-- packet dropped!\n", sc->sc_dev.dv_xname); 760 return(ENOBUFS); 761 } 762 763 MCLGET(m_new, M_DONTWAIT); 764 if (!(m_new->m_flags & M_EXT)) { 765 printf("%s: cluster allocation failed " 766 "-- packet dropped!\n", sc->sc_dev.dv_xname); 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 m_adj(m_new, ETHER_ALIGN); 772 773 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 774 mtod(m_new, caddr_t), m_new->m_len, NULL, 775 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 776 printf("%s: can't load recv map, error = %d\n", 777 sc->sc_dev.dv_xname, error); 778 return (ENOMEM); 779 } 780 } else { 781 m_new = m; 782 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 783 m_new->m_data = m_new->m_ext.ext_buf; 784 m_adj(m_new, ETHER_ALIGN); 785 786 /* reuse the dmamap */ 787 } 788 789 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 790 r = &sc->ti_rdata->ti_rx_std_ring[i]; 791 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 792 r->ti_type = TI_BDTYPE_RECV_BD; 793 r->ti_flags = 0; 794 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 795 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 796 if (sc->ethercom.ec_if.if_capenable & 797 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 798 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 799 r->ti_len = m_new->m_len; /* == ds_len */ 800 r->ti_idx = i; 801 802 return(0); 803 } 804 805 /* 806 * Intialize a mini receive ring descriptor. This only applies to 807 * the Tigon 2. 808 */ 809 static int ti_newbuf_mini(sc, i, m, dmamap) 810 struct ti_softc *sc; 811 int i; 812 struct mbuf *m; 813 bus_dmamap_t dmamap; /* required if (m != NULL) */ 814 { 815 struct mbuf *m_new = NULL; 816 struct ti_rx_desc *r; 817 int error; 818 819 if (dmamap == NULL) { 820 /* if (m) panic() */ 821 822 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 823 MHLEN, 0, BUS_DMA_NOWAIT, 824 &dmamap)) != 0) { 825 printf("%s: can't create recv map, error = %d\n", 826 sc->sc_dev.dv_xname, error); 827 return(ENOMEM); 828 } 829 } 830 sc->mini_dmamap[i] = dmamap; 831 832 if (m == NULL) { 833 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 834 if (m_new == NULL) { 835 printf("%s: mbuf allocation failed " 836 "-- packet dropped!\n", sc->sc_dev.dv_xname); 837 return(ENOBUFS); 838 } 839 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 840 m_adj(m_new, ETHER_ALIGN); 841 842 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 843 mtod(m_new, caddr_t), m_new->m_len, NULL, 844 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 845 printf("%s: can't load recv map, error = %d\n", 846 sc->sc_dev.dv_xname, error); 847 return (ENOMEM); 848 } 849 } else { 850 m_new = m; 851 m_new->m_data = m_new->m_pktdat; 852 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 853 m_adj(m_new, ETHER_ALIGN); 854 855 /* reuse the dmamap */ 856 } 857 858 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 859 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 860 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 861 r->ti_type = TI_BDTYPE_RECV_BD; 862 r->ti_flags = TI_BDFLAG_MINI_RING; 863 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 864 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 865 if (sc->ethercom.ec_if.if_capenable & 866 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 867 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 868 r->ti_len = m_new->m_len; /* == ds_len */ 869 r->ti_idx = i; 870 871 return(0); 872 } 873 874 /* 875 * Initialize a jumbo receive ring descriptor. This allocates 876 * a jumbo buffer from the pool managed internally by the driver. 877 */ 878 static int ti_newbuf_jumbo(sc, i, m) 879 struct ti_softc *sc; 880 int i; 881 struct mbuf *m; 882 { 883 struct mbuf *m_new = NULL; 884 struct ti_rx_desc *r; 885 886 if (m == NULL) { 887 caddr_t *buf = NULL; 888 889 /* Allocate the mbuf. */ 890 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 891 if (m_new == NULL) { 892 printf("%s: mbuf allocation failed " 893 "-- packet dropped!\n", sc->sc_dev.dv_xname); 894 return(ENOBUFS); 895 } 896 897 /* Allocate the jumbo buffer */ 898 buf = ti_jalloc(sc); 899 if (buf == NULL) { 900 m_freem(m_new); 901 printf("%s: jumbo allocation failed " 902 "-- packet dropped!\n", sc->sc_dev.dv_xname); 903 return(ENOBUFS); 904 } 905 906 /* Attach the buffer to the mbuf. */ 907 MEXTADD(m_new, (void *)buf, ETHER_MAX_LEN_JUMBO, 908 M_DEVBUF, ti_jfree, sc); 909 m_new->m_flags |= M_EXT_RW; 910 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 911 } else { 912 m_new = m; 913 m_new->m_data = m_new->m_ext.ext_buf; 914 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 915 } 916 917 m_adj(m_new, ETHER_ALIGN); 918 /* Set up the descriptor. */ 919 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 920 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 921 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 922 ((caddr_t)mtod(m_new, caddr_t) 923 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 924 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 925 r->ti_flags = TI_BDFLAG_JUMBO_RING; 926 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 927 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 928 if (sc->ethercom.ec_if.if_capenable & 929 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 930 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 931 r->ti_len = m_new->m_len; 932 r->ti_idx = i; 933 934 return(0); 935 } 936 937 /* 938 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 939 * that's 1MB or memory, which is a lot. For now, we fill only the first 940 * 256 ring entries and hope that our CPU is fast enough to keep up with 941 * the NIC. 942 */ 943 static int ti_init_rx_ring_std(sc) 944 struct ti_softc *sc; 945 { 946 int i; 947 struct ti_cmd_desc cmd; 948 949 for (i = 0; i < TI_SSLOTS; i++) { 950 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 951 return(ENOBUFS); 952 }; 953 954 TI_UPDATE_STDPROD(sc, i - 1); 955 sc->ti_std = i - 1; 956 957 return(0); 958 } 959 960 static void ti_free_rx_ring_std(sc) 961 struct ti_softc *sc; 962 { 963 int i; 964 965 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 966 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 967 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 968 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 969 970 /* if (sc->std_dmamap[i] == 0) panic() */ 971 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 972 sc->std_dmamap[i] = 0; 973 } 974 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 975 sizeof(struct ti_rx_desc)); 976 } 977 978 return; 979 } 980 981 static int ti_init_rx_ring_jumbo(sc) 982 struct ti_softc *sc; 983 { 984 int i; 985 struct ti_cmd_desc cmd; 986 987 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 988 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 989 return(ENOBUFS); 990 }; 991 992 TI_UPDATE_JUMBOPROD(sc, i - 1); 993 sc->ti_jumbo = i - 1; 994 995 return(0); 996 } 997 998 static void ti_free_rx_ring_jumbo(sc) 999 struct ti_softc *sc; 1000 { 1001 int i; 1002 1003 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1004 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1005 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1006 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1007 } 1008 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1009 sizeof(struct ti_rx_desc)); 1010 } 1011 1012 return; 1013 } 1014 1015 static int ti_init_rx_ring_mini(sc) 1016 struct ti_softc *sc; 1017 { 1018 int i; 1019 1020 for (i = 0; i < TI_MSLOTS; i++) { 1021 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1022 return(ENOBUFS); 1023 }; 1024 1025 TI_UPDATE_MINIPROD(sc, i - 1); 1026 sc->ti_mini = i - 1; 1027 1028 return(0); 1029 } 1030 1031 static void ti_free_rx_ring_mini(sc) 1032 struct ti_softc *sc; 1033 { 1034 int i; 1035 1036 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1037 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1038 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1039 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1040 1041 /* if (sc->mini_dmamap[i] == 0) panic() */ 1042 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1043 sc->mini_dmamap[i] = 0; 1044 } 1045 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1046 sizeof(struct ti_rx_desc)); 1047 } 1048 1049 return; 1050 } 1051 1052 static void ti_free_tx_ring(sc) 1053 struct ti_softc *sc; 1054 { 1055 int i; 1056 struct txdmamap_pool_entry *dma; 1057 1058 if (sc->ti_rdata->ti_tx_ring == NULL) 1059 return; 1060 1061 for (i = 0; i < TI_TX_RING_CNT; i++) { 1062 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1063 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1064 sc->ti_cdata.ti_tx_chain[i] = NULL; 1065 1066 /* if (sc->txdma[i] == 0) panic() */ 1067 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1068 link); 1069 sc->txdma[i] = 0; 1070 } 1071 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1072 sizeof(struct ti_tx_desc)); 1073 } 1074 1075 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1076 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1077 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1078 free(dma, M_DEVBUF); 1079 } 1080 1081 return; 1082 } 1083 1084 static int ti_init_tx_ring(sc) 1085 struct ti_softc *sc; 1086 { 1087 int i, error; 1088 bus_dmamap_t dmamap; 1089 struct txdmamap_pool_entry *dma; 1090 1091 sc->ti_txcnt = 0; 1092 sc->ti_tx_saved_considx = 0; 1093 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1094 1095 SIMPLEQ_INIT(&sc->txdma_list); 1096 for (i = 0; i < TI_RSLOTS; i++) { 1097 /* I've seen mbufs with 30 fragments. */ 1098 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1099 40, ETHER_MAX_LEN_JUMBO, 0, 1100 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1101 printf("%s: can't create tx map, error = %d\n", 1102 sc->sc_dev.dv_xname, error); 1103 return(ENOMEM); 1104 } 1105 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1106 if (!dma) { 1107 printf("%s: can't alloc txdmamap_pool_entry\n", 1108 sc->sc_dev.dv_xname); 1109 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1110 return (ENOMEM); 1111 } 1112 dma->dmamap = dmamap; 1113 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1114 } 1115 1116 return(0); 1117 } 1118 1119 /* 1120 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1121 * but we have to support the old way too so that Tigon 1 cards will 1122 * work. 1123 */ 1124 void ti_add_mcast(sc, addr) 1125 struct ti_softc *sc; 1126 struct ether_addr *addr; 1127 { 1128 struct ti_cmd_desc cmd; 1129 u_int16_t *m; 1130 u_int32_t ext[2] = {0, 0}; 1131 1132 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1133 1134 switch(sc->ti_hwrev) { 1135 case TI_HWREV_TIGON: 1136 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1137 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1138 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1139 break; 1140 case TI_HWREV_TIGON_II: 1141 ext[0] = htons(m[0]); 1142 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1143 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1144 break; 1145 default: 1146 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1147 break; 1148 } 1149 1150 return; 1151 } 1152 1153 void ti_del_mcast(sc, addr) 1154 struct ti_softc *sc; 1155 struct ether_addr *addr; 1156 { 1157 struct ti_cmd_desc cmd; 1158 u_int16_t *m; 1159 u_int32_t ext[2] = {0, 0}; 1160 1161 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1162 1163 switch(sc->ti_hwrev) { 1164 case TI_HWREV_TIGON: 1165 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1166 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1167 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1168 break; 1169 case TI_HWREV_TIGON_II: 1170 ext[0] = htons(m[0]); 1171 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1172 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1173 break; 1174 default: 1175 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1176 break; 1177 } 1178 1179 return; 1180 } 1181 1182 /* 1183 * Configure the Tigon's multicast address filter. 1184 * 1185 * The actual multicast table management is a bit of a pain, thanks to 1186 * slight brain damage on the part of both Alteon and us. With our 1187 * multicast code, we are only alerted when the multicast address table 1188 * changes and at that point we only have the current list of addresses: 1189 * we only know the current state, not the previous state, so we don't 1190 * actually know what addresses were removed or added. The firmware has 1191 * state, but we can't get our grubby mits on it, and there is no 'delete 1192 * all multicast addresses' command. Hence, we have to maintain our own 1193 * state so we know what addresses have been programmed into the NIC at 1194 * any given time. 1195 */ 1196 static void ti_setmulti(sc) 1197 struct ti_softc *sc; 1198 { 1199 struct ifnet *ifp; 1200 struct ti_cmd_desc cmd; 1201 struct ti_mc_entry *mc; 1202 u_int32_t intrs; 1203 struct ether_multi *enm; 1204 struct ether_multistep step; 1205 1206 ifp = &sc->ethercom.ec_if; 1207 1208 /* Disable interrupts. */ 1209 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1210 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1211 1212 /* First, zot all the existing filters. */ 1213 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1214 ti_del_mcast(sc, &mc->mc_addr); 1215 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1216 free(mc, M_DEVBUF); 1217 } 1218 1219 /* 1220 * Remember all multicast addresses so that we can delete them 1221 * later. Punt if there is a range of addresses or memory shortage. 1222 */ 1223 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1224 while (enm != NULL) { 1225 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1226 ETHER_ADDR_LEN) != 0) 1227 goto allmulti; 1228 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1229 M_NOWAIT)) == NULL) 1230 goto allmulti; 1231 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1232 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1233 ETHER_NEXT_MULTI(step, enm); 1234 } 1235 1236 /* Accept only programmed multicast addresses */ 1237 ifp->if_flags &= ~IFF_ALLMULTI; 1238 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1239 1240 /* Now program new ones. */ 1241 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1242 ti_add_mcast(sc, &mc->mc_addr); 1243 1244 /* Re-enable interrupts. */ 1245 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1246 1247 return; 1248 1249 allmulti: 1250 /* No need to keep individual multicast addresses */ 1251 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1252 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1253 free(mc, M_DEVBUF); 1254 } 1255 1256 /* Accept all multicast addresses */ 1257 ifp->if_flags |= IFF_ALLMULTI; 1258 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1259 1260 /* Re-enable interrupts. */ 1261 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1262 } 1263 1264 /* 1265 * Check to see if the BIOS has configured us for a 64 bit slot when 1266 * we aren't actually in one. If we detect this condition, we can work 1267 * around it on the Tigon 2 by setting a bit in the PCI state register, 1268 * but for the Tigon 1 we must give up and abort the interface attach. 1269 */ 1270 static int ti_64bitslot_war(sc) 1271 struct ti_softc *sc; 1272 { 1273 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1274 CSR_WRITE_4(sc, 0x600, 0); 1275 CSR_WRITE_4(sc, 0x604, 0); 1276 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1277 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1278 if (sc->ti_hwrev == TI_HWREV_TIGON) 1279 return(EINVAL); 1280 else { 1281 TI_SETBIT(sc, TI_PCI_STATE, 1282 TI_PCISTATE_32BIT_BUS); 1283 return(0); 1284 } 1285 } 1286 } 1287 1288 return(0); 1289 } 1290 1291 /* 1292 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1293 * self-test results. 1294 */ 1295 static int ti_chipinit(sc) 1296 struct ti_softc *sc; 1297 { 1298 u_int32_t cacheline; 1299 u_int32_t pci_writemax = 0; 1300 u_int32_t rev; 1301 1302 /* Initialize link to down state. */ 1303 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1304 1305 /* Set endianness before we access any non-PCI registers. */ 1306 #if BYTE_ORDER == BIG_ENDIAN 1307 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1308 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1309 #else 1310 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1311 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1312 #endif 1313 1314 /* Check the ROM failed bit to see if self-tests passed. */ 1315 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1316 printf("%s: board self-diagnostics failed!\n", 1317 sc->sc_dev.dv_xname); 1318 return(ENODEV); 1319 } 1320 1321 /* Halt the CPU. */ 1322 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1323 1324 /* Figure out the hardware revision. */ 1325 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1326 switch(rev) { 1327 case TI_REV_TIGON_I: 1328 sc->ti_hwrev = TI_HWREV_TIGON; 1329 break; 1330 case TI_REV_TIGON_II: 1331 sc->ti_hwrev = TI_HWREV_TIGON_II; 1332 break; 1333 default: 1334 printf("%s: unsupported chip revision 0x%x\n", 1335 sc->sc_dev.dv_xname, rev); 1336 return(ENODEV); 1337 } 1338 1339 /* Do special setup for Tigon 2. */ 1340 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1341 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1342 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1343 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1344 } 1345 1346 /* Set up the PCI state register. */ 1347 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1348 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1349 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1350 } 1351 1352 /* Clear the read/write max DMA parameters. */ 1353 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1354 TI_PCISTATE_READ_MAXDMA)); 1355 1356 /* Get cache line size. */ 1357 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1358 1359 /* 1360 * If the system has set enabled the PCI memory write 1361 * and invalidate command in the command register, set 1362 * the write max parameter accordingly. This is necessary 1363 * to use MWI with the Tigon 2. 1364 */ 1365 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1366 & PCI_COMMAND_INVALIDATE_ENABLE) { 1367 switch(cacheline) { 1368 case 1: 1369 case 4: 1370 case 8: 1371 case 16: 1372 case 32: 1373 case 64: 1374 break; 1375 default: 1376 /* Disable PCI memory write and invalidate. */ 1377 if (bootverbose) 1378 printf("%s: cache line size %d not " 1379 "supported; disabling PCI MWI\n", 1380 sc->sc_dev.dv_xname, cacheline); 1381 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1382 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1383 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1384 break; 1385 } 1386 } 1387 1388 #ifdef __brokenalpha__ 1389 /* 1390 * From the Alteon sample driver: 1391 * Must insure that we do not cross an 8K (bytes) boundary 1392 * for DMA reads. Our highest limit is 1K bytes. This is a 1393 * restriction on some ALPHA platforms with early revision 1394 * 21174 PCI chipsets, such as the AlphaPC 164lx 1395 */ 1396 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1397 #else 1398 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1399 #endif 1400 1401 /* This sets the min dma param all the way up (0xff). */ 1402 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1403 1404 /* Configure DMA variables. */ 1405 #if BYTE_ORDER == BIG_ENDIAN 1406 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1407 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1408 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1409 TI_OPMODE_DONT_FRAG_JUMBO); 1410 #else 1411 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1412 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1413 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1414 #endif 1415 1416 /* 1417 * Only allow 1 DMA channel to be active at a time. 1418 * I don't think this is a good idea, but without it 1419 * the firmware racks up lots of nicDmaReadRingFull 1420 * errors. 1421 * Incompatible with hardware assisted checksums. 1422 */ 1423 if ((sc->ethercom.ec_if.if_capenable & 1424 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1425 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1426 1427 /* Recommended settings from Tigon manual. */ 1428 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1429 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1430 1431 if (ti_64bitslot_war(sc)) { 1432 printf("%s: bios thinks we're in a 64 bit slot, " 1433 "but we aren't", sc->sc_dev.dv_xname); 1434 return(EINVAL); 1435 } 1436 1437 return(0); 1438 } 1439 1440 /* 1441 * Initialize the general information block and firmware, and 1442 * start the CPU(s) running. 1443 */ 1444 static int ti_gibinit(sc) 1445 struct ti_softc *sc; 1446 { 1447 struct ti_rcb *rcb; 1448 int i; 1449 struct ifnet *ifp; 1450 1451 ifp = &sc->ethercom.ec_if; 1452 1453 /* Disable interrupts for now. */ 1454 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1455 1456 /* Tell the chip where to find the general information block. */ 1457 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1458 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1459 1460 /* Load the firmware into SRAM. */ 1461 ti_loadfw(sc); 1462 1463 /* Set up the contents of the general info and ring control blocks. */ 1464 1465 /* Set up the event ring and producer pointer. */ 1466 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1467 1468 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1469 rcb->ti_flags = 0; 1470 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1471 TI_CDEVPRODADDR(sc); 1472 1473 sc->ti_ev_prodidx.ti_idx = 0; 1474 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1475 sc->ti_ev_saved_considx = 0; 1476 1477 /* Set up the command ring and producer mailbox. */ 1478 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1479 1480 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1481 rcb->ti_flags = 0; 1482 rcb->ti_max_len = 0; 1483 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1484 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1485 } 1486 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1487 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1488 sc->ti_cmd_saved_prodidx = 0; 1489 1490 /* 1491 * Assign the address of the stats refresh buffer. 1492 * We re-use the current stats buffer for this to 1493 * conserve memory. 1494 */ 1495 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1496 TI_CDSTATSADDR(sc); 1497 1498 /* Set up the standard receive ring. */ 1499 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1500 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1501 rcb->ti_max_len = ETHER_MAX_LEN; 1502 rcb->ti_flags = 0; 1503 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1504 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1505 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1506 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1507 if (sc->ethercom.ec_nvlans != 0) 1508 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1509 1510 /* Set up the jumbo receive ring. */ 1511 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1512 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1513 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1514 rcb->ti_flags = 0; 1515 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1516 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1517 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1518 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1519 if (sc->ethercom.ec_nvlans != 0) 1520 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1521 1522 /* 1523 * Set up the mini ring. Only activated on the 1524 * Tigon 2 but the slot in the config block is 1525 * still there on the Tigon 1. 1526 */ 1527 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1528 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1529 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1530 if (sc->ti_hwrev == TI_HWREV_TIGON) 1531 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1532 else 1533 rcb->ti_flags = 0; 1534 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1535 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1536 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1537 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1538 if (sc->ethercom.ec_nvlans != 0) 1539 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1540 1541 /* 1542 * Set up the receive return ring. 1543 */ 1544 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1545 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1546 rcb->ti_flags = 0; 1547 rcb->ti_max_len = TI_RETURN_RING_CNT; 1548 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1549 TI_CDRTNPRODADDR(sc); 1550 1551 /* 1552 * Set up the tx ring. Note: for the Tigon 2, we have the option 1553 * of putting the transmit ring in the host's address space and 1554 * letting the chip DMA it instead of leaving the ring in the NIC's 1555 * memory and accessing it through the shared memory region. We 1556 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1557 * so we have to revert to the shared memory scheme if we detect 1558 * a Tigon 1 chip. 1559 */ 1560 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1561 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1562 sc->ti_tx_ring_nic = 1563 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1564 } 1565 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1566 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1567 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1568 if (sc->ti_hwrev == TI_HWREV_TIGON) 1569 rcb->ti_flags = 0; 1570 else 1571 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1572 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1573 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1574 /* 1575 * When we get the packet, there is a pseudo-header seed already 1576 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1577 * compute the pseudo-header checksum again! 1578 */ 1579 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1580 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1581 TI_RCB_FLAG_NO_PHDR_CKSUM; 1582 if (sc->ethercom.ec_nvlans != 0) 1583 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1584 rcb->ti_max_len = TI_TX_RING_CNT; 1585 if (sc->ti_hwrev == TI_HWREV_TIGON) 1586 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1587 else 1588 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1589 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1590 TI_CDTXCONSADDR(sc); 1591 1592 /* 1593 * We're done frobbing the General Information Block. Sync 1594 * it. Note we take care of the first stats sync here, as 1595 * well. 1596 */ 1597 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1598 1599 /* Set up tuneables */ 1600 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1601 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1602 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1603 (sc->ti_rx_coal_ticks / 10)); 1604 else 1605 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1606 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1607 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1608 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1609 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1610 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1611 1612 /* Turn interrupts on. */ 1613 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1614 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1615 1616 /* Start CPU. */ 1617 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1618 1619 return(0); 1620 } 1621 1622 /* 1623 * look for id in the device list, returning the first match 1624 */ 1625 static const struct ti_type * 1626 ti_type_match(pa) 1627 struct pci_attach_args *pa; 1628 { 1629 const struct ti_type *t; 1630 1631 t = ti_devs; 1632 while(t->ti_name != NULL) { 1633 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1634 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1635 return (t); 1636 } 1637 t++; 1638 } 1639 1640 return(NULL); 1641 } 1642 1643 /* 1644 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1645 * against our list and return its name if we find a match. 1646 */ 1647 static int ti_probe(parent, match, aux) 1648 struct device *parent; 1649 struct cfdata *match; 1650 void *aux; 1651 { 1652 struct pci_attach_args *pa = aux; 1653 const struct ti_type *t; 1654 1655 t = ti_type_match(pa); 1656 1657 return((t == NULL) ? 0 : 1); 1658 } 1659 1660 static void ti_attach(parent, self, aux) 1661 struct device *parent, *self; 1662 void *aux; 1663 { 1664 u_int32_t command; 1665 struct ifnet *ifp; 1666 struct ti_softc *sc; 1667 u_char eaddr[ETHER_ADDR_LEN]; 1668 struct pci_attach_args *pa = aux; 1669 pci_chipset_tag_t pc = pa->pa_pc; 1670 pci_intr_handle_t ih; 1671 const char *intrstr = NULL; 1672 bus_dma_segment_t dmaseg; 1673 int error, dmanseg, nolinear; 1674 const struct ti_type *t; 1675 1676 t = ti_type_match(pa); 1677 if (t == NULL) { 1678 printf("ti_attach: were did the card go ?\n"); 1679 return; 1680 } 1681 1682 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1683 1684 sc = (struct ti_softc *)self; 1685 1686 /* 1687 * Map control/status registers. 1688 */ 1689 nolinear = 0; 1690 if (pci_mapreg_map(pa, 0x10, 1691 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1692 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1693 NULL, NULL)) { 1694 nolinear = 1; 1695 if (pci_mapreg_map(pa, 0x10, 1696 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1697 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1698 printf(": can't map memory space\n"); 1699 return; 1700 } 1701 } 1702 if (nolinear == 0) 1703 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1704 else 1705 sc->ti_vhandle = NULL; 1706 1707 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1708 command |= PCI_COMMAND_MASTER_ENABLE; 1709 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1710 1711 /* Allocate interrupt */ 1712 if (pci_intr_map(pa, &ih)) { 1713 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1714 return; 1715 } 1716 intrstr = pci_intr_string(pc, ih); 1717 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1718 if (sc->sc_ih == NULL) { 1719 printf("%s: couldn't establish interrupt", 1720 sc->sc_dev.dv_xname); 1721 if (intrstr != NULL) 1722 printf(" at %s", intrstr); 1723 printf("\n"); 1724 return; 1725 } 1726 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1727 /* 1728 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1729 * doing do could allow DMA to corrupt kernel memory during the 1730 * reboot before the driver initializes. 1731 */ 1732 (void) shutdownhook_establish(ti_shutdown, sc); 1733 1734 if (ti_chipinit(sc)) { 1735 printf("%s: chip initialization failed\n", self->dv_xname); 1736 goto fail2; 1737 } 1738 1739 /* 1740 * Deal with some chip diffrences. 1741 */ 1742 switch (sc->ti_hwrev) { 1743 case TI_HWREV_TIGON: 1744 sc->sc_tx_encap = ti_encap_tigon1; 1745 sc->sc_tx_eof = ti_txeof_tigon1; 1746 if (nolinear == 1) 1747 printf("%s: memory space not mapped linear\n", 1748 self->dv_xname); 1749 break; 1750 1751 case TI_HWREV_TIGON_II: 1752 sc->sc_tx_encap = ti_encap_tigon2; 1753 sc->sc_tx_eof = ti_txeof_tigon2; 1754 break; 1755 1756 default: 1757 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1758 sc->ti_hwrev); 1759 goto fail2; 1760 } 1761 1762 /* Zero out the NIC's on-board SRAM. */ 1763 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1764 1765 /* Init again -- zeroing memory may have clobbered some registers. */ 1766 if (ti_chipinit(sc)) { 1767 printf("%s: chip initialization failed\n", self->dv_xname); 1768 goto fail2; 1769 } 1770 1771 /* 1772 * Get station address from the EEPROM. Note: the manual states 1773 * that the MAC address is at offset 0x8c, however the data is 1774 * stored as two longwords (since that's how it's loaded into 1775 * the NIC). This means the MAC address is actually preceded 1776 * by two zero bytes. We need to skip over those. 1777 */ 1778 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1779 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1780 printf("%s: failed to read station address\n", self->dv_xname); 1781 goto fail2; 1782 } 1783 1784 /* 1785 * A Tigon chip was detected. Inform the world. 1786 */ 1787 printf("%s: Ethernet address: %s\n", self->dv_xname, 1788 ether_sprintf(eaddr)); 1789 1790 sc->sc_dmat = pa->pa_dmat; 1791 1792 /* Allocate the general information block and ring buffers. */ 1793 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1794 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1795 BUS_DMA_NOWAIT)) != 0) { 1796 printf("%s: can't allocate ring buffer, error = %d\n", 1797 sc->sc_dev.dv_xname, error); 1798 goto fail2; 1799 } 1800 1801 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1802 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1803 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1804 printf("%s: can't map ring buffer, error = %d\n", 1805 sc->sc_dev.dv_xname, error); 1806 goto fail2; 1807 } 1808 1809 if ((error = bus_dmamap_create(sc->sc_dmat, 1810 sizeof(struct ti_ring_data), 1, 1811 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1812 &sc->info_dmamap)) != 0) { 1813 printf("%s: can't create ring buffer DMA map, error = %d\n", 1814 sc->sc_dev.dv_xname, error); 1815 goto fail2; 1816 } 1817 1818 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1819 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1820 BUS_DMA_NOWAIT)) != 0) { 1821 printf("%s: can't load ring buffer DMA map, error = %d\n", 1822 sc->sc_dev.dv_xname, error); 1823 goto fail2; 1824 } 1825 1826 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1827 1828 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1829 1830 /* Try to allocate memory for jumbo buffers. */ 1831 if (ti_alloc_jumbo_mem(sc)) { 1832 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1833 goto fail2; 1834 } 1835 1836 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1837 1838 /* 1839 * We really need a better way to tell a 1000baseT card 1840 * from a 1000baseSX one, since in theory there could be 1841 * OEMed 1000baseT cards from lame vendors who aren't 1842 * clever enough to change the PCI ID. For the moment 1843 * though, the AceNIC is the only copper card available. 1844 */ 1845 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1846 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1847 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1848 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1849 sc->ti_copper = 1; 1850 else 1851 sc->ti_copper = 0; 1852 1853 /* Set default tuneable values. */ 1854 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1855 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1856 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1857 sc->ti_rx_max_coal_bds = 64; 1858 sc->ti_tx_max_coal_bds = 128; 1859 sc->ti_tx_buf_ratio = 21; 1860 1861 /* Set up ifnet structure */ 1862 ifp = &sc->ethercom.ec_if; 1863 ifp->if_softc = sc; 1864 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1866 ifp->if_ioctl = ti_ioctl; 1867 ifp->if_start = ti_start; 1868 ifp->if_watchdog = ti_watchdog; 1869 IFQ_SET_READY(&ifp->if_snd); 1870 1871 #if 0 1872 /* 1873 * XXX This is not really correct -- we don't necessarily 1874 * XXX want to queue up as many as we can transmit at the 1875 * XXX upper layer like that. Someone with a board should 1876 * XXX check to see how this affects performance. 1877 */ 1878 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1879 #endif 1880 1881 /* 1882 * We can support 802.1Q VLAN-sized frames. 1883 */ 1884 sc->ethercom.ec_capabilities |= 1885 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1886 1887 /* 1888 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1889 */ 1890 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1891 IFCAP_CSUM_UDPv4; 1892 1893 /* Set up ifmedia support. */ 1894 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1895 if (sc->ti_copper) { 1896 /* 1897 * Copper cards allow manual 10/100 mode selection, 1898 * but not manual 1000baseT mode selection. Why? 1899 * Because currently there's no way to specify the 1900 * master/slave setting through the firmware interface, 1901 * so Alteon decided to just bag it and handle it 1902 * via autonegotiation. 1903 */ 1904 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1905 ifmedia_add(&sc->ifmedia, 1906 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1907 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1908 ifmedia_add(&sc->ifmedia, 1909 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1910 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1911 ifmedia_add(&sc->ifmedia, 1912 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1913 } else { 1914 /* Fiber cards don't support 10/100 modes. */ 1915 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1916 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1917 } 1918 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1919 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1920 1921 /* 1922 * Call MI attach routines. 1923 */ 1924 if_attach(ifp); 1925 ether_ifattach(ifp, eaddr); 1926 1927 return; 1928 fail2: 1929 pci_intr_disestablish(pc, sc->sc_ih); 1930 return; 1931 } 1932 1933 /* 1934 * Frame reception handling. This is called if there's a frame 1935 * on the receive return list. 1936 * 1937 * Note: we have to be able to handle three possibilities here: 1938 * 1) the frame is from the mini receive ring (can only happen) 1939 * on Tigon 2 boards) 1940 * 2) the frame is from the jumbo receive ring 1941 * 3) the frame is from the standard receive ring 1942 */ 1943 1944 static void ti_rxeof(sc) 1945 struct ti_softc *sc; 1946 { 1947 struct ifnet *ifp; 1948 struct ti_cmd_desc cmd; 1949 1950 ifp = &sc->ethercom.ec_if; 1951 1952 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1953 struct ti_rx_desc *cur_rx; 1954 u_int32_t rxidx; 1955 struct mbuf *m = NULL; 1956 u_int16_t vlan_tag = 0; 1957 int have_tag = 0; 1958 struct ether_header *eh; 1959 bus_dmamap_t dmamap; 1960 1961 cur_rx = 1962 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1963 rxidx = cur_rx->ti_idx; 1964 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1965 1966 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1967 have_tag = 1; 1968 /* ti_vlan_tag also has the priority, trim it */ 1969 vlan_tag = cur_rx->ti_vlan_tag & 4095; 1970 } 1971 1972 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1973 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1974 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1975 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1976 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1977 ifp->if_ierrors++; 1978 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1979 continue; 1980 } 1981 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1982 == ENOBUFS) { 1983 ifp->if_ierrors++; 1984 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1985 continue; 1986 } 1987 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1988 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1989 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1990 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1991 dmamap = sc->mini_dmamap[rxidx]; 1992 sc->mini_dmamap[rxidx] = 0; 1993 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1994 ifp->if_ierrors++; 1995 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1996 continue; 1997 } 1998 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1999 == ENOBUFS) { 2000 ifp->if_ierrors++; 2001 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 2002 continue; 2003 } 2004 } else { 2005 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2006 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2007 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2008 dmamap = sc->std_dmamap[rxidx]; 2009 sc->std_dmamap[rxidx] = 0; 2010 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2011 ifp->if_ierrors++; 2012 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2013 continue; 2014 } 2015 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2016 == ENOBUFS) { 2017 ifp->if_ierrors++; 2018 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2019 continue; 2020 } 2021 } 2022 2023 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2024 ifp->if_ipackets++; 2025 m->m_pkthdr.rcvif = ifp; 2026 2027 #if NBPFILTER > 0 2028 /* 2029 * Handle BPF listeners. Let the BPF user see the packet, but 2030 * don't pass it up to the ether_input() layer unless it's 2031 * a broadcast packet, multicast packet, matches our ethernet 2032 * address or the interface is in promiscuous mode. 2033 */ 2034 if (ifp->if_bpf) 2035 bpf_mtap(ifp->if_bpf, m); 2036 #endif 2037 2038 eh = mtod(m, struct ether_header *); 2039 switch (ntohs(eh->ether_type)) { 2040 #ifdef INET 2041 case ETHERTYPE_IP: 2042 { 2043 struct ip *ip = (struct ip *) (eh + 1); 2044 2045 /* 2046 * Note the Tigon firmware does not invert 2047 * the checksum for us, hence the XOR. 2048 */ 2049 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2050 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2051 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2052 /* 2053 * ntohs() the constant so the compiler can 2054 * optimize... 2055 * 2056 * XXX Figure out a sane way to deal with 2057 * fragmented packets. 2058 */ 2059 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2060 switch (ip->ip_p) { 2061 case IPPROTO_TCP: 2062 m->m_pkthdr.csum_data = 2063 cur_rx->ti_tcp_udp_cksum; 2064 m->m_pkthdr.csum_flags |= 2065 M_CSUM_TCPv4|M_CSUM_DATA; 2066 break; 2067 case IPPROTO_UDP: 2068 m->m_pkthdr.csum_data = 2069 cur_rx->ti_tcp_udp_cksum; 2070 m->m_pkthdr.csum_flags |= 2071 M_CSUM_UDPv4|M_CSUM_DATA; 2072 break; 2073 default: 2074 /* Nothing */; 2075 } 2076 } 2077 break; 2078 } 2079 #endif 2080 default: 2081 /* Nothing. */ 2082 break; 2083 } 2084 2085 if (have_tag) { 2086 struct m_tag *mtag; 2087 2088 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2089 M_NOWAIT); 2090 if (mtag) { 2091 *(u_int *)(mtag + 1) = vlan_tag; 2092 m_tag_prepend(m, mtag); 2093 have_tag = vlan_tag = 0; 2094 } else { 2095 printf("%s: no mbuf for tag\n", ifp->if_xname); 2096 m_freem(m); 2097 have_tag = vlan_tag = 0; 2098 continue; 2099 } 2100 } 2101 (*ifp->if_input)(ifp, m); 2102 } 2103 2104 /* Only necessary on the Tigon 1. */ 2105 if (sc->ti_hwrev == TI_HWREV_TIGON) 2106 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2107 sc->ti_rx_saved_considx); 2108 2109 TI_UPDATE_STDPROD(sc, sc->ti_std); 2110 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2111 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2112 2113 return; 2114 } 2115 2116 static void ti_txeof_tigon1(sc) 2117 struct ti_softc *sc; 2118 { 2119 struct ti_tx_desc *cur_tx = NULL; 2120 struct ifnet *ifp; 2121 struct txdmamap_pool_entry *dma; 2122 2123 ifp = &sc->ethercom.ec_if; 2124 2125 /* 2126 * Go through our tx ring and free mbufs for those 2127 * frames that have been sent. 2128 */ 2129 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2130 u_int32_t idx = 0; 2131 2132 idx = sc->ti_tx_saved_considx; 2133 if (idx > 383) 2134 CSR_WRITE_4(sc, TI_WINBASE, 2135 TI_TX_RING_BASE + 6144); 2136 else if (idx > 255) 2137 CSR_WRITE_4(sc, TI_WINBASE, 2138 TI_TX_RING_BASE + 4096); 2139 else if (idx > 127) 2140 CSR_WRITE_4(sc, TI_WINBASE, 2141 TI_TX_RING_BASE + 2048); 2142 else 2143 CSR_WRITE_4(sc, TI_WINBASE, 2144 TI_TX_RING_BASE); 2145 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2146 if (cur_tx->ti_flags & TI_BDFLAG_END) 2147 ifp->if_opackets++; 2148 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2149 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2150 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2151 2152 dma = sc->txdma[idx]; 2153 KDASSERT(dma != NULL); 2154 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2155 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2156 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2157 2158 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2159 sc->txdma[idx] = NULL; 2160 } 2161 sc->ti_txcnt--; 2162 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2163 ifp->if_timer = 0; 2164 } 2165 2166 if (cur_tx != NULL) 2167 ifp->if_flags &= ~IFF_OACTIVE; 2168 2169 return; 2170 } 2171 2172 static void ti_txeof_tigon2(sc) 2173 struct ti_softc *sc; 2174 { 2175 struct ti_tx_desc *cur_tx = NULL; 2176 struct ifnet *ifp; 2177 struct txdmamap_pool_entry *dma; 2178 int firstidx, cnt; 2179 2180 ifp = &sc->ethercom.ec_if; 2181 2182 /* 2183 * Go through our tx ring and free mbufs for those 2184 * frames that have been sent. 2185 */ 2186 firstidx = sc->ti_tx_saved_considx; 2187 cnt = 0; 2188 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2189 u_int32_t idx = 0; 2190 2191 idx = sc->ti_tx_saved_considx; 2192 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2193 if (cur_tx->ti_flags & TI_BDFLAG_END) 2194 ifp->if_opackets++; 2195 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2196 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2197 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2198 2199 dma = sc->txdma[idx]; 2200 KDASSERT(dma != NULL); 2201 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2202 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2203 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2204 2205 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2206 sc->txdma[idx] = NULL; 2207 } 2208 cnt++; 2209 sc->ti_txcnt--; 2210 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2211 ifp->if_timer = 0; 2212 } 2213 2214 if (cnt != 0) 2215 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2216 2217 if (cur_tx != NULL) 2218 ifp->if_flags &= ~IFF_OACTIVE; 2219 2220 return; 2221 } 2222 2223 static int ti_intr(xsc) 2224 void *xsc; 2225 { 2226 struct ti_softc *sc; 2227 struct ifnet *ifp; 2228 2229 sc = xsc; 2230 ifp = &sc->ethercom.ec_if; 2231 2232 #ifdef notdef 2233 /* Avoid this for now -- checking this register is expensive. */ 2234 /* Make sure this is really our interrupt. */ 2235 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2236 return (0); 2237 #endif 2238 2239 /* Ack interrupt and stop others from occuring. */ 2240 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2241 2242 if (ifp->if_flags & IFF_RUNNING) { 2243 /* Check RX return ring producer/consumer */ 2244 ti_rxeof(sc); 2245 2246 /* Check TX ring producer/consumer */ 2247 (*sc->sc_tx_eof)(sc); 2248 } 2249 2250 ti_handle_events(sc); 2251 2252 /* Re-enable interrupts. */ 2253 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2254 2255 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2256 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2257 ti_start(ifp); 2258 2259 return (1); 2260 } 2261 2262 static void ti_stats_update(sc) 2263 struct ti_softc *sc; 2264 { 2265 struct ifnet *ifp; 2266 2267 ifp = &sc->ethercom.ec_if; 2268 2269 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2270 2271 ifp->if_collisions += 2272 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2273 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2274 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2275 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2276 ifp->if_collisions; 2277 2278 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2279 } 2280 2281 /* 2282 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2283 * pointers to descriptors. 2284 */ 2285 static int ti_encap_tigon1(sc, m_head, txidx) 2286 struct ti_softc *sc; 2287 struct mbuf *m_head; 2288 u_int32_t *txidx; 2289 { 2290 struct ti_tx_desc *f = NULL; 2291 u_int32_t frag, cur, cnt = 0; 2292 struct txdmamap_pool_entry *dma; 2293 bus_dmamap_t dmamap; 2294 int error, i; 2295 struct m_tag *mtag; 2296 u_int16_t csum_flags = 0; 2297 2298 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2299 if (dma == NULL) { 2300 return ENOMEM; 2301 } 2302 dmamap = dma->dmamap; 2303 2304 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2305 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2306 if (error) { 2307 struct mbuf *m; 2308 int i = 0; 2309 for (m = m_head; m; m = m->m_next) 2310 i++; 2311 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2312 "error %d\n", m_head->m_pkthdr.len, i, error); 2313 return (ENOMEM); 2314 } 2315 2316 cur = frag = *txidx; 2317 2318 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2319 /* IP header checksum field must be 0! */ 2320 csum_flags |= TI_BDFLAG_IP_CKSUM; 2321 } 2322 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2323 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2324 2325 /* XXX fragmented packet checksum capability? */ 2326 2327 /* 2328 * Start packing the mbufs in this chain into 2329 * the fragment pointers. Stop when we run out 2330 * of fragments or hit the end of the mbuf chain. 2331 */ 2332 for (i = 0; i < dmamap->dm_nsegs; i++) { 2333 if (frag > 383) 2334 CSR_WRITE_4(sc, TI_WINBASE, 2335 TI_TX_RING_BASE + 6144); 2336 else if (frag > 255) 2337 CSR_WRITE_4(sc, TI_WINBASE, 2338 TI_TX_RING_BASE + 4096); 2339 else if (frag > 127) 2340 CSR_WRITE_4(sc, TI_WINBASE, 2341 TI_TX_RING_BASE + 2048); 2342 else 2343 CSR_WRITE_4(sc, TI_WINBASE, 2344 TI_TX_RING_BASE); 2345 f = &sc->ti_tx_ring_nic[frag % 128]; 2346 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2347 break; 2348 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2349 f->ti_len = dmamap->dm_segs[i].ds_len; 2350 f->ti_flags = csum_flags; 2351 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2352 if (mtag) { 2353 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2354 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2355 } else { 2356 f->ti_vlan_tag = 0; 2357 } 2358 /* 2359 * Sanity check: avoid coming within 16 descriptors 2360 * of the end of the ring. 2361 */ 2362 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2363 return(ENOBUFS); 2364 cur = frag; 2365 TI_INC(frag, TI_TX_RING_CNT); 2366 cnt++; 2367 } 2368 2369 if (i < dmamap->dm_nsegs) 2370 return(ENOBUFS); 2371 2372 if (frag == sc->ti_tx_saved_considx) 2373 return(ENOBUFS); 2374 2375 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2376 TI_BDFLAG_END; 2377 2378 /* Sync the packet's DMA map. */ 2379 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2380 BUS_DMASYNC_PREWRITE); 2381 2382 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2383 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2384 sc->txdma[cur] = dma; 2385 sc->ti_txcnt += cnt; 2386 2387 *txidx = frag; 2388 2389 return(0); 2390 } 2391 2392 static int ti_encap_tigon2(sc, m_head, txidx) 2393 struct ti_softc *sc; 2394 struct mbuf *m_head; 2395 u_int32_t *txidx; 2396 { 2397 struct ti_tx_desc *f = NULL; 2398 u_int32_t frag, firstfrag, cur, cnt = 0; 2399 struct txdmamap_pool_entry *dma; 2400 bus_dmamap_t dmamap; 2401 int error, i; 2402 struct m_tag *mtag; 2403 u_int16_t csum_flags = 0; 2404 2405 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2406 if (dma == NULL) { 2407 return ENOMEM; 2408 } 2409 dmamap = dma->dmamap; 2410 2411 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2412 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2413 if (error) { 2414 struct mbuf *m; 2415 int i = 0; 2416 for (m = m_head; m; m = m->m_next) 2417 i++; 2418 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2419 "error %d\n", m_head->m_pkthdr.len, i, error); 2420 return (ENOMEM); 2421 } 2422 2423 cur = firstfrag = frag = *txidx; 2424 2425 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2426 /* IP header checksum field must be 0! */ 2427 csum_flags |= TI_BDFLAG_IP_CKSUM; 2428 } 2429 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2430 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2431 2432 /* XXX fragmented packet checksum capability? */ 2433 2434 /* 2435 * Start packing the mbufs in this chain into 2436 * the fragment pointers. Stop when we run out 2437 * of fragments or hit the end of the mbuf chain. 2438 */ 2439 for (i = 0; i < dmamap->dm_nsegs; i++) { 2440 f = &sc->ti_rdata->ti_tx_ring[frag]; 2441 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2442 break; 2443 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2444 f->ti_len = dmamap->dm_segs[i].ds_len; 2445 f->ti_flags = csum_flags; 2446 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2447 if (mtag) { 2448 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2449 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2450 } else { 2451 f->ti_vlan_tag = 0; 2452 } 2453 /* 2454 * Sanity check: avoid coming within 16 descriptors 2455 * of the end of the ring. 2456 */ 2457 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2458 return(ENOBUFS); 2459 cur = frag; 2460 TI_INC(frag, TI_TX_RING_CNT); 2461 cnt++; 2462 } 2463 2464 if (i < dmamap->dm_nsegs) 2465 return(ENOBUFS); 2466 2467 if (frag == sc->ti_tx_saved_considx) 2468 return(ENOBUFS); 2469 2470 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2471 2472 /* Sync the packet's DMA map. */ 2473 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2474 BUS_DMASYNC_PREWRITE); 2475 2476 /* Sync the descriptors we are using. */ 2477 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2478 2479 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2480 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2481 sc->txdma[cur] = dma; 2482 sc->ti_txcnt += cnt; 2483 2484 *txidx = frag; 2485 2486 return(0); 2487 } 2488 2489 /* 2490 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2491 * to the mbuf data regions directly in the transmit descriptors. 2492 */ 2493 static void ti_start(ifp) 2494 struct ifnet *ifp; 2495 { 2496 struct ti_softc *sc; 2497 struct mbuf *m_head = NULL; 2498 u_int32_t prodidx = 0; 2499 2500 sc = ifp->if_softc; 2501 2502 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2503 2504 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2505 IFQ_POLL(&ifp->if_snd, m_head); 2506 if (m_head == NULL) 2507 break; 2508 2509 /* 2510 * Pack the data into the transmit ring. If we 2511 * don't have room, set the OACTIVE flag and wait 2512 * for the NIC to drain the ring. 2513 */ 2514 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2515 ifp->if_flags |= IFF_OACTIVE; 2516 break; 2517 } 2518 2519 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2520 2521 /* 2522 * If there's a BPF listener, bounce a copy of this frame 2523 * to him. 2524 */ 2525 #if NBPFILTER > 0 2526 if (ifp->if_bpf) 2527 bpf_mtap(ifp->if_bpf, m_head); 2528 #endif 2529 } 2530 2531 /* Transmit */ 2532 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2533 2534 /* 2535 * Set a timeout in case the chip goes out to lunch. 2536 */ 2537 ifp->if_timer = 5; 2538 2539 return; 2540 } 2541 2542 static void ti_init(xsc) 2543 void *xsc; 2544 { 2545 struct ti_softc *sc = xsc; 2546 int s; 2547 2548 s = splnet(); 2549 2550 /* Cancel pending I/O and flush buffers. */ 2551 ti_stop(sc); 2552 2553 /* Init the gen info block, ring control blocks and firmware. */ 2554 if (ti_gibinit(sc)) { 2555 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2556 splx(s); 2557 return; 2558 } 2559 2560 splx(s); 2561 2562 return; 2563 } 2564 2565 static void ti_init2(sc) 2566 struct ti_softc *sc; 2567 { 2568 struct ti_cmd_desc cmd; 2569 struct ifnet *ifp; 2570 u_int8_t *m; 2571 struct ifmedia *ifm; 2572 int tmp; 2573 2574 ifp = &sc->ethercom.ec_if; 2575 2576 /* Specify MTU and interface index. */ 2577 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2578 2579 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2580 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2581 tmp += ETHER_VLAN_ENCAP_LEN; 2582 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2583 2584 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2585 2586 /* Load our MAC address. */ 2587 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2588 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2589 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2590 | (m[4] << 8) | m[5]); 2591 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2592 2593 /* Enable or disable promiscuous mode as needed. */ 2594 if (ifp->if_flags & IFF_PROMISC) { 2595 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2596 } else { 2597 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2598 } 2599 2600 /* Program multicast filter. */ 2601 ti_setmulti(sc); 2602 2603 /* 2604 * If this is a Tigon 1, we should tell the 2605 * firmware to use software packet filtering. 2606 */ 2607 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2608 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2609 } 2610 2611 /* Init RX ring. */ 2612 ti_init_rx_ring_std(sc); 2613 2614 /* Init jumbo RX ring. */ 2615 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2616 ti_init_rx_ring_jumbo(sc); 2617 2618 /* 2619 * If this is a Tigon 2, we can also configure the 2620 * mini ring. 2621 */ 2622 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2623 ti_init_rx_ring_mini(sc); 2624 2625 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2626 sc->ti_rx_saved_considx = 0; 2627 2628 /* Init TX ring. */ 2629 ti_init_tx_ring(sc); 2630 2631 /* Tell firmware we're alive. */ 2632 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2633 2634 /* Enable host interrupts. */ 2635 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2636 2637 ifp->if_flags |= IFF_RUNNING; 2638 ifp->if_flags &= ~IFF_OACTIVE; 2639 2640 /* 2641 * Make sure to set media properly. We have to do this 2642 * here since we have to issue commands in order to set 2643 * the link negotiation and we can't issue commands until 2644 * the firmware is running. 2645 */ 2646 ifm = &sc->ifmedia; 2647 tmp = ifm->ifm_media; 2648 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2649 ti_ifmedia_upd(ifp); 2650 ifm->ifm_media = tmp; 2651 2652 return; 2653 } 2654 2655 /* 2656 * Set media options. 2657 */ 2658 static int ti_ifmedia_upd(ifp) 2659 struct ifnet *ifp; 2660 { 2661 struct ti_softc *sc; 2662 struct ifmedia *ifm; 2663 struct ti_cmd_desc cmd; 2664 2665 sc = ifp->if_softc; 2666 ifm = &sc->ifmedia; 2667 2668 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2669 return(EINVAL); 2670 2671 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2672 case IFM_AUTO: 2673 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2674 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2675 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2676 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2677 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2678 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2679 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2680 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2681 break; 2682 case IFM_1000_SX: 2683 case IFM_1000_T: 2684 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2685 CSR_WRITE_4(sc, TI_GCR_GLINK, 2686 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2687 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2688 } else { 2689 CSR_WRITE_4(sc, TI_GCR_GLINK, 2690 TI_GLNK_PREF|TI_GLNK_1000MB| 2691 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2692 } 2693 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2694 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2695 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2696 break; 2697 case IFM_100_FX: 2698 case IFM_10_FL: 2699 case IFM_100_TX: 2700 case IFM_10_T: 2701 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2702 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2703 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2704 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2705 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2706 } else { 2707 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2708 } 2709 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2710 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2711 } else { 2712 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2713 } 2714 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2715 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2716 break; 2717 } 2718 2719 sc->ethercom.ec_if.if_baudrate = 2720 ifmedia_baudrate(ifm->ifm_media); 2721 2722 return(0); 2723 } 2724 2725 /* 2726 * Report current media status. 2727 */ 2728 static void ti_ifmedia_sts(ifp, ifmr) 2729 struct ifnet *ifp; 2730 struct ifmediareq *ifmr; 2731 { 2732 struct ti_softc *sc; 2733 u_int32_t media = 0; 2734 2735 sc = ifp->if_softc; 2736 2737 ifmr->ifm_status = IFM_AVALID; 2738 ifmr->ifm_active = IFM_ETHER; 2739 2740 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2741 return; 2742 2743 ifmr->ifm_status |= IFM_ACTIVE; 2744 2745 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2746 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2747 if (sc->ti_copper) 2748 ifmr->ifm_active |= IFM_1000_T; 2749 else 2750 ifmr->ifm_active |= IFM_1000_SX; 2751 if (media & TI_GLNK_FULL_DUPLEX) 2752 ifmr->ifm_active |= IFM_FDX; 2753 else 2754 ifmr->ifm_active |= IFM_HDX; 2755 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2756 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2757 if (sc->ti_copper) { 2758 if (media & TI_LNK_100MB) 2759 ifmr->ifm_active |= IFM_100_TX; 2760 if (media & TI_LNK_10MB) 2761 ifmr->ifm_active |= IFM_10_T; 2762 } else { 2763 if (media & TI_LNK_100MB) 2764 ifmr->ifm_active |= IFM_100_FX; 2765 if (media & TI_LNK_10MB) 2766 ifmr->ifm_active |= IFM_10_FL; 2767 } 2768 if (media & TI_LNK_FULL_DUPLEX) 2769 ifmr->ifm_active |= IFM_FDX; 2770 if (media & TI_LNK_HALF_DUPLEX) 2771 ifmr->ifm_active |= IFM_HDX; 2772 } 2773 2774 sc->ethercom.ec_if.if_baudrate = 2775 ifmedia_baudrate(sc->ifmedia.ifm_media); 2776 2777 return; 2778 } 2779 2780 static int 2781 ti_ether_ioctl(ifp, cmd, data) 2782 struct ifnet *ifp; 2783 u_long cmd; 2784 caddr_t data; 2785 { 2786 struct ifaddr *ifa = (struct ifaddr *) data; 2787 struct ti_softc *sc = ifp->if_softc; 2788 2789 if ((ifp->if_flags & IFF_UP) == 0) { 2790 ifp->if_flags |= IFF_UP; 2791 ti_init(sc); 2792 } 2793 2794 switch (cmd) { 2795 case SIOCSIFADDR: 2796 2797 switch (ifa->ifa_addr->sa_family) { 2798 #ifdef INET 2799 case AF_INET: 2800 arp_ifinit(ifp, ifa); 2801 break; 2802 #endif 2803 #ifdef NS 2804 case AF_NS: 2805 { 2806 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2807 2808 if (ns_nullhost(*ina)) 2809 ina->x_host = *(union ns_host *) 2810 LLADDR(ifp->if_sadl); 2811 else 2812 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2813 ifp->if_addrlen); 2814 break; 2815 } 2816 #endif 2817 default: 2818 break; 2819 } 2820 break; 2821 2822 default: 2823 return (EINVAL); 2824 } 2825 2826 return (0); 2827 } 2828 2829 static int ti_ioctl(ifp, command, data) 2830 struct ifnet *ifp; 2831 u_long command; 2832 caddr_t data; 2833 { 2834 struct ti_softc *sc = ifp->if_softc; 2835 struct ifreq *ifr = (struct ifreq *) data; 2836 int s, error = 0; 2837 struct ti_cmd_desc cmd; 2838 2839 s = splnet(); 2840 2841 switch(command) { 2842 case SIOCSIFADDR: 2843 case SIOCGIFADDR: 2844 error = ti_ether_ioctl(ifp, command, data); 2845 break; 2846 case SIOCSIFMTU: 2847 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2848 error = EINVAL; 2849 else { 2850 ifp->if_mtu = ifr->ifr_mtu; 2851 ti_init(sc); 2852 } 2853 break; 2854 case SIOCSIFFLAGS: 2855 if (ifp->if_flags & IFF_UP) { 2856 /* 2857 * If only the state of the PROMISC flag changed, 2858 * then just use the 'set promisc mode' command 2859 * instead of reinitializing the entire NIC. Doing 2860 * a full re-init means reloading the firmware and 2861 * waiting for it to start up, which may take a 2862 * second or two. 2863 */ 2864 if (ifp->if_flags & IFF_RUNNING && 2865 ifp->if_flags & IFF_PROMISC && 2866 !(sc->ti_if_flags & IFF_PROMISC)) { 2867 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2868 TI_CMD_CODE_PROMISC_ENB, 0); 2869 } else if (ifp->if_flags & IFF_RUNNING && 2870 !(ifp->if_flags & IFF_PROMISC) && 2871 sc->ti_if_flags & IFF_PROMISC) { 2872 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2873 TI_CMD_CODE_PROMISC_DIS, 0); 2874 } else 2875 ti_init(sc); 2876 } else { 2877 if (ifp->if_flags & IFF_RUNNING) { 2878 ti_stop(sc); 2879 } 2880 } 2881 sc->ti_if_flags = ifp->if_flags; 2882 error = 0; 2883 break; 2884 case SIOCADDMULTI: 2885 case SIOCDELMULTI: 2886 error = (command == SIOCADDMULTI) ? 2887 ether_addmulti(ifr, &sc->ethercom) : 2888 ether_delmulti(ifr, &sc->ethercom); 2889 if (error == ENETRESET) { 2890 if (ifp->if_flags & IFF_RUNNING) 2891 ti_setmulti(sc); 2892 error = 0; 2893 } 2894 break; 2895 case SIOCSIFMEDIA: 2896 case SIOCGIFMEDIA: 2897 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2898 break; 2899 default: 2900 error = EINVAL; 2901 break; 2902 } 2903 2904 (void)splx(s); 2905 2906 return(error); 2907 } 2908 2909 static void ti_watchdog(ifp) 2910 struct ifnet *ifp; 2911 { 2912 struct ti_softc *sc; 2913 2914 sc = ifp->if_softc; 2915 2916 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2917 ti_stop(sc); 2918 ti_init(sc); 2919 2920 ifp->if_oerrors++; 2921 2922 return; 2923 } 2924 2925 /* 2926 * Stop the adapter and free any mbufs allocated to the 2927 * RX and TX lists. 2928 */ 2929 static void ti_stop(sc) 2930 struct ti_softc *sc; 2931 { 2932 struct ifnet *ifp; 2933 struct ti_cmd_desc cmd; 2934 2935 ifp = &sc->ethercom.ec_if; 2936 2937 /* Disable host interrupts. */ 2938 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2939 /* 2940 * Tell firmware we're shutting down. 2941 */ 2942 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2943 2944 /* Halt and reinitialize. */ 2945 ti_chipinit(sc); 2946 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2947 ti_chipinit(sc); 2948 2949 /* Free the RX lists. */ 2950 ti_free_rx_ring_std(sc); 2951 2952 /* Free jumbo RX list. */ 2953 ti_free_rx_ring_jumbo(sc); 2954 2955 /* Free mini RX list. */ 2956 ti_free_rx_ring_mini(sc); 2957 2958 /* Free TX buffers. */ 2959 ti_free_tx_ring(sc); 2960 2961 sc->ti_ev_prodidx.ti_idx = 0; 2962 sc->ti_return_prodidx.ti_idx = 0; 2963 sc->ti_tx_considx.ti_idx = 0; 2964 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2965 2966 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2967 2968 return; 2969 } 2970 2971 /* 2972 * Stop all chip I/O so that the kernel's probe routines don't 2973 * get confused by errant DMAs when rebooting. 2974 */ 2975 static void ti_shutdown(v) 2976 void *v; 2977 { 2978 struct ti_softc *sc = v; 2979 2980 ti_chipinit(sc); 2981 2982 return; 2983 } 2984
Indexes created Fri Sep 26 20:09:58 GMT 2025