if_ti.c revision 1.64
1 /* $NetBSD: if_ti.c,v 1.64 2005/02/04 02:10:45 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.64 2005/02/04 02:10:45 perry Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match(struct pci_attach_args *); 157 static int ti_probe(struct device *, struct cfdata *, void *); 158 static void ti_attach(struct device *, struct device *, void *); 159 static void ti_shutdown(void *); 160 static void ti_txeof_tigon1(struct ti_softc *); 161 static void ti_txeof_tigon2(struct ti_softc *); 162 static void ti_rxeof(struct ti_softc *); 163 164 static void ti_stats_update(struct ti_softc *); 165 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 166 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 167 168 static int ti_intr(void *); 169 static void ti_start(struct ifnet *); 170 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 171 static void ti_init(void *); 172 static void ti_init2(struct ti_softc *); 173 static void ti_stop(struct ti_softc *); 174 static void ti_watchdog(struct ifnet *); 175 static int ti_ifmedia_upd(struct ifnet *); 176 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 179 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 180 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 181 182 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 184 static void ti_setmulti(struct ti_softc *); 185 186 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, caddr_t); 187 static void ti_loadfw(struct ti_softc *); 188 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 189 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 190 static void ti_handle_events(struct ti_softc *); 191 static int ti_alloc_jumbo_mem(struct ti_softc *); 192 static void *ti_jalloc(struct ti_softc *); 193 static void ti_jfree(struct mbuf *, caddr_t, size_t, void *); 194 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 195 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 196 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 197 static int ti_init_rx_ring_std(struct ti_softc *); 198 static void ti_free_rx_ring_std(struct ti_softc *); 199 static int ti_init_rx_ring_jumbo(struct ti_softc *); 200 static void ti_free_rx_ring_jumbo(struct ti_softc *); 201 static int ti_init_rx_ring_mini(struct ti_softc *); 202 static void ti_free_rx_ring_mini(struct ti_softc *); 203 static void ti_free_tx_ring(struct ti_softc *); 204 static int ti_init_tx_ring(struct ti_softc *); 205 206 static int ti_64bitslot_war(struct ti_softc *); 207 static int ti_chipinit(struct ti_softc *); 208 static int ti_gibinit(struct ti_softc *); 209 210 static int ti_ether_ioctl(struct ifnet *, u_long, caddr_t); 211 212 CFATTACH_DECL(ti, sizeof(struct ti_softc), 213 ti_probe, ti_attach, NULL, NULL); 214 215 /* 216 * Send an instruction or address to the EEPROM, check for ACK. 217 */ 218 static u_int32_t ti_eeprom_putbyte(sc, byte) 219 struct ti_softc *sc; 220 int byte; 221 { 222 int i, ack = 0; 223 224 /* 225 * Make sure we're in TX mode. 226 */ 227 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 228 229 /* 230 * Feed in each bit and stobe the clock. 231 */ 232 for (i = 0x80; i; i >>= 1) { 233 if (byte & i) { 234 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 235 } else { 236 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 237 } 238 DELAY(1); 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 240 DELAY(1); 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 242 } 243 244 /* 245 * Turn off TX mode. 246 */ 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 248 249 /* 250 * Check for ack. 251 */ 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 256 return(ack); 257 } 258 259 /* 260 * Read a byte of data stored in the EEPROM at address 'addr.' 261 * We have to send two address bytes since the EEPROM can hold 262 * more than 256 bytes of data. 263 */ 264 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 265 struct ti_softc *sc; 266 int addr; 267 u_int8_t *dest; 268 { 269 int i; 270 u_int8_t byte = 0; 271 272 EEPROM_START; 273 274 /* 275 * Send write control code to EEPROM. 276 */ 277 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 278 printf("%s: failed to send write command, status: %x\n", 279 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 280 return(1); 281 } 282 283 /* 284 * Send first byte of address of byte we want to read. 285 */ 286 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 287 printf("%s: failed to send address, status: %x\n", 288 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return(1); 290 } 291 /* 292 * Send second byte address of byte we want to read. 293 */ 294 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 295 printf("%s: failed to send address, status: %x\n", 296 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return(1); 298 } 299 300 EEPROM_STOP; 301 EEPROM_START; 302 /* 303 * Send read control code to EEPROM. 304 */ 305 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 306 printf("%s: failed to send read command, status: %x\n", 307 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 /* 312 * Start reading bits from EEPROM. 313 */ 314 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 315 for (i = 0x80; i; i >>= 1) { 316 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 317 DELAY(1); 318 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 319 byte |= i; 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 321 DELAY(1); 322 } 323 324 EEPROM_STOP; 325 326 /* 327 * No ACK generated for read, so just return byte. 328 */ 329 330 *dest = byte; 331 332 return(0); 333 } 334 335 /* 336 * Read a sequence of bytes from the EEPROM. 337 */ 338 static int ti_read_eeprom(sc, dest, off, cnt) 339 struct ti_softc *sc; 340 caddr_t dest; 341 int off; 342 int cnt; 343 { 344 int err = 0, i; 345 u_int8_t byte = 0; 346 347 for (i = 0; i < cnt; i++) { 348 err = ti_eeprom_getbyte(sc, off + i, &byte); 349 if (err) 350 break; 351 *(dest + i) = byte; 352 } 353 354 return(err ? 1 : 0); 355 } 356 357 /* 358 * NIC memory access function. Can be used to either clear a section 359 * of NIC local memory or (if buf is non-NULL) copy data into it. 360 */ 361 static void ti_mem(sc, addr, len, buf) 362 struct ti_softc *sc; 363 u_int32_t addr, len; 364 caddr_t buf; 365 { 366 int segptr, segsize, cnt; 367 caddr_t ptr; 368 369 segptr = addr; 370 cnt = len; 371 ptr = buf; 372 373 while(cnt) { 374 if (cnt < TI_WINLEN) 375 segsize = cnt; 376 else 377 segsize = TI_WINLEN - (segptr % TI_WINLEN); 378 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 379 if (buf == NULL) { 380 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 381 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 382 segsize / 4); 383 } else { 384 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 385 bus_space_write_region_stream_4(sc->ti_btag, 386 sc->ti_bhandle, 387 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 388 (u_int32_t *)ptr, segsize / 4); 389 #else 390 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 391 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 392 (u_int32_t *)ptr, segsize / 4); 393 #endif 394 ptr += segsize; 395 } 396 segptr += segsize; 397 cnt -= segsize; 398 } 399 400 return; 401 } 402 403 /* 404 * Load firmware image into the NIC. Check that the firmware revision 405 * is acceptable and see if we want the firmware for the Tigon 1 or 406 * Tigon 2. 407 */ 408 static void ti_loadfw(sc) 409 struct ti_softc *sc; 410 { 411 switch(sc->ti_hwrev) { 412 case TI_HWREV_TIGON: 413 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 414 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 415 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 416 printf("%s: firmware revision mismatch; want " 417 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 418 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 419 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 420 tigonFwReleaseMinor, tigonFwReleaseFix); 421 return; 422 } 423 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 424 (caddr_t)tigonFwText); 425 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 426 (caddr_t)tigonFwData); 427 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 428 (caddr_t)tigonFwRodata); 429 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 430 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 431 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 432 break; 433 case TI_HWREV_TIGON_II: 434 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 435 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 436 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 437 printf("%s: firmware revision mismatch; want " 438 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 439 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 440 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 441 tigon2FwReleaseMinor, tigon2FwReleaseFix); 442 return; 443 } 444 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 445 (caddr_t)tigon2FwText); 446 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 447 (caddr_t)tigon2FwData); 448 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 449 (caddr_t)tigon2FwRodata); 450 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 451 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 452 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 453 break; 454 default: 455 printf("%s: can't load firmware: unknown hardware rev\n", 456 sc->sc_dev.dv_xname); 457 break; 458 } 459 460 return; 461 } 462 463 /* 464 * Send the NIC a command via the command ring. 465 */ 466 static void ti_cmd(sc, cmd) 467 struct ti_softc *sc; 468 struct ti_cmd_desc *cmd; 469 { 470 u_int32_t index; 471 472 index = sc->ti_cmd_saved_prodidx; 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 474 TI_INC(index, TI_CMD_RING_CNT); 475 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 476 sc->ti_cmd_saved_prodidx = index; 477 478 return; 479 } 480 481 /* 482 * Send the NIC an extended command. The 'len' parameter specifies the 483 * number of command slots to include after the initial command. 484 */ 485 static void ti_cmd_ext(sc, cmd, arg, len) 486 struct ti_softc *sc; 487 struct ti_cmd_desc *cmd; 488 caddr_t arg; 489 int len; 490 { 491 u_int32_t index; 492 int i; 493 494 index = sc->ti_cmd_saved_prodidx; 495 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 496 TI_INC(index, TI_CMD_RING_CNT); 497 for (i = 0; i < len; i++) { 498 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 499 *(u_int32_t *)(&arg[i * 4])); 500 TI_INC(index, TI_CMD_RING_CNT); 501 } 502 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 503 sc->ti_cmd_saved_prodidx = index; 504 505 return; 506 } 507 508 /* 509 * Handle events that have triggered interrupts. 510 */ 511 static void ti_handle_events(sc) 512 struct ti_softc *sc; 513 { 514 struct ti_event_desc *e; 515 516 if (sc->ti_rdata->ti_event_ring == NULL) 517 return; 518 519 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 520 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 521 switch(e->ti_event) { 522 case TI_EV_LINKSTAT_CHANGED: 523 sc->ti_linkstat = e->ti_code; 524 if (e->ti_code == TI_EV_CODE_LINK_UP) 525 printf("%s: 10/100 link up\n", 526 sc->sc_dev.dv_xname); 527 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 528 printf("%s: gigabit link up\n", 529 sc->sc_dev.dv_xname); 530 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 531 printf("%s: link down\n", 532 sc->sc_dev.dv_xname); 533 break; 534 case TI_EV_ERROR: 535 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 536 printf("%s: invalid command\n", 537 sc->sc_dev.dv_xname); 538 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 539 printf("%s: unknown command\n", 540 sc->sc_dev.dv_xname); 541 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 542 printf("%s: bad config data\n", 543 sc->sc_dev.dv_xname); 544 break; 545 case TI_EV_FIRMWARE_UP: 546 ti_init2(sc); 547 break; 548 case TI_EV_STATS_UPDATED: 549 ti_stats_update(sc); 550 break; 551 case TI_EV_RESET_JUMBO_RING: 552 case TI_EV_MCAST_UPDATED: 553 /* Who cares. */ 554 break; 555 default: 556 printf("%s: unknown event: %d\n", 557 sc->sc_dev.dv_xname, e->ti_event); 558 break; 559 } 560 /* Advance the consumer index. */ 561 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 562 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 563 } 564 565 return; 566 } 567 568 /* 569 * Memory management for the jumbo receive ring is a pain in the 570 * butt. We need to allocate at least 9018 bytes of space per frame, 571 * _and_ it has to be contiguous (unless you use the extended 572 * jumbo descriptor format). Using malloc() all the time won't 573 * work: malloc() allocates memory in powers of two, which means we 574 * would end up wasting a considerable amount of space by allocating 575 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 576 * to do our own memory management. 577 * 578 * The driver needs to allocate a contiguous chunk of memory at boot 579 * time. We then chop this up ourselves into 9K pieces and use them 580 * as external mbuf storage. 581 * 582 * One issue here is how much memory to allocate. The jumbo ring has 583 * 256 slots in it, but at 9K per slot than can consume over 2MB of 584 * RAM. This is a bit much, especially considering we also need 585 * RAM for the standard ring and mini ring (on the Tigon 2). To 586 * save space, we only actually allocate enough memory for 64 slots 587 * by default, which works out to between 500 and 600K. This can 588 * be tuned by changing a #define in if_tireg.h. 589 */ 590 591 static int ti_alloc_jumbo_mem(sc) 592 struct ti_softc *sc; 593 { 594 caddr_t ptr; 595 int i; 596 struct ti_jpool_entry *entry; 597 bus_dma_segment_t dmaseg; 598 int error, dmanseg; 599 600 /* Grab a big chunk o' storage. */ 601 if ((error = bus_dmamem_alloc(sc->sc_dmat, 602 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 603 BUS_DMA_NOWAIT)) != 0) { 604 printf("%s: can't allocate jumbo buffer, error = %d\n", 605 sc->sc_dev.dv_xname, error); 606 return (error); 607 } 608 609 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 610 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 611 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 612 printf("%s: can't map jumbo buffer, error = %d\n", 613 sc->sc_dev.dv_xname, error); 614 return (error); 615 } 616 617 if ((error = bus_dmamap_create(sc->sc_dmat, 618 TI_JMEM, 1, 619 TI_JMEM, 0, BUS_DMA_NOWAIT, 620 &sc->jumbo_dmamap)) != 0) { 621 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 622 sc->sc_dev.dv_xname, error); 623 return (error); 624 } 625 626 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 627 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 628 BUS_DMA_NOWAIT)) != 0) { 629 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 630 sc->sc_dev.dv_xname, error); 631 return (error); 632 } 633 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 634 635 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 636 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 637 638 /* 639 * Now divide it up into 9K pieces and save the addresses 640 * in an array. 641 */ 642 ptr = sc->ti_cdata.ti_jumbo_buf; 643 for (i = 0; i < TI_JSLOTS; i++) { 644 sc->ti_cdata.ti_jslots[i] = ptr; 645 ptr += TI_JLEN; 646 entry = malloc(sizeof(struct ti_jpool_entry), 647 M_DEVBUF, M_NOWAIT); 648 if (entry == NULL) { 649 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 650 sc->ti_cdata.ti_jumbo_buf = NULL; 651 printf("%s: no memory for jumbo " 652 "buffer queue!\n", sc->sc_dev.dv_xname); 653 return(ENOBUFS); 654 } 655 entry->slot = i; 656 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 657 jpool_entries); 658 } 659 660 return(0); 661 } 662 663 /* 664 * Allocate a jumbo buffer. 665 */ 666 static void *ti_jalloc(sc) 667 struct ti_softc *sc; 668 { 669 struct ti_jpool_entry *entry; 670 671 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 672 673 if (entry == NULL) { 674 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 675 return(NULL); 676 } 677 678 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 679 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 680 return(sc->ti_cdata.ti_jslots[entry->slot]); 681 } 682 683 /* 684 * Release a jumbo buffer. 685 */ 686 static void ti_jfree(m, buf, size, arg) 687 struct mbuf *m; 688 caddr_t buf; 689 size_t size; 690 void *arg; 691 { 692 struct ti_softc *sc; 693 int i, s; 694 struct ti_jpool_entry *entry; 695 696 /* Extract the softc struct pointer. */ 697 sc = (struct ti_softc *)arg; 698 699 if (sc == NULL) 700 panic("ti_jfree: didn't get softc pointer!"); 701 702 /* calculate the slot this buffer belongs to */ 703 704 i = ((caddr_t)buf 705 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 706 707 if ((i < 0) || (i >= TI_JSLOTS)) 708 panic("ti_jfree: asked to free buffer that we don't manage!"); 709 710 s = splvm(); 711 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 712 if (entry == NULL) 713 panic("ti_jfree: buffer not in use!"); 714 entry->slot = i; 715 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 716 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 717 718 if (__predict_true(m != NULL)) 719 pool_cache_put(&mbpool_cache, m); 720 splx(s); 721 } 722 723 724 /* 725 * Intialize a standard receive ring descriptor. 726 */ 727 static int ti_newbuf_std(sc, i, m, dmamap) 728 struct ti_softc *sc; 729 int i; 730 struct mbuf *m; 731 bus_dmamap_t dmamap; /* required if (m != NULL) */ 732 { 733 struct mbuf *m_new = NULL; 734 struct ti_rx_desc *r; 735 int error; 736 737 if (dmamap == NULL) { 738 /* if (m) panic() */ 739 740 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 741 MCLBYTES, 0, BUS_DMA_NOWAIT, 742 &dmamap)) != 0) { 743 printf("%s: can't create recv map, error = %d\n", 744 sc->sc_dev.dv_xname, error); 745 return(ENOMEM); 746 } 747 } 748 sc->std_dmamap[i] = dmamap; 749 750 if (m == NULL) { 751 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 752 if (m_new == NULL) { 753 printf("%s: mbuf allocation failed " 754 "-- packet dropped!\n", sc->sc_dev.dv_xname); 755 return(ENOBUFS); 756 } 757 758 MCLGET(m_new, M_DONTWAIT); 759 if (!(m_new->m_flags & M_EXT)) { 760 printf("%s: cluster allocation failed " 761 "-- packet dropped!\n", sc->sc_dev.dv_xname); 762 m_freem(m_new); 763 return(ENOBUFS); 764 } 765 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 766 m_adj(m_new, ETHER_ALIGN); 767 768 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 769 mtod(m_new, caddr_t), m_new->m_len, NULL, 770 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 771 printf("%s: can't load recv map, error = %d\n", 772 sc->sc_dev.dv_xname, error); 773 return (ENOMEM); 774 } 775 } else { 776 m_new = m; 777 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 778 m_new->m_data = m_new->m_ext.ext_buf; 779 m_adj(m_new, ETHER_ALIGN); 780 781 /* reuse the dmamap */ 782 } 783 784 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 785 r = &sc->ti_rdata->ti_rx_std_ring[i]; 786 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 787 r->ti_type = TI_BDTYPE_RECV_BD; 788 r->ti_flags = 0; 789 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 790 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 791 if (sc->ethercom.ec_if.if_capenable & 792 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 793 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 794 r->ti_len = m_new->m_len; /* == ds_len */ 795 r->ti_idx = i; 796 797 return(0); 798 } 799 800 /* 801 * Intialize a mini receive ring descriptor. This only applies to 802 * the Tigon 2. 803 */ 804 static int ti_newbuf_mini(sc, i, m, dmamap) 805 struct ti_softc *sc; 806 int i; 807 struct mbuf *m; 808 bus_dmamap_t dmamap; /* required if (m != NULL) */ 809 { 810 struct mbuf *m_new = NULL; 811 struct ti_rx_desc *r; 812 int error; 813 814 if (dmamap == NULL) { 815 /* if (m) panic() */ 816 817 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 818 MHLEN, 0, BUS_DMA_NOWAIT, 819 &dmamap)) != 0) { 820 printf("%s: can't create recv map, error = %d\n", 821 sc->sc_dev.dv_xname, error); 822 return(ENOMEM); 823 } 824 } 825 sc->mini_dmamap[i] = dmamap; 826 827 if (m == NULL) { 828 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 829 if (m_new == NULL) { 830 printf("%s: mbuf allocation failed " 831 "-- packet dropped!\n", sc->sc_dev.dv_xname); 832 return(ENOBUFS); 833 } 834 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 835 m_adj(m_new, ETHER_ALIGN); 836 837 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 838 mtod(m_new, caddr_t), m_new->m_len, NULL, 839 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 840 printf("%s: can't load recv map, error = %d\n", 841 sc->sc_dev.dv_xname, error); 842 return (ENOMEM); 843 } 844 } else { 845 m_new = m; 846 m_new->m_data = m_new->m_pktdat; 847 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 848 m_adj(m_new, ETHER_ALIGN); 849 850 /* reuse the dmamap */ 851 } 852 853 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 854 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 855 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 856 r->ti_type = TI_BDTYPE_RECV_BD; 857 r->ti_flags = TI_BDFLAG_MINI_RING; 858 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 859 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 860 if (sc->ethercom.ec_if.if_capenable & 861 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 862 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 863 r->ti_len = m_new->m_len; /* == ds_len */ 864 r->ti_idx = i; 865 866 return(0); 867 } 868 869 /* 870 * Initialize a jumbo receive ring descriptor. This allocates 871 * a jumbo buffer from the pool managed internally by the driver. 872 */ 873 static int ti_newbuf_jumbo(sc, i, m) 874 struct ti_softc *sc; 875 int i; 876 struct mbuf *m; 877 { 878 struct mbuf *m_new = NULL; 879 struct ti_rx_desc *r; 880 881 if (m == NULL) { 882 caddr_t buf = NULL; 883 884 /* Allocate the mbuf. */ 885 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 886 if (m_new == NULL) { 887 printf("%s: mbuf allocation failed " 888 "-- packet dropped!\n", sc->sc_dev.dv_xname); 889 return(ENOBUFS); 890 } 891 892 /* Allocate the jumbo buffer */ 893 buf = ti_jalloc(sc); 894 if (buf == NULL) { 895 m_freem(m_new); 896 printf("%s: jumbo allocation failed " 897 "-- packet dropped!\n", sc->sc_dev.dv_xname); 898 return(ENOBUFS); 899 } 900 901 /* Attach the buffer to the mbuf. */ 902 MEXTADD(m_new, buf, ETHER_MAX_LEN_JUMBO, 903 M_DEVBUF, ti_jfree, sc); 904 m_new->m_flags |= M_EXT_RW; 905 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 906 } else { 907 m_new = m; 908 m_new->m_data = m_new->m_ext.ext_buf; 909 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 910 } 911 912 m_adj(m_new, ETHER_ALIGN); 913 /* Set up the descriptor. */ 914 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 915 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 916 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 917 ((caddr_t)mtod(m_new, caddr_t) 918 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 919 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 920 r->ti_flags = TI_BDFLAG_JUMBO_RING; 921 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 922 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 923 if (sc->ethercom.ec_if.if_capenable & 924 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 925 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 926 r->ti_len = m_new->m_len; 927 r->ti_idx = i; 928 929 return(0); 930 } 931 932 /* 933 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 934 * that's 1MB or memory, which is a lot. For now, we fill only the first 935 * 256 ring entries and hope that our CPU is fast enough to keep up with 936 * the NIC. 937 */ 938 static int ti_init_rx_ring_std(sc) 939 struct ti_softc *sc; 940 { 941 int i; 942 struct ti_cmd_desc cmd; 943 944 for (i = 0; i < TI_SSLOTS; i++) { 945 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 946 return(ENOBUFS); 947 }; 948 949 TI_UPDATE_STDPROD(sc, i - 1); 950 sc->ti_std = i - 1; 951 952 return(0); 953 } 954 955 static void ti_free_rx_ring_std(sc) 956 struct ti_softc *sc; 957 { 958 int i; 959 960 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 961 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 962 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 963 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 964 965 /* if (sc->std_dmamap[i] == 0) panic() */ 966 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 967 sc->std_dmamap[i] = 0; 968 } 969 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 970 sizeof(struct ti_rx_desc)); 971 } 972 973 return; 974 } 975 976 static int ti_init_rx_ring_jumbo(sc) 977 struct ti_softc *sc; 978 { 979 int i; 980 struct ti_cmd_desc cmd; 981 982 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 983 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 984 return(ENOBUFS); 985 }; 986 987 TI_UPDATE_JUMBOPROD(sc, i - 1); 988 sc->ti_jumbo = i - 1; 989 990 return(0); 991 } 992 993 static void ti_free_rx_ring_jumbo(sc) 994 struct ti_softc *sc; 995 { 996 int i; 997 998 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 999 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1000 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1001 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1002 } 1003 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1004 sizeof(struct ti_rx_desc)); 1005 } 1006 1007 return; 1008 } 1009 1010 static int ti_init_rx_ring_mini(sc) 1011 struct ti_softc *sc; 1012 { 1013 int i; 1014 1015 for (i = 0; i < TI_MSLOTS; i++) { 1016 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1017 return(ENOBUFS); 1018 }; 1019 1020 TI_UPDATE_MINIPROD(sc, i - 1); 1021 sc->ti_mini = i - 1; 1022 1023 return(0); 1024 } 1025 1026 static void ti_free_rx_ring_mini(sc) 1027 struct ti_softc *sc; 1028 { 1029 int i; 1030 1031 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1032 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1033 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1034 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1035 1036 /* if (sc->mini_dmamap[i] == 0) panic() */ 1037 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1038 sc->mini_dmamap[i] = 0; 1039 } 1040 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1041 sizeof(struct ti_rx_desc)); 1042 } 1043 1044 return; 1045 } 1046 1047 static void ti_free_tx_ring(sc) 1048 struct ti_softc *sc; 1049 { 1050 int i; 1051 struct txdmamap_pool_entry *dma; 1052 1053 if (sc->ti_rdata->ti_tx_ring == NULL) 1054 return; 1055 1056 for (i = 0; i < TI_TX_RING_CNT; i++) { 1057 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1058 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1059 sc->ti_cdata.ti_tx_chain[i] = NULL; 1060 1061 /* if (sc->txdma[i] == 0) panic() */ 1062 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1063 link); 1064 sc->txdma[i] = 0; 1065 } 1066 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1067 sizeof(struct ti_tx_desc)); 1068 } 1069 1070 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1071 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1072 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1073 free(dma, M_DEVBUF); 1074 } 1075 1076 return; 1077 } 1078 1079 static int ti_init_tx_ring(sc) 1080 struct ti_softc *sc; 1081 { 1082 int i, error; 1083 bus_dmamap_t dmamap; 1084 struct txdmamap_pool_entry *dma; 1085 1086 sc->ti_txcnt = 0; 1087 sc->ti_tx_saved_considx = 0; 1088 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1089 1090 SIMPLEQ_INIT(&sc->txdma_list); 1091 for (i = 0; i < TI_RSLOTS; i++) { 1092 /* I've seen mbufs with 30 fragments. */ 1093 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1094 40, ETHER_MAX_LEN_JUMBO, 0, 1095 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1096 printf("%s: can't create tx map, error = %d\n", 1097 sc->sc_dev.dv_xname, error); 1098 return(ENOMEM); 1099 } 1100 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1101 if (!dma) { 1102 printf("%s: can't alloc txdmamap_pool_entry\n", 1103 sc->sc_dev.dv_xname); 1104 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1105 return (ENOMEM); 1106 } 1107 dma->dmamap = dmamap; 1108 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1109 } 1110 1111 return(0); 1112 } 1113 1114 /* 1115 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1116 * but we have to support the old way too so that Tigon 1 cards will 1117 * work. 1118 */ 1119 void ti_add_mcast(sc, addr) 1120 struct ti_softc *sc; 1121 struct ether_addr *addr; 1122 { 1123 struct ti_cmd_desc cmd; 1124 u_int16_t *m; 1125 u_int32_t ext[2] = {0, 0}; 1126 1127 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1128 1129 switch(sc->ti_hwrev) { 1130 case TI_HWREV_TIGON: 1131 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1132 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1133 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1134 break; 1135 case TI_HWREV_TIGON_II: 1136 ext[0] = htons(m[0]); 1137 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1138 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1139 break; 1140 default: 1141 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1142 break; 1143 } 1144 1145 return; 1146 } 1147 1148 void ti_del_mcast(sc, addr) 1149 struct ti_softc *sc; 1150 struct ether_addr *addr; 1151 { 1152 struct ti_cmd_desc cmd; 1153 u_int16_t *m; 1154 u_int32_t ext[2] = {0, 0}; 1155 1156 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1157 1158 switch(sc->ti_hwrev) { 1159 case TI_HWREV_TIGON: 1160 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1161 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1162 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1163 break; 1164 case TI_HWREV_TIGON_II: 1165 ext[0] = htons(m[0]); 1166 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1167 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1168 break; 1169 default: 1170 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1171 break; 1172 } 1173 1174 return; 1175 } 1176 1177 /* 1178 * Configure the Tigon's multicast address filter. 1179 * 1180 * The actual multicast table management is a bit of a pain, thanks to 1181 * slight brain damage on the part of both Alteon and us. With our 1182 * multicast code, we are only alerted when the multicast address table 1183 * changes and at that point we only have the current list of addresses: 1184 * we only know the current state, not the previous state, so we don't 1185 * actually know what addresses were removed or added. The firmware has 1186 * state, but we can't get our grubby mits on it, and there is no 'delete 1187 * all multicast addresses' command. Hence, we have to maintain our own 1188 * state so we know what addresses have been programmed into the NIC at 1189 * any given time. 1190 */ 1191 static void ti_setmulti(sc) 1192 struct ti_softc *sc; 1193 { 1194 struct ifnet *ifp; 1195 struct ti_cmd_desc cmd; 1196 struct ti_mc_entry *mc; 1197 u_int32_t intrs; 1198 struct ether_multi *enm; 1199 struct ether_multistep step; 1200 1201 ifp = &sc->ethercom.ec_if; 1202 1203 /* Disable interrupts. */ 1204 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1205 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1206 1207 /* First, zot all the existing filters. */ 1208 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1209 ti_del_mcast(sc, &mc->mc_addr); 1210 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1211 free(mc, M_DEVBUF); 1212 } 1213 1214 /* 1215 * Remember all multicast addresses so that we can delete them 1216 * later. Punt if there is a range of addresses or memory shortage. 1217 */ 1218 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1219 while (enm != NULL) { 1220 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1221 ETHER_ADDR_LEN) != 0) 1222 goto allmulti; 1223 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1224 M_NOWAIT)) == NULL) 1225 goto allmulti; 1226 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1227 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1228 ETHER_NEXT_MULTI(step, enm); 1229 } 1230 1231 /* Accept only programmed multicast addresses */ 1232 ifp->if_flags &= ~IFF_ALLMULTI; 1233 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1234 1235 /* Now program new ones. */ 1236 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1237 ti_add_mcast(sc, &mc->mc_addr); 1238 1239 /* Re-enable interrupts. */ 1240 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1241 1242 return; 1243 1244 allmulti: 1245 /* No need to keep individual multicast addresses */ 1246 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1247 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1248 free(mc, M_DEVBUF); 1249 } 1250 1251 /* Accept all multicast addresses */ 1252 ifp->if_flags |= IFF_ALLMULTI; 1253 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1254 1255 /* Re-enable interrupts. */ 1256 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1257 } 1258 1259 /* 1260 * Check to see if the BIOS has configured us for a 64 bit slot when 1261 * we aren't actually in one. If we detect this condition, we can work 1262 * around it on the Tigon 2 by setting a bit in the PCI state register, 1263 * but for the Tigon 1 we must give up and abort the interface attach. 1264 */ 1265 static int ti_64bitslot_war(sc) 1266 struct ti_softc *sc; 1267 { 1268 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1269 CSR_WRITE_4(sc, 0x600, 0); 1270 CSR_WRITE_4(sc, 0x604, 0); 1271 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1272 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1273 if (sc->ti_hwrev == TI_HWREV_TIGON) 1274 return(EINVAL); 1275 else { 1276 TI_SETBIT(sc, TI_PCI_STATE, 1277 TI_PCISTATE_32BIT_BUS); 1278 return(0); 1279 } 1280 } 1281 } 1282 1283 return(0); 1284 } 1285 1286 /* 1287 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1288 * self-test results. 1289 */ 1290 static int ti_chipinit(sc) 1291 struct ti_softc *sc; 1292 { 1293 u_int32_t cacheline; 1294 u_int32_t pci_writemax = 0; 1295 u_int32_t rev; 1296 1297 /* Initialize link to down state. */ 1298 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1299 1300 /* Set endianness before we access any non-PCI registers. */ 1301 #if BYTE_ORDER == BIG_ENDIAN 1302 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1303 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1304 #else 1305 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1306 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1307 #endif 1308 1309 /* Check the ROM failed bit to see if self-tests passed. */ 1310 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1311 printf("%s: board self-diagnostics failed!\n", 1312 sc->sc_dev.dv_xname); 1313 return(ENODEV); 1314 } 1315 1316 /* Halt the CPU. */ 1317 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1318 1319 /* Figure out the hardware revision. */ 1320 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1321 switch(rev) { 1322 case TI_REV_TIGON_I: 1323 sc->ti_hwrev = TI_HWREV_TIGON; 1324 break; 1325 case TI_REV_TIGON_II: 1326 sc->ti_hwrev = TI_HWREV_TIGON_II; 1327 break; 1328 default: 1329 printf("%s: unsupported chip revision 0x%x\n", 1330 sc->sc_dev.dv_xname, rev); 1331 return(ENODEV); 1332 } 1333 1334 /* Do special setup for Tigon 2. */ 1335 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1336 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1337 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1338 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1339 } 1340 1341 /* Set up the PCI state register. */ 1342 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1343 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1344 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1345 } 1346 1347 /* Clear the read/write max DMA parameters. */ 1348 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1349 TI_PCISTATE_READ_MAXDMA)); 1350 1351 /* Get cache line size. */ 1352 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1353 1354 /* 1355 * If the system has set enabled the PCI memory write 1356 * and invalidate command in the command register, set 1357 * the write max parameter accordingly. This is necessary 1358 * to use MWI with the Tigon 2. 1359 */ 1360 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1361 & PCI_COMMAND_INVALIDATE_ENABLE) { 1362 switch(cacheline) { 1363 case 1: 1364 case 4: 1365 case 8: 1366 case 16: 1367 case 32: 1368 case 64: 1369 break; 1370 default: 1371 /* Disable PCI memory write and invalidate. */ 1372 if (bootverbose) 1373 printf("%s: cache line size %d not " 1374 "supported; disabling PCI MWI\n", 1375 sc->sc_dev.dv_xname, cacheline); 1376 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1377 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1378 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1379 break; 1380 } 1381 } 1382 1383 #ifdef __brokenalpha__ 1384 /* 1385 * From the Alteon sample driver: 1386 * Must insure that we do not cross an 8K (bytes) boundary 1387 * for DMA reads. Our highest limit is 1K bytes. This is a 1388 * restriction on some ALPHA platforms with early revision 1389 * 21174 PCI chipsets, such as the AlphaPC 164lx 1390 */ 1391 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1392 #else 1393 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1394 #endif 1395 1396 /* This sets the min dma param all the way up (0xff). */ 1397 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1398 1399 /* Configure DMA variables. */ 1400 #if BYTE_ORDER == BIG_ENDIAN 1401 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1402 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1403 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1404 TI_OPMODE_DONT_FRAG_JUMBO); 1405 #else 1406 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1407 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1408 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1409 #endif 1410 1411 /* 1412 * Only allow 1 DMA channel to be active at a time. 1413 * I don't think this is a good idea, but without it 1414 * the firmware racks up lots of nicDmaReadRingFull 1415 * errors. 1416 * Incompatible with hardware assisted checksums. 1417 */ 1418 if ((sc->ethercom.ec_if.if_capenable & 1419 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1420 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1421 1422 /* Recommended settings from Tigon manual. */ 1423 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1424 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1425 1426 if (ti_64bitslot_war(sc)) { 1427 printf("%s: bios thinks we're in a 64 bit slot, " 1428 "but we aren't", sc->sc_dev.dv_xname); 1429 return(EINVAL); 1430 } 1431 1432 return(0); 1433 } 1434 1435 /* 1436 * Initialize the general information block and firmware, and 1437 * start the CPU(s) running. 1438 */ 1439 static int ti_gibinit(sc) 1440 struct ti_softc *sc; 1441 { 1442 struct ti_rcb *rcb; 1443 int i; 1444 struct ifnet *ifp; 1445 1446 ifp = &sc->ethercom.ec_if; 1447 1448 /* Disable interrupts for now. */ 1449 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1450 1451 /* Tell the chip where to find the general information block. */ 1452 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1453 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1454 1455 /* Load the firmware into SRAM. */ 1456 ti_loadfw(sc); 1457 1458 /* Set up the contents of the general info and ring control blocks. */ 1459 1460 /* Set up the event ring and producer pointer. */ 1461 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1462 1463 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1464 rcb->ti_flags = 0; 1465 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1466 TI_CDEVPRODADDR(sc); 1467 1468 sc->ti_ev_prodidx.ti_idx = 0; 1469 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1470 sc->ti_ev_saved_considx = 0; 1471 1472 /* Set up the command ring and producer mailbox. */ 1473 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1474 1475 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1476 rcb->ti_flags = 0; 1477 rcb->ti_max_len = 0; 1478 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1479 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1480 } 1481 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1482 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1483 sc->ti_cmd_saved_prodidx = 0; 1484 1485 /* 1486 * Assign the address of the stats refresh buffer. 1487 * We re-use the current stats buffer for this to 1488 * conserve memory. 1489 */ 1490 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1491 TI_CDSTATSADDR(sc); 1492 1493 /* Set up the standard receive ring. */ 1494 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1495 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1496 rcb->ti_max_len = ETHER_MAX_LEN; 1497 rcb->ti_flags = 0; 1498 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1499 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1500 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1501 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1502 if (sc->ethercom.ec_nvlans != 0) 1503 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1504 1505 /* Set up the jumbo receive ring. */ 1506 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1507 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1508 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1509 rcb->ti_flags = 0; 1510 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1511 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1512 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1513 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1514 if (sc->ethercom.ec_nvlans != 0) 1515 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1516 1517 /* 1518 * Set up the mini ring. Only activated on the 1519 * Tigon 2 but the slot in the config block is 1520 * still there on the Tigon 1. 1521 */ 1522 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1523 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1524 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1525 if (sc->ti_hwrev == TI_HWREV_TIGON) 1526 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1527 else 1528 rcb->ti_flags = 0; 1529 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1530 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1531 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1532 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1533 if (sc->ethercom.ec_nvlans != 0) 1534 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1535 1536 /* 1537 * Set up the receive return ring. 1538 */ 1539 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1540 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1541 rcb->ti_flags = 0; 1542 rcb->ti_max_len = TI_RETURN_RING_CNT; 1543 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1544 TI_CDRTNPRODADDR(sc); 1545 1546 /* 1547 * Set up the tx ring. Note: for the Tigon 2, we have the option 1548 * of putting the transmit ring in the host's address space and 1549 * letting the chip DMA it instead of leaving the ring in the NIC's 1550 * memory and accessing it through the shared memory region. We 1551 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1552 * so we have to revert to the shared memory scheme if we detect 1553 * a Tigon 1 chip. 1554 */ 1555 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1556 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1557 sc->ti_tx_ring_nic = 1558 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1559 } 1560 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1561 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1562 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1563 if (sc->ti_hwrev == TI_HWREV_TIGON) 1564 rcb->ti_flags = 0; 1565 else 1566 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1567 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1568 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1569 /* 1570 * When we get the packet, there is a pseudo-header seed already 1571 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1572 * compute the pseudo-header checksum again! 1573 */ 1574 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1575 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1576 TI_RCB_FLAG_NO_PHDR_CKSUM; 1577 if (sc->ethercom.ec_nvlans != 0) 1578 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1579 rcb->ti_max_len = TI_TX_RING_CNT; 1580 if (sc->ti_hwrev == TI_HWREV_TIGON) 1581 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1582 else 1583 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1584 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1585 TI_CDTXCONSADDR(sc); 1586 1587 /* 1588 * We're done frobbing the General Information Block. Sync 1589 * it. Note we take care of the first stats sync here, as 1590 * well. 1591 */ 1592 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1593 1594 /* Set up tuneables */ 1595 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1596 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1597 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1598 (sc->ti_rx_coal_ticks / 10)); 1599 else 1600 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1601 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1602 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1603 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1604 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1605 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1606 1607 /* Turn interrupts on. */ 1608 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1609 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1610 1611 /* Start CPU. */ 1612 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1613 1614 return(0); 1615 } 1616 1617 /* 1618 * look for id in the device list, returning the first match 1619 */ 1620 static const struct ti_type * 1621 ti_type_match(pa) 1622 struct pci_attach_args *pa; 1623 { 1624 const struct ti_type *t; 1625 1626 t = ti_devs; 1627 while(t->ti_name != NULL) { 1628 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1629 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1630 return (t); 1631 } 1632 t++; 1633 } 1634 1635 return(NULL); 1636 } 1637 1638 /* 1639 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1640 * against our list and return its name if we find a match. 1641 */ 1642 static int ti_probe(parent, match, aux) 1643 struct device *parent; 1644 struct cfdata *match; 1645 void *aux; 1646 { 1647 struct pci_attach_args *pa = aux; 1648 const struct ti_type *t; 1649 1650 t = ti_type_match(pa); 1651 1652 return((t == NULL) ? 0 : 1); 1653 } 1654 1655 static void ti_attach(parent, self, aux) 1656 struct device *parent, *self; 1657 void *aux; 1658 { 1659 u_int32_t command; 1660 struct ifnet *ifp; 1661 struct ti_softc *sc; 1662 u_char eaddr[ETHER_ADDR_LEN]; 1663 struct pci_attach_args *pa = aux; 1664 pci_chipset_tag_t pc = pa->pa_pc; 1665 pci_intr_handle_t ih; 1666 const char *intrstr = NULL; 1667 bus_dma_segment_t dmaseg; 1668 int error, dmanseg, nolinear; 1669 const struct ti_type *t; 1670 1671 t = ti_type_match(pa); 1672 if (t == NULL) { 1673 printf("ti_attach: were did the card go ?\n"); 1674 return; 1675 } 1676 1677 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1678 1679 sc = (struct ti_softc *)self; 1680 1681 /* 1682 * Map control/status registers. 1683 */ 1684 nolinear = 0; 1685 if (pci_mapreg_map(pa, 0x10, 1686 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1687 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1688 NULL, NULL)) { 1689 nolinear = 1; 1690 if (pci_mapreg_map(pa, 0x10, 1691 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1692 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1693 printf(": can't map memory space\n"); 1694 return; 1695 } 1696 } 1697 if (nolinear == 0) 1698 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1699 else 1700 sc->ti_vhandle = NULL; 1701 1702 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1703 command |= PCI_COMMAND_MASTER_ENABLE; 1704 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1705 1706 /* Allocate interrupt */ 1707 if (pci_intr_map(pa, &ih)) { 1708 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1709 return; 1710 } 1711 intrstr = pci_intr_string(pc, ih); 1712 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1713 if (sc->sc_ih == NULL) { 1714 printf("%s: couldn't establish interrupt", 1715 sc->sc_dev.dv_xname); 1716 if (intrstr != NULL) 1717 printf(" at %s", intrstr); 1718 printf("\n"); 1719 return; 1720 } 1721 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1722 /* 1723 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1724 * doing do could allow DMA to corrupt kernel memory during the 1725 * reboot before the driver initializes. 1726 */ 1727 (void) shutdownhook_establish(ti_shutdown, sc); 1728 1729 if (ti_chipinit(sc)) { 1730 printf("%s: chip initialization failed\n", self->dv_xname); 1731 goto fail2; 1732 } 1733 1734 /* 1735 * Deal with some chip diffrences. 1736 */ 1737 switch (sc->ti_hwrev) { 1738 case TI_HWREV_TIGON: 1739 sc->sc_tx_encap = ti_encap_tigon1; 1740 sc->sc_tx_eof = ti_txeof_tigon1; 1741 if (nolinear == 1) 1742 printf("%s: memory space not mapped linear\n", 1743 self->dv_xname); 1744 break; 1745 1746 case TI_HWREV_TIGON_II: 1747 sc->sc_tx_encap = ti_encap_tigon2; 1748 sc->sc_tx_eof = ti_txeof_tigon2; 1749 break; 1750 1751 default: 1752 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1753 sc->ti_hwrev); 1754 goto fail2; 1755 } 1756 1757 /* Zero out the NIC's on-board SRAM. */ 1758 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1759 1760 /* Init again -- zeroing memory may have clobbered some registers. */ 1761 if (ti_chipinit(sc)) { 1762 printf("%s: chip initialization failed\n", self->dv_xname); 1763 goto fail2; 1764 } 1765 1766 /* 1767 * Get station address from the EEPROM. Note: the manual states 1768 * that the MAC address is at offset 0x8c, however the data is 1769 * stored as two longwords (since that's how it's loaded into 1770 * the NIC). This means the MAC address is actually preceded 1771 * by two zero bytes. We need to skip over those. 1772 */ 1773 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1774 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1775 printf("%s: failed to read station address\n", self->dv_xname); 1776 goto fail2; 1777 } 1778 1779 /* 1780 * A Tigon chip was detected. Inform the world. 1781 */ 1782 printf("%s: Ethernet address: %s\n", self->dv_xname, 1783 ether_sprintf(eaddr)); 1784 1785 sc->sc_dmat = pa->pa_dmat; 1786 1787 /* Allocate the general information block and ring buffers. */ 1788 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1789 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1790 BUS_DMA_NOWAIT)) != 0) { 1791 printf("%s: can't allocate ring buffer, error = %d\n", 1792 sc->sc_dev.dv_xname, error); 1793 goto fail2; 1794 } 1795 1796 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1797 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1798 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1799 printf("%s: can't map ring buffer, error = %d\n", 1800 sc->sc_dev.dv_xname, error); 1801 goto fail2; 1802 } 1803 1804 if ((error = bus_dmamap_create(sc->sc_dmat, 1805 sizeof(struct ti_ring_data), 1, 1806 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1807 &sc->info_dmamap)) != 0) { 1808 printf("%s: can't create ring buffer DMA map, error = %d\n", 1809 sc->sc_dev.dv_xname, error); 1810 goto fail2; 1811 } 1812 1813 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1814 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1815 BUS_DMA_NOWAIT)) != 0) { 1816 printf("%s: can't load ring buffer DMA map, error = %d\n", 1817 sc->sc_dev.dv_xname, error); 1818 goto fail2; 1819 } 1820 1821 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1822 1823 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1824 1825 /* Try to allocate memory for jumbo buffers. */ 1826 if (ti_alloc_jumbo_mem(sc)) { 1827 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1828 goto fail2; 1829 } 1830 1831 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1832 1833 /* 1834 * We really need a better way to tell a 1000baseT card 1835 * from a 1000baseSX one, since in theory there could be 1836 * OEMed 1000baseT cards from lame vendors who aren't 1837 * clever enough to change the PCI ID. For the moment 1838 * though, the AceNIC is the only copper card available. 1839 */ 1840 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1841 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1842 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1843 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1844 sc->ti_copper = 1; 1845 else 1846 sc->ti_copper = 0; 1847 1848 /* Set default tuneable values. */ 1849 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1850 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1851 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1852 sc->ti_rx_max_coal_bds = 64; 1853 sc->ti_tx_max_coal_bds = 128; 1854 sc->ti_tx_buf_ratio = 21; 1855 1856 /* Set up ifnet structure */ 1857 ifp = &sc->ethercom.ec_if; 1858 ifp->if_softc = sc; 1859 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1860 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1861 ifp->if_ioctl = ti_ioctl; 1862 ifp->if_start = ti_start; 1863 ifp->if_watchdog = ti_watchdog; 1864 IFQ_SET_READY(&ifp->if_snd); 1865 1866 #if 0 1867 /* 1868 * XXX This is not really correct -- we don't necessarily 1869 * XXX want to queue up as many as we can transmit at the 1870 * XXX upper layer like that. Someone with a board should 1871 * XXX check to see how this affects performance. 1872 */ 1873 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1874 #endif 1875 1876 /* 1877 * We can support 802.1Q VLAN-sized frames. 1878 */ 1879 sc->ethercom.ec_capabilities |= 1880 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1881 1882 /* 1883 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1884 */ 1885 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1886 IFCAP_CSUM_UDPv4; 1887 1888 /* Set up ifmedia support. */ 1889 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1890 if (sc->ti_copper) { 1891 /* 1892 * Copper cards allow manual 10/100 mode selection, 1893 * but not manual 1000baseT mode selection. Why? 1894 * Because currently there's no way to specify the 1895 * master/slave setting through the firmware interface, 1896 * so Alteon decided to just bag it and handle it 1897 * via autonegotiation. 1898 */ 1899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, 1901 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1902 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1903 ifmedia_add(&sc->ifmedia, 1904 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1905 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1906 ifmedia_add(&sc->ifmedia, 1907 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1908 } else { 1909 /* Fiber cards don't support 10/100 modes. */ 1910 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1911 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1912 } 1913 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1914 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1915 1916 /* 1917 * Call MI attach routines. 1918 */ 1919 if_attach(ifp); 1920 ether_ifattach(ifp, eaddr); 1921 1922 return; 1923 fail2: 1924 pci_intr_disestablish(pc, sc->sc_ih); 1925 return; 1926 } 1927 1928 /* 1929 * Frame reception handling. This is called if there's a frame 1930 * on the receive return list. 1931 * 1932 * Note: we have to be able to handle three possibilities here: 1933 * 1) the frame is from the mini receive ring (can only happen) 1934 * on Tigon 2 boards) 1935 * 2) the frame is from the jumbo receive ring 1936 * 3) the frame is from the standard receive ring 1937 */ 1938 1939 static void ti_rxeof(sc) 1940 struct ti_softc *sc; 1941 { 1942 struct ifnet *ifp; 1943 struct ti_cmd_desc cmd; 1944 1945 ifp = &sc->ethercom.ec_if; 1946 1947 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1948 struct ti_rx_desc *cur_rx; 1949 u_int32_t rxidx; 1950 struct mbuf *m = NULL; 1951 u_int16_t vlan_tag = 0; 1952 int have_tag = 0; 1953 struct ether_header *eh; 1954 bus_dmamap_t dmamap; 1955 1956 cur_rx = 1957 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1958 rxidx = cur_rx->ti_idx; 1959 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1960 1961 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1962 have_tag = 1; 1963 /* ti_vlan_tag also has the priority, trim it */ 1964 vlan_tag = cur_rx->ti_vlan_tag & 4095; 1965 } 1966 1967 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1968 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1969 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1970 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1971 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1972 ifp->if_ierrors++; 1973 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1974 continue; 1975 } 1976 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1977 == ENOBUFS) { 1978 ifp->if_ierrors++; 1979 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1980 continue; 1981 } 1982 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1983 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1984 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1985 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1986 dmamap = sc->mini_dmamap[rxidx]; 1987 sc->mini_dmamap[rxidx] = 0; 1988 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1989 ifp->if_ierrors++; 1990 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1991 continue; 1992 } 1993 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1994 == ENOBUFS) { 1995 ifp->if_ierrors++; 1996 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1997 continue; 1998 } 1999 } else { 2000 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 2001 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 2002 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2003 dmamap = sc->std_dmamap[rxidx]; 2004 sc->std_dmamap[rxidx] = 0; 2005 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2006 ifp->if_ierrors++; 2007 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2008 continue; 2009 } 2010 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2011 == ENOBUFS) { 2012 ifp->if_ierrors++; 2013 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2014 continue; 2015 } 2016 } 2017 2018 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2019 ifp->if_ipackets++; 2020 m->m_pkthdr.rcvif = ifp; 2021 2022 #if NBPFILTER > 0 2023 /* 2024 * Handle BPF listeners. Let the BPF user see the packet, but 2025 * don't pass it up to the ether_input() layer unless it's 2026 * a broadcast packet, multicast packet, matches our ethernet 2027 * address or the interface is in promiscuous mode. 2028 */ 2029 if (ifp->if_bpf) 2030 bpf_mtap(ifp->if_bpf, m); 2031 #endif 2032 2033 eh = mtod(m, struct ether_header *); 2034 switch (ntohs(eh->ether_type)) { 2035 #ifdef INET 2036 case ETHERTYPE_IP: 2037 { 2038 struct ip *ip = (struct ip *) (eh + 1); 2039 2040 /* 2041 * Note the Tigon firmware does not invert 2042 * the checksum for us, hence the XOR. 2043 */ 2044 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2045 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2046 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2047 /* 2048 * ntohs() the constant so the compiler can 2049 * optimize... 2050 * 2051 * XXX Figure out a sane way to deal with 2052 * fragmented packets. 2053 */ 2054 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2055 switch (ip->ip_p) { 2056 case IPPROTO_TCP: 2057 m->m_pkthdr.csum_data = 2058 cur_rx->ti_tcp_udp_cksum; 2059 m->m_pkthdr.csum_flags |= 2060 M_CSUM_TCPv4|M_CSUM_DATA; 2061 break; 2062 case IPPROTO_UDP: 2063 m->m_pkthdr.csum_data = 2064 cur_rx->ti_tcp_udp_cksum; 2065 m->m_pkthdr.csum_flags |= 2066 M_CSUM_UDPv4|M_CSUM_DATA; 2067 break; 2068 default: 2069 /* Nothing */; 2070 } 2071 } 2072 break; 2073 } 2074 #endif 2075 default: 2076 /* Nothing. */ 2077 break; 2078 } 2079 2080 if (have_tag) { 2081 struct m_tag *mtag; 2082 2083 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int), 2084 M_NOWAIT); 2085 if (mtag) { 2086 *(u_int *)(mtag + 1) = vlan_tag; 2087 m_tag_prepend(m, mtag); 2088 have_tag = vlan_tag = 0; 2089 } else { 2090 printf("%s: no mbuf for tag\n", ifp->if_xname); 2091 m_freem(m); 2092 have_tag = vlan_tag = 0; 2093 continue; 2094 } 2095 } 2096 (*ifp->if_input)(ifp, m); 2097 } 2098 2099 /* Only necessary on the Tigon 1. */ 2100 if (sc->ti_hwrev == TI_HWREV_TIGON) 2101 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2102 sc->ti_rx_saved_considx); 2103 2104 TI_UPDATE_STDPROD(sc, sc->ti_std); 2105 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2106 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2107 2108 return; 2109 } 2110 2111 static void ti_txeof_tigon1(sc) 2112 struct ti_softc *sc; 2113 { 2114 struct ti_tx_desc *cur_tx = NULL; 2115 struct ifnet *ifp; 2116 struct txdmamap_pool_entry *dma; 2117 2118 ifp = &sc->ethercom.ec_if; 2119 2120 /* 2121 * Go through our tx ring and free mbufs for those 2122 * frames that have been sent. 2123 */ 2124 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2125 u_int32_t idx = 0; 2126 2127 idx = sc->ti_tx_saved_considx; 2128 if (idx > 383) 2129 CSR_WRITE_4(sc, TI_WINBASE, 2130 TI_TX_RING_BASE + 6144); 2131 else if (idx > 255) 2132 CSR_WRITE_4(sc, TI_WINBASE, 2133 TI_TX_RING_BASE + 4096); 2134 else if (idx > 127) 2135 CSR_WRITE_4(sc, TI_WINBASE, 2136 TI_TX_RING_BASE + 2048); 2137 else 2138 CSR_WRITE_4(sc, TI_WINBASE, 2139 TI_TX_RING_BASE); 2140 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2141 if (cur_tx->ti_flags & TI_BDFLAG_END) 2142 ifp->if_opackets++; 2143 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2144 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2145 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2146 2147 dma = sc->txdma[idx]; 2148 KDASSERT(dma != NULL); 2149 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2150 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2151 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2152 2153 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2154 sc->txdma[idx] = NULL; 2155 } 2156 sc->ti_txcnt--; 2157 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2158 ifp->if_timer = 0; 2159 } 2160 2161 if (cur_tx != NULL) 2162 ifp->if_flags &= ~IFF_OACTIVE; 2163 2164 return; 2165 } 2166 2167 static void ti_txeof_tigon2(sc) 2168 struct ti_softc *sc; 2169 { 2170 struct ti_tx_desc *cur_tx = NULL; 2171 struct ifnet *ifp; 2172 struct txdmamap_pool_entry *dma; 2173 int firstidx, cnt; 2174 2175 ifp = &sc->ethercom.ec_if; 2176 2177 /* 2178 * Go through our tx ring and free mbufs for those 2179 * frames that have been sent. 2180 */ 2181 firstidx = sc->ti_tx_saved_considx; 2182 cnt = 0; 2183 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2184 u_int32_t idx = 0; 2185 2186 idx = sc->ti_tx_saved_considx; 2187 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2188 if (cur_tx->ti_flags & TI_BDFLAG_END) 2189 ifp->if_opackets++; 2190 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2191 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2192 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2193 2194 dma = sc->txdma[idx]; 2195 KDASSERT(dma != NULL); 2196 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2197 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2198 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2199 2200 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2201 sc->txdma[idx] = NULL; 2202 } 2203 cnt++; 2204 sc->ti_txcnt--; 2205 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2206 ifp->if_timer = 0; 2207 } 2208 2209 if (cnt != 0) 2210 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2211 2212 if (cur_tx != NULL) 2213 ifp->if_flags &= ~IFF_OACTIVE; 2214 2215 return; 2216 } 2217 2218 static int ti_intr(xsc) 2219 void *xsc; 2220 { 2221 struct ti_softc *sc; 2222 struct ifnet *ifp; 2223 2224 sc = xsc; 2225 ifp = &sc->ethercom.ec_if; 2226 2227 #ifdef notdef 2228 /* Avoid this for now -- checking this register is expensive. */ 2229 /* Make sure this is really our interrupt. */ 2230 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2231 return (0); 2232 #endif 2233 2234 /* Ack interrupt and stop others from occuring. */ 2235 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2236 2237 if (ifp->if_flags & IFF_RUNNING) { 2238 /* Check RX return ring producer/consumer */ 2239 ti_rxeof(sc); 2240 2241 /* Check TX ring producer/consumer */ 2242 (*sc->sc_tx_eof)(sc); 2243 } 2244 2245 ti_handle_events(sc); 2246 2247 /* Re-enable interrupts. */ 2248 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2249 2250 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2251 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2252 ti_start(ifp); 2253 2254 return (1); 2255 } 2256 2257 static void ti_stats_update(sc) 2258 struct ti_softc *sc; 2259 { 2260 struct ifnet *ifp; 2261 2262 ifp = &sc->ethercom.ec_if; 2263 2264 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2265 2266 ifp->if_collisions += 2267 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2268 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2269 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2270 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2271 ifp->if_collisions; 2272 2273 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2274 } 2275 2276 /* 2277 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2278 * pointers to descriptors. 2279 */ 2280 static int ti_encap_tigon1(sc, m_head, txidx) 2281 struct ti_softc *sc; 2282 struct mbuf *m_head; 2283 u_int32_t *txidx; 2284 { 2285 struct ti_tx_desc *f = NULL; 2286 u_int32_t frag, cur, cnt = 0; 2287 struct txdmamap_pool_entry *dma; 2288 bus_dmamap_t dmamap; 2289 int error, i; 2290 struct m_tag *mtag; 2291 u_int16_t csum_flags = 0; 2292 2293 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2294 if (dma == NULL) { 2295 return ENOMEM; 2296 } 2297 dmamap = dma->dmamap; 2298 2299 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2300 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2301 if (error) { 2302 struct mbuf *m; 2303 int i = 0; 2304 for (m = m_head; m; m = m->m_next) 2305 i++; 2306 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2307 "error %d\n", m_head->m_pkthdr.len, i, error); 2308 return (ENOMEM); 2309 } 2310 2311 cur = frag = *txidx; 2312 2313 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2314 /* IP header checksum field must be 0! */ 2315 csum_flags |= TI_BDFLAG_IP_CKSUM; 2316 } 2317 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2318 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2319 2320 /* XXX fragmented packet checksum capability? */ 2321 2322 /* 2323 * Start packing the mbufs in this chain into 2324 * the fragment pointers. Stop when we run out 2325 * of fragments or hit the end of the mbuf chain. 2326 */ 2327 for (i = 0; i < dmamap->dm_nsegs; i++) { 2328 if (frag > 383) 2329 CSR_WRITE_4(sc, TI_WINBASE, 2330 TI_TX_RING_BASE + 6144); 2331 else if (frag > 255) 2332 CSR_WRITE_4(sc, TI_WINBASE, 2333 TI_TX_RING_BASE + 4096); 2334 else if (frag > 127) 2335 CSR_WRITE_4(sc, TI_WINBASE, 2336 TI_TX_RING_BASE + 2048); 2337 else 2338 CSR_WRITE_4(sc, TI_WINBASE, 2339 TI_TX_RING_BASE); 2340 f = &sc->ti_tx_ring_nic[frag % 128]; 2341 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2342 break; 2343 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2344 f->ti_len = dmamap->dm_segs[i].ds_len; 2345 f->ti_flags = csum_flags; 2346 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2347 if (mtag) { 2348 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2349 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2350 } else { 2351 f->ti_vlan_tag = 0; 2352 } 2353 /* 2354 * Sanity check: avoid coming within 16 descriptors 2355 * of the end of the ring. 2356 */ 2357 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2358 return(ENOBUFS); 2359 cur = frag; 2360 TI_INC(frag, TI_TX_RING_CNT); 2361 cnt++; 2362 } 2363 2364 if (i < dmamap->dm_nsegs) 2365 return(ENOBUFS); 2366 2367 if (frag == sc->ti_tx_saved_considx) 2368 return(ENOBUFS); 2369 2370 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2371 TI_BDFLAG_END; 2372 2373 /* Sync the packet's DMA map. */ 2374 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2375 BUS_DMASYNC_PREWRITE); 2376 2377 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2378 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2379 sc->txdma[cur] = dma; 2380 sc->ti_txcnt += cnt; 2381 2382 *txidx = frag; 2383 2384 return(0); 2385 } 2386 2387 static int ti_encap_tigon2(sc, m_head, txidx) 2388 struct ti_softc *sc; 2389 struct mbuf *m_head; 2390 u_int32_t *txidx; 2391 { 2392 struct ti_tx_desc *f = NULL; 2393 u_int32_t frag, firstfrag, cur, cnt = 0; 2394 struct txdmamap_pool_entry *dma; 2395 bus_dmamap_t dmamap; 2396 int error, i; 2397 struct m_tag *mtag; 2398 u_int16_t csum_flags = 0; 2399 2400 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2401 if (dma == NULL) { 2402 return ENOMEM; 2403 } 2404 dmamap = dma->dmamap; 2405 2406 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2407 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2408 if (error) { 2409 struct mbuf *m; 2410 int i = 0; 2411 for (m = m_head; m; m = m->m_next) 2412 i++; 2413 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2414 "error %d\n", m_head->m_pkthdr.len, i, error); 2415 return (ENOMEM); 2416 } 2417 2418 cur = firstfrag = frag = *txidx; 2419 2420 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2421 /* IP header checksum field must be 0! */ 2422 csum_flags |= TI_BDFLAG_IP_CKSUM; 2423 } 2424 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2425 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2426 2427 /* XXX fragmented packet checksum capability? */ 2428 2429 /* 2430 * Start packing the mbufs in this chain into 2431 * the fragment pointers. Stop when we run out 2432 * of fragments or hit the end of the mbuf chain. 2433 */ 2434 for (i = 0; i < dmamap->dm_nsegs; i++) { 2435 f = &sc->ti_rdata->ti_tx_ring[frag]; 2436 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2437 break; 2438 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2439 f->ti_len = dmamap->dm_segs[i].ds_len; 2440 f->ti_flags = csum_flags; 2441 mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL); 2442 if (mtag) { 2443 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2444 f->ti_vlan_tag = *(u_int *)(mtag + 1); 2445 } else { 2446 f->ti_vlan_tag = 0; 2447 } 2448 /* 2449 * Sanity check: avoid coming within 16 descriptors 2450 * of the end of the ring. 2451 */ 2452 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2453 return(ENOBUFS); 2454 cur = frag; 2455 TI_INC(frag, TI_TX_RING_CNT); 2456 cnt++; 2457 } 2458 2459 if (i < dmamap->dm_nsegs) 2460 return(ENOBUFS); 2461 2462 if (frag == sc->ti_tx_saved_considx) 2463 return(ENOBUFS); 2464 2465 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2466 2467 /* Sync the packet's DMA map. */ 2468 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2469 BUS_DMASYNC_PREWRITE); 2470 2471 /* Sync the descriptors we are using. */ 2472 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2473 2474 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2475 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2476 sc->txdma[cur] = dma; 2477 sc->ti_txcnt += cnt; 2478 2479 *txidx = frag; 2480 2481 return(0); 2482 } 2483 2484 /* 2485 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2486 * to the mbuf data regions directly in the transmit descriptors. 2487 */ 2488 static void ti_start(ifp) 2489 struct ifnet *ifp; 2490 { 2491 struct ti_softc *sc; 2492 struct mbuf *m_head = NULL; 2493 u_int32_t prodidx = 0; 2494 2495 sc = ifp->if_softc; 2496 2497 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2498 2499 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2500 IFQ_POLL(&ifp->if_snd, m_head); 2501 if (m_head == NULL) 2502 break; 2503 2504 /* 2505 * Pack the data into the transmit ring. If we 2506 * don't have room, set the OACTIVE flag and wait 2507 * for the NIC to drain the ring. 2508 */ 2509 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2510 ifp->if_flags |= IFF_OACTIVE; 2511 break; 2512 } 2513 2514 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2515 2516 /* 2517 * If there's a BPF listener, bounce a copy of this frame 2518 * to him. 2519 */ 2520 #if NBPFILTER > 0 2521 if (ifp->if_bpf) 2522 bpf_mtap(ifp->if_bpf, m_head); 2523 #endif 2524 } 2525 2526 /* Transmit */ 2527 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2528 2529 /* 2530 * Set a timeout in case the chip goes out to lunch. 2531 */ 2532 ifp->if_timer = 5; 2533 2534 return; 2535 } 2536 2537 static void ti_init(xsc) 2538 void *xsc; 2539 { 2540 struct ti_softc *sc = xsc; 2541 int s; 2542 2543 s = splnet(); 2544 2545 /* Cancel pending I/O and flush buffers. */ 2546 ti_stop(sc); 2547 2548 /* Init the gen info block, ring control blocks and firmware. */ 2549 if (ti_gibinit(sc)) { 2550 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2551 splx(s); 2552 return; 2553 } 2554 2555 splx(s); 2556 2557 return; 2558 } 2559 2560 static void ti_init2(sc) 2561 struct ti_softc *sc; 2562 { 2563 struct ti_cmd_desc cmd; 2564 struct ifnet *ifp; 2565 u_int8_t *m; 2566 struct ifmedia *ifm; 2567 int tmp; 2568 2569 ifp = &sc->ethercom.ec_if; 2570 2571 /* Specify MTU and interface index. */ 2572 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2573 2574 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2575 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2576 tmp += ETHER_VLAN_ENCAP_LEN; 2577 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2578 2579 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2580 2581 /* Load our MAC address. */ 2582 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2583 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2584 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2585 | (m[4] << 8) | m[5]); 2586 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2587 2588 /* Enable or disable promiscuous mode as needed. */ 2589 if (ifp->if_flags & IFF_PROMISC) { 2590 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2591 } else { 2592 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2593 } 2594 2595 /* Program multicast filter. */ 2596 ti_setmulti(sc); 2597 2598 /* 2599 * If this is a Tigon 1, we should tell the 2600 * firmware to use software packet filtering. 2601 */ 2602 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2603 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2604 } 2605 2606 /* Init RX ring. */ 2607 ti_init_rx_ring_std(sc); 2608 2609 /* Init jumbo RX ring. */ 2610 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2611 ti_init_rx_ring_jumbo(sc); 2612 2613 /* 2614 * If this is a Tigon 2, we can also configure the 2615 * mini ring. 2616 */ 2617 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2618 ti_init_rx_ring_mini(sc); 2619 2620 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2621 sc->ti_rx_saved_considx = 0; 2622 2623 /* Init TX ring. */ 2624 ti_init_tx_ring(sc); 2625 2626 /* Tell firmware we're alive. */ 2627 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2628 2629 /* Enable host interrupts. */ 2630 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2631 2632 ifp->if_flags |= IFF_RUNNING; 2633 ifp->if_flags &= ~IFF_OACTIVE; 2634 2635 /* 2636 * Make sure to set media properly. We have to do this 2637 * here since we have to issue commands in order to set 2638 * the link negotiation and we can't issue commands until 2639 * the firmware is running. 2640 */ 2641 ifm = &sc->ifmedia; 2642 tmp = ifm->ifm_media; 2643 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2644 ti_ifmedia_upd(ifp); 2645 ifm->ifm_media = tmp; 2646 2647 return; 2648 } 2649 2650 /* 2651 * Set media options. 2652 */ 2653 static int ti_ifmedia_upd(ifp) 2654 struct ifnet *ifp; 2655 { 2656 struct ti_softc *sc; 2657 struct ifmedia *ifm; 2658 struct ti_cmd_desc cmd; 2659 2660 sc = ifp->if_softc; 2661 ifm = &sc->ifmedia; 2662 2663 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2664 return(EINVAL); 2665 2666 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2667 case IFM_AUTO: 2668 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2669 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2670 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2671 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2672 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2673 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2674 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2675 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2676 break; 2677 case IFM_1000_SX: 2678 case IFM_1000_T: 2679 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2680 CSR_WRITE_4(sc, TI_GCR_GLINK, 2681 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2682 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2683 } else { 2684 CSR_WRITE_4(sc, TI_GCR_GLINK, 2685 TI_GLNK_PREF|TI_GLNK_1000MB| 2686 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2687 } 2688 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2689 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2690 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2691 break; 2692 case IFM_100_FX: 2693 case IFM_10_FL: 2694 case IFM_100_TX: 2695 case IFM_10_T: 2696 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2697 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2698 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2699 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2700 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2701 } else { 2702 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2703 } 2704 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2705 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2706 } else { 2707 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2708 } 2709 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2710 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2711 break; 2712 } 2713 2714 sc->ethercom.ec_if.if_baudrate = 2715 ifmedia_baudrate(ifm->ifm_media); 2716 2717 return(0); 2718 } 2719 2720 /* 2721 * Report current media status. 2722 */ 2723 static void ti_ifmedia_sts(ifp, ifmr) 2724 struct ifnet *ifp; 2725 struct ifmediareq *ifmr; 2726 { 2727 struct ti_softc *sc; 2728 u_int32_t media = 0; 2729 2730 sc = ifp->if_softc; 2731 2732 ifmr->ifm_status = IFM_AVALID; 2733 ifmr->ifm_active = IFM_ETHER; 2734 2735 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2736 return; 2737 2738 ifmr->ifm_status |= IFM_ACTIVE; 2739 2740 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2741 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2742 if (sc->ti_copper) 2743 ifmr->ifm_active |= IFM_1000_T; 2744 else 2745 ifmr->ifm_active |= IFM_1000_SX; 2746 if (media & TI_GLNK_FULL_DUPLEX) 2747 ifmr->ifm_active |= IFM_FDX; 2748 else 2749 ifmr->ifm_active |= IFM_HDX; 2750 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2751 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2752 if (sc->ti_copper) { 2753 if (media & TI_LNK_100MB) 2754 ifmr->ifm_active |= IFM_100_TX; 2755 if (media & TI_LNK_10MB) 2756 ifmr->ifm_active |= IFM_10_T; 2757 } else { 2758 if (media & TI_LNK_100MB) 2759 ifmr->ifm_active |= IFM_100_FX; 2760 if (media & TI_LNK_10MB) 2761 ifmr->ifm_active |= IFM_10_FL; 2762 } 2763 if (media & TI_LNK_FULL_DUPLEX) 2764 ifmr->ifm_active |= IFM_FDX; 2765 if (media & TI_LNK_HALF_DUPLEX) 2766 ifmr->ifm_active |= IFM_HDX; 2767 } 2768 2769 sc->ethercom.ec_if.if_baudrate = 2770 ifmedia_baudrate(sc->ifmedia.ifm_media); 2771 2772 return; 2773 } 2774 2775 static int 2776 ti_ether_ioctl(ifp, cmd, data) 2777 struct ifnet *ifp; 2778 u_long cmd; 2779 caddr_t data; 2780 { 2781 struct ifaddr *ifa = (struct ifaddr *) data; 2782 struct ti_softc *sc = ifp->if_softc; 2783 2784 if ((ifp->if_flags & IFF_UP) == 0) { 2785 ifp->if_flags |= IFF_UP; 2786 ti_init(sc); 2787 } 2788 2789 switch (cmd) { 2790 case SIOCSIFADDR: 2791 2792 switch (ifa->ifa_addr->sa_family) { 2793 #ifdef INET 2794 case AF_INET: 2795 arp_ifinit(ifp, ifa); 2796 break; 2797 #endif 2798 #ifdef NS 2799 case AF_NS: 2800 { 2801 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2802 2803 if (ns_nullhost(*ina)) 2804 ina->x_host = *(union ns_host *) 2805 LLADDR(ifp->if_sadl); 2806 else 2807 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2808 ifp->if_addrlen); 2809 break; 2810 } 2811 #endif 2812 default: 2813 break; 2814 } 2815 break; 2816 2817 default: 2818 return (EINVAL); 2819 } 2820 2821 return (0); 2822 } 2823 2824 static int ti_ioctl(ifp, command, data) 2825 struct ifnet *ifp; 2826 u_long command; 2827 caddr_t data; 2828 { 2829 struct ti_softc *sc = ifp->if_softc; 2830 struct ifreq *ifr = (struct ifreq *) data; 2831 int s, error = 0; 2832 struct ti_cmd_desc cmd; 2833 2834 s = splnet(); 2835 2836 switch(command) { 2837 case SIOCSIFADDR: 2838 case SIOCGIFADDR: 2839 error = ti_ether_ioctl(ifp, command, data); 2840 break; 2841 case SIOCSIFMTU: 2842 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2843 error = EINVAL; 2844 else { 2845 ifp->if_mtu = ifr->ifr_mtu; 2846 ti_init(sc); 2847 } 2848 break; 2849 case SIOCSIFFLAGS: 2850 if (ifp->if_flags & IFF_UP) { 2851 /* 2852 * If only the state of the PROMISC flag changed, 2853 * then just use the 'set promisc mode' command 2854 * instead of reinitializing the entire NIC. Doing 2855 * a full re-init means reloading the firmware and 2856 * waiting for it to start up, which may take a 2857 * second or two. 2858 */ 2859 if (ifp->if_flags & IFF_RUNNING && 2860 ifp->if_flags & IFF_PROMISC && 2861 !(sc->ti_if_flags & IFF_PROMISC)) { 2862 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2863 TI_CMD_CODE_PROMISC_ENB, 0); 2864 } else if (ifp->if_flags & IFF_RUNNING && 2865 !(ifp->if_flags & IFF_PROMISC) && 2866 sc->ti_if_flags & IFF_PROMISC) { 2867 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2868 TI_CMD_CODE_PROMISC_DIS, 0); 2869 } else 2870 ti_init(sc); 2871 } else { 2872 if (ifp->if_flags & IFF_RUNNING) { 2873 ti_stop(sc); 2874 } 2875 } 2876 sc->ti_if_flags = ifp->if_flags; 2877 error = 0; 2878 break; 2879 case SIOCADDMULTI: 2880 case SIOCDELMULTI: 2881 error = (command == SIOCADDMULTI) ? 2882 ether_addmulti(ifr, &sc->ethercom) : 2883 ether_delmulti(ifr, &sc->ethercom); 2884 if (error == ENETRESET) { 2885 if (ifp->if_flags & IFF_RUNNING) 2886 ti_setmulti(sc); 2887 error = 0; 2888 } 2889 break; 2890 case SIOCSIFMEDIA: 2891 case SIOCGIFMEDIA: 2892 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2893 break; 2894 default: 2895 error = EINVAL; 2896 break; 2897 } 2898 2899 (void)splx(s); 2900 2901 return(error); 2902 } 2903 2904 static void ti_watchdog(ifp) 2905 struct ifnet *ifp; 2906 { 2907 struct ti_softc *sc; 2908 2909 sc = ifp->if_softc; 2910 2911 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2912 ti_stop(sc); 2913 ti_init(sc); 2914 2915 ifp->if_oerrors++; 2916 2917 return; 2918 } 2919 2920 /* 2921 * Stop the adapter and free any mbufs allocated to the 2922 * RX and TX lists. 2923 */ 2924 static void ti_stop(sc) 2925 struct ti_softc *sc; 2926 { 2927 struct ifnet *ifp; 2928 struct ti_cmd_desc cmd; 2929 2930 ifp = &sc->ethercom.ec_if; 2931 2932 /* Disable host interrupts. */ 2933 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2934 /* 2935 * Tell firmware we're shutting down. 2936 */ 2937 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2938 2939 /* Halt and reinitialize. */ 2940 ti_chipinit(sc); 2941 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2942 ti_chipinit(sc); 2943 2944 /* Free the RX lists. */ 2945 ti_free_rx_ring_std(sc); 2946 2947 /* Free jumbo RX list. */ 2948 ti_free_rx_ring_jumbo(sc); 2949 2950 /* Free mini RX list. */ 2951 ti_free_rx_ring_mini(sc); 2952 2953 /* Free TX buffers. */ 2954 ti_free_tx_ring(sc); 2955 2956 sc->ti_ev_prodidx.ti_idx = 0; 2957 sc->ti_return_prodidx.ti_idx = 0; 2958 sc->ti_tx_considx.ti_idx = 0; 2959 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2960 2961 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2962 2963 return; 2964 } 2965 2966 /* 2967 * Stop all chip I/O so that the kernel's probe routines don't 2968 * get confused by errant DMAs when rebooting. 2969 */ 2970 static void ti_shutdown(v) 2971 void *v; 2972 { 2973 struct ti_softc *sc = v; 2974 2975 ti_chipinit(sc); 2976 2977 return; 2978 } 2979
Indexes created Fri Sep 26 20:09:58 GMT 2025