if_ti.c revision 1.70
1 /* $NetBSD: if_ti.c,v 1.70 2006/03/28 17:38:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.70 2006/03/28 17:38:34 thorpej Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match(struct pci_attach_args *); 157 static int ti_probe(struct device *, struct cfdata *, void *); 158 static void ti_attach(struct device *, struct device *, void *); 159 static void ti_shutdown(void *); 160 static void ti_txeof_tigon1(struct ti_softc *); 161 static void ti_txeof_tigon2(struct ti_softc *); 162 static void ti_rxeof(struct ti_softc *); 163 164 static void ti_stats_update(struct ti_softc *); 165 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 166 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 167 168 static int ti_intr(void *); 169 static void ti_start(struct ifnet *); 170 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 171 static void ti_init(void *); 172 static void ti_init2(struct ti_softc *); 173 static void ti_stop(struct ti_softc *); 174 static void ti_watchdog(struct ifnet *); 175 static int ti_ifmedia_upd(struct ifnet *); 176 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 179 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 180 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 181 182 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 183 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 184 static void ti_setmulti(struct ti_softc *); 185 186 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 187 static void ti_loadfw(struct ti_softc *); 188 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 189 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 190 static void ti_handle_events(struct ti_softc *); 191 static int ti_alloc_jumbo_mem(struct ti_softc *); 192 static void *ti_jalloc(struct ti_softc *); 193 static void ti_jfree(struct mbuf *, caddr_t, size_t, void *); 194 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 195 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 196 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 197 static int ti_init_rx_ring_std(struct ti_softc *); 198 static void ti_free_rx_ring_std(struct ti_softc *); 199 static int ti_init_rx_ring_jumbo(struct ti_softc *); 200 static void ti_free_rx_ring_jumbo(struct ti_softc *); 201 static int ti_init_rx_ring_mini(struct ti_softc *); 202 static void ti_free_rx_ring_mini(struct ti_softc *); 203 static void ti_free_tx_ring(struct ti_softc *); 204 static int ti_init_tx_ring(struct ti_softc *); 205 206 static int ti_64bitslot_war(struct ti_softc *); 207 static int ti_chipinit(struct ti_softc *); 208 static int ti_gibinit(struct ti_softc *); 209 210 static int ti_ether_ioctl(struct ifnet *, u_long, caddr_t); 211 212 CFATTACH_DECL(ti, sizeof(struct ti_softc), 213 ti_probe, ti_attach, NULL, NULL); 214 215 /* 216 * Send an instruction or address to the EEPROM, check for ACK. 217 */ 218 static u_int32_t ti_eeprom_putbyte(sc, byte) 219 struct ti_softc *sc; 220 int byte; 221 { 222 int i, ack = 0; 223 224 /* 225 * Make sure we're in TX mode. 226 */ 227 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 228 229 /* 230 * Feed in each bit and stobe the clock. 231 */ 232 for (i = 0x80; i; i >>= 1) { 233 if (byte & i) { 234 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 235 } else { 236 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 237 } 238 DELAY(1); 239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 240 DELAY(1); 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 242 } 243 244 /* 245 * Turn off TX mode. 246 */ 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 248 249 /* 250 * Check for ack. 251 */ 252 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 253 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 254 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 255 256 return(ack); 257 } 258 259 /* 260 * Read a byte of data stored in the EEPROM at address 'addr.' 261 * We have to send two address bytes since the EEPROM can hold 262 * more than 256 bytes of data. 263 */ 264 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 265 struct ti_softc *sc; 266 int addr; 267 u_int8_t *dest; 268 { 269 int i; 270 u_int8_t byte = 0; 271 272 EEPROM_START; 273 274 /* 275 * Send write control code to EEPROM. 276 */ 277 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 278 printf("%s: failed to send write command, status: %x\n", 279 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 280 return(1); 281 } 282 283 /* 284 * Send first byte of address of byte we want to read. 285 */ 286 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 287 printf("%s: failed to send address, status: %x\n", 288 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return(1); 290 } 291 /* 292 * Send second byte address of byte we want to read. 293 */ 294 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 295 printf("%s: failed to send address, status: %x\n", 296 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return(1); 298 } 299 300 EEPROM_STOP; 301 EEPROM_START; 302 /* 303 * Send read control code to EEPROM. 304 */ 305 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 306 printf("%s: failed to send read command, status: %x\n", 307 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 308 return(1); 309 } 310 311 /* 312 * Start reading bits from EEPROM. 313 */ 314 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 315 for (i = 0x80; i; i >>= 1) { 316 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 317 DELAY(1); 318 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 319 byte |= i; 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 321 DELAY(1); 322 } 323 324 EEPROM_STOP; 325 326 /* 327 * No ACK generated for read, so just return byte. 328 */ 329 330 *dest = byte; 331 332 return(0); 333 } 334 335 /* 336 * Read a sequence of bytes from the EEPROM. 337 */ 338 static int ti_read_eeprom(sc, dest, off, cnt) 339 struct ti_softc *sc; 340 caddr_t dest; 341 int off; 342 int cnt; 343 { 344 int err = 0, i; 345 u_int8_t byte = 0; 346 347 for (i = 0; i < cnt; i++) { 348 err = ti_eeprom_getbyte(sc, off + i, &byte); 349 if (err) 350 break; 351 *(dest + i) = byte; 352 } 353 354 return(err ? 1 : 0); 355 } 356 357 /* 358 * NIC memory access function. Can be used to either clear a section 359 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 360 */ 361 static void ti_mem(sc, addr, len, xbuf) 362 struct ti_softc *sc; 363 u_int32_t addr, len; 364 const void *xbuf; 365 { 366 int segptr, segsize, cnt; 367 const void *ptr; 368 369 segptr = addr; 370 cnt = len; 371 ptr = xbuf; 372 373 while(cnt) { 374 if (cnt < TI_WINLEN) 375 segsize = cnt; 376 else 377 segsize = TI_WINLEN - (segptr % TI_WINLEN); 378 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 379 if (xbuf == NULL) { 380 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 381 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 382 segsize / 4); 383 } else { 384 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 385 bus_space_write_region_stream_4(sc->ti_btag, 386 sc->ti_bhandle, 387 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 388 (const u_int32_t *)ptr, segsize / 4); 389 #else 390 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 391 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 392 (const u_int32_t *)ptr, segsize / 4); 393 #endif 394 ptr = (const char *)ptr + segsize; 395 } 396 segptr += segsize; 397 cnt -= segsize; 398 } 399 400 return; 401 } 402 403 /* 404 * Load firmware image into the NIC. Check that the firmware revision 405 * is acceptable and see if we want the firmware for the Tigon 1 or 406 * Tigon 2. 407 */ 408 static void ti_loadfw(sc) 409 struct ti_softc *sc; 410 { 411 switch(sc->ti_hwrev) { 412 case TI_HWREV_TIGON: 413 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 414 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 415 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 416 printf("%s: firmware revision mismatch; want " 417 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 418 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 419 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 420 tigonFwReleaseMinor, tigonFwReleaseFix); 421 return; 422 } 423 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 424 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 426 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 427 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 428 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 429 break; 430 case TI_HWREV_TIGON_II: 431 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 432 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 433 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 434 printf("%s: firmware revision mismatch; want " 435 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 436 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 437 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 438 tigon2FwReleaseMinor, tigon2FwReleaseFix); 439 return; 440 } 441 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 442 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 443 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 444 tigon2FwRodata); 445 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 446 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 447 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 448 break; 449 default: 450 printf("%s: can't load firmware: unknown hardware rev\n", 451 sc->sc_dev.dv_xname); 452 break; 453 } 454 455 return; 456 } 457 458 /* 459 * Send the NIC a command via the command ring. 460 */ 461 static void ti_cmd(sc, cmd) 462 struct ti_softc *sc; 463 struct ti_cmd_desc *cmd; 464 { 465 u_int32_t index; 466 467 index = sc->ti_cmd_saved_prodidx; 468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 469 TI_INC(index, TI_CMD_RING_CNT); 470 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 471 sc->ti_cmd_saved_prodidx = index; 472 473 return; 474 } 475 476 /* 477 * Send the NIC an extended command. The 'len' parameter specifies the 478 * number of command slots to include after the initial command. 479 */ 480 static void ti_cmd_ext(sc, cmd, arg, len) 481 struct ti_softc *sc; 482 struct ti_cmd_desc *cmd; 483 caddr_t arg; 484 int len; 485 { 486 u_int32_t index; 487 int i; 488 489 index = sc->ti_cmd_saved_prodidx; 490 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 491 TI_INC(index, TI_CMD_RING_CNT); 492 for (i = 0; i < len; i++) { 493 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 494 *(u_int32_t *)(&arg[i * 4])); 495 TI_INC(index, TI_CMD_RING_CNT); 496 } 497 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 498 sc->ti_cmd_saved_prodidx = index; 499 500 return; 501 } 502 503 /* 504 * Handle events that have triggered interrupts. 505 */ 506 static void ti_handle_events(sc) 507 struct ti_softc *sc; 508 { 509 struct ti_event_desc *e; 510 511 if (sc->ti_rdata->ti_event_ring == NULL) 512 return; 513 514 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 515 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 516 switch(e->ti_event) { 517 case TI_EV_LINKSTAT_CHANGED: 518 sc->ti_linkstat = e->ti_code; 519 if (e->ti_code == TI_EV_CODE_LINK_UP) 520 printf("%s: 10/100 link up\n", 521 sc->sc_dev.dv_xname); 522 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 523 printf("%s: gigabit link up\n", 524 sc->sc_dev.dv_xname); 525 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 526 printf("%s: link down\n", 527 sc->sc_dev.dv_xname); 528 break; 529 case TI_EV_ERROR: 530 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 531 printf("%s: invalid command\n", 532 sc->sc_dev.dv_xname); 533 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 534 printf("%s: unknown command\n", 535 sc->sc_dev.dv_xname); 536 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 537 printf("%s: bad config data\n", 538 sc->sc_dev.dv_xname); 539 break; 540 case TI_EV_FIRMWARE_UP: 541 ti_init2(sc); 542 break; 543 case TI_EV_STATS_UPDATED: 544 ti_stats_update(sc); 545 break; 546 case TI_EV_RESET_JUMBO_RING: 547 case TI_EV_MCAST_UPDATED: 548 /* Who cares. */ 549 break; 550 default: 551 printf("%s: unknown event: %d\n", 552 sc->sc_dev.dv_xname, e->ti_event); 553 break; 554 } 555 /* Advance the consumer index. */ 556 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 557 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 558 } 559 560 return; 561 } 562 563 /* 564 * Memory management for the jumbo receive ring is a pain in the 565 * butt. We need to allocate at least 9018 bytes of space per frame, 566 * _and_ it has to be contiguous (unless you use the extended 567 * jumbo descriptor format). Using malloc() all the time won't 568 * work: malloc() allocates memory in powers of two, which means we 569 * would end up wasting a considerable amount of space by allocating 570 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 571 * to do our own memory management. 572 * 573 * The driver needs to allocate a contiguous chunk of memory at boot 574 * time. We then chop this up ourselves into 9K pieces and use them 575 * as external mbuf storage. 576 * 577 * One issue here is how much memory to allocate. The jumbo ring has 578 * 256 slots in it, but at 9K per slot than can consume over 2MB of 579 * RAM. This is a bit much, especially considering we also need 580 * RAM for the standard ring and mini ring (on the Tigon 2). To 581 * save space, we only actually allocate enough memory for 64 slots 582 * by default, which works out to between 500 and 600K. This can 583 * be tuned by changing a #define in if_tireg.h. 584 */ 585 586 static int ti_alloc_jumbo_mem(sc) 587 struct ti_softc *sc; 588 { 589 caddr_t ptr; 590 int i; 591 struct ti_jpool_entry *entry; 592 bus_dma_segment_t dmaseg; 593 int error, dmanseg; 594 595 /* Grab a big chunk o' storage. */ 596 if ((error = bus_dmamem_alloc(sc->sc_dmat, 597 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 598 BUS_DMA_NOWAIT)) != 0) { 599 printf("%s: can't allocate jumbo buffer, error = %d\n", 600 sc->sc_dev.dv_xname, error); 601 return (error); 602 } 603 604 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 605 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 606 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 607 printf("%s: can't map jumbo buffer, error = %d\n", 608 sc->sc_dev.dv_xname, error); 609 return (error); 610 } 611 612 if ((error = bus_dmamap_create(sc->sc_dmat, 613 TI_JMEM, 1, 614 TI_JMEM, 0, BUS_DMA_NOWAIT, 615 &sc->jumbo_dmamap)) != 0) { 616 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 617 sc->sc_dev.dv_xname, error); 618 return (error); 619 } 620 621 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 622 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 623 BUS_DMA_NOWAIT)) != 0) { 624 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 625 sc->sc_dev.dv_xname, error); 626 return (error); 627 } 628 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 629 630 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 631 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 632 633 /* 634 * Now divide it up into 9K pieces and save the addresses 635 * in an array. 636 */ 637 ptr = sc->ti_cdata.ti_jumbo_buf; 638 for (i = 0; i < TI_JSLOTS; i++) { 639 sc->ti_cdata.ti_jslots[i] = ptr; 640 ptr += TI_JLEN; 641 entry = malloc(sizeof(struct ti_jpool_entry), 642 M_DEVBUF, M_NOWAIT); 643 if (entry == NULL) { 644 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 645 sc->ti_cdata.ti_jumbo_buf = NULL; 646 printf("%s: no memory for jumbo " 647 "buffer queue!\n", sc->sc_dev.dv_xname); 648 return(ENOBUFS); 649 } 650 entry->slot = i; 651 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 652 jpool_entries); 653 } 654 655 return(0); 656 } 657 658 /* 659 * Allocate a jumbo buffer. 660 */ 661 static void *ti_jalloc(sc) 662 struct ti_softc *sc; 663 { 664 struct ti_jpool_entry *entry; 665 666 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 667 668 if (entry == NULL) { 669 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 670 return(NULL); 671 } 672 673 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 674 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 675 return(sc->ti_cdata.ti_jslots[entry->slot]); 676 } 677 678 /* 679 * Release a jumbo buffer. 680 */ 681 static void ti_jfree(m, tbuf, size, arg) 682 struct mbuf *m; 683 caddr_t tbuf; 684 size_t size; 685 void *arg; 686 { 687 struct ti_softc *sc; 688 int i, s; 689 struct ti_jpool_entry *entry; 690 691 /* Extract the softc struct pointer. */ 692 sc = (struct ti_softc *)arg; 693 694 if (sc == NULL) 695 panic("ti_jfree: didn't get softc pointer!"); 696 697 /* calculate the slot this buffer belongs to */ 698 699 i = ((caddr_t)tbuf 700 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 701 702 if ((i < 0) || (i >= TI_JSLOTS)) 703 panic("ti_jfree: asked to free buffer that we don't manage!"); 704 705 s = splvm(); 706 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 707 if (entry == NULL) 708 panic("ti_jfree: buffer not in use!"); 709 entry->slot = i; 710 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 711 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 712 713 if (__predict_true(m != NULL)) 714 pool_cache_put(&mbpool_cache, m); 715 splx(s); 716 } 717 718 719 /* 720 * Intialize a standard receive ring descriptor. 721 */ 722 static int ti_newbuf_std(sc, i, m, dmamap) 723 struct ti_softc *sc; 724 int i; 725 struct mbuf *m; 726 bus_dmamap_t dmamap; /* required if (m != NULL) */ 727 { 728 struct mbuf *m_new = NULL; 729 struct ti_rx_desc *r; 730 int error; 731 732 if (dmamap == NULL) { 733 /* if (m) panic() */ 734 735 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 736 MCLBYTES, 0, BUS_DMA_NOWAIT, 737 &dmamap)) != 0) { 738 printf("%s: can't create recv map, error = %d\n", 739 sc->sc_dev.dv_xname, error); 740 return(ENOMEM); 741 } 742 } 743 sc->std_dmamap[i] = dmamap; 744 745 if (m == NULL) { 746 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 747 if (m_new == NULL) { 748 printf("%s: mbuf allocation failed " 749 "-- packet dropped!\n", sc->sc_dev.dv_xname); 750 return(ENOBUFS); 751 } 752 753 MCLGET(m_new, M_DONTWAIT); 754 if (!(m_new->m_flags & M_EXT)) { 755 printf("%s: cluster allocation failed " 756 "-- packet dropped!\n", sc->sc_dev.dv_xname); 757 m_freem(m_new); 758 return(ENOBUFS); 759 } 760 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 761 m_adj(m_new, ETHER_ALIGN); 762 763 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 764 mtod(m_new, caddr_t), m_new->m_len, NULL, 765 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 766 printf("%s: can't load recv map, error = %d\n", 767 sc->sc_dev.dv_xname, error); 768 return (ENOMEM); 769 } 770 } else { 771 m_new = m; 772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 773 m_new->m_data = m_new->m_ext.ext_buf; 774 m_adj(m_new, ETHER_ALIGN); 775 776 /* reuse the dmamap */ 777 } 778 779 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 780 r = &sc->ti_rdata->ti_rx_std_ring[i]; 781 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 782 r->ti_type = TI_BDTYPE_RECV_BD; 783 r->ti_flags = 0; 784 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 785 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 786 if (sc->ethercom.ec_if.if_capenable & 787 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 788 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 789 r->ti_len = m_new->m_len; /* == ds_len */ 790 r->ti_idx = i; 791 792 return(0); 793 } 794 795 /* 796 * Intialize a mini receive ring descriptor. This only applies to 797 * the Tigon 2. 798 */ 799 static int ti_newbuf_mini(sc, i, m, dmamap) 800 struct ti_softc *sc; 801 int i; 802 struct mbuf *m; 803 bus_dmamap_t dmamap; /* required if (m != NULL) */ 804 { 805 struct mbuf *m_new = NULL; 806 struct ti_rx_desc *r; 807 int error; 808 809 if (dmamap == NULL) { 810 /* if (m) panic() */ 811 812 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 813 MHLEN, 0, BUS_DMA_NOWAIT, 814 &dmamap)) != 0) { 815 printf("%s: can't create recv map, error = %d\n", 816 sc->sc_dev.dv_xname, error); 817 return(ENOMEM); 818 } 819 } 820 sc->mini_dmamap[i] = dmamap; 821 822 if (m == NULL) { 823 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 824 if (m_new == NULL) { 825 printf("%s: mbuf allocation failed " 826 "-- packet dropped!\n", sc->sc_dev.dv_xname); 827 return(ENOBUFS); 828 } 829 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 830 m_adj(m_new, ETHER_ALIGN); 831 832 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 833 mtod(m_new, caddr_t), m_new->m_len, NULL, 834 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 835 printf("%s: can't load recv map, error = %d\n", 836 sc->sc_dev.dv_xname, error); 837 return (ENOMEM); 838 } 839 } else { 840 m_new = m; 841 m_new->m_data = m_new->m_pktdat; 842 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 843 m_adj(m_new, ETHER_ALIGN); 844 845 /* reuse the dmamap */ 846 } 847 848 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 849 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 850 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 851 r->ti_type = TI_BDTYPE_RECV_BD; 852 r->ti_flags = TI_BDFLAG_MINI_RING; 853 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 854 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 855 if (sc->ethercom.ec_if.if_capenable & 856 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 857 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 858 r->ti_len = m_new->m_len; /* == ds_len */ 859 r->ti_idx = i; 860 861 return(0); 862 } 863 864 /* 865 * Initialize a jumbo receive ring descriptor. This allocates 866 * a jumbo buffer from the pool managed internally by the driver. 867 */ 868 static int ti_newbuf_jumbo(sc, i, m) 869 struct ti_softc *sc; 870 int i; 871 struct mbuf *m; 872 { 873 struct mbuf *m_new = NULL; 874 struct ti_rx_desc *r; 875 876 if (m == NULL) { 877 caddr_t tbuf = NULL; 878 879 /* Allocate the mbuf. */ 880 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 881 if (m_new == NULL) { 882 printf("%s: mbuf allocation failed " 883 "-- packet dropped!\n", sc->sc_dev.dv_xname); 884 return(ENOBUFS); 885 } 886 887 /* Allocate the jumbo buffer */ 888 tbuf = ti_jalloc(sc); 889 if (tbuf == NULL) { 890 m_freem(m_new); 891 printf("%s: jumbo allocation failed " 892 "-- packet dropped!\n", sc->sc_dev.dv_xname); 893 return(ENOBUFS); 894 } 895 896 /* Attach the buffer to the mbuf. */ 897 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 898 M_DEVBUF, ti_jfree, sc); 899 m_new->m_flags |= M_EXT_RW; 900 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 901 } else { 902 m_new = m; 903 m_new->m_data = m_new->m_ext.ext_buf; 904 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 905 } 906 907 m_adj(m_new, ETHER_ALIGN); 908 /* Set up the descriptor. */ 909 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 910 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 911 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 912 ((caddr_t)mtod(m_new, caddr_t) 913 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 914 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 915 r->ti_flags = TI_BDFLAG_JUMBO_RING; 916 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 917 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 918 if (sc->ethercom.ec_if.if_capenable & 919 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 920 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 921 r->ti_len = m_new->m_len; 922 r->ti_idx = i; 923 924 return(0); 925 } 926 927 /* 928 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 929 * that's 1MB or memory, which is a lot. For now, we fill only the first 930 * 256 ring entries and hope that our CPU is fast enough to keep up with 931 * the NIC. 932 */ 933 static int ti_init_rx_ring_std(sc) 934 struct ti_softc *sc; 935 { 936 int i; 937 struct ti_cmd_desc cmd; 938 939 for (i = 0; i < TI_SSLOTS; i++) { 940 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 941 return(ENOBUFS); 942 }; 943 944 TI_UPDATE_STDPROD(sc, i - 1); 945 sc->ti_std = i - 1; 946 947 return(0); 948 } 949 950 static void ti_free_rx_ring_std(sc) 951 struct ti_softc *sc; 952 { 953 int i; 954 955 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 956 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 957 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 958 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 959 960 /* if (sc->std_dmamap[i] == 0) panic() */ 961 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 962 sc->std_dmamap[i] = 0; 963 } 964 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 965 sizeof(struct ti_rx_desc)); 966 } 967 968 return; 969 } 970 971 static int ti_init_rx_ring_jumbo(sc) 972 struct ti_softc *sc; 973 { 974 int i; 975 struct ti_cmd_desc cmd; 976 977 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 978 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 979 return(ENOBUFS); 980 }; 981 982 TI_UPDATE_JUMBOPROD(sc, i - 1); 983 sc->ti_jumbo = i - 1; 984 985 return(0); 986 } 987 988 static void ti_free_rx_ring_jumbo(sc) 989 struct ti_softc *sc; 990 { 991 int i; 992 993 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 994 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 995 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 996 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 997 } 998 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 999 sizeof(struct ti_rx_desc)); 1000 } 1001 1002 return; 1003 } 1004 1005 static int ti_init_rx_ring_mini(sc) 1006 struct ti_softc *sc; 1007 { 1008 int i; 1009 1010 for (i = 0; i < TI_MSLOTS; i++) { 1011 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1012 return(ENOBUFS); 1013 }; 1014 1015 TI_UPDATE_MINIPROD(sc, i - 1); 1016 sc->ti_mini = i - 1; 1017 1018 return(0); 1019 } 1020 1021 static void ti_free_rx_ring_mini(sc) 1022 struct ti_softc *sc; 1023 { 1024 int i; 1025 1026 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1027 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1028 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1029 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1030 1031 /* if (sc->mini_dmamap[i] == 0) panic() */ 1032 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1033 sc->mini_dmamap[i] = 0; 1034 } 1035 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1036 sizeof(struct ti_rx_desc)); 1037 } 1038 1039 return; 1040 } 1041 1042 static void ti_free_tx_ring(sc) 1043 struct ti_softc *sc; 1044 { 1045 int i; 1046 struct txdmamap_pool_entry *dma; 1047 1048 if (sc->ti_rdata->ti_tx_ring == NULL) 1049 return; 1050 1051 for (i = 0; i < TI_TX_RING_CNT; i++) { 1052 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1053 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1054 sc->ti_cdata.ti_tx_chain[i] = NULL; 1055 1056 /* if (sc->txdma[i] == 0) panic() */ 1057 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1058 link); 1059 sc->txdma[i] = 0; 1060 } 1061 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1062 sizeof(struct ti_tx_desc)); 1063 } 1064 1065 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1066 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1067 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1068 free(dma, M_DEVBUF); 1069 } 1070 1071 return; 1072 } 1073 1074 static int ti_init_tx_ring(sc) 1075 struct ti_softc *sc; 1076 { 1077 int i, error; 1078 bus_dmamap_t dmamap; 1079 struct txdmamap_pool_entry *dma; 1080 1081 sc->ti_txcnt = 0; 1082 sc->ti_tx_saved_considx = 0; 1083 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1084 1085 SIMPLEQ_INIT(&sc->txdma_list); 1086 for (i = 0; i < TI_RSLOTS; i++) { 1087 /* I've seen mbufs with 30 fragments. */ 1088 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1089 40, ETHER_MAX_LEN_JUMBO, 0, 1090 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1091 printf("%s: can't create tx map, error = %d\n", 1092 sc->sc_dev.dv_xname, error); 1093 return(ENOMEM); 1094 } 1095 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1096 if (!dma) { 1097 printf("%s: can't alloc txdmamap_pool_entry\n", 1098 sc->sc_dev.dv_xname); 1099 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1100 return (ENOMEM); 1101 } 1102 dma->dmamap = dmamap; 1103 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1104 } 1105 1106 return(0); 1107 } 1108 1109 /* 1110 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1111 * but we have to support the old way too so that Tigon 1 cards will 1112 * work. 1113 */ 1114 void ti_add_mcast(sc, addr) 1115 struct ti_softc *sc; 1116 struct ether_addr *addr; 1117 { 1118 struct ti_cmd_desc cmd; 1119 u_int16_t *m; 1120 u_int32_t ext[2] = {0, 0}; 1121 1122 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1123 1124 switch(sc->ti_hwrev) { 1125 case TI_HWREV_TIGON: 1126 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1127 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1128 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1129 break; 1130 case TI_HWREV_TIGON_II: 1131 ext[0] = htons(m[0]); 1132 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1133 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1134 break; 1135 default: 1136 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1137 break; 1138 } 1139 1140 return; 1141 } 1142 1143 void ti_del_mcast(sc, addr) 1144 struct ti_softc *sc; 1145 struct ether_addr *addr; 1146 { 1147 struct ti_cmd_desc cmd; 1148 u_int16_t *m; 1149 u_int32_t ext[2] = {0, 0}; 1150 1151 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1152 1153 switch(sc->ti_hwrev) { 1154 case TI_HWREV_TIGON: 1155 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1156 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1157 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1158 break; 1159 case TI_HWREV_TIGON_II: 1160 ext[0] = htons(m[0]); 1161 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1162 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1163 break; 1164 default: 1165 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1166 break; 1167 } 1168 1169 return; 1170 } 1171 1172 /* 1173 * Configure the Tigon's multicast address filter. 1174 * 1175 * The actual multicast table management is a bit of a pain, thanks to 1176 * slight brain damage on the part of both Alteon and us. With our 1177 * multicast code, we are only alerted when the multicast address table 1178 * changes and at that point we only have the current list of addresses: 1179 * we only know the current state, not the previous state, so we don't 1180 * actually know what addresses were removed or added. The firmware has 1181 * state, but we can't get our grubby mits on it, and there is no 'delete 1182 * all multicast addresses' command. Hence, we have to maintain our own 1183 * state so we know what addresses have been programmed into the NIC at 1184 * any given time. 1185 */ 1186 static void ti_setmulti(sc) 1187 struct ti_softc *sc; 1188 { 1189 struct ifnet *ifp; 1190 struct ti_cmd_desc cmd; 1191 struct ti_mc_entry *mc; 1192 u_int32_t intrs; 1193 struct ether_multi *enm; 1194 struct ether_multistep step; 1195 1196 ifp = &sc->ethercom.ec_if; 1197 1198 /* Disable interrupts. */ 1199 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1200 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1201 1202 /* First, zot all the existing filters. */ 1203 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1204 ti_del_mcast(sc, &mc->mc_addr); 1205 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1206 free(mc, M_DEVBUF); 1207 } 1208 1209 /* 1210 * Remember all multicast addresses so that we can delete them 1211 * later. Punt if there is a range of addresses or memory shortage. 1212 */ 1213 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1214 while (enm != NULL) { 1215 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1216 ETHER_ADDR_LEN) != 0) 1217 goto allmulti; 1218 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1219 M_NOWAIT)) == NULL) 1220 goto allmulti; 1221 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1222 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1223 ETHER_NEXT_MULTI(step, enm); 1224 } 1225 1226 /* Accept only programmed multicast addresses */ 1227 ifp->if_flags &= ~IFF_ALLMULTI; 1228 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1229 1230 /* Now program new ones. */ 1231 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1232 ti_add_mcast(sc, &mc->mc_addr); 1233 1234 /* Re-enable interrupts. */ 1235 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1236 1237 return; 1238 1239 allmulti: 1240 /* No need to keep individual multicast addresses */ 1241 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1242 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1243 free(mc, M_DEVBUF); 1244 } 1245 1246 /* Accept all multicast addresses */ 1247 ifp->if_flags |= IFF_ALLMULTI; 1248 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1249 1250 /* Re-enable interrupts. */ 1251 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1252 } 1253 1254 /* 1255 * Check to see if the BIOS has configured us for a 64 bit slot when 1256 * we aren't actually in one. If we detect this condition, we can work 1257 * around it on the Tigon 2 by setting a bit in the PCI state register, 1258 * but for the Tigon 1 we must give up and abort the interface attach. 1259 */ 1260 static int ti_64bitslot_war(sc) 1261 struct ti_softc *sc; 1262 { 1263 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1264 CSR_WRITE_4(sc, 0x600, 0); 1265 CSR_WRITE_4(sc, 0x604, 0); 1266 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1267 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1268 if (sc->ti_hwrev == TI_HWREV_TIGON) 1269 return(EINVAL); 1270 else { 1271 TI_SETBIT(sc, TI_PCI_STATE, 1272 TI_PCISTATE_32BIT_BUS); 1273 return(0); 1274 } 1275 } 1276 } 1277 1278 return(0); 1279 } 1280 1281 /* 1282 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1283 * self-test results. 1284 */ 1285 static int ti_chipinit(sc) 1286 struct ti_softc *sc; 1287 { 1288 u_int32_t cacheline; 1289 u_int32_t pci_writemax = 0; 1290 u_int32_t rev; 1291 1292 /* Initialize link to down state. */ 1293 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1294 1295 /* Set endianness before we access any non-PCI registers. */ 1296 #if BYTE_ORDER == BIG_ENDIAN 1297 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1298 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1299 #else 1300 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1301 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1302 #endif 1303 1304 /* Check the ROM failed bit to see if self-tests passed. */ 1305 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1306 printf("%s: board self-diagnostics failed!\n", 1307 sc->sc_dev.dv_xname); 1308 return(ENODEV); 1309 } 1310 1311 /* Halt the CPU. */ 1312 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1313 1314 /* Figure out the hardware revision. */ 1315 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1316 switch(rev) { 1317 case TI_REV_TIGON_I: 1318 sc->ti_hwrev = TI_HWREV_TIGON; 1319 break; 1320 case TI_REV_TIGON_II: 1321 sc->ti_hwrev = TI_HWREV_TIGON_II; 1322 break; 1323 default: 1324 printf("%s: unsupported chip revision 0x%x\n", 1325 sc->sc_dev.dv_xname, rev); 1326 return(ENODEV); 1327 } 1328 1329 /* Do special setup for Tigon 2. */ 1330 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1331 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1332 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1333 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1334 } 1335 1336 /* Set up the PCI state register. */ 1337 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1338 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1339 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1340 } 1341 1342 /* Clear the read/write max DMA parameters. */ 1343 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1344 TI_PCISTATE_READ_MAXDMA)); 1345 1346 /* Get cache line size. */ 1347 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1348 1349 /* 1350 * If the system has set enabled the PCI memory write 1351 * and invalidate command in the command register, set 1352 * the write max parameter accordingly. This is necessary 1353 * to use MWI with the Tigon 2. 1354 */ 1355 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1356 & PCI_COMMAND_INVALIDATE_ENABLE) { 1357 switch(cacheline) { 1358 case 1: 1359 case 4: 1360 case 8: 1361 case 16: 1362 case 32: 1363 case 64: 1364 break; 1365 default: 1366 /* Disable PCI memory write and invalidate. */ 1367 if (bootverbose) 1368 printf("%s: cache line size %d not " 1369 "supported; disabling PCI MWI\n", 1370 sc->sc_dev.dv_xname, cacheline); 1371 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1372 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1373 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1374 break; 1375 } 1376 } 1377 1378 #ifdef __brokenalpha__ 1379 /* 1380 * From the Alteon sample driver: 1381 * Must insure that we do not cross an 8K (bytes) boundary 1382 * for DMA reads. Our highest limit is 1K bytes. This is a 1383 * restriction on some ALPHA platforms with early revision 1384 * 21174 PCI chipsets, such as the AlphaPC 164lx 1385 */ 1386 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1387 #else 1388 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1389 #endif 1390 1391 /* This sets the min dma param all the way up (0xff). */ 1392 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1393 1394 /* Configure DMA variables. */ 1395 #if BYTE_ORDER == BIG_ENDIAN 1396 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1397 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1398 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1399 TI_OPMODE_DONT_FRAG_JUMBO); 1400 #else 1401 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1402 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1403 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1404 #endif 1405 1406 /* 1407 * Only allow 1 DMA channel to be active at a time. 1408 * I don't think this is a good idea, but without it 1409 * the firmware racks up lots of nicDmaReadRingFull 1410 * errors. 1411 * Incompatible with hardware assisted checksums. 1412 */ 1413 if ((sc->ethercom.ec_if.if_capenable & 1414 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1415 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1416 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1417 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1418 1419 /* Recommended settings from Tigon manual. */ 1420 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1421 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1422 1423 if (ti_64bitslot_war(sc)) { 1424 printf("%s: bios thinks we're in a 64 bit slot, " 1425 "but we aren't", sc->sc_dev.dv_xname); 1426 return(EINVAL); 1427 } 1428 1429 return(0); 1430 } 1431 1432 /* 1433 * Initialize the general information block and firmware, and 1434 * start the CPU(s) running. 1435 */ 1436 static int ti_gibinit(sc) 1437 struct ti_softc *sc; 1438 { 1439 struct ti_rcb *rcb; 1440 int i; 1441 struct ifnet *ifp; 1442 1443 ifp = &sc->ethercom.ec_if; 1444 1445 /* Disable interrupts for now. */ 1446 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1447 1448 /* Tell the chip where to find the general information block. */ 1449 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1450 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1451 1452 /* Load the firmware into SRAM. */ 1453 ti_loadfw(sc); 1454 1455 /* Set up the contents of the general info and ring control blocks. */ 1456 1457 /* Set up the event ring and producer pointer. */ 1458 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1459 1460 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1461 rcb->ti_flags = 0; 1462 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1463 TI_CDEVPRODADDR(sc); 1464 1465 sc->ti_ev_prodidx.ti_idx = 0; 1466 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1467 sc->ti_ev_saved_considx = 0; 1468 1469 /* Set up the command ring and producer mailbox. */ 1470 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1471 1472 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1473 rcb->ti_flags = 0; 1474 rcb->ti_max_len = 0; 1475 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1477 } 1478 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1479 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1480 sc->ti_cmd_saved_prodidx = 0; 1481 1482 /* 1483 * Assign the address of the stats refresh buffer. 1484 * We re-use the current stats buffer for this to 1485 * conserve memory. 1486 */ 1487 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1488 TI_CDSTATSADDR(sc); 1489 1490 /* Set up the standard receive ring. */ 1491 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1492 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1493 rcb->ti_max_len = ETHER_MAX_LEN; 1494 rcb->ti_flags = 0; 1495 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1496 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1497 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1498 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1499 if (VLAN_ATTACHED(&sc->ethercom)) 1500 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1501 1502 /* Set up the jumbo receive ring. */ 1503 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1504 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1505 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1506 rcb->ti_flags = 0; 1507 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1508 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1509 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1510 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1511 if (VLAN_ATTACHED(&sc->ethercom)) 1512 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1513 1514 /* 1515 * Set up the mini ring. Only activated on the 1516 * Tigon 2 but the slot in the config block is 1517 * still there on the Tigon 1. 1518 */ 1519 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1520 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1521 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1522 if (sc->ti_hwrev == TI_HWREV_TIGON) 1523 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1524 else 1525 rcb->ti_flags = 0; 1526 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1527 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1528 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1529 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1530 if (VLAN_ATTACHED(&sc->ethercom)) 1531 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1532 1533 /* 1534 * Set up the receive return ring. 1535 */ 1536 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1537 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1538 rcb->ti_flags = 0; 1539 rcb->ti_max_len = TI_RETURN_RING_CNT; 1540 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1541 TI_CDRTNPRODADDR(sc); 1542 1543 /* 1544 * Set up the tx ring. Note: for the Tigon 2, we have the option 1545 * of putting the transmit ring in the host's address space and 1546 * letting the chip DMA it instead of leaving the ring in the NIC's 1547 * memory and accessing it through the shared memory region. We 1548 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1549 * so we have to revert to the shared memory scheme if we detect 1550 * a Tigon 1 chip. 1551 */ 1552 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1553 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1554 sc->ti_tx_ring_nic = 1555 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1556 } 1557 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1558 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1559 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1560 if (sc->ti_hwrev == TI_HWREV_TIGON) 1561 rcb->ti_flags = 0; 1562 else 1563 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1564 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1565 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1566 /* 1567 * When we get the packet, there is a pseudo-header seed already 1568 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1569 * compute the pseudo-header checksum again! 1570 */ 1571 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1572 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1573 TI_RCB_FLAG_NO_PHDR_CKSUM; 1574 if (VLAN_ATTACHED(&sc->ethercom)) 1575 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1576 rcb->ti_max_len = TI_TX_RING_CNT; 1577 if (sc->ti_hwrev == TI_HWREV_TIGON) 1578 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1579 else 1580 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1581 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1582 TI_CDTXCONSADDR(sc); 1583 1584 /* 1585 * We're done frobbing the General Information Block. Sync 1586 * it. Note we take care of the first stats sync here, as 1587 * well. 1588 */ 1589 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1590 1591 /* Set up tuneables */ 1592 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1593 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1594 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1595 (sc->ti_rx_coal_ticks / 10)); 1596 else 1597 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1598 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1599 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1600 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1601 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1602 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1603 1604 /* Turn interrupts on. */ 1605 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1606 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1607 1608 /* Start CPU. */ 1609 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1610 1611 return(0); 1612 } 1613 1614 /* 1615 * look for id in the device list, returning the first match 1616 */ 1617 static const struct ti_type * 1618 ti_type_match(pa) 1619 struct pci_attach_args *pa; 1620 { 1621 const struct ti_type *t; 1622 1623 t = ti_devs; 1624 while(t->ti_name != NULL) { 1625 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1626 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1627 return (t); 1628 } 1629 t++; 1630 } 1631 1632 return(NULL); 1633 } 1634 1635 /* 1636 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1637 * against our list and return its name if we find a match. 1638 */ 1639 static int ti_probe(parent, match, aux) 1640 struct device *parent; 1641 struct cfdata *match; 1642 void *aux; 1643 { 1644 struct pci_attach_args *pa = aux; 1645 const struct ti_type *t; 1646 1647 t = ti_type_match(pa); 1648 1649 return((t == NULL) ? 0 : 1); 1650 } 1651 1652 static void ti_attach(parent, self, aux) 1653 struct device *parent, *self; 1654 void *aux; 1655 { 1656 u_int32_t command; 1657 struct ifnet *ifp; 1658 struct ti_softc *sc; 1659 u_char eaddr[ETHER_ADDR_LEN]; 1660 struct pci_attach_args *pa = aux; 1661 pci_chipset_tag_t pc = pa->pa_pc; 1662 pci_intr_handle_t ih; 1663 const char *intrstr = NULL; 1664 bus_dma_segment_t dmaseg; 1665 int error, dmanseg, nolinear; 1666 const struct ti_type *t; 1667 1668 t = ti_type_match(pa); 1669 if (t == NULL) { 1670 printf("ti_attach: were did the card go ?\n"); 1671 return; 1672 } 1673 1674 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1675 1676 sc = (struct ti_softc *)self; 1677 1678 /* 1679 * Map control/status registers. 1680 */ 1681 nolinear = 0; 1682 if (pci_mapreg_map(pa, 0x10, 1683 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1684 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1685 NULL, NULL)) { 1686 nolinear = 1; 1687 if (pci_mapreg_map(pa, 0x10, 1688 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1689 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1690 printf(": can't map memory space\n"); 1691 return; 1692 } 1693 } 1694 if (nolinear == 0) 1695 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1696 else 1697 sc->ti_vhandle = NULL; 1698 1699 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1700 command |= PCI_COMMAND_MASTER_ENABLE; 1701 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1702 1703 /* Allocate interrupt */ 1704 if (pci_intr_map(pa, &ih)) { 1705 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1706 return; 1707 } 1708 intrstr = pci_intr_string(pc, ih); 1709 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1710 if (sc->sc_ih == NULL) { 1711 printf("%s: couldn't establish interrupt", 1712 sc->sc_dev.dv_xname); 1713 if (intrstr != NULL) 1714 printf(" at %s", intrstr); 1715 printf("\n"); 1716 return; 1717 } 1718 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1719 /* 1720 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1721 * doing do could allow DMA to corrupt kernel memory during the 1722 * reboot before the driver initializes. 1723 */ 1724 (void) shutdownhook_establish(ti_shutdown, sc); 1725 1726 if (ti_chipinit(sc)) { 1727 printf("%s: chip initialization failed\n", self->dv_xname); 1728 goto fail2; 1729 } 1730 1731 /* 1732 * Deal with some chip diffrences. 1733 */ 1734 switch (sc->ti_hwrev) { 1735 case TI_HWREV_TIGON: 1736 sc->sc_tx_encap = ti_encap_tigon1; 1737 sc->sc_tx_eof = ti_txeof_tigon1; 1738 if (nolinear == 1) 1739 printf("%s: memory space not mapped linear\n", 1740 self->dv_xname); 1741 break; 1742 1743 case TI_HWREV_TIGON_II: 1744 sc->sc_tx_encap = ti_encap_tigon2; 1745 sc->sc_tx_eof = ti_txeof_tigon2; 1746 break; 1747 1748 default: 1749 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1750 sc->ti_hwrev); 1751 goto fail2; 1752 } 1753 1754 /* Zero out the NIC's on-board SRAM. */ 1755 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1756 1757 /* Init again -- zeroing memory may have clobbered some registers. */ 1758 if (ti_chipinit(sc)) { 1759 printf("%s: chip initialization failed\n", self->dv_xname); 1760 goto fail2; 1761 } 1762 1763 /* 1764 * Get station address from the EEPROM. Note: the manual states 1765 * that the MAC address is at offset 0x8c, however the data is 1766 * stored as two longwords (since that's how it's loaded into 1767 * the NIC). This means the MAC address is actually preceded 1768 * by two zero bytes. We need to skip over those. 1769 */ 1770 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1771 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1772 printf("%s: failed to read station address\n", self->dv_xname); 1773 goto fail2; 1774 } 1775 1776 /* 1777 * A Tigon chip was detected. Inform the world. 1778 */ 1779 printf("%s: Ethernet address: %s\n", self->dv_xname, 1780 ether_sprintf(eaddr)); 1781 1782 sc->sc_dmat = pa->pa_dmat; 1783 1784 /* Allocate the general information block and ring buffers. */ 1785 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1786 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1787 BUS_DMA_NOWAIT)) != 0) { 1788 printf("%s: can't allocate ring buffer, error = %d\n", 1789 sc->sc_dev.dv_xname, error); 1790 goto fail2; 1791 } 1792 1793 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1794 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1795 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1796 printf("%s: can't map ring buffer, error = %d\n", 1797 sc->sc_dev.dv_xname, error); 1798 goto fail2; 1799 } 1800 1801 if ((error = bus_dmamap_create(sc->sc_dmat, 1802 sizeof(struct ti_ring_data), 1, 1803 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1804 &sc->info_dmamap)) != 0) { 1805 printf("%s: can't create ring buffer DMA map, error = %d\n", 1806 sc->sc_dev.dv_xname, error); 1807 goto fail2; 1808 } 1809 1810 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1811 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1812 BUS_DMA_NOWAIT)) != 0) { 1813 printf("%s: can't load ring buffer DMA map, error = %d\n", 1814 sc->sc_dev.dv_xname, error); 1815 goto fail2; 1816 } 1817 1818 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1819 1820 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1821 1822 /* Try to allocate memory for jumbo buffers. */ 1823 if (ti_alloc_jumbo_mem(sc)) { 1824 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1825 goto fail2; 1826 } 1827 1828 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1829 1830 /* 1831 * We really need a better way to tell a 1000baseT card 1832 * from a 1000baseSX one, since in theory there could be 1833 * OEMed 1000baseT cards from lame vendors who aren't 1834 * clever enough to change the PCI ID. For the moment 1835 * though, the AceNIC is the only copper card available. 1836 */ 1837 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1838 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1839 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1840 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1841 sc->ti_copper = 1; 1842 else 1843 sc->ti_copper = 0; 1844 1845 /* Set default tuneable values. */ 1846 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1847 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1848 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1849 sc->ti_rx_max_coal_bds = 64; 1850 sc->ti_tx_max_coal_bds = 128; 1851 sc->ti_tx_buf_ratio = 21; 1852 1853 /* Set up ifnet structure */ 1854 ifp = &sc->ethercom.ec_if; 1855 ifp->if_softc = sc; 1856 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1858 ifp->if_ioctl = ti_ioctl; 1859 ifp->if_start = ti_start; 1860 ifp->if_watchdog = ti_watchdog; 1861 IFQ_SET_READY(&ifp->if_snd); 1862 1863 #if 0 1864 /* 1865 * XXX This is not really correct -- we don't necessarily 1866 * XXX want to queue up as many as we can transmit at the 1867 * XXX upper layer like that. Someone with a board should 1868 * XXX check to see how this affects performance. 1869 */ 1870 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1871 #endif 1872 1873 /* 1874 * We can support 802.1Q VLAN-sized frames. 1875 */ 1876 sc->ethercom.ec_capabilities |= 1877 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1878 1879 /* 1880 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1881 */ 1882 ifp->if_capabilities |= 1883 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1884 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1885 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1886 1887 /* Set up ifmedia support. */ 1888 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1889 if (sc->ti_copper) { 1890 /* 1891 * Copper cards allow manual 10/100 mode selection, 1892 * but not manual 1000baseT mode selection. Why? 1893 * Because currently there's no way to specify the 1894 * master/slave setting through the firmware interface, 1895 * so Alteon decided to just bag it and handle it 1896 * via autonegotiation. 1897 */ 1898 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1899 ifmedia_add(&sc->ifmedia, 1900 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1901 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1902 ifmedia_add(&sc->ifmedia, 1903 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1904 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1905 ifmedia_add(&sc->ifmedia, 1906 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1907 } else { 1908 /* Fiber cards don't support 10/100 modes. */ 1909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1910 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1911 } 1912 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1913 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1914 1915 /* 1916 * Call MI attach routines. 1917 */ 1918 if_attach(ifp); 1919 ether_ifattach(ifp, eaddr); 1920 1921 return; 1922 fail2: 1923 pci_intr_disestablish(pc, sc->sc_ih); 1924 return; 1925 } 1926 1927 /* 1928 * Frame reception handling. This is called if there's a frame 1929 * on the receive return list. 1930 * 1931 * Note: we have to be able to handle three possibilities here: 1932 * 1) the frame is from the mini receive ring (can only happen) 1933 * on Tigon 2 boards) 1934 * 2) the frame is from the jumbo receive ring 1935 * 3) the frame is from the standard receive ring 1936 */ 1937 1938 static void ti_rxeof(sc) 1939 struct ti_softc *sc; 1940 { 1941 struct ifnet *ifp; 1942 struct ti_cmd_desc cmd; 1943 1944 ifp = &sc->ethercom.ec_if; 1945 1946 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1947 struct ti_rx_desc *cur_rx; 1948 u_int32_t rxidx; 1949 struct mbuf *m = NULL; 1950 struct ether_header *eh; 1951 bus_dmamap_t dmamap; 1952 1953 cur_rx = 1954 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1955 rxidx = cur_rx->ti_idx; 1956 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1957 1958 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1959 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1960 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1961 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1962 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1963 ifp->if_ierrors++; 1964 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1965 continue; 1966 } 1967 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1968 == ENOBUFS) { 1969 ifp->if_ierrors++; 1970 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1971 continue; 1972 } 1973 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1974 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1975 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1976 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1977 dmamap = sc->mini_dmamap[rxidx]; 1978 sc->mini_dmamap[rxidx] = 0; 1979 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1980 ifp->if_ierrors++; 1981 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1982 continue; 1983 } 1984 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1985 == ENOBUFS) { 1986 ifp->if_ierrors++; 1987 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1988 continue; 1989 } 1990 } else { 1991 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1992 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1993 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1994 dmamap = sc->std_dmamap[rxidx]; 1995 sc->std_dmamap[rxidx] = 0; 1996 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1997 ifp->if_ierrors++; 1998 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1999 continue; 2000 } 2001 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2002 == ENOBUFS) { 2003 ifp->if_ierrors++; 2004 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2005 continue; 2006 } 2007 } 2008 2009 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2010 ifp->if_ipackets++; 2011 m->m_pkthdr.rcvif = ifp; 2012 2013 #if NBPFILTER > 0 2014 /* 2015 * Handle BPF listeners. Let the BPF user see the packet, but 2016 * don't pass it up to the ether_input() layer unless it's 2017 * a broadcast packet, multicast packet, matches our ethernet 2018 * address or the interface is in promiscuous mode. 2019 */ 2020 if (ifp->if_bpf) 2021 bpf_mtap(ifp->if_bpf, m); 2022 #endif 2023 2024 eh = mtod(m, struct ether_header *); 2025 switch (ntohs(eh->ether_type)) { 2026 #ifdef INET 2027 case ETHERTYPE_IP: 2028 { 2029 struct ip *ip = (struct ip *) (eh + 1); 2030 2031 /* 2032 * Note the Tigon firmware does not invert 2033 * the checksum for us, hence the XOR. 2034 */ 2035 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2036 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2037 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2038 /* 2039 * ntohs() the constant so the compiler can 2040 * optimize... 2041 * 2042 * XXX Figure out a sane way to deal with 2043 * fragmented packets. 2044 */ 2045 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2046 switch (ip->ip_p) { 2047 case IPPROTO_TCP: 2048 m->m_pkthdr.csum_data = 2049 cur_rx->ti_tcp_udp_cksum; 2050 m->m_pkthdr.csum_flags |= 2051 M_CSUM_TCPv4|M_CSUM_DATA; 2052 break; 2053 case IPPROTO_UDP: 2054 m->m_pkthdr.csum_data = 2055 cur_rx->ti_tcp_udp_cksum; 2056 m->m_pkthdr.csum_flags |= 2057 M_CSUM_UDPv4|M_CSUM_DATA; 2058 break; 2059 default: 2060 /* Nothing */; 2061 } 2062 } 2063 break; 2064 } 2065 #endif 2066 default: 2067 /* Nothing. */ 2068 break; 2069 } 2070 2071 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2072 VLAN_INPUT_TAG(ifp, m, 2073 /* ti_vlan_tag also has the priority, trim it */ 2074 cur_rx->ti_vlan_tag & 4095, 2075 continue); 2076 } 2077 2078 (*ifp->if_input)(ifp, m); 2079 } 2080 2081 /* Only necessary on the Tigon 1. */ 2082 if (sc->ti_hwrev == TI_HWREV_TIGON) 2083 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2084 sc->ti_rx_saved_considx); 2085 2086 TI_UPDATE_STDPROD(sc, sc->ti_std); 2087 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2088 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2089 2090 return; 2091 } 2092 2093 static void ti_txeof_tigon1(sc) 2094 struct ti_softc *sc; 2095 { 2096 struct ti_tx_desc *cur_tx = NULL; 2097 struct ifnet *ifp; 2098 struct txdmamap_pool_entry *dma; 2099 2100 ifp = &sc->ethercom.ec_if; 2101 2102 /* 2103 * Go through our tx ring and free mbufs for those 2104 * frames that have been sent. 2105 */ 2106 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2107 u_int32_t idx = 0; 2108 2109 idx = sc->ti_tx_saved_considx; 2110 if (idx > 383) 2111 CSR_WRITE_4(sc, TI_WINBASE, 2112 TI_TX_RING_BASE + 6144); 2113 else if (idx > 255) 2114 CSR_WRITE_4(sc, TI_WINBASE, 2115 TI_TX_RING_BASE + 4096); 2116 else if (idx > 127) 2117 CSR_WRITE_4(sc, TI_WINBASE, 2118 TI_TX_RING_BASE + 2048); 2119 else 2120 CSR_WRITE_4(sc, TI_WINBASE, 2121 TI_TX_RING_BASE); 2122 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2123 if (cur_tx->ti_flags & TI_BDFLAG_END) 2124 ifp->if_opackets++; 2125 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2126 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2127 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2128 2129 dma = sc->txdma[idx]; 2130 KDASSERT(dma != NULL); 2131 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2132 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2133 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2134 2135 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2136 sc->txdma[idx] = NULL; 2137 } 2138 sc->ti_txcnt--; 2139 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2140 ifp->if_timer = 0; 2141 } 2142 2143 if (cur_tx != NULL) 2144 ifp->if_flags &= ~IFF_OACTIVE; 2145 2146 return; 2147 } 2148 2149 static void ti_txeof_tigon2(sc) 2150 struct ti_softc *sc; 2151 { 2152 struct ti_tx_desc *cur_tx = NULL; 2153 struct ifnet *ifp; 2154 struct txdmamap_pool_entry *dma; 2155 int firstidx, cnt; 2156 2157 ifp = &sc->ethercom.ec_if; 2158 2159 /* 2160 * Go through our tx ring and free mbufs for those 2161 * frames that have been sent. 2162 */ 2163 firstidx = sc->ti_tx_saved_considx; 2164 cnt = 0; 2165 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2166 u_int32_t idx = 0; 2167 2168 idx = sc->ti_tx_saved_considx; 2169 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2170 if (cur_tx->ti_flags & TI_BDFLAG_END) 2171 ifp->if_opackets++; 2172 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2173 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2174 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2175 2176 dma = sc->txdma[idx]; 2177 KDASSERT(dma != NULL); 2178 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2179 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2180 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2181 2182 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2183 sc->txdma[idx] = NULL; 2184 } 2185 cnt++; 2186 sc->ti_txcnt--; 2187 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2188 ifp->if_timer = 0; 2189 } 2190 2191 if (cnt != 0) 2192 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2193 2194 if (cur_tx != NULL) 2195 ifp->if_flags &= ~IFF_OACTIVE; 2196 2197 return; 2198 } 2199 2200 static int ti_intr(xsc) 2201 void *xsc; 2202 { 2203 struct ti_softc *sc; 2204 struct ifnet *ifp; 2205 2206 sc = xsc; 2207 ifp = &sc->ethercom.ec_if; 2208 2209 #ifdef notdef 2210 /* Avoid this for now -- checking this register is expensive. */ 2211 /* Make sure this is really our interrupt. */ 2212 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2213 return (0); 2214 #endif 2215 2216 /* Ack interrupt and stop others from occuring. */ 2217 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2218 2219 if (ifp->if_flags & IFF_RUNNING) { 2220 /* Check RX return ring producer/consumer */ 2221 ti_rxeof(sc); 2222 2223 /* Check TX ring producer/consumer */ 2224 (*sc->sc_tx_eof)(sc); 2225 } 2226 2227 ti_handle_events(sc); 2228 2229 /* Re-enable interrupts. */ 2230 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2231 2232 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2233 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2234 ti_start(ifp); 2235 2236 return (1); 2237 } 2238 2239 static void ti_stats_update(sc) 2240 struct ti_softc *sc; 2241 { 2242 struct ifnet *ifp; 2243 2244 ifp = &sc->ethercom.ec_if; 2245 2246 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2247 2248 ifp->if_collisions += 2249 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2250 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2251 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2252 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2253 ifp->if_collisions; 2254 2255 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2256 } 2257 2258 /* 2259 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2260 * pointers to descriptors. 2261 */ 2262 static int ti_encap_tigon1(sc, m_head, txidx) 2263 struct ti_softc *sc; 2264 struct mbuf *m_head; 2265 u_int32_t *txidx; 2266 { 2267 struct ti_tx_desc *f = NULL; 2268 u_int32_t frag, cur, cnt = 0; 2269 struct txdmamap_pool_entry *dma; 2270 bus_dmamap_t dmamap; 2271 int error, i; 2272 struct m_tag *mtag; 2273 u_int16_t csum_flags = 0; 2274 2275 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2276 if (dma == NULL) { 2277 return ENOMEM; 2278 } 2279 dmamap = dma->dmamap; 2280 2281 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2282 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2283 if (error) { 2284 struct mbuf *m; 2285 int j = 0; 2286 for (m = m_head; m; m = m->m_next) 2287 j++; 2288 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2289 "error %d\n", m_head->m_pkthdr.len, j, error); 2290 return (ENOMEM); 2291 } 2292 2293 cur = frag = *txidx; 2294 2295 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2296 /* IP header checksum field must be 0! */ 2297 csum_flags |= TI_BDFLAG_IP_CKSUM; 2298 } 2299 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2300 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2301 2302 /* XXX fragmented packet checksum capability? */ 2303 2304 /* 2305 * Start packing the mbufs in this chain into 2306 * the fragment pointers. Stop when we run out 2307 * of fragments or hit the end of the mbuf chain. 2308 */ 2309 for (i = 0; i < dmamap->dm_nsegs; i++) { 2310 if (frag > 383) 2311 CSR_WRITE_4(sc, TI_WINBASE, 2312 TI_TX_RING_BASE + 6144); 2313 else if (frag > 255) 2314 CSR_WRITE_4(sc, TI_WINBASE, 2315 TI_TX_RING_BASE + 4096); 2316 else if (frag > 127) 2317 CSR_WRITE_4(sc, TI_WINBASE, 2318 TI_TX_RING_BASE + 2048); 2319 else 2320 CSR_WRITE_4(sc, TI_WINBASE, 2321 TI_TX_RING_BASE); 2322 f = &sc->ti_tx_ring_nic[frag % 128]; 2323 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2324 break; 2325 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2326 f->ti_len = dmamap->dm_segs[i].ds_len; 2327 f->ti_flags = csum_flags; 2328 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2329 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2330 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2331 } else { 2332 f->ti_vlan_tag = 0; 2333 } 2334 /* 2335 * Sanity check: avoid coming within 16 descriptors 2336 * of the end of the ring. 2337 */ 2338 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2339 return(ENOBUFS); 2340 cur = frag; 2341 TI_INC(frag, TI_TX_RING_CNT); 2342 cnt++; 2343 } 2344 2345 if (i < dmamap->dm_nsegs) 2346 return(ENOBUFS); 2347 2348 if (frag == sc->ti_tx_saved_considx) 2349 return(ENOBUFS); 2350 2351 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2352 TI_BDFLAG_END; 2353 2354 /* Sync the packet's DMA map. */ 2355 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2356 BUS_DMASYNC_PREWRITE); 2357 2358 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2359 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2360 sc->txdma[cur] = dma; 2361 sc->ti_txcnt += cnt; 2362 2363 *txidx = frag; 2364 2365 return(0); 2366 } 2367 2368 static int ti_encap_tigon2(sc, m_head, txidx) 2369 struct ti_softc *sc; 2370 struct mbuf *m_head; 2371 u_int32_t *txidx; 2372 { 2373 struct ti_tx_desc *f = NULL; 2374 u_int32_t frag, firstfrag, cur, cnt = 0; 2375 struct txdmamap_pool_entry *dma; 2376 bus_dmamap_t dmamap; 2377 int error, i; 2378 struct m_tag *mtag; 2379 u_int16_t csum_flags = 0; 2380 2381 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2382 if (dma == NULL) { 2383 return ENOMEM; 2384 } 2385 dmamap = dma->dmamap; 2386 2387 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2388 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2389 if (error) { 2390 struct mbuf *m; 2391 int j = 0; 2392 for (m = m_head; m; m = m->m_next) 2393 j++; 2394 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2395 "error %d\n", m_head->m_pkthdr.len, j, error); 2396 return (ENOMEM); 2397 } 2398 2399 cur = firstfrag = frag = *txidx; 2400 2401 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2402 /* IP header checksum field must be 0! */ 2403 csum_flags |= TI_BDFLAG_IP_CKSUM; 2404 } 2405 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2406 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2407 2408 /* XXX fragmented packet checksum capability? */ 2409 2410 /* 2411 * Start packing the mbufs in this chain into 2412 * the fragment pointers. Stop when we run out 2413 * of fragments or hit the end of the mbuf chain. 2414 */ 2415 for (i = 0; i < dmamap->dm_nsegs; i++) { 2416 f = &sc->ti_rdata->ti_tx_ring[frag]; 2417 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2418 break; 2419 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2420 f->ti_len = dmamap->dm_segs[i].ds_len; 2421 f->ti_flags = csum_flags; 2422 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2423 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2424 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2425 } else { 2426 f->ti_vlan_tag = 0; 2427 } 2428 /* 2429 * Sanity check: avoid coming within 16 descriptors 2430 * of the end of the ring. 2431 */ 2432 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2433 return(ENOBUFS); 2434 cur = frag; 2435 TI_INC(frag, TI_TX_RING_CNT); 2436 cnt++; 2437 } 2438 2439 if (i < dmamap->dm_nsegs) 2440 return(ENOBUFS); 2441 2442 if (frag == sc->ti_tx_saved_considx) 2443 return(ENOBUFS); 2444 2445 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2446 2447 /* Sync the packet's DMA map. */ 2448 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2449 BUS_DMASYNC_PREWRITE); 2450 2451 /* Sync the descriptors we are using. */ 2452 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2453 2454 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2455 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2456 sc->txdma[cur] = dma; 2457 sc->ti_txcnt += cnt; 2458 2459 *txidx = frag; 2460 2461 return(0); 2462 } 2463 2464 /* 2465 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2466 * to the mbuf data regions directly in the transmit descriptors. 2467 */ 2468 static void ti_start(ifp) 2469 struct ifnet *ifp; 2470 { 2471 struct ti_softc *sc; 2472 struct mbuf *m_head = NULL; 2473 u_int32_t prodidx = 0; 2474 2475 sc = ifp->if_softc; 2476 2477 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2478 2479 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2480 IFQ_POLL(&ifp->if_snd, m_head); 2481 if (m_head == NULL) 2482 break; 2483 2484 /* 2485 * Pack the data into the transmit ring. If we 2486 * don't have room, set the OACTIVE flag and wait 2487 * for the NIC to drain the ring. 2488 */ 2489 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2490 ifp->if_flags |= IFF_OACTIVE; 2491 break; 2492 } 2493 2494 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2495 2496 /* 2497 * If there's a BPF listener, bounce a copy of this frame 2498 * to him. 2499 */ 2500 #if NBPFILTER > 0 2501 if (ifp->if_bpf) 2502 bpf_mtap(ifp->if_bpf, m_head); 2503 #endif 2504 } 2505 2506 /* Transmit */ 2507 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2508 2509 /* 2510 * Set a timeout in case the chip goes out to lunch. 2511 */ 2512 ifp->if_timer = 5; 2513 2514 return; 2515 } 2516 2517 static void ti_init(xsc) 2518 void *xsc; 2519 { 2520 struct ti_softc *sc = xsc; 2521 int s; 2522 2523 s = splnet(); 2524 2525 /* Cancel pending I/O and flush buffers. */ 2526 ti_stop(sc); 2527 2528 /* Init the gen info block, ring control blocks and firmware. */ 2529 if (ti_gibinit(sc)) { 2530 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2531 splx(s); 2532 return; 2533 } 2534 2535 splx(s); 2536 2537 return; 2538 } 2539 2540 static void ti_init2(sc) 2541 struct ti_softc *sc; 2542 { 2543 struct ti_cmd_desc cmd; 2544 struct ifnet *ifp; 2545 u_int8_t *m; 2546 struct ifmedia *ifm; 2547 int tmp; 2548 2549 ifp = &sc->ethercom.ec_if; 2550 2551 /* Specify MTU and interface index. */ 2552 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2553 2554 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2555 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2556 tmp += ETHER_VLAN_ENCAP_LEN; 2557 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2558 2559 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2560 2561 /* Load our MAC address. */ 2562 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2563 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2564 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2565 | (m[4] << 8) | m[5]); 2566 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2567 2568 /* Enable or disable promiscuous mode as needed. */ 2569 if (ifp->if_flags & IFF_PROMISC) { 2570 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2571 } else { 2572 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2573 } 2574 2575 /* Program multicast filter. */ 2576 ti_setmulti(sc); 2577 2578 /* 2579 * If this is a Tigon 1, we should tell the 2580 * firmware to use software packet filtering. 2581 */ 2582 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2583 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2584 } 2585 2586 /* Init RX ring. */ 2587 ti_init_rx_ring_std(sc); 2588 2589 /* Init jumbo RX ring. */ 2590 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2591 ti_init_rx_ring_jumbo(sc); 2592 2593 /* 2594 * If this is a Tigon 2, we can also configure the 2595 * mini ring. 2596 */ 2597 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2598 ti_init_rx_ring_mini(sc); 2599 2600 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2601 sc->ti_rx_saved_considx = 0; 2602 2603 /* Init TX ring. */ 2604 ti_init_tx_ring(sc); 2605 2606 /* Tell firmware we're alive. */ 2607 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2608 2609 /* Enable host interrupts. */ 2610 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2611 2612 ifp->if_flags |= IFF_RUNNING; 2613 ifp->if_flags &= ~IFF_OACTIVE; 2614 2615 /* 2616 * Make sure to set media properly. We have to do this 2617 * here since we have to issue commands in order to set 2618 * the link negotiation and we can't issue commands until 2619 * the firmware is running. 2620 */ 2621 ifm = &sc->ifmedia; 2622 tmp = ifm->ifm_media; 2623 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2624 ti_ifmedia_upd(ifp); 2625 ifm->ifm_media = tmp; 2626 2627 return; 2628 } 2629 2630 /* 2631 * Set media options. 2632 */ 2633 static int ti_ifmedia_upd(ifp) 2634 struct ifnet *ifp; 2635 { 2636 struct ti_softc *sc; 2637 struct ifmedia *ifm; 2638 struct ti_cmd_desc cmd; 2639 2640 sc = ifp->if_softc; 2641 ifm = &sc->ifmedia; 2642 2643 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2644 return(EINVAL); 2645 2646 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2647 case IFM_AUTO: 2648 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2649 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2650 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2651 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2652 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2653 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2654 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2655 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2656 break; 2657 case IFM_1000_SX: 2658 case IFM_1000_T: 2659 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2660 CSR_WRITE_4(sc, TI_GCR_GLINK, 2661 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2662 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2663 } else { 2664 CSR_WRITE_4(sc, TI_GCR_GLINK, 2665 TI_GLNK_PREF|TI_GLNK_1000MB| 2666 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2667 } 2668 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2669 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2670 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2671 break; 2672 case IFM_100_FX: 2673 case IFM_10_FL: 2674 case IFM_100_TX: 2675 case IFM_10_T: 2676 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2677 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2678 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2679 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2680 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2681 } else { 2682 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2683 } 2684 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2685 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2686 } else { 2687 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2688 } 2689 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2690 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2691 break; 2692 } 2693 2694 sc->ethercom.ec_if.if_baudrate = 2695 ifmedia_baudrate(ifm->ifm_media); 2696 2697 return(0); 2698 } 2699 2700 /* 2701 * Report current media status. 2702 */ 2703 static void ti_ifmedia_sts(ifp, ifmr) 2704 struct ifnet *ifp; 2705 struct ifmediareq *ifmr; 2706 { 2707 struct ti_softc *sc; 2708 u_int32_t media = 0; 2709 2710 sc = ifp->if_softc; 2711 2712 ifmr->ifm_status = IFM_AVALID; 2713 ifmr->ifm_active = IFM_ETHER; 2714 2715 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2716 return; 2717 2718 ifmr->ifm_status |= IFM_ACTIVE; 2719 2720 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2721 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2722 if (sc->ti_copper) 2723 ifmr->ifm_active |= IFM_1000_T; 2724 else 2725 ifmr->ifm_active |= IFM_1000_SX; 2726 if (media & TI_GLNK_FULL_DUPLEX) 2727 ifmr->ifm_active |= IFM_FDX; 2728 else 2729 ifmr->ifm_active |= IFM_HDX; 2730 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2731 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2732 if (sc->ti_copper) { 2733 if (media & TI_LNK_100MB) 2734 ifmr->ifm_active |= IFM_100_TX; 2735 if (media & TI_LNK_10MB) 2736 ifmr->ifm_active |= IFM_10_T; 2737 } else { 2738 if (media & TI_LNK_100MB) 2739 ifmr->ifm_active |= IFM_100_FX; 2740 if (media & TI_LNK_10MB) 2741 ifmr->ifm_active |= IFM_10_FL; 2742 } 2743 if (media & TI_LNK_FULL_DUPLEX) 2744 ifmr->ifm_active |= IFM_FDX; 2745 if (media & TI_LNK_HALF_DUPLEX) 2746 ifmr->ifm_active |= IFM_HDX; 2747 } 2748 2749 sc->ethercom.ec_if.if_baudrate = 2750 ifmedia_baudrate(sc->ifmedia.ifm_media); 2751 2752 return; 2753 } 2754 2755 static int 2756 ti_ether_ioctl(ifp, cmd, data) 2757 struct ifnet *ifp; 2758 u_long cmd; 2759 caddr_t data; 2760 { 2761 struct ifaddr *ifa = (struct ifaddr *) data; 2762 struct ti_softc *sc = ifp->if_softc; 2763 2764 if ((ifp->if_flags & IFF_UP) == 0) { 2765 ifp->if_flags |= IFF_UP; 2766 ti_init(sc); 2767 } 2768 2769 switch (cmd) { 2770 case SIOCSIFADDR: 2771 2772 switch (ifa->ifa_addr->sa_family) { 2773 #ifdef INET 2774 case AF_INET: 2775 arp_ifinit(ifp, ifa); 2776 break; 2777 #endif 2778 #ifdef NS 2779 case AF_NS: 2780 { 2781 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2782 2783 if (ns_nullhost(*ina)) 2784 ina->x_host = *(union ns_host *) 2785 LLADDR(ifp->if_sadl); 2786 else 2787 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2788 ifp->if_addrlen); 2789 break; 2790 } 2791 #endif 2792 default: 2793 break; 2794 } 2795 break; 2796 2797 default: 2798 return (EINVAL); 2799 } 2800 2801 return (0); 2802 } 2803 2804 static int ti_ioctl(ifp, command, data) 2805 struct ifnet *ifp; 2806 u_long command; 2807 caddr_t data; 2808 { 2809 struct ti_softc *sc = ifp->if_softc; 2810 struct ifreq *ifr = (struct ifreq *) data; 2811 int s, error = 0; 2812 struct ti_cmd_desc cmd; 2813 2814 s = splnet(); 2815 2816 switch(command) { 2817 case SIOCSIFADDR: 2818 case SIOCGIFADDR: 2819 error = ti_ether_ioctl(ifp, command, data); 2820 break; 2821 case SIOCSIFMTU: 2822 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2823 error = EINVAL; 2824 else { 2825 ifp->if_mtu = ifr->ifr_mtu; 2826 ti_init(sc); 2827 } 2828 break; 2829 case SIOCSIFFLAGS: 2830 if (ifp->if_flags & IFF_UP) { 2831 /* 2832 * If only the state of the PROMISC flag changed, 2833 * then just use the 'set promisc mode' command 2834 * instead of reinitializing the entire NIC. Doing 2835 * a full re-init means reloading the firmware and 2836 * waiting for it to start up, which may take a 2837 * second or two. 2838 */ 2839 if (ifp->if_flags & IFF_RUNNING && 2840 ifp->if_flags & IFF_PROMISC && 2841 !(sc->ti_if_flags & IFF_PROMISC)) { 2842 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2843 TI_CMD_CODE_PROMISC_ENB, 0); 2844 } else if (ifp->if_flags & IFF_RUNNING && 2845 !(ifp->if_flags & IFF_PROMISC) && 2846 sc->ti_if_flags & IFF_PROMISC) { 2847 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2848 TI_CMD_CODE_PROMISC_DIS, 0); 2849 } else 2850 ti_init(sc); 2851 } else { 2852 if (ifp->if_flags & IFF_RUNNING) { 2853 ti_stop(sc); 2854 } 2855 } 2856 sc->ti_if_flags = ifp->if_flags; 2857 error = 0; 2858 break; 2859 case SIOCADDMULTI: 2860 case SIOCDELMULTI: 2861 error = (command == SIOCADDMULTI) ? 2862 ether_addmulti(ifr, &sc->ethercom) : 2863 ether_delmulti(ifr, &sc->ethercom); 2864 if (error == ENETRESET) { 2865 if (ifp->if_flags & IFF_RUNNING) 2866 ti_setmulti(sc); 2867 error = 0; 2868 } 2869 break; 2870 case SIOCSIFMEDIA: 2871 case SIOCGIFMEDIA: 2872 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2873 break; 2874 default: 2875 error = EINVAL; 2876 break; 2877 } 2878 2879 (void)splx(s); 2880 2881 return(error); 2882 } 2883 2884 static void ti_watchdog(ifp) 2885 struct ifnet *ifp; 2886 { 2887 struct ti_softc *sc; 2888 2889 sc = ifp->if_softc; 2890 2891 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2892 ti_stop(sc); 2893 ti_init(sc); 2894 2895 ifp->if_oerrors++; 2896 2897 return; 2898 } 2899 2900 /* 2901 * Stop the adapter and free any mbufs allocated to the 2902 * RX and TX lists. 2903 */ 2904 static void ti_stop(sc) 2905 struct ti_softc *sc; 2906 { 2907 struct ifnet *ifp; 2908 struct ti_cmd_desc cmd; 2909 2910 ifp = &sc->ethercom.ec_if; 2911 2912 /* Disable host interrupts. */ 2913 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2914 /* 2915 * Tell firmware we're shutting down. 2916 */ 2917 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2918 2919 /* Halt and reinitialize. */ 2920 ti_chipinit(sc); 2921 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2922 ti_chipinit(sc); 2923 2924 /* Free the RX lists. */ 2925 ti_free_rx_ring_std(sc); 2926 2927 /* Free jumbo RX list. */ 2928 ti_free_rx_ring_jumbo(sc); 2929 2930 /* Free mini RX list. */ 2931 ti_free_rx_ring_mini(sc); 2932 2933 /* Free TX buffers. */ 2934 ti_free_tx_ring(sc); 2935 2936 sc->ti_ev_prodidx.ti_idx = 0; 2937 sc->ti_return_prodidx.ti_idx = 0; 2938 sc->ti_tx_considx.ti_idx = 0; 2939 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2940 2941 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2942 2943 return; 2944 } 2945 2946 /* 2947 * Stop all chip I/O so that the kernel's probe routines don't 2948 * get confused by errant DMAs when rebooting. 2949 */ 2950 static void ti_shutdown(v) 2951 void *v; 2952 { 2953 struct ti_softc *sc = v; 2954 2955 ti_chipinit(sc); 2956 2957 return; 2958 } 2959
Indexes created Fri Sep 26 20:09:58 GMT 2025