if_ti.c revision 1.72
1 /* $NetBSD: if_ti.c,v 1.72 2006/10/12 01:31:30 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.72 2006/10/12 01:31:30 christos Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/device.h> 98 #include <sys/reboot.h> 99 100 #include <uvm/uvm_extern.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/if_ether.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/ip.h> 117 #endif 118 119 120 #include <machine/bus.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_tireg.h> 127 128 #include <dev/microcode/tigon/ti_fw.h> 129 #include <dev/microcode/tigon/ti_fw2.h> 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 135 static const struct ti_type ti_devs[] = { 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 137 "Alteon AceNIC 1000BASE-SX Ethernet" }, 138 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 139 "Alteon AceNIC 1000BASE-T Ethernet" }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 143 "Netgear GA620 1000BASE-SX Ethernet" }, 144 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 145 "Netgear GA620 1000BASE-T Ethernet" }, 146 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { 0, 0, NULL } 149 }; 150 151 static const struct ti_type *ti_type_match(struct pci_attach_args *); 152 static int ti_probe(struct device *, struct cfdata *, void *); 153 static void ti_attach(struct device *, struct device *, void *); 154 static void ti_shutdown(void *); 155 static void ti_txeof_tigon1(struct ti_softc *); 156 static void ti_txeof_tigon2(struct ti_softc *); 157 static void ti_rxeof(struct ti_softc *); 158 159 static void ti_stats_update(struct ti_softc *); 160 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 161 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 162 163 static int ti_intr(void *); 164 static void ti_start(struct ifnet *); 165 static int ti_ioctl(struct ifnet *, u_long, caddr_t); 166 static void ti_init(void *); 167 static void ti_init2(struct ti_softc *); 168 static void ti_stop(struct ti_softc *); 169 static void ti_watchdog(struct ifnet *); 170 static int ti_ifmedia_upd(struct ifnet *); 171 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 172 173 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 174 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 175 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int); 176 177 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 178 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 179 static void ti_setmulti(struct ti_softc *); 180 181 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 182 static void ti_loadfw(struct ti_softc *); 183 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 184 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, caddr_t, int); 185 static void ti_handle_events(struct ti_softc *); 186 static int ti_alloc_jumbo_mem(struct ti_softc *); 187 static void *ti_jalloc(struct ti_softc *); 188 static void ti_jfree(struct mbuf *, caddr_t, size_t, void *); 189 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 190 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 191 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 192 static int ti_init_rx_ring_std(struct ti_softc *); 193 static void ti_free_rx_ring_std(struct ti_softc *); 194 static int ti_init_rx_ring_jumbo(struct ti_softc *); 195 static void ti_free_rx_ring_jumbo(struct ti_softc *); 196 static int ti_init_rx_ring_mini(struct ti_softc *); 197 static void ti_free_rx_ring_mini(struct ti_softc *); 198 static void ti_free_tx_ring(struct ti_softc *); 199 static int ti_init_tx_ring(struct ti_softc *); 200 201 static int ti_64bitslot_war(struct ti_softc *); 202 static int ti_chipinit(struct ti_softc *); 203 static int ti_gibinit(struct ti_softc *); 204 205 static int ti_ether_ioctl(struct ifnet *, u_long, caddr_t); 206 207 CFATTACH_DECL(ti, sizeof(struct ti_softc), 208 ti_probe, ti_attach, NULL, NULL); 209 210 /* 211 * Send an instruction or address to the EEPROM, check for ACK. 212 */ 213 static u_int32_t ti_eeprom_putbyte(sc, byte) 214 struct ti_softc *sc; 215 int byte; 216 { 217 int i, ack = 0; 218 219 /* 220 * Make sure we're in TX mode. 221 */ 222 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 223 224 /* 225 * Feed in each bit and stobe the clock. 226 */ 227 for (i = 0x80; i; i >>= 1) { 228 if (byte & i) { 229 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 230 } else { 231 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 232 } 233 DELAY(1); 234 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 235 DELAY(1); 236 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 237 } 238 239 /* 240 * Turn off TX mode. 241 */ 242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 243 244 /* 245 * Check for ack. 246 */ 247 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 249 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 250 251 return(ack); 252 } 253 254 /* 255 * Read a byte of data stored in the EEPROM at address 'addr.' 256 * We have to send two address bytes since the EEPROM can hold 257 * more than 256 bytes of data. 258 */ 259 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 260 struct ti_softc *sc; 261 int addr; 262 u_int8_t *dest; 263 { 264 int i; 265 u_int8_t byte = 0; 266 267 EEPROM_START; 268 269 /* 270 * Send write control code to EEPROM. 271 */ 272 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 273 printf("%s: failed to send write command, status: %x\n", 274 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 275 return(1); 276 } 277 278 /* 279 * Send first byte of address of byte we want to read. 280 */ 281 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 282 printf("%s: failed to send address, status: %x\n", 283 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 284 return(1); 285 } 286 /* 287 * Send second byte address of byte we want to read. 288 */ 289 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 290 printf("%s: failed to send address, status: %x\n", 291 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 292 return(1); 293 } 294 295 EEPROM_STOP; 296 EEPROM_START; 297 /* 298 * Send read control code to EEPROM. 299 */ 300 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 301 printf("%s: failed to send read command, status: %x\n", 302 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 306 /* 307 * Start reading bits from EEPROM. 308 */ 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 310 for (i = 0x80; i; i >>= 1) { 311 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 312 DELAY(1); 313 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 314 byte |= i; 315 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 DELAY(1); 317 } 318 319 EEPROM_STOP; 320 321 /* 322 * No ACK generated for read, so just return byte. 323 */ 324 325 *dest = byte; 326 327 return(0); 328 } 329 330 /* 331 * Read a sequence of bytes from the EEPROM. 332 */ 333 static int ti_read_eeprom(sc, dest, off, cnt) 334 struct ti_softc *sc; 335 caddr_t dest; 336 int off; 337 int cnt; 338 { 339 int err = 0, i; 340 u_int8_t byte = 0; 341 342 for (i = 0; i < cnt; i++) { 343 err = ti_eeprom_getbyte(sc, off + i, &byte); 344 if (err) 345 break; 346 *(dest + i) = byte; 347 } 348 349 return(err ? 1 : 0); 350 } 351 352 /* 353 * NIC memory access function. Can be used to either clear a section 354 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 355 */ 356 static void ti_mem(sc, addr, len, xbuf) 357 struct ti_softc *sc; 358 u_int32_t addr, len; 359 const void *xbuf; 360 { 361 int segptr, segsize, cnt; 362 const void *ptr; 363 364 segptr = addr; 365 cnt = len; 366 ptr = xbuf; 367 368 while(cnt) { 369 if (cnt < TI_WINLEN) 370 segsize = cnt; 371 else 372 segsize = TI_WINLEN - (segptr % TI_WINLEN); 373 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 374 if (xbuf == NULL) { 375 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 376 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 377 segsize / 4); 378 } else { 379 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 380 bus_space_write_region_stream_4(sc->ti_btag, 381 sc->ti_bhandle, 382 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 383 (const u_int32_t *)ptr, segsize / 4); 384 #else 385 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 387 (const u_int32_t *)ptr, segsize / 4); 388 #endif 389 ptr = (const char *)ptr + segsize; 390 } 391 segptr += segsize; 392 cnt -= segsize; 393 } 394 395 return; 396 } 397 398 /* 399 * Load firmware image into the NIC. Check that the firmware revision 400 * is acceptable and see if we want the firmware for the Tigon 1 or 401 * Tigon 2. 402 */ 403 static void ti_loadfw(sc) 404 struct ti_softc *sc; 405 { 406 switch(sc->ti_hwrev) { 407 case TI_HWREV_TIGON: 408 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 409 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 410 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 411 printf("%s: firmware revision mismatch; want " 412 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 413 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 414 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 415 tigonFwReleaseMinor, tigonFwReleaseFix); 416 return; 417 } 418 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 419 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 420 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 421 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 422 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 423 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 424 break; 425 case TI_HWREV_TIGON_II: 426 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 427 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 428 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 429 printf("%s: firmware revision mismatch; want " 430 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 431 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 432 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 433 tigon2FwReleaseMinor, tigon2FwReleaseFix); 434 return; 435 } 436 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 437 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 438 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 439 tigon2FwRodata); 440 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 441 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 442 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 443 break; 444 default: 445 printf("%s: can't load firmware: unknown hardware rev\n", 446 sc->sc_dev.dv_xname); 447 break; 448 } 449 450 return; 451 } 452 453 /* 454 * Send the NIC a command via the command ring. 455 */ 456 static void ti_cmd(sc, cmd) 457 struct ti_softc *sc; 458 struct ti_cmd_desc *cmd; 459 { 460 u_int32_t index; 461 462 index = sc->ti_cmd_saved_prodidx; 463 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 464 TI_INC(index, TI_CMD_RING_CNT); 465 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 466 sc->ti_cmd_saved_prodidx = index; 467 468 return; 469 } 470 471 /* 472 * Send the NIC an extended command. The 'len' parameter specifies the 473 * number of command slots to include after the initial command. 474 */ 475 static void ti_cmd_ext(sc, cmd, arg, len) 476 struct ti_softc *sc; 477 struct ti_cmd_desc *cmd; 478 caddr_t arg; 479 int len; 480 { 481 u_int32_t index; 482 int i; 483 484 index = sc->ti_cmd_saved_prodidx; 485 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 486 TI_INC(index, TI_CMD_RING_CNT); 487 for (i = 0; i < len; i++) { 488 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 489 *(u_int32_t *)(&arg[i * 4])); 490 TI_INC(index, TI_CMD_RING_CNT); 491 } 492 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 493 sc->ti_cmd_saved_prodidx = index; 494 495 return; 496 } 497 498 /* 499 * Handle events that have triggered interrupts. 500 */ 501 static void ti_handle_events(sc) 502 struct ti_softc *sc; 503 { 504 struct ti_event_desc *e; 505 506 if (sc->ti_rdata->ti_event_ring == NULL) 507 return; 508 509 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 510 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 511 switch(e->ti_event) { 512 case TI_EV_LINKSTAT_CHANGED: 513 sc->ti_linkstat = e->ti_code; 514 if (e->ti_code == TI_EV_CODE_LINK_UP) 515 printf("%s: 10/100 link up\n", 516 sc->sc_dev.dv_xname); 517 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 518 printf("%s: gigabit link up\n", 519 sc->sc_dev.dv_xname); 520 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 521 printf("%s: link down\n", 522 sc->sc_dev.dv_xname); 523 break; 524 case TI_EV_ERROR: 525 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 526 printf("%s: invalid command\n", 527 sc->sc_dev.dv_xname); 528 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 529 printf("%s: unknown command\n", 530 sc->sc_dev.dv_xname); 531 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 532 printf("%s: bad config data\n", 533 sc->sc_dev.dv_xname); 534 break; 535 case TI_EV_FIRMWARE_UP: 536 ti_init2(sc); 537 break; 538 case TI_EV_STATS_UPDATED: 539 ti_stats_update(sc); 540 break; 541 case TI_EV_RESET_JUMBO_RING: 542 case TI_EV_MCAST_UPDATED: 543 /* Who cares. */ 544 break; 545 default: 546 printf("%s: unknown event: %d\n", 547 sc->sc_dev.dv_xname, e->ti_event); 548 break; 549 } 550 /* Advance the consumer index. */ 551 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 552 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 553 } 554 555 return; 556 } 557 558 /* 559 * Memory management for the jumbo receive ring is a pain in the 560 * butt. We need to allocate at least 9018 bytes of space per frame, 561 * _and_ it has to be contiguous (unless you use the extended 562 * jumbo descriptor format). Using malloc() all the time won't 563 * work: malloc() allocates memory in powers of two, which means we 564 * would end up wasting a considerable amount of space by allocating 565 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 566 * to do our own memory management. 567 * 568 * The driver needs to allocate a contiguous chunk of memory at boot 569 * time. We then chop this up ourselves into 9K pieces and use them 570 * as external mbuf storage. 571 * 572 * One issue here is how much memory to allocate. The jumbo ring has 573 * 256 slots in it, but at 9K per slot than can consume over 2MB of 574 * RAM. This is a bit much, especially considering we also need 575 * RAM for the standard ring and mini ring (on the Tigon 2). To 576 * save space, we only actually allocate enough memory for 64 slots 577 * by default, which works out to between 500 and 600K. This can 578 * be tuned by changing a #define in if_tireg.h. 579 */ 580 581 static int ti_alloc_jumbo_mem(sc) 582 struct ti_softc *sc; 583 { 584 caddr_t ptr; 585 int i; 586 struct ti_jpool_entry *entry; 587 bus_dma_segment_t dmaseg; 588 int error, dmanseg; 589 590 /* Grab a big chunk o' storage. */ 591 if ((error = bus_dmamem_alloc(sc->sc_dmat, 592 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 593 BUS_DMA_NOWAIT)) != 0) { 594 printf("%s: can't allocate jumbo buffer, error = %d\n", 595 sc->sc_dev.dv_xname, error); 596 return (error); 597 } 598 599 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 600 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 601 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 602 printf("%s: can't map jumbo buffer, error = %d\n", 603 sc->sc_dev.dv_xname, error); 604 return (error); 605 } 606 607 if ((error = bus_dmamap_create(sc->sc_dmat, 608 TI_JMEM, 1, 609 TI_JMEM, 0, BUS_DMA_NOWAIT, 610 &sc->jumbo_dmamap)) != 0) { 611 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 612 sc->sc_dev.dv_xname, error); 613 return (error); 614 } 615 616 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 617 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 618 BUS_DMA_NOWAIT)) != 0) { 619 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 620 sc->sc_dev.dv_xname, error); 621 return (error); 622 } 623 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 624 625 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 626 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 627 628 /* 629 * Now divide it up into 9K pieces and save the addresses 630 * in an array. 631 */ 632 ptr = sc->ti_cdata.ti_jumbo_buf; 633 for (i = 0; i < TI_JSLOTS; i++) { 634 sc->ti_cdata.ti_jslots[i] = ptr; 635 ptr += TI_JLEN; 636 entry = malloc(sizeof(struct ti_jpool_entry), 637 M_DEVBUF, M_NOWAIT); 638 if (entry == NULL) { 639 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 640 sc->ti_cdata.ti_jumbo_buf = NULL; 641 printf("%s: no memory for jumbo " 642 "buffer queue!\n", sc->sc_dev.dv_xname); 643 return(ENOBUFS); 644 } 645 entry->slot = i; 646 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 647 jpool_entries); 648 } 649 650 return(0); 651 } 652 653 /* 654 * Allocate a jumbo buffer. 655 */ 656 static void *ti_jalloc(sc) 657 struct ti_softc *sc; 658 { 659 struct ti_jpool_entry *entry; 660 661 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 662 663 if (entry == NULL) { 664 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 665 return(NULL); 666 } 667 668 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 669 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 670 return(sc->ti_cdata.ti_jslots[entry->slot]); 671 } 672 673 /* 674 * Release a jumbo buffer. 675 */ 676 static void ti_jfree(struct mbuf *m, caddr_t tbuf, size_t size __unused, 677 void *arg) 678 { 679 struct ti_softc *sc; 680 int i, s; 681 struct ti_jpool_entry *entry; 682 683 /* Extract the softc struct pointer. */ 684 sc = (struct ti_softc *)arg; 685 686 if (sc == NULL) 687 panic("ti_jfree: didn't get softc pointer!"); 688 689 /* calculate the slot this buffer belongs to */ 690 691 i = ((caddr_t)tbuf 692 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 693 694 if ((i < 0) || (i >= TI_JSLOTS)) 695 panic("ti_jfree: asked to free buffer that we don't manage!"); 696 697 s = splvm(); 698 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 699 if (entry == NULL) 700 panic("ti_jfree: buffer not in use!"); 701 entry->slot = i; 702 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 703 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 704 705 if (__predict_true(m != NULL)) 706 pool_cache_put(&mbpool_cache, m); 707 splx(s); 708 } 709 710 711 /* 712 * Intialize a standard receive ring descriptor. 713 */ 714 static int ti_newbuf_std(sc, i, m, dmamap) 715 struct ti_softc *sc; 716 int i; 717 struct mbuf *m; 718 bus_dmamap_t dmamap; /* required if (m != NULL) */ 719 { 720 struct mbuf *m_new = NULL; 721 struct ti_rx_desc *r; 722 int error; 723 724 if (dmamap == NULL) { 725 /* if (m) panic() */ 726 727 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 728 MCLBYTES, 0, BUS_DMA_NOWAIT, 729 &dmamap)) != 0) { 730 printf("%s: can't create recv map, error = %d\n", 731 sc->sc_dev.dv_xname, error); 732 return(ENOMEM); 733 } 734 } 735 sc->std_dmamap[i] = dmamap; 736 737 if (m == NULL) { 738 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 739 if (m_new == NULL) { 740 printf("%s: mbuf allocation failed " 741 "-- packet dropped!\n", sc->sc_dev.dv_xname); 742 return(ENOBUFS); 743 } 744 745 MCLGET(m_new, M_DONTWAIT); 746 if (!(m_new->m_flags & M_EXT)) { 747 printf("%s: cluster allocation failed " 748 "-- packet dropped!\n", sc->sc_dev.dv_xname); 749 m_freem(m_new); 750 return(ENOBUFS); 751 } 752 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 753 m_adj(m_new, ETHER_ALIGN); 754 755 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 756 mtod(m_new, caddr_t), m_new->m_len, NULL, 757 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 758 printf("%s: can't load recv map, error = %d\n", 759 sc->sc_dev.dv_xname, error); 760 return (ENOMEM); 761 } 762 } else { 763 m_new = m; 764 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 765 m_new->m_data = m_new->m_ext.ext_buf; 766 m_adj(m_new, ETHER_ALIGN); 767 768 /* reuse the dmamap */ 769 } 770 771 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 772 r = &sc->ti_rdata->ti_rx_std_ring[i]; 773 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 774 r->ti_type = TI_BDTYPE_RECV_BD; 775 r->ti_flags = 0; 776 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 777 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 778 if (sc->ethercom.ec_if.if_capenable & 779 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 780 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 781 r->ti_len = m_new->m_len; /* == ds_len */ 782 r->ti_idx = i; 783 784 return(0); 785 } 786 787 /* 788 * Intialize a mini receive ring descriptor. This only applies to 789 * the Tigon 2. 790 */ 791 static int ti_newbuf_mini(sc, i, m, dmamap) 792 struct ti_softc *sc; 793 int i; 794 struct mbuf *m; 795 bus_dmamap_t dmamap; /* required if (m != NULL) */ 796 { 797 struct mbuf *m_new = NULL; 798 struct ti_rx_desc *r; 799 int error; 800 801 if (dmamap == NULL) { 802 /* if (m) panic() */ 803 804 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 805 MHLEN, 0, BUS_DMA_NOWAIT, 806 &dmamap)) != 0) { 807 printf("%s: can't create recv map, error = %d\n", 808 sc->sc_dev.dv_xname, error); 809 return(ENOMEM); 810 } 811 } 812 sc->mini_dmamap[i] = dmamap; 813 814 if (m == NULL) { 815 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 816 if (m_new == NULL) { 817 printf("%s: mbuf allocation failed " 818 "-- packet dropped!\n", sc->sc_dev.dv_xname); 819 return(ENOBUFS); 820 } 821 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 822 m_adj(m_new, ETHER_ALIGN); 823 824 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 825 mtod(m_new, caddr_t), m_new->m_len, NULL, 826 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 827 printf("%s: can't load recv map, error = %d\n", 828 sc->sc_dev.dv_xname, error); 829 return (ENOMEM); 830 } 831 } else { 832 m_new = m; 833 m_new->m_data = m_new->m_pktdat; 834 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 835 m_adj(m_new, ETHER_ALIGN); 836 837 /* reuse the dmamap */ 838 } 839 840 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 841 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 842 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 843 r->ti_type = TI_BDTYPE_RECV_BD; 844 r->ti_flags = TI_BDFLAG_MINI_RING; 845 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 846 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 847 if (sc->ethercom.ec_if.if_capenable & 848 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 849 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 850 r->ti_len = m_new->m_len; /* == ds_len */ 851 r->ti_idx = i; 852 853 return(0); 854 } 855 856 /* 857 * Initialize a jumbo receive ring descriptor. This allocates 858 * a jumbo buffer from the pool managed internally by the driver. 859 */ 860 static int ti_newbuf_jumbo(sc, i, m) 861 struct ti_softc *sc; 862 int i; 863 struct mbuf *m; 864 { 865 struct mbuf *m_new = NULL; 866 struct ti_rx_desc *r; 867 868 if (m == NULL) { 869 caddr_t tbuf = NULL; 870 871 /* Allocate the mbuf. */ 872 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 873 if (m_new == NULL) { 874 printf("%s: mbuf allocation failed " 875 "-- packet dropped!\n", sc->sc_dev.dv_xname); 876 return(ENOBUFS); 877 } 878 879 /* Allocate the jumbo buffer */ 880 tbuf = ti_jalloc(sc); 881 if (tbuf == NULL) { 882 m_freem(m_new); 883 printf("%s: jumbo allocation failed " 884 "-- packet dropped!\n", sc->sc_dev.dv_xname); 885 return(ENOBUFS); 886 } 887 888 /* Attach the buffer to the mbuf. */ 889 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 890 M_DEVBUF, ti_jfree, sc); 891 m_new->m_flags |= M_EXT_RW; 892 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 893 } else { 894 m_new = m; 895 m_new->m_data = m_new->m_ext.ext_buf; 896 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 897 } 898 899 m_adj(m_new, ETHER_ALIGN); 900 /* Set up the descriptor. */ 901 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 902 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 903 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 904 ((caddr_t)mtod(m_new, caddr_t) 905 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 906 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 907 r->ti_flags = TI_BDFLAG_JUMBO_RING; 908 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 909 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 910 if (sc->ethercom.ec_if.if_capenable & 911 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 912 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 913 r->ti_len = m_new->m_len; 914 r->ti_idx = i; 915 916 return(0); 917 } 918 919 /* 920 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 921 * that's 1MB or memory, which is a lot. For now, we fill only the first 922 * 256 ring entries and hope that our CPU is fast enough to keep up with 923 * the NIC. 924 */ 925 static int ti_init_rx_ring_std(sc) 926 struct ti_softc *sc; 927 { 928 int i; 929 struct ti_cmd_desc cmd; 930 931 for (i = 0; i < TI_SSLOTS; i++) { 932 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 933 return(ENOBUFS); 934 }; 935 936 TI_UPDATE_STDPROD(sc, i - 1); 937 sc->ti_std = i - 1; 938 939 return(0); 940 } 941 942 static void ti_free_rx_ring_std(sc) 943 struct ti_softc *sc; 944 { 945 int i; 946 947 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 948 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 949 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 950 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 951 952 /* if (sc->std_dmamap[i] == 0) panic() */ 953 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 954 sc->std_dmamap[i] = 0; 955 } 956 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 957 sizeof(struct ti_rx_desc)); 958 } 959 960 return; 961 } 962 963 static int ti_init_rx_ring_jumbo(sc) 964 struct ti_softc *sc; 965 { 966 int i; 967 struct ti_cmd_desc cmd; 968 969 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 970 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 971 return(ENOBUFS); 972 }; 973 974 TI_UPDATE_JUMBOPROD(sc, i - 1); 975 sc->ti_jumbo = i - 1; 976 977 return(0); 978 } 979 980 static void ti_free_rx_ring_jumbo(sc) 981 struct ti_softc *sc; 982 { 983 int i; 984 985 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 986 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 987 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 988 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 989 } 990 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 991 sizeof(struct ti_rx_desc)); 992 } 993 994 return; 995 } 996 997 static int ti_init_rx_ring_mini(sc) 998 struct ti_softc *sc; 999 { 1000 int i; 1001 1002 for (i = 0; i < TI_MSLOTS; i++) { 1003 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1004 return(ENOBUFS); 1005 }; 1006 1007 TI_UPDATE_MINIPROD(sc, i - 1); 1008 sc->ti_mini = i - 1; 1009 1010 return(0); 1011 } 1012 1013 static void ti_free_rx_ring_mini(sc) 1014 struct ti_softc *sc; 1015 { 1016 int i; 1017 1018 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1019 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1020 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1021 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1022 1023 /* if (sc->mini_dmamap[i] == 0) panic() */ 1024 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1025 sc->mini_dmamap[i] = 0; 1026 } 1027 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1028 sizeof(struct ti_rx_desc)); 1029 } 1030 1031 return; 1032 } 1033 1034 static void ti_free_tx_ring(sc) 1035 struct ti_softc *sc; 1036 { 1037 int i; 1038 struct txdmamap_pool_entry *dma; 1039 1040 if (sc->ti_rdata->ti_tx_ring == NULL) 1041 return; 1042 1043 for (i = 0; i < TI_TX_RING_CNT; i++) { 1044 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1045 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1046 sc->ti_cdata.ti_tx_chain[i] = NULL; 1047 1048 /* if (sc->txdma[i] == 0) panic() */ 1049 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1050 link); 1051 sc->txdma[i] = 0; 1052 } 1053 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1054 sizeof(struct ti_tx_desc)); 1055 } 1056 1057 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1058 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1059 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1060 free(dma, M_DEVBUF); 1061 } 1062 1063 return; 1064 } 1065 1066 static int ti_init_tx_ring(sc) 1067 struct ti_softc *sc; 1068 { 1069 int i, error; 1070 bus_dmamap_t dmamap; 1071 struct txdmamap_pool_entry *dma; 1072 1073 sc->ti_txcnt = 0; 1074 sc->ti_tx_saved_considx = 0; 1075 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1076 1077 SIMPLEQ_INIT(&sc->txdma_list); 1078 for (i = 0; i < TI_RSLOTS; i++) { 1079 /* I've seen mbufs with 30 fragments. */ 1080 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1081 40, ETHER_MAX_LEN_JUMBO, 0, 1082 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1083 printf("%s: can't create tx map, error = %d\n", 1084 sc->sc_dev.dv_xname, error); 1085 return(ENOMEM); 1086 } 1087 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1088 if (!dma) { 1089 printf("%s: can't alloc txdmamap_pool_entry\n", 1090 sc->sc_dev.dv_xname); 1091 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1092 return (ENOMEM); 1093 } 1094 dma->dmamap = dmamap; 1095 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1096 } 1097 1098 return(0); 1099 } 1100 1101 /* 1102 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1103 * but we have to support the old way too so that Tigon 1 cards will 1104 * work. 1105 */ 1106 void ti_add_mcast(sc, addr) 1107 struct ti_softc *sc; 1108 struct ether_addr *addr; 1109 { 1110 struct ti_cmd_desc cmd; 1111 u_int16_t *m; 1112 u_int32_t ext[2] = {0, 0}; 1113 1114 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1115 1116 switch(sc->ti_hwrev) { 1117 case TI_HWREV_TIGON: 1118 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1119 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1120 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1121 break; 1122 case TI_HWREV_TIGON_II: 1123 ext[0] = htons(m[0]); 1124 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1125 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1126 break; 1127 default: 1128 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1129 break; 1130 } 1131 1132 return; 1133 } 1134 1135 void ti_del_mcast(sc, addr) 1136 struct ti_softc *sc; 1137 struct ether_addr *addr; 1138 { 1139 struct ti_cmd_desc cmd; 1140 u_int16_t *m; 1141 u_int32_t ext[2] = {0, 0}; 1142 1143 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1144 1145 switch(sc->ti_hwrev) { 1146 case TI_HWREV_TIGON: 1147 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1148 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1149 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1150 break; 1151 case TI_HWREV_TIGON_II: 1152 ext[0] = htons(m[0]); 1153 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1154 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1155 break; 1156 default: 1157 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1158 break; 1159 } 1160 1161 return; 1162 } 1163 1164 /* 1165 * Configure the Tigon's multicast address filter. 1166 * 1167 * The actual multicast table management is a bit of a pain, thanks to 1168 * slight brain damage on the part of both Alteon and us. With our 1169 * multicast code, we are only alerted when the multicast address table 1170 * changes and at that point we only have the current list of addresses: 1171 * we only know the current state, not the previous state, so we don't 1172 * actually know what addresses were removed or added. The firmware has 1173 * state, but we can't get our grubby mits on it, and there is no 'delete 1174 * all multicast addresses' command. Hence, we have to maintain our own 1175 * state so we know what addresses have been programmed into the NIC at 1176 * any given time. 1177 */ 1178 static void ti_setmulti(sc) 1179 struct ti_softc *sc; 1180 { 1181 struct ifnet *ifp; 1182 struct ti_cmd_desc cmd; 1183 struct ti_mc_entry *mc; 1184 u_int32_t intrs; 1185 struct ether_multi *enm; 1186 struct ether_multistep step; 1187 1188 ifp = &sc->ethercom.ec_if; 1189 1190 /* Disable interrupts. */ 1191 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1192 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1193 1194 /* First, zot all the existing filters. */ 1195 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1196 ti_del_mcast(sc, &mc->mc_addr); 1197 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1198 free(mc, M_DEVBUF); 1199 } 1200 1201 /* 1202 * Remember all multicast addresses so that we can delete them 1203 * later. Punt if there is a range of addresses or memory shortage. 1204 */ 1205 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1206 while (enm != NULL) { 1207 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1208 ETHER_ADDR_LEN) != 0) 1209 goto allmulti; 1210 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1211 M_NOWAIT)) == NULL) 1212 goto allmulti; 1213 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1214 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1215 ETHER_NEXT_MULTI(step, enm); 1216 } 1217 1218 /* Accept only programmed multicast addresses */ 1219 ifp->if_flags &= ~IFF_ALLMULTI; 1220 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1221 1222 /* Now program new ones. */ 1223 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1224 ti_add_mcast(sc, &mc->mc_addr); 1225 1226 /* Re-enable interrupts. */ 1227 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1228 1229 return; 1230 1231 allmulti: 1232 /* No need to keep individual multicast addresses */ 1233 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1234 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1235 free(mc, M_DEVBUF); 1236 } 1237 1238 /* Accept all multicast addresses */ 1239 ifp->if_flags |= IFF_ALLMULTI; 1240 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1241 1242 /* Re-enable interrupts. */ 1243 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1244 } 1245 1246 /* 1247 * Check to see if the BIOS has configured us for a 64 bit slot when 1248 * we aren't actually in one. If we detect this condition, we can work 1249 * around it on the Tigon 2 by setting a bit in the PCI state register, 1250 * but for the Tigon 1 we must give up and abort the interface attach. 1251 */ 1252 static int ti_64bitslot_war(sc) 1253 struct ti_softc *sc; 1254 { 1255 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1256 CSR_WRITE_4(sc, 0x600, 0); 1257 CSR_WRITE_4(sc, 0x604, 0); 1258 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1259 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1260 if (sc->ti_hwrev == TI_HWREV_TIGON) 1261 return(EINVAL); 1262 else { 1263 TI_SETBIT(sc, TI_PCI_STATE, 1264 TI_PCISTATE_32BIT_BUS); 1265 return(0); 1266 } 1267 } 1268 } 1269 1270 return(0); 1271 } 1272 1273 /* 1274 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1275 * self-test results. 1276 */ 1277 static int ti_chipinit(sc) 1278 struct ti_softc *sc; 1279 { 1280 u_int32_t cacheline; 1281 u_int32_t pci_writemax = 0; 1282 u_int32_t rev; 1283 1284 /* Initialize link to down state. */ 1285 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1286 1287 /* Set endianness before we access any non-PCI registers. */ 1288 #if BYTE_ORDER == BIG_ENDIAN 1289 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1290 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1291 #else 1292 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1293 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1294 #endif 1295 1296 /* Check the ROM failed bit to see if self-tests passed. */ 1297 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1298 printf("%s: board self-diagnostics failed!\n", 1299 sc->sc_dev.dv_xname); 1300 return(ENODEV); 1301 } 1302 1303 /* Halt the CPU. */ 1304 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1305 1306 /* Figure out the hardware revision. */ 1307 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1308 switch(rev) { 1309 case TI_REV_TIGON_I: 1310 sc->ti_hwrev = TI_HWREV_TIGON; 1311 break; 1312 case TI_REV_TIGON_II: 1313 sc->ti_hwrev = TI_HWREV_TIGON_II; 1314 break; 1315 default: 1316 printf("%s: unsupported chip revision 0x%x\n", 1317 sc->sc_dev.dv_xname, rev); 1318 return(ENODEV); 1319 } 1320 1321 /* Do special setup for Tigon 2. */ 1322 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1323 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1324 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1325 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1326 } 1327 1328 /* Set up the PCI state register. */ 1329 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1330 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1331 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1332 } 1333 1334 /* Clear the read/write max DMA parameters. */ 1335 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1336 TI_PCISTATE_READ_MAXDMA)); 1337 1338 /* Get cache line size. */ 1339 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1340 1341 /* 1342 * If the system has set enabled the PCI memory write 1343 * and invalidate command in the command register, set 1344 * the write max parameter accordingly. This is necessary 1345 * to use MWI with the Tigon 2. 1346 */ 1347 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1348 & PCI_COMMAND_INVALIDATE_ENABLE) { 1349 switch(cacheline) { 1350 case 1: 1351 case 4: 1352 case 8: 1353 case 16: 1354 case 32: 1355 case 64: 1356 break; 1357 default: 1358 /* Disable PCI memory write and invalidate. */ 1359 if (bootverbose) 1360 printf("%s: cache line size %d not " 1361 "supported; disabling PCI MWI\n", 1362 sc->sc_dev.dv_xname, cacheline); 1363 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1364 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1365 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1366 break; 1367 } 1368 } 1369 1370 #ifdef __brokenalpha__ 1371 /* 1372 * From the Alteon sample driver: 1373 * Must insure that we do not cross an 8K (bytes) boundary 1374 * for DMA reads. Our highest limit is 1K bytes. This is a 1375 * restriction on some ALPHA platforms with early revision 1376 * 21174 PCI chipsets, such as the AlphaPC 164lx 1377 */ 1378 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1379 #else 1380 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1381 #endif 1382 1383 /* This sets the min dma param all the way up (0xff). */ 1384 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1385 1386 /* Configure DMA variables. */ 1387 #if BYTE_ORDER == BIG_ENDIAN 1388 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1389 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1390 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1391 TI_OPMODE_DONT_FRAG_JUMBO); 1392 #else 1393 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1394 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1395 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1396 #endif 1397 1398 /* 1399 * Only allow 1 DMA channel to be active at a time. 1400 * I don't think this is a good idea, but without it 1401 * the firmware racks up lots of nicDmaReadRingFull 1402 * errors. 1403 * Incompatible with hardware assisted checksums. 1404 */ 1405 if ((sc->ethercom.ec_if.if_capenable & 1406 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1407 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1408 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1409 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1410 1411 /* Recommended settings from Tigon manual. */ 1412 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1413 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1414 1415 if (ti_64bitslot_war(sc)) { 1416 printf("%s: bios thinks we're in a 64 bit slot, " 1417 "but we aren't", sc->sc_dev.dv_xname); 1418 return(EINVAL); 1419 } 1420 1421 return(0); 1422 } 1423 1424 /* 1425 * Initialize the general information block and firmware, and 1426 * start the CPU(s) running. 1427 */ 1428 static int ti_gibinit(sc) 1429 struct ti_softc *sc; 1430 { 1431 struct ti_rcb *rcb; 1432 int i; 1433 struct ifnet *ifp; 1434 1435 ifp = &sc->ethercom.ec_if; 1436 1437 /* Disable interrupts for now. */ 1438 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1439 1440 /* Tell the chip where to find the general information block. */ 1441 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1442 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1443 1444 /* Load the firmware into SRAM. */ 1445 ti_loadfw(sc); 1446 1447 /* Set up the contents of the general info and ring control blocks. */ 1448 1449 /* Set up the event ring and producer pointer. */ 1450 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1451 1452 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1453 rcb->ti_flags = 0; 1454 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1455 TI_CDEVPRODADDR(sc); 1456 1457 sc->ti_ev_prodidx.ti_idx = 0; 1458 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1459 sc->ti_ev_saved_considx = 0; 1460 1461 /* Set up the command ring and producer mailbox. */ 1462 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1463 1464 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1465 rcb->ti_flags = 0; 1466 rcb->ti_max_len = 0; 1467 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1469 } 1470 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1471 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1472 sc->ti_cmd_saved_prodidx = 0; 1473 1474 /* 1475 * Assign the address of the stats refresh buffer. 1476 * We re-use the current stats buffer for this to 1477 * conserve memory. 1478 */ 1479 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1480 TI_CDSTATSADDR(sc); 1481 1482 /* Set up the standard receive ring. */ 1483 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1484 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1485 rcb->ti_max_len = ETHER_MAX_LEN; 1486 rcb->ti_flags = 0; 1487 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1488 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1489 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1490 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1491 if (VLAN_ATTACHED(&sc->ethercom)) 1492 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1493 1494 /* Set up the jumbo receive ring. */ 1495 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1496 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1497 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1498 rcb->ti_flags = 0; 1499 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1500 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1501 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1502 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1503 if (VLAN_ATTACHED(&sc->ethercom)) 1504 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1505 1506 /* 1507 * Set up the mini ring. Only activated on the 1508 * Tigon 2 but the slot in the config block is 1509 * still there on the Tigon 1. 1510 */ 1511 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1512 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1513 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1514 if (sc->ti_hwrev == TI_HWREV_TIGON) 1515 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1516 else 1517 rcb->ti_flags = 0; 1518 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1519 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1520 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1521 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1522 if (VLAN_ATTACHED(&sc->ethercom)) 1523 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1524 1525 /* 1526 * Set up the receive return ring. 1527 */ 1528 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1529 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1530 rcb->ti_flags = 0; 1531 rcb->ti_max_len = TI_RETURN_RING_CNT; 1532 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1533 TI_CDRTNPRODADDR(sc); 1534 1535 /* 1536 * Set up the tx ring. Note: for the Tigon 2, we have the option 1537 * of putting the transmit ring in the host's address space and 1538 * letting the chip DMA it instead of leaving the ring in the NIC's 1539 * memory and accessing it through the shared memory region. We 1540 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1541 * so we have to revert to the shared memory scheme if we detect 1542 * a Tigon 1 chip. 1543 */ 1544 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1545 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1546 sc->ti_tx_ring_nic = 1547 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1548 } 1549 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1550 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1551 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1552 if (sc->ti_hwrev == TI_HWREV_TIGON) 1553 rcb->ti_flags = 0; 1554 else 1555 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1556 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1557 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1558 /* 1559 * When we get the packet, there is a pseudo-header seed already 1560 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1561 * compute the pseudo-header checksum again! 1562 */ 1563 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1564 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1565 TI_RCB_FLAG_NO_PHDR_CKSUM; 1566 if (VLAN_ATTACHED(&sc->ethercom)) 1567 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1568 rcb->ti_max_len = TI_TX_RING_CNT; 1569 if (sc->ti_hwrev == TI_HWREV_TIGON) 1570 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1571 else 1572 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1573 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1574 TI_CDTXCONSADDR(sc); 1575 1576 /* 1577 * We're done frobbing the General Information Block. Sync 1578 * it. Note we take care of the first stats sync here, as 1579 * well. 1580 */ 1581 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1582 1583 /* Set up tuneables */ 1584 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1585 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1586 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1587 (sc->ti_rx_coal_ticks / 10)); 1588 else 1589 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1590 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1591 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1592 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1593 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1594 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1595 1596 /* Turn interrupts on. */ 1597 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1598 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1599 1600 /* Start CPU. */ 1601 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1602 1603 return(0); 1604 } 1605 1606 /* 1607 * look for id in the device list, returning the first match 1608 */ 1609 static const struct ti_type * 1610 ti_type_match(pa) 1611 struct pci_attach_args *pa; 1612 { 1613 const struct ti_type *t; 1614 1615 t = ti_devs; 1616 while(t->ti_name != NULL) { 1617 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1618 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1619 return (t); 1620 } 1621 t++; 1622 } 1623 1624 return(NULL); 1625 } 1626 1627 /* 1628 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1629 * against our list and return its name if we find a match. 1630 */ 1631 static int 1632 ti_probe(struct device *parent __unused, struct cfdata *match __unused, 1633 void *aux) 1634 { 1635 struct pci_attach_args *pa = aux; 1636 const struct ti_type *t; 1637 1638 t = ti_type_match(pa); 1639 1640 return((t == NULL) ? 0 : 1); 1641 } 1642 1643 static void 1644 ti_attach(struct device *parent __unused, struct device *self, void *aux) 1645 { 1646 u_int32_t command; 1647 struct ifnet *ifp; 1648 struct ti_softc *sc; 1649 u_char eaddr[ETHER_ADDR_LEN]; 1650 struct pci_attach_args *pa = aux; 1651 pci_chipset_tag_t pc = pa->pa_pc; 1652 pci_intr_handle_t ih; 1653 const char *intrstr = NULL; 1654 bus_dma_segment_t dmaseg; 1655 int error, dmanseg, nolinear; 1656 const struct ti_type *t; 1657 1658 t = ti_type_match(pa); 1659 if (t == NULL) { 1660 printf("ti_attach: were did the card go ?\n"); 1661 return; 1662 } 1663 1664 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1665 1666 sc = (struct ti_softc *)self; 1667 1668 /* 1669 * Map control/status registers. 1670 */ 1671 nolinear = 0; 1672 if (pci_mapreg_map(pa, 0x10, 1673 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1674 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1675 NULL, NULL)) { 1676 nolinear = 1; 1677 if (pci_mapreg_map(pa, 0x10, 1678 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1679 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1680 printf(": can't map memory space\n"); 1681 return; 1682 } 1683 } 1684 if (nolinear == 0) 1685 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1686 else 1687 sc->ti_vhandle = NULL; 1688 1689 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1690 command |= PCI_COMMAND_MASTER_ENABLE; 1691 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1692 1693 /* Allocate interrupt */ 1694 if (pci_intr_map(pa, &ih)) { 1695 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1696 return; 1697 } 1698 intrstr = pci_intr_string(pc, ih); 1699 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1700 if (sc->sc_ih == NULL) { 1701 printf("%s: couldn't establish interrupt", 1702 sc->sc_dev.dv_xname); 1703 if (intrstr != NULL) 1704 printf(" at %s", intrstr); 1705 printf("\n"); 1706 return; 1707 } 1708 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1709 /* 1710 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1711 * doing do could allow DMA to corrupt kernel memory during the 1712 * reboot before the driver initializes. 1713 */ 1714 (void) shutdownhook_establish(ti_shutdown, sc); 1715 1716 if (ti_chipinit(sc)) { 1717 printf("%s: chip initialization failed\n", self->dv_xname); 1718 goto fail2; 1719 } 1720 1721 /* 1722 * Deal with some chip diffrences. 1723 */ 1724 switch (sc->ti_hwrev) { 1725 case TI_HWREV_TIGON: 1726 sc->sc_tx_encap = ti_encap_tigon1; 1727 sc->sc_tx_eof = ti_txeof_tigon1; 1728 if (nolinear == 1) 1729 printf("%s: memory space not mapped linear\n", 1730 self->dv_xname); 1731 break; 1732 1733 case TI_HWREV_TIGON_II: 1734 sc->sc_tx_encap = ti_encap_tigon2; 1735 sc->sc_tx_eof = ti_txeof_tigon2; 1736 break; 1737 1738 default: 1739 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1740 sc->ti_hwrev); 1741 goto fail2; 1742 } 1743 1744 /* Zero out the NIC's on-board SRAM. */ 1745 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1746 1747 /* Init again -- zeroing memory may have clobbered some registers. */ 1748 if (ti_chipinit(sc)) { 1749 printf("%s: chip initialization failed\n", self->dv_xname); 1750 goto fail2; 1751 } 1752 1753 /* 1754 * Get station address from the EEPROM. Note: the manual states 1755 * that the MAC address is at offset 0x8c, however the data is 1756 * stored as two longwords (since that's how it's loaded into 1757 * the NIC). This means the MAC address is actually preceded 1758 * by two zero bytes. We need to skip over those. 1759 */ 1760 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1761 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1762 printf("%s: failed to read station address\n", self->dv_xname); 1763 goto fail2; 1764 } 1765 1766 /* 1767 * A Tigon chip was detected. Inform the world. 1768 */ 1769 printf("%s: Ethernet address: %s\n", self->dv_xname, 1770 ether_sprintf(eaddr)); 1771 1772 sc->sc_dmat = pa->pa_dmat; 1773 1774 /* Allocate the general information block and ring buffers. */ 1775 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1776 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1777 BUS_DMA_NOWAIT)) != 0) { 1778 printf("%s: can't allocate ring buffer, error = %d\n", 1779 sc->sc_dev.dv_xname, error); 1780 goto fail2; 1781 } 1782 1783 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1784 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1785 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1786 printf("%s: can't map ring buffer, error = %d\n", 1787 sc->sc_dev.dv_xname, error); 1788 goto fail2; 1789 } 1790 1791 if ((error = bus_dmamap_create(sc->sc_dmat, 1792 sizeof(struct ti_ring_data), 1, 1793 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1794 &sc->info_dmamap)) != 0) { 1795 printf("%s: can't create ring buffer DMA map, error = %d\n", 1796 sc->sc_dev.dv_xname, error); 1797 goto fail2; 1798 } 1799 1800 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1801 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1802 BUS_DMA_NOWAIT)) != 0) { 1803 printf("%s: can't load ring buffer DMA map, error = %d\n", 1804 sc->sc_dev.dv_xname, error); 1805 goto fail2; 1806 } 1807 1808 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1809 1810 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1811 1812 /* Try to allocate memory for jumbo buffers. */ 1813 if (ti_alloc_jumbo_mem(sc)) { 1814 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1815 goto fail2; 1816 } 1817 1818 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1819 1820 /* 1821 * We really need a better way to tell a 1000baseT card 1822 * from a 1000baseSX one, since in theory there could be 1823 * OEMed 1000baseT cards from lame vendors who aren't 1824 * clever enough to change the PCI ID. For the moment 1825 * though, the AceNIC is the only copper card available. 1826 */ 1827 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1828 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1829 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1830 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1831 sc->ti_copper = 1; 1832 else 1833 sc->ti_copper = 0; 1834 1835 /* Set default tuneable values. */ 1836 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1837 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1838 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1839 sc->ti_rx_max_coal_bds = 64; 1840 sc->ti_tx_max_coal_bds = 128; 1841 sc->ti_tx_buf_ratio = 21; 1842 1843 /* Set up ifnet structure */ 1844 ifp = &sc->ethercom.ec_if; 1845 ifp->if_softc = sc; 1846 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1847 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1848 ifp->if_ioctl = ti_ioctl; 1849 ifp->if_start = ti_start; 1850 ifp->if_watchdog = ti_watchdog; 1851 IFQ_SET_READY(&ifp->if_snd); 1852 1853 #if 0 1854 /* 1855 * XXX This is not really correct -- we don't necessarily 1856 * XXX want to queue up as many as we can transmit at the 1857 * XXX upper layer like that. Someone with a board should 1858 * XXX check to see how this affects performance. 1859 */ 1860 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1861 #endif 1862 1863 /* 1864 * We can support 802.1Q VLAN-sized frames. 1865 */ 1866 sc->ethercom.ec_capabilities |= 1867 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1868 1869 /* 1870 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1871 */ 1872 ifp->if_capabilities |= 1873 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1874 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1875 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1876 1877 /* Set up ifmedia support. */ 1878 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1879 if (sc->ti_copper) { 1880 /* 1881 * Copper cards allow manual 10/100 mode selection, 1882 * but not manual 1000baseT mode selection. Why? 1883 * Because currently there's no way to specify the 1884 * master/slave setting through the firmware interface, 1885 * so Alteon decided to just bag it and handle it 1886 * via autonegotiation. 1887 */ 1888 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1889 ifmedia_add(&sc->ifmedia, 1890 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1891 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1892 ifmedia_add(&sc->ifmedia, 1893 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1894 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1895 ifmedia_add(&sc->ifmedia, 1896 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1897 } else { 1898 /* Fiber cards don't support 10/100 modes. */ 1899 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1901 } 1902 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1903 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1904 1905 /* 1906 * Call MI attach routines. 1907 */ 1908 if_attach(ifp); 1909 ether_ifattach(ifp, eaddr); 1910 1911 return; 1912 fail2: 1913 pci_intr_disestablish(pc, sc->sc_ih); 1914 return; 1915 } 1916 1917 /* 1918 * Frame reception handling. This is called if there's a frame 1919 * on the receive return list. 1920 * 1921 * Note: we have to be able to handle three possibilities here: 1922 * 1) the frame is from the mini receive ring (can only happen) 1923 * on Tigon 2 boards) 1924 * 2) the frame is from the jumbo receive ring 1925 * 3) the frame is from the standard receive ring 1926 */ 1927 1928 static void ti_rxeof(sc) 1929 struct ti_softc *sc; 1930 { 1931 struct ifnet *ifp; 1932 struct ti_cmd_desc cmd; 1933 1934 ifp = &sc->ethercom.ec_if; 1935 1936 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1937 struct ti_rx_desc *cur_rx; 1938 u_int32_t rxidx; 1939 struct mbuf *m = NULL; 1940 struct ether_header *eh; 1941 bus_dmamap_t dmamap; 1942 1943 cur_rx = 1944 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1945 rxidx = cur_rx->ti_idx; 1946 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1947 1948 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1949 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1950 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1951 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1952 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1953 ifp->if_ierrors++; 1954 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1955 continue; 1956 } 1957 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1958 == ENOBUFS) { 1959 ifp->if_ierrors++; 1960 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1961 continue; 1962 } 1963 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1964 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1965 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1966 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1967 dmamap = sc->mini_dmamap[rxidx]; 1968 sc->mini_dmamap[rxidx] = 0; 1969 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1970 ifp->if_ierrors++; 1971 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1972 continue; 1973 } 1974 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1975 == ENOBUFS) { 1976 ifp->if_ierrors++; 1977 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1978 continue; 1979 } 1980 } else { 1981 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1982 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1983 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1984 dmamap = sc->std_dmamap[rxidx]; 1985 sc->std_dmamap[rxidx] = 0; 1986 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1987 ifp->if_ierrors++; 1988 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1989 continue; 1990 } 1991 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1992 == ENOBUFS) { 1993 ifp->if_ierrors++; 1994 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1995 continue; 1996 } 1997 } 1998 1999 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2000 ifp->if_ipackets++; 2001 m->m_pkthdr.rcvif = ifp; 2002 2003 #if NBPFILTER > 0 2004 /* 2005 * Handle BPF listeners. Let the BPF user see the packet, but 2006 * don't pass it up to the ether_input() layer unless it's 2007 * a broadcast packet, multicast packet, matches our ethernet 2008 * address or the interface is in promiscuous mode. 2009 */ 2010 if (ifp->if_bpf) 2011 bpf_mtap(ifp->if_bpf, m); 2012 #endif 2013 2014 eh = mtod(m, struct ether_header *); 2015 switch (ntohs(eh->ether_type)) { 2016 #ifdef INET 2017 case ETHERTYPE_IP: 2018 { 2019 struct ip *ip = (struct ip *) (eh + 1); 2020 2021 /* 2022 * Note the Tigon firmware does not invert 2023 * the checksum for us, hence the XOR. 2024 */ 2025 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2026 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2027 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2028 /* 2029 * ntohs() the constant so the compiler can 2030 * optimize... 2031 * 2032 * XXX Figure out a sane way to deal with 2033 * fragmented packets. 2034 */ 2035 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2036 switch (ip->ip_p) { 2037 case IPPROTO_TCP: 2038 m->m_pkthdr.csum_data = 2039 cur_rx->ti_tcp_udp_cksum; 2040 m->m_pkthdr.csum_flags |= 2041 M_CSUM_TCPv4|M_CSUM_DATA; 2042 break; 2043 case IPPROTO_UDP: 2044 m->m_pkthdr.csum_data = 2045 cur_rx->ti_tcp_udp_cksum; 2046 m->m_pkthdr.csum_flags |= 2047 M_CSUM_UDPv4|M_CSUM_DATA; 2048 break; 2049 default: 2050 /* Nothing */; 2051 } 2052 } 2053 break; 2054 } 2055 #endif 2056 default: 2057 /* Nothing. */ 2058 break; 2059 } 2060 2061 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2062 VLAN_INPUT_TAG(ifp, m, 2063 /* ti_vlan_tag also has the priority, trim it */ 2064 cur_rx->ti_vlan_tag & 4095, 2065 continue); 2066 } 2067 2068 (*ifp->if_input)(ifp, m); 2069 } 2070 2071 /* Only necessary on the Tigon 1. */ 2072 if (sc->ti_hwrev == TI_HWREV_TIGON) 2073 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2074 sc->ti_rx_saved_considx); 2075 2076 TI_UPDATE_STDPROD(sc, sc->ti_std); 2077 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2078 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2079 2080 return; 2081 } 2082 2083 static void ti_txeof_tigon1(sc) 2084 struct ti_softc *sc; 2085 { 2086 struct ti_tx_desc *cur_tx = NULL; 2087 struct ifnet *ifp; 2088 struct txdmamap_pool_entry *dma; 2089 2090 ifp = &sc->ethercom.ec_if; 2091 2092 /* 2093 * Go through our tx ring and free mbufs for those 2094 * frames that have been sent. 2095 */ 2096 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2097 u_int32_t idx = 0; 2098 2099 idx = sc->ti_tx_saved_considx; 2100 if (idx > 383) 2101 CSR_WRITE_4(sc, TI_WINBASE, 2102 TI_TX_RING_BASE + 6144); 2103 else if (idx > 255) 2104 CSR_WRITE_4(sc, TI_WINBASE, 2105 TI_TX_RING_BASE + 4096); 2106 else if (idx > 127) 2107 CSR_WRITE_4(sc, TI_WINBASE, 2108 TI_TX_RING_BASE + 2048); 2109 else 2110 CSR_WRITE_4(sc, TI_WINBASE, 2111 TI_TX_RING_BASE); 2112 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2113 if (cur_tx->ti_flags & TI_BDFLAG_END) 2114 ifp->if_opackets++; 2115 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2116 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2117 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2118 2119 dma = sc->txdma[idx]; 2120 KDASSERT(dma != NULL); 2121 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2122 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2123 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2124 2125 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2126 sc->txdma[idx] = NULL; 2127 } 2128 sc->ti_txcnt--; 2129 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2130 ifp->if_timer = 0; 2131 } 2132 2133 if (cur_tx != NULL) 2134 ifp->if_flags &= ~IFF_OACTIVE; 2135 2136 return; 2137 } 2138 2139 static void ti_txeof_tigon2(sc) 2140 struct ti_softc *sc; 2141 { 2142 struct ti_tx_desc *cur_tx = NULL; 2143 struct ifnet *ifp; 2144 struct txdmamap_pool_entry *dma; 2145 int firstidx, cnt; 2146 2147 ifp = &sc->ethercom.ec_if; 2148 2149 /* 2150 * Go through our tx ring and free mbufs for those 2151 * frames that have been sent. 2152 */ 2153 firstidx = sc->ti_tx_saved_considx; 2154 cnt = 0; 2155 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2156 u_int32_t idx = 0; 2157 2158 idx = sc->ti_tx_saved_considx; 2159 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2160 if (cur_tx->ti_flags & TI_BDFLAG_END) 2161 ifp->if_opackets++; 2162 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2163 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2164 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2165 2166 dma = sc->txdma[idx]; 2167 KDASSERT(dma != NULL); 2168 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2169 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2170 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2171 2172 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2173 sc->txdma[idx] = NULL; 2174 } 2175 cnt++; 2176 sc->ti_txcnt--; 2177 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2178 ifp->if_timer = 0; 2179 } 2180 2181 if (cnt != 0) 2182 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2183 2184 if (cur_tx != NULL) 2185 ifp->if_flags &= ~IFF_OACTIVE; 2186 2187 return; 2188 } 2189 2190 static int ti_intr(xsc) 2191 void *xsc; 2192 { 2193 struct ti_softc *sc; 2194 struct ifnet *ifp; 2195 2196 sc = xsc; 2197 ifp = &sc->ethercom.ec_if; 2198 2199 #ifdef notdef 2200 /* Avoid this for now -- checking this register is expensive. */ 2201 /* Make sure this is really our interrupt. */ 2202 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2203 return (0); 2204 #endif 2205 2206 /* Ack interrupt and stop others from occuring. */ 2207 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2208 2209 if (ifp->if_flags & IFF_RUNNING) { 2210 /* Check RX return ring producer/consumer */ 2211 ti_rxeof(sc); 2212 2213 /* Check TX ring producer/consumer */ 2214 (*sc->sc_tx_eof)(sc); 2215 } 2216 2217 ti_handle_events(sc); 2218 2219 /* Re-enable interrupts. */ 2220 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2221 2222 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2223 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2224 ti_start(ifp); 2225 2226 return (1); 2227 } 2228 2229 static void ti_stats_update(sc) 2230 struct ti_softc *sc; 2231 { 2232 struct ifnet *ifp; 2233 2234 ifp = &sc->ethercom.ec_if; 2235 2236 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2237 2238 ifp->if_collisions += 2239 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2240 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2241 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2242 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2243 ifp->if_collisions; 2244 2245 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2246 } 2247 2248 /* 2249 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2250 * pointers to descriptors. 2251 */ 2252 static int ti_encap_tigon1(sc, m_head, txidx) 2253 struct ti_softc *sc; 2254 struct mbuf *m_head; 2255 u_int32_t *txidx; 2256 { 2257 struct ti_tx_desc *f = NULL; 2258 u_int32_t frag, cur, cnt = 0; 2259 struct txdmamap_pool_entry *dma; 2260 bus_dmamap_t dmamap; 2261 int error, i; 2262 struct m_tag *mtag; 2263 u_int16_t csum_flags = 0; 2264 2265 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2266 if (dma == NULL) { 2267 return ENOMEM; 2268 } 2269 dmamap = dma->dmamap; 2270 2271 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2272 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2273 if (error) { 2274 struct mbuf *m; 2275 int j = 0; 2276 for (m = m_head; m; m = m->m_next) 2277 j++; 2278 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2279 "error %d\n", m_head->m_pkthdr.len, j, error); 2280 return (ENOMEM); 2281 } 2282 2283 cur = frag = *txidx; 2284 2285 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2286 /* IP header checksum field must be 0! */ 2287 csum_flags |= TI_BDFLAG_IP_CKSUM; 2288 } 2289 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2290 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2291 2292 /* XXX fragmented packet checksum capability? */ 2293 2294 /* 2295 * Start packing the mbufs in this chain into 2296 * the fragment pointers. Stop when we run out 2297 * of fragments or hit the end of the mbuf chain. 2298 */ 2299 for (i = 0; i < dmamap->dm_nsegs; i++) { 2300 if (frag > 383) 2301 CSR_WRITE_4(sc, TI_WINBASE, 2302 TI_TX_RING_BASE + 6144); 2303 else if (frag > 255) 2304 CSR_WRITE_4(sc, TI_WINBASE, 2305 TI_TX_RING_BASE + 4096); 2306 else if (frag > 127) 2307 CSR_WRITE_4(sc, TI_WINBASE, 2308 TI_TX_RING_BASE + 2048); 2309 else 2310 CSR_WRITE_4(sc, TI_WINBASE, 2311 TI_TX_RING_BASE); 2312 f = &sc->ti_tx_ring_nic[frag % 128]; 2313 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2314 break; 2315 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2316 f->ti_len = dmamap->dm_segs[i].ds_len; 2317 f->ti_flags = csum_flags; 2318 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2319 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2320 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2321 } else { 2322 f->ti_vlan_tag = 0; 2323 } 2324 /* 2325 * Sanity check: avoid coming within 16 descriptors 2326 * of the end of the ring. 2327 */ 2328 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2329 return(ENOBUFS); 2330 cur = frag; 2331 TI_INC(frag, TI_TX_RING_CNT); 2332 cnt++; 2333 } 2334 2335 if (i < dmamap->dm_nsegs) 2336 return(ENOBUFS); 2337 2338 if (frag == sc->ti_tx_saved_considx) 2339 return(ENOBUFS); 2340 2341 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2342 TI_BDFLAG_END; 2343 2344 /* Sync the packet's DMA map. */ 2345 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2346 BUS_DMASYNC_PREWRITE); 2347 2348 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2349 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2350 sc->txdma[cur] = dma; 2351 sc->ti_txcnt += cnt; 2352 2353 *txidx = frag; 2354 2355 return(0); 2356 } 2357 2358 static int ti_encap_tigon2(sc, m_head, txidx) 2359 struct ti_softc *sc; 2360 struct mbuf *m_head; 2361 u_int32_t *txidx; 2362 { 2363 struct ti_tx_desc *f = NULL; 2364 u_int32_t frag, firstfrag, cur, cnt = 0; 2365 struct txdmamap_pool_entry *dma; 2366 bus_dmamap_t dmamap; 2367 int error, i; 2368 struct m_tag *mtag; 2369 u_int16_t csum_flags = 0; 2370 2371 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2372 if (dma == NULL) { 2373 return ENOMEM; 2374 } 2375 dmamap = dma->dmamap; 2376 2377 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2378 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2379 if (error) { 2380 struct mbuf *m; 2381 int j = 0; 2382 for (m = m_head; m; m = m->m_next) 2383 j++; 2384 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2385 "error %d\n", m_head->m_pkthdr.len, j, error); 2386 return (ENOMEM); 2387 } 2388 2389 cur = firstfrag = frag = *txidx; 2390 2391 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2392 /* IP header checksum field must be 0! */ 2393 csum_flags |= TI_BDFLAG_IP_CKSUM; 2394 } 2395 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2396 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2397 2398 /* XXX fragmented packet checksum capability? */ 2399 2400 /* 2401 * Start packing the mbufs in this chain into 2402 * the fragment pointers. Stop when we run out 2403 * of fragments or hit the end of the mbuf chain. 2404 */ 2405 for (i = 0; i < dmamap->dm_nsegs; i++) { 2406 f = &sc->ti_rdata->ti_tx_ring[frag]; 2407 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2408 break; 2409 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2410 f->ti_len = dmamap->dm_segs[i].ds_len; 2411 f->ti_flags = csum_flags; 2412 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2413 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2414 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2415 } else { 2416 f->ti_vlan_tag = 0; 2417 } 2418 /* 2419 * Sanity check: avoid coming within 16 descriptors 2420 * of the end of the ring. 2421 */ 2422 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2423 return(ENOBUFS); 2424 cur = frag; 2425 TI_INC(frag, TI_TX_RING_CNT); 2426 cnt++; 2427 } 2428 2429 if (i < dmamap->dm_nsegs) 2430 return(ENOBUFS); 2431 2432 if (frag == sc->ti_tx_saved_considx) 2433 return(ENOBUFS); 2434 2435 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2436 2437 /* Sync the packet's DMA map. */ 2438 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2439 BUS_DMASYNC_PREWRITE); 2440 2441 /* Sync the descriptors we are using. */ 2442 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2443 2444 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2445 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2446 sc->txdma[cur] = dma; 2447 sc->ti_txcnt += cnt; 2448 2449 *txidx = frag; 2450 2451 return(0); 2452 } 2453 2454 /* 2455 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2456 * to the mbuf data regions directly in the transmit descriptors. 2457 */ 2458 static void ti_start(ifp) 2459 struct ifnet *ifp; 2460 { 2461 struct ti_softc *sc; 2462 struct mbuf *m_head = NULL; 2463 u_int32_t prodidx = 0; 2464 2465 sc = ifp->if_softc; 2466 2467 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2468 2469 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2470 IFQ_POLL(&ifp->if_snd, m_head); 2471 if (m_head == NULL) 2472 break; 2473 2474 /* 2475 * Pack the data into the transmit ring. If we 2476 * don't have room, set the OACTIVE flag and wait 2477 * for the NIC to drain the ring. 2478 */ 2479 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2480 ifp->if_flags |= IFF_OACTIVE; 2481 break; 2482 } 2483 2484 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2485 2486 /* 2487 * If there's a BPF listener, bounce a copy of this frame 2488 * to him. 2489 */ 2490 #if NBPFILTER > 0 2491 if (ifp->if_bpf) 2492 bpf_mtap(ifp->if_bpf, m_head); 2493 #endif 2494 } 2495 2496 /* Transmit */ 2497 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2498 2499 /* 2500 * Set a timeout in case the chip goes out to lunch. 2501 */ 2502 ifp->if_timer = 5; 2503 2504 return; 2505 } 2506 2507 static void ti_init(xsc) 2508 void *xsc; 2509 { 2510 struct ti_softc *sc = xsc; 2511 int s; 2512 2513 s = splnet(); 2514 2515 /* Cancel pending I/O and flush buffers. */ 2516 ti_stop(sc); 2517 2518 /* Init the gen info block, ring control blocks and firmware. */ 2519 if (ti_gibinit(sc)) { 2520 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2521 splx(s); 2522 return; 2523 } 2524 2525 splx(s); 2526 2527 return; 2528 } 2529 2530 static void ti_init2(sc) 2531 struct ti_softc *sc; 2532 { 2533 struct ti_cmd_desc cmd; 2534 struct ifnet *ifp; 2535 u_int8_t *m; 2536 struct ifmedia *ifm; 2537 int tmp; 2538 2539 ifp = &sc->ethercom.ec_if; 2540 2541 /* Specify MTU and interface index. */ 2542 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2543 2544 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2545 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2546 tmp += ETHER_VLAN_ENCAP_LEN; 2547 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2548 2549 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2550 2551 /* Load our MAC address. */ 2552 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2553 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2554 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2555 | (m[4] << 8) | m[5]); 2556 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2557 2558 /* Enable or disable promiscuous mode as needed. */ 2559 if (ifp->if_flags & IFF_PROMISC) { 2560 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2561 } else { 2562 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2563 } 2564 2565 /* Program multicast filter. */ 2566 ti_setmulti(sc); 2567 2568 /* 2569 * If this is a Tigon 1, we should tell the 2570 * firmware to use software packet filtering. 2571 */ 2572 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2573 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2574 } 2575 2576 /* Init RX ring. */ 2577 ti_init_rx_ring_std(sc); 2578 2579 /* Init jumbo RX ring. */ 2580 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2581 ti_init_rx_ring_jumbo(sc); 2582 2583 /* 2584 * If this is a Tigon 2, we can also configure the 2585 * mini ring. 2586 */ 2587 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2588 ti_init_rx_ring_mini(sc); 2589 2590 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2591 sc->ti_rx_saved_considx = 0; 2592 2593 /* Init TX ring. */ 2594 ti_init_tx_ring(sc); 2595 2596 /* Tell firmware we're alive. */ 2597 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2598 2599 /* Enable host interrupts. */ 2600 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2601 2602 ifp->if_flags |= IFF_RUNNING; 2603 ifp->if_flags &= ~IFF_OACTIVE; 2604 2605 /* 2606 * Make sure to set media properly. We have to do this 2607 * here since we have to issue commands in order to set 2608 * the link negotiation and we can't issue commands until 2609 * the firmware is running. 2610 */ 2611 ifm = &sc->ifmedia; 2612 tmp = ifm->ifm_media; 2613 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2614 ti_ifmedia_upd(ifp); 2615 ifm->ifm_media = tmp; 2616 2617 return; 2618 } 2619 2620 /* 2621 * Set media options. 2622 */ 2623 static int ti_ifmedia_upd(ifp) 2624 struct ifnet *ifp; 2625 { 2626 struct ti_softc *sc; 2627 struct ifmedia *ifm; 2628 struct ti_cmd_desc cmd; 2629 2630 sc = ifp->if_softc; 2631 ifm = &sc->ifmedia; 2632 2633 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2634 return(EINVAL); 2635 2636 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2637 case IFM_AUTO: 2638 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2639 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2640 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2641 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2642 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2643 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2644 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2645 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2646 break; 2647 case IFM_1000_SX: 2648 case IFM_1000_T: 2649 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2650 CSR_WRITE_4(sc, TI_GCR_GLINK, 2651 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2652 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2653 } else { 2654 CSR_WRITE_4(sc, TI_GCR_GLINK, 2655 TI_GLNK_PREF|TI_GLNK_1000MB| 2656 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2657 } 2658 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2659 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2660 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2661 break; 2662 case IFM_100_FX: 2663 case IFM_10_FL: 2664 case IFM_100_TX: 2665 case IFM_10_T: 2666 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2667 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2668 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2669 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2670 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2671 } else { 2672 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2673 } 2674 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2675 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2676 } else { 2677 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2678 } 2679 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2680 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2681 break; 2682 } 2683 2684 sc->ethercom.ec_if.if_baudrate = 2685 ifmedia_baudrate(ifm->ifm_media); 2686 2687 return(0); 2688 } 2689 2690 /* 2691 * Report current media status. 2692 */ 2693 static void ti_ifmedia_sts(ifp, ifmr) 2694 struct ifnet *ifp; 2695 struct ifmediareq *ifmr; 2696 { 2697 struct ti_softc *sc; 2698 u_int32_t media = 0; 2699 2700 sc = ifp->if_softc; 2701 2702 ifmr->ifm_status = IFM_AVALID; 2703 ifmr->ifm_active = IFM_ETHER; 2704 2705 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2706 return; 2707 2708 ifmr->ifm_status |= IFM_ACTIVE; 2709 2710 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2711 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2712 if (sc->ti_copper) 2713 ifmr->ifm_active |= IFM_1000_T; 2714 else 2715 ifmr->ifm_active |= IFM_1000_SX; 2716 if (media & TI_GLNK_FULL_DUPLEX) 2717 ifmr->ifm_active |= IFM_FDX; 2718 else 2719 ifmr->ifm_active |= IFM_HDX; 2720 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2721 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2722 if (sc->ti_copper) { 2723 if (media & TI_LNK_100MB) 2724 ifmr->ifm_active |= IFM_100_TX; 2725 if (media & TI_LNK_10MB) 2726 ifmr->ifm_active |= IFM_10_T; 2727 } else { 2728 if (media & TI_LNK_100MB) 2729 ifmr->ifm_active |= IFM_100_FX; 2730 if (media & TI_LNK_10MB) 2731 ifmr->ifm_active |= IFM_10_FL; 2732 } 2733 if (media & TI_LNK_FULL_DUPLEX) 2734 ifmr->ifm_active |= IFM_FDX; 2735 if (media & TI_LNK_HALF_DUPLEX) 2736 ifmr->ifm_active |= IFM_HDX; 2737 } 2738 2739 sc->ethercom.ec_if.if_baudrate = 2740 ifmedia_baudrate(sc->ifmedia.ifm_media); 2741 2742 return; 2743 } 2744 2745 static int 2746 ti_ether_ioctl(ifp, cmd, data) 2747 struct ifnet *ifp; 2748 u_long cmd; 2749 caddr_t data; 2750 { 2751 struct ifaddr *ifa = (struct ifaddr *) data; 2752 struct ti_softc *sc = ifp->if_softc; 2753 2754 if ((ifp->if_flags & IFF_UP) == 0) { 2755 ifp->if_flags |= IFF_UP; 2756 ti_init(sc); 2757 } 2758 2759 switch (cmd) { 2760 case SIOCSIFADDR: 2761 2762 switch (ifa->ifa_addr->sa_family) { 2763 #ifdef INET 2764 case AF_INET: 2765 arp_ifinit(ifp, ifa); 2766 break; 2767 #endif 2768 default: 2769 break; 2770 } 2771 break; 2772 2773 default: 2774 return (EINVAL); 2775 } 2776 2777 return (0); 2778 } 2779 2780 static int ti_ioctl(ifp, command, data) 2781 struct ifnet *ifp; 2782 u_long command; 2783 caddr_t data; 2784 { 2785 struct ti_softc *sc = ifp->if_softc; 2786 struct ifreq *ifr = (struct ifreq *) data; 2787 int s, error = 0; 2788 struct ti_cmd_desc cmd; 2789 2790 s = splnet(); 2791 2792 switch(command) { 2793 case SIOCSIFADDR: 2794 case SIOCGIFADDR: 2795 error = ti_ether_ioctl(ifp, command, data); 2796 break; 2797 case SIOCSIFMTU: 2798 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2799 error = EINVAL; 2800 else { 2801 ifp->if_mtu = ifr->ifr_mtu; 2802 ti_init(sc); 2803 } 2804 break; 2805 case SIOCSIFFLAGS: 2806 if (ifp->if_flags & IFF_UP) { 2807 /* 2808 * If only the state of the PROMISC flag changed, 2809 * then just use the 'set promisc mode' command 2810 * instead of reinitializing the entire NIC. Doing 2811 * a full re-init means reloading the firmware and 2812 * waiting for it to start up, which may take a 2813 * second or two. 2814 */ 2815 if (ifp->if_flags & IFF_RUNNING && 2816 ifp->if_flags & IFF_PROMISC && 2817 !(sc->ti_if_flags & IFF_PROMISC)) { 2818 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2819 TI_CMD_CODE_PROMISC_ENB, 0); 2820 } else if (ifp->if_flags & IFF_RUNNING && 2821 !(ifp->if_flags & IFF_PROMISC) && 2822 sc->ti_if_flags & IFF_PROMISC) { 2823 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2824 TI_CMD_CODE_PROMISC_DIS, 0); 2825 } else 2826 ti_init(sc); 2827 } else { 2828 if (ifp->if_flags & IFF_RUNNING) { 2829 ti_stop(sc); 2830 } 2831 } 2832 sc->ti_if_flags = ifp->if_flags; 2833 error = 0; 2834 break; 2835 case SIOCADDMULTI: 2836 case SIOCDELMULTI: 2837 error = (command == SIOCADDMULTI) ? 2838 ether_addmulti(ifr, &sc->ethercom) : 2839 ether_delmulti(ifr, &sc->ethercom); 2840 if (error == ENETRESET) { 2841 if (ifp->if_flags & IFF_RUNNING) 2842 ti_setmulti(sc); 2843 error = 0; 2844 } 2845 break; 2846 case SIOCSIFMEDIA: 2847 case SIOCGIFMEDIA: 2848 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2849 break; 2850 default: 2851 error = EINVAL; 2852 break; 2853 } 2854 2855 (void)splx(s); 2856 2857 return(error); 2858 } 2859 2860 static void ti_watchdog(ifp) 2861 struct ifnet *ifp; 2862 { 2863 struct ti_softc *sc; 2864 2865 sc = ifp->if_softc; 2866 2867 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2868 ti_stop(sc); 2869 ti_init(sc); 2870 2871 ifp->if_oerrors++; 2872 2873 return; 2874 } 2875 2876 /* 2877 * Stop the adapter and free any mbufs allocated to the 2878 * RX and TX lists. 2879 */ 2880 static void ti_stop(sc) 2881 struct ti_softc *sc; 2882 { 2883 struct ifnet *ifp; 2884 struct ti_cmd_desc cmd; 2885 2886 ifp = &sc->ethercom.ec_if; 2887 2888 /* Disable host interrupts. */ 2889 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2890 /* 2891 * Tell firmware we're shutting down. 2892 */ 2893 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2894 2895 /* Halt and reinitialize. */ 2896 ti_chipinit(sc); 2897 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2898 ti_chipinit(sc); 2899 2900 /* Free the RX lists. */ 2901 ti_free_rx_ring_std(sc); 2902 2903 /* Free jumbo RX list. */ 2904 ti_free_rx_ring_jumbo(sc); 2905 2906 /* Free mini RX list. */ 2907 ti_free_rx_ring_mini(sc); 2908 2909 /* Free TX buffers. */ 2910 ti_free_tx_ring(sc); 2911 2912 sc->ti_ev_prodidx.ti_idx = 0; 2913 sc->ti_return_prodidx.ti_idx = 0; 2914 sc->ti_tx_considx.ti_idx = 0; 2915 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2916 2917 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2918 2919 return; 2920 } 2921 2922 /* 2923 * Stop all chip I/O so that the kernel's probe routines don't 2924 * get confused by errant DMAs when rebooting. 2925 */ 2926 static void ti_shutdown(v) 2927 void *v; 2928 { 2929 struct ti_softc *sc = v; 2930 2931 ti_chipinit(sc); 2932 2933 return; 2934 } 2935
Indexes created Fri Sep 26 20:09:58 GMT 2025