if_ti.c revision 1.85
1 /* $NetBSD: if_ti.c,v 1.85 2009/05/12 08:23:01 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul (at) ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul (at) ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.85 2009/05/12 08:23:01 cegger Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/device.h> 98 #include <sys/reboot.h> 99 100 #include <uvm/uvm_extern.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/if_ether.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/ip.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_tireg.h> 127 128 #include <dev/microcode/tigon/ti_fw.h> 129 #include <dev/microcode/tigon/ti_fw2.h> 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 135 static const struct ti_type ti_devs[] = { 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 137 "Alteon AceNIC 1000BASE-SX Ethernet" }, 138 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 139 "Alteon AceNIC 1000BASE-T Ethernet" }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 143 "Netgear GA620 1000BASE-SX Ethernet" }, 144 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 145 "Netgear GA620 1000BASE-T Ethernet" }, 146 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { 0, 0, NULL } 149 }; 150 151 static const struct ti_type *ti_type_match(struct pci_attach_args *); 152 static int ti_probe(device_t, cfdata_t, void *); 153 static void ti_attach(device_t, device_t, void *); 154 static void ti_shutdown(void *); 155 static void ti_txeof_tigon1(struct ti_softc *); 156 static void ti_txeof_tigon2(struct ti_softc *); 157 static void ti_rxeof(struct ti_softc *); 158 159 static void ti_stats_update(struct ti_softc *); 160 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 161 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 162 163 static int ti_intr(void *); 164 static void ti_start(struct ifnet *); 165 static int ti_ioctl(struct ifnet *, u_long, void *); 166 static void ti_init(void *); 167 static void ti_init2(struct ti_softc *); 168 static void ti_stop(struct ti_softc *); 169 static void ti_watchdog(struct ifnet *); 170 static int ti_ifmedia_upd(struct ifnet *); 171 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 172 173 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 174 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 175 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 176 177 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 178 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 179 static void ti_setmulti(struct ti_softc *); 180 181 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 182 static void ti_loadfw(struct ti_softc *); 183 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 184 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 185 static void ti_handle_events(struct ti_softc *); 186 static int ti_alloc_jumbo_mem(struct ti_softc *); 187 static void *ti_jalloc(struct ti_softc *); 188 static void ti_jfree(struct mbuf *, void *, size_t, void *); 189 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 190 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 191 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 192 static int ti_init_rx_ring_std(struct ti_softc *); 193 static void ti_free_rx_ring_std(struct ti_softc *); 194 static int ti_init_rx_ring_jumbo(struct ti_softc *); 195 static void ti_free_rx_ring_jumbo(struct ti_softc *); 196 static int ti_init_rx_ring_mini(struct ti_softc *); 197 static void ti_free_rx_ring_mini(struct ti_softc *); 198 static void ti_free_tx_ring(struct ti_softc *); 199 static int ti_init_tx_ring(struct ti_softc *); 200 201 static int ti_64bitslot_war(struct ti_softc *); 202 static int ti_chipinit(struct ti_softc *); 203 static int ti_gibinit(struct ti_softc *); 204 205 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 206 207 CFATTACH_DECL(ti, sizeof(struct ti_softc), 208 ti_probe, ti_attach, NULL, NULL); 209 210 /* 211 * Send an instruction or address to the EEPROM, check for ACK. 212 */ 213 static u_int32_t 214 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 215 { 216 int i, ack = 0; 217 218 /* 219 * Make sure we're in TX mode. 220 */ 221 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 222 223 /* 224 * Feed in each bit and stobe the clock. 225 */ 226 for (i = 0x80; i; i >>= 1) { 227 if (byte & i) { 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 229 } else { 230 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 231 } 232 DELAY(1); 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 234 DELAY(1); 235 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 236 } 237 238 /* 239 * Turn off TX mode. 240 */ 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 242 243 /* 244 * Check for ack. 245 */ 246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 249 250 return (ack); 251 } 252 253 /* 254 * Read a byte of data stored in the EEPROM at address 'addr.' 255 * We have to send two address bytes since the EEPROM can hold 256 * more than 256 bytes of data. 257 */ 258 static u_int8_t 259 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest) 260 { 261 int i; 262 u_int8_t byte = 0; 263 264 EEPROM_START(); 265 266 /* 267 * Send write control code to EEPROM. 268 */ 269 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 270 printf("%s: failed to send write command, status: %x\n", 271 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 272 return (1); 273 } 274 275 /* 276 * Send first byte of address of byte we want to read. 277 */ 278 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 279 printf("%s: failed to send address, status: %x\n", 280 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 281 return (1); 282 } 283 /* 284 * Send second byte address of byte we want to read. 285 */ 286 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 287 printf("%s: failed to send address, status: %x\n", 288 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return (1); 290 } 291 292 EEPROM_STOP(); 293 EEPROM_START(); 294 /* 295 * Send read control code to EEPROM. 296 */ 297 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 298 printf("%s: failed to send read command, status: %x\n", 299 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return (1); 301 } 302 303 /* 304 * Start reading bits from EEPROM. 305 */ 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 307 for (i = 0x80; i; i >>= 1) { 308 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 309 DELAY(1); 310 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 311 byte |= i; 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 DELAY(1); 314 } 315 316 EEPROM_STOP(); 317 318 /* 319 * No ACK generated for read, so just return byte. 320 */ 321 322 *dest = byte; 323 324 return (0); 325 } 326 327 /* 328 * Read a sequence of bytes from the EEPROM. 329 */ 330 static int 331 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 332 { 333 char *dest = destv; 334 int err = 0, i; 335 u_int8_t byte = 0; 336 337 for (i = 0; i < cnt; i++) { 338 err = ti_eeprom_getbyte(sc, off + i, &byte); 339 if (err) 340 break; 341 *(dest + i) = byte; 342 } 343 344 return (err ? 1 : 0); 345 } 346 347 /* 348 * NIC memory access function. Can be used to either clear a section 349 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 350 */ 351 static void 352 ti_mem(struct ti_softc *sc, u_int32_t addr, u_int32_t len, const void *xbuf) 353 { 354 int segptr, segsize, cnt; 355 const void *ptr; 356 357 segptr = addr; 358 cnt = len; 359 ptr = xbuf; 360 361 while (cnt) { 362 if (cnt < TI_WINLEN) 363 segsize = cnt; 364 else 365 segsize = TI_WINLEN - (segptr % TI_WINLEN); 366 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 367 if (xbuf == NULL) { 368 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 369 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 370 segsize / 4); 371 } else { 372 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 373 bus_space_write_region_stream_4(sc->ti_btag, 374 sc->ti_bhandle, 375 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 376 (const u_int32_t *)ptr, segsize / 4); 377 #else 378 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 379 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 380 (const u_int32_t *)ptr, segsize / 4); 381 #endif 382 ptr = (const char *)ptr + segsize; 383 } 384 segptr += segsize; 385 cnt -= segsize; 386 } 387 388 return; 389 } 390 391 /* 392 * Load firmware image into the NIC. Check that the firmware revision 393 * is acceptable and see if we want the firmware for the Tigon 1 or 394 * Tigon 2. 395 */ 396 static void 397 ti_loadfw(struct ti_softc *sc) 398 { 399 switch (sc->ti_hwrev) { 400 case TI_HWREV_TIGON: 401 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 402 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 403 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 404 printf("%s: firmware revision mismatch; want " 405 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 406 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 407 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 408 tigonFwReleaseMinor, tigonFwReleaseFix); 409 return; 410 } 411 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 412 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 413 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 414 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 415 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 416 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 417 break; 418 case TI_HWREV_TIGON_II: 419 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 420 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 421 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 422 printf("%s: firmware revision mismatch; want " 423 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 424 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 425 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 426 tigon2FwReleaseMinor, tigon2FwReleaseFix); 427 return; 428 } 429 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 430 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 431 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 432 tigon2FwRodata); 433 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 434 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 435 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 436 break; 437 default: 438 printf("%s: can't load firmware: unknown hardware rev\n", 439 device_xname(&sc->sc_dev)); 440 break; 441 } 442 443 return; 444 } 445 446 /* 447 * Send the NIC a command via the command ring. 448 */ 449 static void 450 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 451 { 452 u_int32_t index; 453 454 index = sc->ti_cmd_saved_prodidx; 455 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 456 TI_INC(index, TI_CMD_RING_CNT); 457 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 458 sc->ti_cmd_saved_prodidx = index; 459 } 460 461 /* 462 * Send the NIC an extended command. The 'len' parameter specifies the 463 * number of command slots to include after the initial command. 464 */ 465 static void 466 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 467 { 468 char *arg = argv; 469 u_int32_t index; 470 int i; 471 472 index = sc->ti_cmd_saved_prodidx; 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 474 TI_INC(index, TI_CMD_RING_CNT); 475 for (i = 0; i < len; i++) { 476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 477 *(u_int32_t *)(&arg[i * 4])); 478 TI_INC(index, TI_CMD_RING_CNT); 479 } 480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 481 sc->ti_cmd_saved_prodidx = index; 482 } 483 484 /* 485 * Handle events that have triggered interrupts. 486 */ 487 static void 488 ti_handle_events(struct ti_softc *sc) 489 { 490 struct ti_event_desc *e; 491 492 if (sc->ti_rdata->ti_event_ring == NULL) 493 return; 494 495 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 496 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 497 switch (TI_EVENT_EVENT(e)) { 498 case TI_EV_LINKSTAT_CHANGED: 499 sc->ti_linkstat = TI_EVENT_CODE(e); 500 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 501 printf("%s: 10/100 link up\n", 502 device_xname(&sc->sc_dev)); 503 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 504 printf("%s: gigabit link up\n", 505 device_xname(&sc->sc_dev)); 506 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 507 printf("%s: link down\n", 508 device_xname(&sc->sc_dev)); 509 break; 510 case TI_EV_ERROR: 511 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 512 printf("%s: invalid command\n", 513 device_xname(&sc->sc_dev)); 514 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 515 printf("%s: unknown command\n", 516 device_xname(&sc->sc_dev)); 517 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 518 printf("%s: bad config data\n", 519 device_xname(&sc->sc_dev)); 520 break; 521 case TI_EV_FIRMWARE_UP: 522 ti_init2(sc); 523 break; 524 case TI_EV_STATS_UPDATED: 525 ti_stats_update(sc); 526 break; 527 case TI_EV_RESET_JUMBO_RING: 528 case TI_EV_MCAST_UPDATED: 529 /* Who cares. */ 530 break; 531 default: 532 printf("%s: unknown event: %d\n", 533 device_xname(&sc->sc_dev), TI_EVENT_EVENT(e)); 534 break; 535 } 536 /* Advance the consumer index. */ 537 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 538 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 539 } 540 541 return; 542 } 543 544 /* 545 * Memory management for the jumbo receive ring is a pain in the 546 * butt. We need to allocate at least 9018 bytes of space per frame, 547 * _and_ it has to be contiguous (unless you use the extended 548 * jumbo descriptor format). Using malloc() all the time won't 549 * work: malloc() allocates memory in powers of two, which means we 550 * would end up wasting a considerable amount of space by allocating 551 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 552 * to do our own memory management. 553 * 554 * The driver needs to allocate a contiguous chunk of memory at boot 555 * time. We then chop this up ourselves into 9K pieces and use them 556 * as external mbuf storage. 557 * 558 * One issue here is how much memory to allocate. The jumbo ring has 559 * 256 slots in it, but at 9K per slot than can consume over 2MB of 560 * RAM. This is a bit much, especially considering we also need 561 * RAM for the standard ring and mini ring (on the Tigon 2). To 562 * save space, we only actually allocate enough memory for 64 slots 563 * by default, which works out to between 500 and 600K. This can 564 * be tuned by changing a #define in if_tireg.h. 565 */ 566 567 static int 568 ti_alloc_jumbo_mem(struct ti_softc *sc) 569 { 570 char *ptr; 571 int i; 572 struct ti_jpool_entry *entry; 573 bus_dma_segment_t dmaseg; 574 int error, dmanseg; 575 576 /* Grab a big chunk o' storage. */ 577 if ((error = bus_dmamem_alloc(sc->sc_dmat, 578 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 579 BUS_DMA_NOWAIT)) != 0) { 580 aprint_error_dev(&sc->sc_dev, "can't allocate jumbo buffer, error = %d\n", 581 error); 582 return (error); 583 } 584 585 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 586 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 587 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 588 aprint_error_dev(&sc->sc_dev, "can't map jumbo buffer, error = %d\n", 589 error); 590 return (error); 591 } 592 593 if ((error = bus_dmamap_create(sc->sc_dmat, 594 TI_JMEM, 1, 595 TI_JMEM, 0, BUS_DMA_NOWAIT, 596 &sc->jumbo_dmamap)) != 0) { 597 aprint_error_dev(&sc->sc_dev, "can't create jumbo buffer DMA map, error = %d\n", 598 error); 599 return (error); 600 } 601 602 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 603 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 604 BUS_DMA_NOWAIT)) != 0) { 605 aprint_error_dev(&sc->sc_dev, "can't load jumbo buffer DMA map, error = %d\n", 606 error); 607 return (error); 608 } 609 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 610 611 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 612 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 613 614 /* 615 * Now divide it up into 9K pieces and save the addresses 616 * in an array. 617 */ 618 ptr = sc->ti_cdata.ti_jumbo_buf; 619 for (i = 0; i < TI_JSLOTS; i++) { 620 sc->ti_cdata.ti_jslots[i] = ptr; 621 ptr += TI_JLEN; 622 entry = malloc(sizeof(struct ti_jpool_entry), 623 M_DEVBUF, M_NOWAIT); 624 if (entry == NULL) { 625 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 626 sc->ti_cdata.ti_jumbo_buf = NULL; 627 printf("%s: no memory for jumbo " 628 "buffer queue!\n", device_xname(&sc->sc_dev)); 629 return (ENOBUFS); 630 } 631 entry->slot = i; 632 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 633 jpool_entries); 634 } 635 636 return (0); 637 } 638 639 /* 640 * Allocate a jumbo buffer. 641 */ 642 static void * 643 ti_jalloc(struct ti_softc *sc) 644 { 645 struct ti_jpool_entry *entry; 646 647 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 648 649 if (entry == NULL) { 650 printf("%s: no free jumbo buffers\n", device_xname(&sc->sc_dev)); 651 return (NULL); 652 } 653 654 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 655 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 656 657 return (sc->ti_cdata.ti_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 static void 664 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 665 { 666 struct ti_softc *sc; 667 int i, s; 668 struct ti_jpool_entry *entry; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct ti_softc *)arg; 672 673 if (sc == NULL) 674 panic("ti_jfree: didn't get softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 678 i = ((char *)tbuf 679 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 680 681 if ((i < 0) || (i >= TI_JSLOTS)) 682 panic("ti_jfree: asked to free buffer that we don't manage!"); 683 684 s = splvm(); 685 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 686 if (entry == NULL) 687 panic("ti_jfree: buffer not in use!"); 688 entry->slot = i; 689 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 690 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 splx(s); 695 } 696 697 698 /* 699 * Intialize a standard receive ring descriptor. 700 */ 701 static int 702 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 703 { 704 struct mbuf *m_new = NULL; 705 struct ti_rx_desc *r; 706 int error; 707 708 if (dmamap == NULL) { 709 /* if (m) panic() */ 710 711 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 712 MCLBYTES, 0, BUS_DMA_NOWAIT, 713 &dmamap)) != 0) { 714 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 715 error); 716 return (ENOMEM); 717 } 718 } 719 sc->std_dmamap[i] = dmamap; 720 721 if (m == NULL) { 722 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 723 if (m_new == NULL) { 724 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 725 "-- packet dropped!\n"); 726 return (ENOBUFS); 727 } 728 729 MCLGET(m_new, M_DONTWAIT); 730 if (!(m_new->m_flags & M_EXT)) { 731 aprint_error_dev(&sc->sc_dev, "cluster allocation failed " 732 "-- packet dropped!\n"); 733 m_freem(m_new); 734 return (ENOBUFS); 735 } 736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 737 m_adj(m_new, ETHER_ALIGN); 738 739 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 740 mtod(m_new, void *), m_new->m_len, NULL, 741 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 742 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 743 error); 744 return (ENOMEM); 745 } 746 } else { 747 m_new = m; 748 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 749 m_new->m_data = m_new->m_ext.ext_buf; 750 m_adj(m_new, ETHER_ALIGN); 751 752 /* reuse the dmamap */ 753 } 754 755 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 756 r = &sc->ti_rdata->ti_rx_std_ring[i]; 757 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 758 r->ti_type = TI_BDTYPE_RECV_BD; 759 r->ti_flags = 0; 760 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 761 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 762 if (sc->ethercom.ec_if.if_capenable & 763 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 764 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 765 r->ti_len = m_new->m_len; /* == ds_len */ 766 r->ti_idx = i; 767 768 return (0); 769 } 770 771 /* 772 * Intialize a mini receive ring descriptor. This only applies to 773 * the Tigon 2. 774 */ 775 static int 776 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 777 { 778 struct mbuf *m_new = NULL; 779 struct ti_rx_desc *r; 780 int error; 781 782 if (dmamap == NULL) { 783 /* if (m) panic() */ 784 785 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 786 MHLEN, 0, BUS_DMA_NOWAIT, 787 &dmamap)) != 0) { 788 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 789 error); 790 return (ENOMEM); 791 } 792 } 793 sc->mini_dmamap[i] = dmamap; 794 795 if (m == NULL) { 796 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 797 if (m_new == NULL) { 798 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 799 "-- packet dropped!\n"); 800 return (ENOBUFS); 801 } 802 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 803 m_adj(m_new, ETHER_ALIGN); 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 806 mtod(m_new, void *), m_new->m_len, NULL, 807 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 808 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 809 error); 810 return (ENOMEM); 811 } 812 } else { 813 m_new = m; 814 m_new->m_data = m_new->m_pktdat; 815 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 816 m_adj(m_new, ETHER_ALIGN); 817 818 /* reuse the dmamap */ 819 } 820 821 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 822 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 823 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 824 r->ti_type = TI_BDTYPE_RECV_BD; 825 r->ti_flags = TI_BDFLAG_MINI_RING; 826 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 827 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 828 if (sc->ethercom.ec_if.if_capenable & 829 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 830 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 831 r->ti_len = m_new->m_len; /* == ds_len */ 832 r->ti_idx = i; 833 834 return (0); 835 } 836 837 /* 838 * Initialize a jumbo receive ring descriptor. This allocates 839 * a jumbo buffer from the pool managed internally by the driver. 840 */ 841 static int 842 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 843 { 844 struct mbuf *m_new = NULL; 845 struct ti_rx_desc *r; 846 847 if (m == NULL) { 848 void * tbuf = NULL; 849 850 /* Allocate the mbuf. */ 851 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 852 if (m_new == NULL) { 853 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 854 "-- packet dropped!\n"); 855 return (ENOBUFS); 856 } 857 858 /* Allocate the jumbo buffer */ 859 tbuf = ti_jalloc(sc); 860 if (tbuf == NULL) { 861 m_freem(m_new); 862 aprint_error_dev(&sc->sc_dev, "jumbo allocation failed " 863 "-- packet dropped!\n"); 864 return (ENOBUFS); 865 } 866 867 /* Attach the buffer to the mbuf. */ 868 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 869 M_DEVBUF, ti_jfree, sc); 870 m_new->m_flags |= M_EXT_RW; 871 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 872 } else { 873 m_new = m; 874 m_new->m_data = m_new->m_ext.ext_buf; 875 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 876 } 877 878 m_adj(m_new, ETHER_ALIGN); 879 /* Set up the descriptor. */ 880 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 881 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 882 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 883 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 884 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 885 r->ti_flags = TI_BDFLAG_JUMBO_RING; 886 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 887 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 888 if (sc->ethercom.ec_if.if_capenable & 889 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 890 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 891 r->ti_len = m_new->m_len; 892 r->ti_idx = i; 893 894 return (0); 895 } 896 897 /* 898 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 899 * that's 1MB or memory, which is a lot. For now, we fill only the first 900 * 256 ring entries and hope that our CPU is fast enough to keep up with 901 * the NIC. 902 */ 903 static int 904 ti_init_rx_ring_std(struct ti_softc *sc) 905 { 906 int i; 907 struct ti_cmd_desc cmd; 908 909 for (i = 0; i < TI_SSLOTS; i++) { 910 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 911 return (ENOBUFS); 912 }; 913 914 TI_UPDATE_STDPROD(sc, i - 1); 915 sc->ti_std = i - 1; 916 917 return (0); 918 } 919 920 static void 921 ti_free_rx_ring_std(struct ti_softc *sc) 922 { 923 int i; 924 925 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 926 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 927 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 928 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 929 930 /* if (sc->std_dmamap[i] == 0) panic() */ 931 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 932 sc->std_dmamap[i] = 0; 933 } 934 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 935 sizeof(struct ti_rx_desc)); 936 } 937 938 return; 939 } 940 941 static int 942 ti_init_rx_ring_jumbo(struct ti_softc *sc) 943 { 944 int i; 945 struct ti_cmd_desc cmd; 946 947 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 948 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 949 return (ENOBUFS); 950 }; 951 952 TI_UPDATE_JUMBOPROD(sc, i - 1); 953 sc->ti_jumbo = i - 1; 954 955 return (0); 956 } 957 958 static void 959 ti_free_rx_ring_jumbo(struct ti_softc *sc) 960 { 961 int i; 962 963 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 964 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 965 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 966 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 967 } 968 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 969 sizeof(struct ti_rx_desc)); 970 } 971 972 return; 973 } 974 975 static int 976 ti_init_rx_ring_mini(struct ti_softc *sc) 977 { 978 int i; 979 980 for (i = 0; i < TI_MSLOTS; i++) { 981 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 982 return (ENOBUFS); 983 }; 984 985 TI_UPDATE_MINIPROD(sc, i - 1); 986 sc->ti_mini = i - 1; 987 988 return (0); 989 } 990 991 static void 992 ti_free_rx_ring_mini(struct ti_softc *sc) 993 { 994 int i; 995 996 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 997 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 998 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 999 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1000 1001 /* if (sc->mini_dmamap[i] == 0) panic() */ 1002 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1003 sc->mini_dmamap[i] = 0; 1004 } 1005 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1006 sizeof(struct ti_rx_desc)); 1007 } 1008 1009 return; 1010 } 1011 1012 static void 1013 ti_free_tx_ring(struct ti_softc *sc) 1014 { 1015 int i; 1016 struct txdmamap_pool_entry *dma; 1017 1018 if (sc->ti_rdata->ti_tx_ring == NULL) 1019 return; 1020 1021 for (i = 0; i < TI_TX_RING_CNT; i++) { 1022 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1023 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1024 sc->ti_cdata.ti_tx_chain[i] = NULL; 1025 1026 /* if (sc->txdma[i] == 0) panic() */ 1027 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1028 link); 1029 sc->txdma[i] = 0; 1030 } 1031 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1032 sizeof(struct ti_tx_desc)); 1033 } 1034 1035 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1036 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1037 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1038 free(dma, M_DEVBUF); 1039 } 1040 1041 return; 1042 } 1043 1044 static int 1045 ti_init_tx_ring(struct ti_softc *sc) 1046 { 1047 int i, error; 1048 bus_dmamap_t dmamap; 1049 struct txdmamap_pool_entry *dma; 1050 1051 sc->ti_txcnt = 0; 1052 sc->ti_tx_saved_considx = 0; 1053 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1054 1055 SIMPLEQ_INIT(&sc->txdma_list); 1056 for (i = 0; i < TI_RSLOTS; i++) { 1057 /* I've seen mbufs with 30 fragments. */ 1058 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1059 40, ETHER_MAX_LEN_JUMBO, 0, 1060 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1061 aprint_error_dev(&sc->sc_dev, "can't create tx map, error = %d\n", 1062 error); 1063 return (ENOMEM); 1064 } 1065 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1066 if (!dma) { 1067 aprint_error_dev(&sc->sc_dev, "can't alloc txdmamap_pool_entry\n"); 1068 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1069 return (ENOMEM); 1070 } 1071 dma->dmamap = dmamap; 1072 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1073 } 1074 1075 return (0); 1076 } 1077 1078 /* 1079 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1080 * but we have to support the old way too so that Tigon 1 cards will 1081 * work. 1082 */ 1083 static void 1084 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1085 { 1086 struct ti_cmd_desc cmd; 1087 u_int16_t *m; 1088 u_int32_t ext[2] = {0, 0}; 1089 1090 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1091 1092 switch (sc->ti_hwrev) { 1093 case TI_HWREV_TIGON: 1094 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1095 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1096 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1097 break; 1098 case TI_HWREV_TIGON_II: 1099 ext[0] = htons(m[0]); 1100 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1101 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1102 break; 1103 default: 1104 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1105 break; 1106 } 1107 1108 return; 1109 } 1110 1111 static void 1112 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1113 { 1114 struct ti_cmd_desc cmd; 1115 u_int16_t *m; 1116 u_int32_t ext[2] = {0, 0}; 1117 1118 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1119 1120 switch (sc->ti_hwrev) { 1121 case TI_HWREV_TIGON: 1122 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1123 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1124 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1125 break; 1126 case TI_HWREV_TIGON_II: 1127 ext[0] = htons(m[0]); 1128 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1129 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1130 break; 1131 default: 1132 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1133 break; 1134 } 1135 1136 return; 1137 } 1138 1139 /* 1140 * Configure the Tigon's multicast address filter. 1141 * 1142 * The actual multicast table management is a bit of a pain, thanks to 1143 * slight brain damage on the part of both Alteon and us. With our 1144 * multicast code, we are only alerted when the multicast address table 1145 * changes and at that point we only have the current list of addresses: 1146 * we only know the current state, not the previous state, so we don't 1147 * actually know what addresses were removed or added. The firmware has 1148 * state, but we can't get our grubby mits on it, and there is no 'delete 1149 * all multicast addresses' command. Hence, we have to maintain our own 1150 * state so we know what addresses have been programmed into the NIC at 1151 * any given time. 1152 */ 1153 static void 1154 ti_setmulti(struct ti_softc *sc) 1155 { 1156 struct ifnet *ifp; 1157 struct ti_cmd_desc cmd; 1158 struct ti_mc_entry *mc; 1159 u_int32_t intrs; 1160 struct ether_multi *enm; 1161 struct ether_multistep step; 1162 1163 ifp = &sc->ethercom.ec_if; 1164 1165 /* Disable interrupts. */ 1166 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1167 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1168 1169 /* First, zot all the existing filters. */ 1170 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1171 ti_del_mcast(sc, &mc->mc_addr); 1172 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1173 free(mc, M_DEVBUF); 1174 } 1175 1176 /* 1177 * Remember all multicast addresses so that we can delete them 1178 * later. Punt if there is a range of addresses or memory shortage. 1179 */ 1180 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1181 while (enm != NULL) { 1182 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1183 ETHER_ADDR_LEN) != 0) 1184 goto allmulti; 1185 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1186 M_NOWAIT)) == NULL) 1187 goto allmulti; 1188 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1189 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1190 ETHER_NEXT_MULTI(step, enm); 1191 } 1192 1193 /* Accept only programmed multicast addresses */ 1194 ifp->if_flags &= ~IFF_ALLMULTI; 1195 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1196 1197 /* Now program new ones. */ 1198 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1199 ti_add_mcast(sc, &mc->mc_addr); 1200 1201 /* Re-enable interrupts. */ 1202 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1203 1204 return; 1205 1206 allmulti: 1207 /* No need to keep individual multicast addresses */ 1208 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1209 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1210 free(mc, M_DEVBUF); 1211 } 1212 1213 /* Accept all multicast addresses */ 1214 ifp->if_flags |= IFF_ALLMULTI; 1215 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1216 1217 /* Re-enable interrupts. */ 1218 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1219 } 1220 1221 /* 1222 * Check to see if the BIOS has configured us for a 64 bit slot when 1223 * we aren't actually in one. If we detect this condition, we can work 1224 * around it on the Tigon 2 by setting a bit in the PCI state register, 1225 * but for the Tigon 1 we must give up and abort the interface attach. 1226 */ 1227 static int 1228 ti_64bitslot_war(struct ti_softc *sc) 1229 { 1230 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1231 CSR_WRITE_4(sc, 0x600, 0); 1232 CSR_WRITE_4(sc, 0x604, 0); 1233 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1234 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1235 if (sc->ti_hwrev == TI_HWREV_TIGON) 1236 return (EINVAL); 1237 else { 1238 TI_SETBIT(sc, TI_PCI_STATE, 1239 TI_PCISTATE_32BIT_BUS); 1240 return (0); 1241 } 1242 } 1243 } 1244 1245 return (0); 1246 } 1247 1248 /* 1249 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1250 * self-test results. 1251 */ 1252 static int 1253 ti_chipinit(struct ti_softc *sc) 1254 { 1255 u_int32_t cacheline; 1256 u_int32_t pci_writemax = 0; 1257 u_int32_t rev; 1258 1259 /* Initialize link to down state. */ 1260 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1261 1262 /* Set endianness before we access any non-PCI registers. */ 1263 #if BYTE_ORDER == BIG_ENDIAN 1264 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1265 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1266 #else 1267 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1268 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1269 #endif 1270 1271 /* Check the ROM failed bit to see if self-tests passed. */ 1272 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1273 printf("%s: board self-diagnostics failed!\n", 1274 device_xname(&sc->sc_dev)); 1275 return (ENODEV); 1276 } 1277 1278 /* Halt the CPU. */ 1279 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1280 1281 /* Figure out the hardware revision. */ 1282 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1283 switch (rev) { 1284 case TI_REV_TIGON_I: 1285 sc->ti_hwrev = TI_HWREV_TIGON; 1286 break; 1287 case TI_REV_TIGON_II: 1288 sc->ti_hwrev = TI_HWREV_TIGON_II; 1289 break; 1290 default: 1291 printf("%s: unsupported chip revision 0x%x\n", 1292 device_xname(&sc->sc_dev), rev); 1293 return (ENODEV); 1294 } 1295 1296 /* Do special setup for Tigon 2. */ 1297 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1298 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1299 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1300 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1301 } 1302 1303 /* Set up the PCI state register. */ 1304 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1305 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1306 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1307 } 1308 1309 /* Clear the read/write max DMA parameters. */ 1310 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1311 TI_PCISTATE_READ_MAXDMA)); 1312 1313 /* Get cache line size. */ 1314 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1315 1316 /* 1317 * If the system has set enabled the PCI memory write 1318 * and invalidate command in the command register, set 1319 * the write max parameter accordingly. This is necessary 1320 * to use MWI with the Tigon 2. 1321 */ 1322 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1323 & PCI_COMMAND_INVALIDATE_ENABLE) { 1324 switch (cacheline) { 1325 case 1: 1326 case 4: 1327 case 8: 1328 case 16: 1329 case 32: 1330 case 64: 1331 break; 1332 default: 1333 /* Disable PCI memory write and invalidate. */ 1334 if (bootverbose) 1335 printf("%s: cache line size %d not " 1336 "supported; disabling PCI MWI\n", 1337 device_xname(&sc->sc_dev), cacheline); 1338 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1339 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1340 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1341 break; 1342 } 1343 } 1344 1345 #ifdef __brokenalpha__ 1346 /* 1347 * From the Alteon sample driver: 1348 * Must insure that we do not cross an 8K (bytes) boundary 1349 * for DMA reads. Our highest limit is 1K bytes. This is a 1350 * restriction on some ALPHA platforms with early revision 1351 * 21174 PCI chipsets, such as the AlphaPC 164lx 1352 */ 1353 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1354 #else 1355 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1356 #endif 1357 1358 /* This sets the min dma param all the way up (0xff). */ 1359 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1360 1361 /* Configure DMA variables. */ 1362 #if BYTE_ORDER == BIG_ENDIAN 1363 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1364 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1365 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1366 TI_OPMODE_DONT_FRAG_JUMBO); 1367 #else 1368 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1369 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1370 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1371 #endif 1372 1373 /* 1374 * Only allow 1 DMA channel to be active at a time. 1375 * I don't think this is a good idea, but without it 1376 * the firmware racks up lots of nicDmaReadRingFull 1377 * errors. 1378 * Incompatible with hardware assisted checksums. 1379 */ 1380 if ((sc->ethercom.ec_if.if_capenable & 1381 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1382 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1383 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1384 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1385 1386 /* Recommended settings from Tigon manual. */ 1387 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1388 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1389 1390 if (ti_64bitslot_war(sc)) { 1391 printf("%s: bios thinks we're in a 64 bit slot, " 1392 "but we aren't", device_xname(&sc->sc_dev)); 1393 return (EINVAL); 1394 } 1395 1396 return (0); 1397 } 1398 1399 /* 1400 * Initialize the general information block and firmware, and 1401 * start the CPU(s) running. 1402 */ 1403 static int 1404 ti_gibinit(struct ti_softc *sc) 1405 { 1406 struct ti_rcb *rcb; 1407 int i; 1408 struct ifnet *ifp; 1409 1410 ifp = &sc->ethercom.ec_if; 1411 1412 /* Disable interrupts for now. */ 1413 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1414 1415 /* Tell the chip where to find the general information block. */ 1416 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1417 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1418 1419 /* Load the firmware into SRAM. */ 1420 ti_loadfw(sc); 1421 1422 /* Set up the contents of the general info and ring control blocks. */ 1423 1424 /* Set up the event ring and producer pointer. */ 1425 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1426 1427 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1428 rcb->ti_flags = 0; 1429 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1430 TI_CDEVPRODADDR(sc); 1431 1432 sc->ti_ev_prodidx.ti_idx = 0; 1433 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1434 sc->ti_ev_saved_considx = 0; 1435 1436 /* Set up the command ring and producer mailbox. */ 1437 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1438 1439 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1440 rcb->ti_flags = 0; 1441 rcb->ti_max_len = 0; 1442 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1443 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1444 } 1445 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1446 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1447 sc->ti_cmd_saved_prodidx = 0; 1448 1449 /* 1450 * Assign the address of the stats refresh buffer. 1451 * We re-use the current stats buffer for this to 1452 * conserve memory. 1453 */ 1454 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1455 TI_CDSTATSADDR(sc); 1456 1457 /* Set up the standard receive ring. */ 1458 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1459 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1460 rcb->ti_max_len = ETHER_MAX_LEN; 1461 rcb->ti_flags = 0; 1462 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1463 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1464 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1465 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1466 if (VLAN_ATTACHED(&sc->ethercom)) 1467 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1468 1469 /* Set up the jumbo receive ring. */ 1470 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1471 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1472 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1473 rcb->ti_flags = 0; 1474 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1475 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1476 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1477 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1478 if (VLAN_ATTACHED(&sc->ethercom)) 1479 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1480 1481 /* 1482 * Set up the mini ring. Only activated on the 1483 * Tigon 2 but the slot in the config block is 1484 * still there on the Tigon 1. 1485 */ 1486 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1487 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1488 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1489 if (sc->ti_hwrev == TI_HWREV_TIGON) 1490 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1491 else 1492 rcb->ti_flags = 0; 1493 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1494 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1495 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1496 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1497 if (VLAN_ATTACHED(&sc->ethercom)) 1498 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1499 1500 /* 1501 * Set up the receive return ring. 1502 */ 1503 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1504 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1505 rcb->ti_flags = 0; 1506 rcb->ti_max_len = TI_RETURN_RING_CNT; 1507 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1508 TI_CDRTNPRODADDR(sc); 1509 1510 /* 1511 * Set up the tx ring. Note: for the Tigon 2, we have the option 1512 * of putting the transmit ring in the host's address space and 1513 * letting the chip DMA it instead of leaving the ring in the NIC's 1514 * memory and accessing it through the shared memory region. We 1515 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1516 * so we have to revert to the shared memory scheme if we detect 1517 * a Tigon 1 chip. 1518 */ 1519 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1520 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1521 sc->ti_tx_ring_nic = 1522 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1523 } 1524 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1525 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1526 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1527 if (sc->ti_hwrev == TI_HWREV_TIGON) 1528 rcb->ti_flags = 0; 1529 else 1530 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1531 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1532 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1533 /* 1534 * When we get the packet, there is a pseudo-header seed already 1535 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1536 * compute the pseudo-header checksum again! 1537 */ 1538 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1539 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1540 TI_RCB_FLAG_NO_PHDR_CKSUM; 1541 if (VLAN_ATTACHED(&sc->ethercom)) 1542 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1543 rcb->ti_max_len = TI_TX_RING_CNT; 1544 if (sc->ti_hwrev == TI_HWREV_TIGON) 1545 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1546 else 1547 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1548 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1549 TI_CDTXCONSADDR(sc); 1550 1551 /* 1552 * We're done frobbing the General Information Block. Sync 1553 * it. Note we take care of the first stats sync here, as 1554 * well. 1555 */ 1556 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1557 1558 /* Set up tuneables */ 1559 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1560 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1561 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1562 (sc->ti_rx_coal_ticks / 10)); 1563 else 1564 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1565 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1566 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1567 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1568 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1569 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1570 1571 /* Turn interrupts on. */ 1572 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1573 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1574 1575 /* Start CPU. */ 1576 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1577 1578 return (0); 1579 } 1580 1581 /* 1582 * look for id in the device list, returning the first match 1583 */ 1584 static const struct ti_type * 1585 ti_type_match(struct pci_attach_args *pa) 1586 { 1587 const struct ti_type *t; 1588 1589 t = ti_devs; 1590 while (t->ti_name != NULL) { 1591 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1592 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1593 return (t); 1594 } 1595 t++; 1596 } 1597 1598 return (NULL); 1599 } 1600 1601 /* 1602 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1603 * against our list and return its name if we find a match. 1604 */ 1605 static int 1606 ti_probe(device_t parent, cfdata_t match, void *aux) 1607 { 1608 struct pci_attach_args *pa = aux; 1609 const struct ti_type *t; 1610 1611 t = ti_type_match(pa); 1612 1613 return ((t == NULL) ? 0 : 1); 1614 } 1615 1616 static void 1617 ti_attach(device_t parent, device_t self, void *aux) 1618 { 1619 u_int32_t command; 1620 struct ifnet *ifp; 1621 struct ti_softc *sc; 1622 u_int8_t eaddr[ETHER_ADDR_LEN]; 1623 struct pci_attach_args *pa = aux; 1624 pci_chipset_tag_t pc = pa->pa_pc; 1625 pci_intr_handle_t ih; 1626 const char *intrstr = NULL; 1627 bus_dma_segment_t dmaseg; 1628 int error, dmanseg, nolinear; 1629 const struct ti_type *t; 1630 1631 t = ti_type_match(pa); 1632 if (t == NULL) { 1633 printf("ti_attach: were did the card go ?\n"); 1634 return; 1635 } 1636 1637 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1638 1639 sc = device_private(self); 1640 1641 /* 1642 * Map control/status registers. 1643 */ 1644 nolinear = 0; 1645 if (pci_mapreg_map(pa, 0x10, 1646 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1647 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1648 NULL, NULL)) { 1649 nolinear = 1; 1650 if (pci_mapreg_map(pa, 0x10, 1651 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1652 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1653 printf(": can't map memory space\n"); 1654 return; 1655 } 1656 } 1657 if (nolinear == 0) 1658 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1659 else 1660 sc->ti_vhandle = NULL; 1661 1662 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1663 command |= PCI_COMMAND_MASTER_ENABLE; 1664 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1665 1666 /* Allocate interrupt */ 1667 if (pci_intr_map(pa, &ih)) { 1668 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 1669 return; 1670 } 1671 intrstr = pci_intr_string(pc, ih); 1672 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1673 if (sc->sc_ih == NULL) { 1674 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 1675 if (intrstr != NULL) 1676 printf(" at %s", intrstr); 1677 printf("\n"); 1678 return; 1679 } 1680 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1681 /* 1682 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1683 * doing do could allow DMA to corrupt kernel memory during the 1684 * reboot before the driver initializes. 1685 */ 1686 (void) shutdownhook_establish(ti_shutdown, sc); 1687 1688 if (ti_chipinit(sc)) { 1689 aprint_error_dev(self, "chip initialization failed\n"); 1690 goto fail2; 1691 } 1692 1693 /* 1694 * Deal with some chip diffrences. 1695 */ 1696 switch (sc->ti_hwrev) { 1697 case TI_HWREV_TIGON: 1698 sc->sc_tx_encap = ti_encap_tigon1; 1699 sc->sc_tx_eof = ti_txeof_tigon1; 1700 if (nolinear == 1) 1701 aprint_error_dev(self, "memory space not mapped linear\n"); 1702 break; 1703 1704 case TI_HWREV_TIGON_II: 1705 sc->sc_tx_encap = ti_encap_tigon2; 1706 sc->sc_tx_eof = ti_txeof_tigon2; 1707 break; 1708 1709 default: 1710 printf("%s: Unknown chip version: %d\n", device_xname(self), 1711 sc->ti_hwrev); 1712 goto fail2; 1713 } 1714 1715 /* Zero out the NIC's on-board SRAM. */ 1716 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1717 1718 /* Init again -- zeroing memory may have clobbered some registers. */ 1719 if (ti_chipinit(sc)) { 1720 aprint_error_dev(self, "chip initialization failed\n"); 1721 goto fail2; 1722 } 1723 1724 /* 1725 * Get station address from the EEPROM. Note: the manual states 1726 * that the MAC address is at offset 0x8c, however the data is 1727 * stored as two longwords (since that's how it's loaded into 1728 * the NIC). This means the MAC address is actually preceded 1729 * by two zero bytes. We need to skip over those. 1730 */ 1731 if (ti_read_eeprom(sc, (void *)&eaddr, 1732 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1733 aprint_error_dev(self, "failed to read station address\n"); 1734 goto fail2; 1735 } 1736 1737 /* 1738 * A Tigon chip was detected. Inform the world. 1739 */ 1740 aprint_error_dev(self, "Ethernet address: %s\n", 1741 ether_sprintf(eaddr)); 1742 1743 sc->sc_dmat = pa->pa_dmat; 1744 1745 /* Allocate the general information block and ring buffers. */ 1746 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1747 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1748 BUS_DMA_NOWAIT)) != 0) { 1749 aprint_error_dev(&sc->sc_dev, "can't allocate ring buffer, error = %d\n", 1750 error); 1751 goto fail2; 1752 } 1753 1754 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1755 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1756 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1757 aprint_error_dev(&sc->sc_dev, "can't map ring buffer, error = %d\n", 1758 error); 1759 goto fail2; 1760 } 1761 1762 if ((error = bus_dmamap_create(sc->sc_dmat, 1763 sizeof(struct ti_ring_data), 1, 1764 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1765 &sc->info_dmamap)) != 0) { 1766 aprint_error_dev(&sc->sc_dev, "can't create ring buffer DMA map, error = %d\n", 1767 error); 1768 goto fail2; 1769 } 1770 1771 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1772 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1773 BUS_DMA_NOWAIT)) != 0) { 1774 aprint_error_dev(&sc->sc_dev, "can't load ring buffer DMA map, error = %d\n", 1775 error); 1776 goto fail2; 1777 } 1778 1779 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1780 1781 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1782 1783 /* Try to allocate memory for jumbo buffers. */ 1784 if (ti_alloc_jumbo_mem(sc)) { 1785 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1786 goto fail2; 1787 } 1788 1789 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1790 1791 /* 1792 * We really need a better way to tell a 1000baseT card 1793 * from a 1000baseSX one, since in theory there could be 1794 * OEMed 1000baseT cards from lame vendors who aren't 1795 * clever enough to change the PCI ID. For the moment 1796 * though, the AceNIC is the only copper card available. 1797 */ 1798 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1799 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1800 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1801 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1802 sc->ti_copper = 1; 1803 else 1804 sc->ti_copper = 0; 1805 1806 /* Set default tuneable values. */ 1807 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1808 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1809 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1810 sc->ti_rx_max_coal_bds = 64; 1811 sc->ti_tx_max_coal_bds = 128; 1812 sc->ti_tx_buf_ratio = 21; 1813 1814 /* Set up ifnet structure */ 1815 ifp = &sc->ethercom.ec_if; 1816 ifp->if_softc = sc; 1817 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1819 ifp->if_ioctl = ti_ioctl; 1820 ifp->if_start = ti_start; 1821 ifp->if_watchdog = ti_watchdog; 1822 IFQ_SET_READY(&ifp->if_snd); 1823 1824 #if 0 1825 /* 1826 * XXX This is not really correct -- we don't necessarily 1827 * XXX want to queue up as many as we can transmit at the 1828 * XXX upper layer like that. Someone with a board should 1829 * XXX check to see how this affects performance. 1830 */ 1831 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1832 #endif 1833 1834 /* 1835 * We can support 802.1Q VLAN-sized frames. 1836 */ 1837 sc->ethercom.ec_capabilities |= 1838 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1839 1840 /* 1841 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1842 */ 1843 ifp->if_capabilities |= 1844 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1845 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1846 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1847 1848 /* Set up ifmedia support. */ 1849 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1850 if (sc->ti_copper) { 1851 /* 1852 * Copper cards allow manual 10/100 mode selection, 1853 * but not manual 1000baseT mode selection. Why? 1854 * Because currently there's no way to specify the 1855 * master/slave setting through the firmware interface, 1856 * so Alteon decided to just bag it and handle it 1857 * via autonegotiation. 1858 */ 1859 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1860 ifmedia_add(&sc->ifmedia, 1861 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1863 ifmedia_add(&sc->ifmedia, 1864 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1865 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1866 ifmedia_add(&sc->ifmedia, 1867 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1868 } else { 1869 /* Fiber cards don't support 10/100 modes. */ 1870 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1871 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1872 } 1873 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1874 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1875 1876 /* 1877 * Call MI attach routines. 1878 */ 1879 if_attach(ifp); 1880 ether_ifattach(ifp, eaddr); 1881 1882 return; 1883 fail2: 1884 pci_intr_disestablish(pc, sc->sc_ih); 1885 return; 1886 } 1887 1888 /* 1889 * Frame reception handling. This is called if there's a frame 1890 * on the receive return list. 1891 * 1892 * Note: we have to be able to handle three possibilities here: 1893 * 1) the frame is from the mini receive ring (can only happen) 1894 * on Tigon 2 boards) 1895 * 2) the frame is from the jumbo receive ring 1896 * 3) the frame is from the standard receive ring 1897 */ 1898 1899 static void 1900 ti_rxeof(struct ti_softc *sc) 1901 { 1902 struct ifnet *ifp; 1903 struct ti_cmd_desc cmd; 1904 1905 ifp = &sc->ethercom.ec_if; 1906 1907 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1908 struct ti_rx_desc *cur_rx; 1909 u_int32_t rxidx; 1910 struct mbuf *m = NULL; 1911 struct ether_header *eh; 1912 bus_dmamap_t dmamap; 1913 1914 cur_rx = 1915 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1916 rxidx = cur_rx->ti_idx; 1917 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1918 1919 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1920 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1921 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1922 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1923 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1924 ifp->if_ierrors++; 1925 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1926 continue; 1927 } 1928 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1929 == ENOBUFS) { 1930 ifp->if_ierrors++; 1931 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1932 continue; 1933 } 1934 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1935 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1936 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1937 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1938 dmamap = sc->mini_dmamap[rxidx]; 1939 sc->mini_dmamap[rxidx] = 0; 1940 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1941 ifp->if_ierrors++; 1942 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1943 continue; 1944 } 1945 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1946 == ENOBUFS) { 1947 ifp->if_ierrors++; 1948 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1949 continue; 1950 } 1951 } else { 1952 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1953 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1954 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1955 dmamap = sc->std_dmamap[rxidx]; 1956 sc->std_dmamap[rxidx] = 0; 1957 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1958 ifp->if_ierrors++; 1959 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1960 continue; 1961 } 1962 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1963 == ENOBUFS) { 1964 ifp->if_ierrors++; 1965 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1966 continue; 1967 } 1968 } 1969 1970 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1971 ifp->if_ipackets++; 1972 m->m_pkthdr.rcvif = ifp; 1973 1974 #if NBPFILTER > 0 1975 /* 1976 * Handle BPF listeners. Let the BPF user see the packet, but 1977 * don't pass it up to the ether_input() layer unless it's 1978 * a broadcast packet, multicast packet, matches our ethernet 1979 * address or the interface is in promiscuous mode. 1980 */ 1981 if (ifp->if_bpf) 1982 bpf_mtap(ifp->if_bpf, m); 1983 #endif 1984 1985 eh = mtod(m, struct ether_header *); 1986 switch (ntohs(eh->ether_type)) { 1987 #ifdef INET 1988 case ETHERTYPE_IP: 1989 { 1990 struct ip *ip = (struct ip *) (eh + 1); 1991 1992 /* 1993 * Note the Tigon firmware does not invert 1994 * the checksum for us, hence the XOR. 1995 */ 1996 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1997 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1998 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1999 /* 2000 * ntohs() the constant so the compiler can 2001 * optimize... 2002 * 2003 * XXX Figure out a sane way to deal with 2004 * fragmented packets. 2005 */ 2006 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2007 switch (ip->ip_p) { 2008 case IPPROTO_TCP: 2009 m->m_pkthdr.csum_data = 2010 cur_rx->ti_tcp_udp_cksum; 2011 m->m_pkthdr.csum_flags |= 2012 M_CSUM_TCPv4|M_CSUM_DATA; 2013 break; 2014 case IPPROTO_UDP: 2015 m->m_pkthdr.csum_data = 2016 cur_rx->ti_tcp_udp_cksum; 2017 m->m_pkthdr.csum_flags |= 2018 M_CSUM_UDPv4|M_CSUM_DATA; 2019 break; 2020 default: 2021 /* Nothing */; 2022 } 2023 } 2024 break; 2025 } 2026 #endif 2027 default: 2028 /* Nothing. */ 2029 break; 2030 } 2031 2032 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2033 VLAN_INPUT_TAG(ifp, m, 2034 /* ti_vlan_tag also has the priority, trim it */ 2035 cur_rx->ti_vlan_tag & 4095, 2036 continue); 2037 } 2038 2039 (*ifp->if_input)(ifp, m); 2040 } 2041 2042 /* Only necessary on the Tigon 1. */ 2043 if (sc->ti_hwrev == TI_HWREV_TIGON) 2044 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2045 sc->ti_rx_saved_considx); 2046 2047 TI_UPDATE_STDPROD(sc, sc->ti_std); 2048 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2049 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2050 } 2051 2052 static void 2053 ti_txeof_tigon1(struct ti_softc *sc) 2054 { 2055 struct ti_tx_desc *cur_tx = NULL; 2056 struct ifnet *ifp; 2057 struct txdmamap_pool_entry *dma; 2058 2059 ifp = &sc->ethercom.ec_if; 2060 2061 /* 2062 * Go through our tx ring and free mbufs for those 2063 * frames that have been sent. 2064 */ 2065 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2066 u_int32_t idx = 0; 2067 2068 idx = sc->ti_tx_saved_considx; 2069 if (idx > 383) 2070 CSR_WRITE_4(sc, TI_WINBASE, 2071 TI_TX_RING_BASE + 6144); 2072 else if (idx > 255) 2073 CSR_WRITE_4(sc, TI_WINBASE, 2074 TI_TX_RING_BASE + 4096); 2075 else if (idx > 127) 2076 CSR_WRITE_4(sc, TI_WINBASE, 2077 TI_TX_RING_BASE + 2048); 2078 else 2079 CSR_WRITE_4(sc, TI_WINBASE, 2080 TI_TX_RING_BASE); 2081 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2082 if (cur_tx->ti_flags & TI_BDFLAG_END) 2083 ifp->if_opackets++; 2084 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2085 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2086 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2087 2088 dma = sc->txdma[idx]; 2089 KDASSERT(dma != NULL); 2090 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2091 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2092 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2093 2094 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2095 sc->txdma[idx] = NULL; 2096 } 2097 sc->ti_txcnt--; 2098 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2099 ifp->if_timer = 0; 2100 } 2101 2102 if (cur_tx != NULL) 2103 ifp->if_flags &= ~IFF_OACTIVE; 2104 } 2105 2106 static void 2107 ti_txeof_tigon2(struct ti_softc *sc) 2108 { 2109 struct ti_tx_desc *cur_tx = NULL; 2110 struct ifnet *ifp; 2111 struct txdmamap_pool_entry *dma; 2112 int firstidx, cnt; 2113 2114 ifp = &sc->ethercom.ec_if; 2115 2116 /* 2117 * Go through our tx ring and free mbufs for those 2118 * frames that have been sent. 2119 */ 2120 firstidx = sc->ti_tx_saved_considx; 2121 cnt = 0; 2122 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2123 u_int32_t idx = 0; 2124 2125 idx = sc->ti_tx_saved_considx; 2126 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2127 if (cur_tx->ti_flags & TI_BDFLAG_END) 2128 ifp->if_opackets++; 2129 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2130 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2131 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2132 2133 dma = sc->txdma[idx]; 2134 KDASSERT(dma != NULL); 2135 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2136 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2137 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2138 2139 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2140 sc->txdma[idx] = NULL; 2141 } 2142 cnt++; 2143 sc->ti_txcnt--; 2144 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2145 ifp->if_timer = 0; 2146 } 2147 2148 if (cnt != 0) 2149 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2150 2151 if (cur_tx != NULL) 2152 ifp->if_flags &= ~IFF_OACTIVE; 2153 } 2154 2155 static int 2156 ti_intr(void *xsc) 2157 { 2158 struct ti_softc *sc; 2159 struct ifnet *ifp; 2160 2161 sc = xsc; 2162 ifp = &sc->ethercom.ec_if; 2163 2164 #ifdef notdef 2165 /* Avoid this for now -- checking this register is expensive. */ 2166 /* Make sure this is really our interrupt. */ 2167 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2168 return (0); 2169 #endif 2170 2171 /* Ack interrupt and stop others from occuring. */ 2172 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2173 2174 if (ifp->if_flags & IFF_RUNNING) { 2175 /* Check RX return ring producer/consumer */ 2176 ti_rxeof(sc); 2177 2178 /* Check TX ring producer/consumer */ 2179 (*sc->sc_tx_eof)(sc); 2180 } 2181 2182 ti_handle_events(sc); 2183 2184 /* Re-enable interrupts. */ 2185 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2186 2187 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2188 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2189 ti_start(ifp); 2190 2191 return (1); 2192 } 2193 2194 static void 2195 ti_stats_update(struct ti_softc *sc) 2196 { 2197 struct ifnet *ifp; 2198 2199 ifp = &sc->ethercom.ec_if; 2200 2201 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2202 2203 ifp->if_collisions += 2204 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2205 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2206 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2207 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2208 ifp->if_collisions; 2209 2210 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2211 } 2212 2213 /* 2214 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2215 * pointers to descriptors. 2216 */ 2217 static int 2218 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2219 { 2220 struct ti_tx_desc *f = NULL; 2221 u_int32_t frag, cur, cnt = 0; 2222 struct txdmamap_pool_entry *dma; 2223 bus_dmamap_t dmamap; 2224 int error, i; 2225 struct m_tag *mtag; 2226 u_int16_t csum_flags = 0; 2227 2228 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2229 if (dma == NULL) { 2230 return ENOMEM; 2231 } 2232 dmamap = dma->dmamap; 2233 2234 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2235 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2236 if (error) { 2237 struct mbuf *m; 2238 int j = 0; 2239 for (m = m_head; m; m = m->m_next) 2240 j++; 2241 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2242 "error %d\n", m_head->m_pkthdr.len, j, error); 2243 return (ENOMEM); 2244 } 2245 2246 cur = frag = *txidx; 2247 2248 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2249 /* IP header checksum field must be 0! */ 2250 csum_flags |= TI_BDFLAG_IP_CKSUM; 2251 } 2252 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2253 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2254 2255 /* XXX fragmented packet checksum capability? */ 2256 2257 /* 2258 * Start packing the mbufs in this chain into 2259 * the fragment pointers. Stop when we run out 2260 * of fragments or hit the end of the mbuf chain. 2261 */ 2262 for (i = 0; i < dmamap->dm_nsegs; i++) { 2263 if (frag > 383) 2264 CSR_WRITE_4(sc, TI_WINBASE, 2265 TI_TX_RING_BASE + 6144); 2266 else if (frag > 255) 2267 CSR_WRITE_4(sc, TI_WINBASE, 2268 TI_TX_RING_BASE + 4096); 2269 else if (frag > 127) 2270 CSR_WRITE_4(sc, TI_WINBASE, 2271 TI_TX_RING_BASE + 2048); 2272 else 2273 CSR_WRITE_4(sc, TI_WINBASE, 2274 TI_TX_RING_BASE); 2275 f = &sc->ti_tx_ring_nic[frag % 128]; 2276 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2277 break; 2278 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2279 f->ti_len = dmamap->dm_segs[i].ds_len; 2280 f->ti_flags = csum_flags; 2281 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2282 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2283 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2284 } else { 2285 f->ti_vlan_tag = 0; 2286 } 2287 /* 2288 * Sanity check: avoid coming within 16 descriptors 2289 * of the end of the ring. 2290 */ 2291 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2292 return (ENOBUFS); 2293 cur = frag; 2294 TI_INC(frag, TI_TX_RING_CNT); 2295 cnt++; 2296 } 2297 2298 if (i < dmamap->dm_nsegs) 2299 return (ENOBUFS); 2300 2301 if (frag == sc->ti_tx_saved_considx) 2302 return (ENOBUFS); 2303 2304 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2305 TI_BDFLAG_END; 2306 2307 /* Sync the packet's DMA map. */ 2308 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2309 BUS_DMASYNC_PREWRITE); 2310 2311 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2312 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2313 sc->txdma[cur] = dma; 2314 sc->ti_txcnt += cnt; 2315 2316 *txidx = frag; 2317 2318 return (0); 2319 } 2320 2321 static int 2322 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2323 { 2324 struct ti_tx_desc *f = NULL; 2325 u_int32_t frag, firstfrag, cur, cnt = 0; 2326 struct txdmamap_pool_entry *dma; 2327 bus_dmamap_t dmamap; 2328 int error, i; 2329 struct m_tag *mtag; 2330 u_int16_t csum_flags = 0; 2331 2332 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2333 if (dma == NULL) { 2334 return ENOMEM; 2335 } 2336 dmamap = dma->dmamap; 2337 2338 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2339 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2340 if (error) { 2341 struct mbuf *m; 2342 int j = 0; 2343 for (m = m_head; m; m = m->m_next) 2344 j++; 2345 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2346 "error %d\n", m_head->m_pkthdr.len, j, error); 2347 return (ENOMEM); 2348 } 2349 2350 cur = firstfrag = frag = *txidx; 2351 2352 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2353 /* IP header checksum field must be 0! */ 2354 csum_flags |= TI_BDFLAG_IP_CKSUM; 2355 } 2356 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2357 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2358 2359 /* XXX fragmented packet checksum capability? */ 2360 2361 /* 2362 * Start packing the mbufs in this chain into 2363 * the fragment pointers. Stop when we run out 2364 * of fragments or hit the end of the mbuf chain. 2365 */ 2366 for (i = 0; i < dmamap->dm_nsegs; i++) { 2367 f = &sc->ti_rdata->ti_tx_ring[frag]; 2368 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2369 break; 2370 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2371 f->ti_len = dmamap->dm_segs[i].ds_len; 2372 f->ti_flags = csum_flags; 2373 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2374 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2375 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2376 } else { 2377 f->ti_vlan_tag = 0; 2378 } 2379 /* 2380 * Sanity check: avoid coming within 16 descriptors 2381 * of the end of the ring. 2382 */ 2383 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2384 return (ENOBUFS); 2385 cur = frag; 2386 TI_INC(frag, TI_TX_RING_CNT); 2387 cnt++; 2388 } 2389 2390 if (i < dmamap->dm_nsegs) 2391 return (ENOBUFS); 2392 2393 if (frag == sc->ti_tx_saved_considx) 2394 return (ENOBUFS); 2395 2396 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2397 2398 /* Sync the packet's DMA map. */ 2399 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2400 BUS_DMASYNC_PREWRITE); 2401 2402 /* Sync the descriptors we are using. */ 2403 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2404 2405 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2406 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2407 sc->txdma[cur] = dma; 2408 sc->ti_txcnt += cnt; 2409 2410 *txidx = frag; 2411 2412 return (0); 2413 } 2414 2415 /* 2416 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2417 * to the mbuf data regions directly in the transmit descriptors. 2418 */ 2419 static void 2420 ti_start(struct ifnet *ifp) 2421 { 2422 struct ti_softc *sc; 2423 struct mbuf *m_head = NULL; 2424 u_int32_t prodidx = 0; 2425 2426 sc = ifp->if_softc; 2427 2428 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2429 2430 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2431 IFQ_POLL(&ifp->if_snd, m_head); 2432 if (m_head == NULL) 2433 break; 2434 2435 /* 2436 * Pack the data into the transmit ring. If we 2437 * don't have room, set the OACTIVE flag and wait 2438 * for the NIC to drain the ring. 2439 */ 2440 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2441 ifp->if_flags |= IFF_OACTIVE; 2442 break; 2443 } 2444 2445 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2446 2447 /* 2448 * If there's a BPF listener, bounce a copy of this frame 2449 * to him. 2450 */ 2451 #if NBPFILTER > 0 2452 if (ifp->if_bpf) 2453 bpf_mtap(ifp->if_bpf, m_head); 2454 #endif 2455 } 2456 2457 /* Transmit */ 2458 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2459 2460 /* 2461 * Set a timeout in case the chip goes out to lunch. 2462 */ 2463 ifp->if_timer = 5; 2464 } 2465 2466 static void 2467 ti_init(void *xsc) 2468 { 2469 struct ti_softc *sc = xsc; 2470 int s; 2471 2472 s = splnet(); 2473 2474 /* Cancel pending I/O and flush buffers. */ 2475 ti_stop(sc); 2476 2477 /* Init the gen info block, ring control blocks and firmware. */ 2478 if (ti_gibinit(sc)) { 2479 aprint_error_dev(&sc->sc_dev, "initialization failure\n"); 2480 splx(s); 2481 return; 2482 } 2483 2484 splx(s); 2485 } 2486 2487 static void 2488 ti_init2(struct ti_softc *sc) 2489 { 2490 struct ti_cmd_desc cmd; 2491 struct ifnet *ifp; 2492 const u_int8_t *m; 2493 struct ifmedia *ifm; 2494 int tmp; 2495 2496 ifp = &sc->ethercom.ec_if; 2497 2498 /* Specify MTU and interface index. */ 2499 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2500 2501 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2502 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2503 tmp += ETHER_VLAN_ENCAP_LEN; 2504 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2505 2506 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2507 2508 /* Load our MAC address. */ 2509 m = (const u_int8_t *)CLLADDR(ifp->if_sadl); 2510 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2511 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2512 | (m[4] << 8) | m[5]); 2513 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2514 2515 /* Enable or disable promiscuous mode as needed. */ 2516 if (ifp->if_flags & IFF_PROMISC) { 2517 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2518 } else { 2519 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2520 } 2521 2522 /* Program multicast filter. */ 2523 ti_setmulti(sc); 2524 2525 /* 2526 * If this is a Tigon 1, we should tell the 2527 * firmware to use software packet filtering. 2528 */ 2529 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2530 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2531 } 2532 2533 /* Init RX ring. */ 2534 ti_init_rx_ring_std(sc); 2535 2536 /* Init jumbo RX ring. */ 2537 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2538 ti_init_rx_ring_jumbo(sc); 2539 2540 /* 2541 * If this is a Tigon 2, we can also configure the 2542 * mini ring. 2543 */ 2544 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2545 ti_init_rx_ring_mini(sc); 2546 2547 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2548 sc->ti_rx_saved_considx = 0; 2549 2550 /* Init TX ring. */ 2551 ti_init_tx_ring(sc); 2552 2553 /* Tell firmware we're alive. */ 2554 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2555 2556 /* Enable host interrupts. */ 2557 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2558 2559 ifp->if_flags |= IFF_RUNNING; 2560 ifp->if_flags &= ~IFF_OACTIVE; 2561 2562 /* 2563 * Make sure to set media properly. We have to do this 2564 * here since we have to issue commands in order to set 2565 * the link negotiation and we can't issue commands until 2566 * the firmware is running. 2567 */ 2568 ifm = &sc->ifmedia; 2569 tmp = ifm->ifm_media; 2570 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2571 ti_ifmedia_upd(ifp); 2572 ifm->ifm_media = tmp; 2573 } 2574 2575 /* 2576 * Set media options. 2577 */ 2578 static int 2579 ti_ifmedia_upd(struct ifnet *ifp) 2580 { 2581 struct ti_softc *sc; 2582 struct ifmedia *ifm; 2583 struct ti_cmd_desc cmd; 2584 2585 sc = ifp->if_softc; 2586 ifm = &sc->ifmedia; 2587 2588 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2589 return (EINVAL); 2590 2591 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2592 case IFM_AUTO: 2593 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2594 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2595 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2596 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2597 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2598 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2599 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2600 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2601 break; 2602 case IFM_1000_SX: 2603 case IFM_1000_T: 2604 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2605 CSR_WRITE_4(sc, TI_GCR_GLINK, 2606 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2607 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2608 } else { 2609 CSR_WRITE_4(sc, TI_GCR_GLINK, 2610 TI_GLNK_PREF|TI_GLNK_1000MB| 2611 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2612 } 2613 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2614 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2615 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2616 break; 2617 case IFM_100_FX: 2618 case IFM_10_FL: 2619 case IFM_100_TX: 2620 case IFM_10_T: 2621 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2622 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2623 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2624 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2625 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2626 } else { 2627 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2628 } 2629 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2630 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2631 } else { 2632 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2633 } 2634 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2635 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2636 break; 2637 } 2638 2639 sc->ethercom.ec_if.if_baudrate = 2640 ifmedia_baudrate(ifm->ifm_media); 2641 2642 return (0); 2643 } 2644 2645 /* 2646 * Report current media status. 2647 */ 2648 static void 2649 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2650 { 2651 struct ti_softc *sc; 2652 u_int32_t media = 0; 2653 2654 sc = ifp->if_softc; 2655 2656 ifmr->ifm_status = IFM_AVALID; 2657 ifmr->ifm_active = IFM_ETHER; 2658 2659 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2660 return; 2661 2662 ifmr->ifm_status |= IFM_ACTIVE; 2663 2664 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2665 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2666 if (sc->ti_copper) 2667 ifmr->ifm_active |= IFM_1000_T; 2668 else 2669 ifmr->ifm_active |= IFM_1000_SX; 2670 if (media & TI_GLNK_FULL_DUPLEX) 2671 ifmr->ifm_active |= IFM_FDX; 2672 else 2673 ifmr->ifm_active |= IFM_HDX; 2674 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2675 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2676 if (sc->ti_copper) { 2677 if (media & TI_LNK_100MB) 2678 ifmr->ifm_active |= IFM_100_TX; 2679 if (media & TI_LNK_10MB) 2680 ifmr->ifm_active |= IFM_10_T; 2681 } else { 2682 if (media & TI_LNK_100MB) 2683 ifmr->ifm_active |= IFM_100_FX; 2684 if (media & TI_LNK_10MB) 2685 ifmr->ifm_active |= IFM_10_FL; 2686 } 2687 if (media & TI_LNK_FULL_DUPLEX) 2688 ifmr->ifm_active |= IFM_FDX; 2689 if (media & TI_LNK_HALF_DUPLEX) 2690 ifmr->ifm_active |= IFM_HDX; 2691 } 2692 2693 sc->ethercom.ec_if.if_baudrate = 2694 ifmedia_baudrate(sc->ifmedia.ifm_media); 2695 } 2696 2697 static int 2698 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2699 { 2700 struct ifaddr *ifa = (struct ifaddr *) data; 2701 struct ti_softc *sc = ifp->if_softc; 2702 2703 if ((ifp->if_flags & IFF_UP) == 0) { 2704 ifp->if_flags |= IFF_UP; 2705 ti_init(sc); 2706 } 2707 2708 switch (cmd) { 2709 case SIOCINITIFADDR: 2710 2711 switch (ifa->ifa_addr->sa_family) { 2712 #ifdef INET 2713 case AF_INET: 2714 arp_ifinit(ifp, ifa); 2715 break; 2716 #endif 2717 default: 2718 break; 2719 } 2720 break; 2721 2722 default: 2723 return (EINVAL); 2724 } 2725 2726 return (0); 2727 } 2728 2729 static int 2730 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2731 { 2732 struct ti_softc *sc = ifp->if_softc; 2733 struct ifreq *ifr = (struct ifreq *) data; 2734 int s, error = 0; 2735 struct ti_cmd_desc cmd; 2736 2737 s = splnet(); 2738 2739 switch (command) { 2740 case SIOCINITIFADDR: 2741 error = ti_ether_ioctl(ifp, command, data); 2742 break; 2743 case SIOCSIFMTU: 2744 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2745 error = EINVAL; 2746 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET){ 2747 ti_init(sc); 2748 error = 0; 2749 } 2750 break; 2751 case SIOCSIFFLAGS: 2752 if ((error = ifioctl_common(ifp, command, data)) != 0) 2753 break; 2754 if (ifp->if_flags & IFF_UP) { 2755 /* 2756 * If only the state of the PROMISC flag changed, 2757 * then just use the 'set promisc mode' command 2758 * instead of reinitializing the entire NIC. Doing 2759 * a full re-init means reloading the firmware and 2760 * waiting for it to start up, which may take a 2761 * second or two. 2762 */ 2763 if (ifp->if_flags & IFF_RUNNING && 2764 ifp->if_flags & IFF_PROMISC && 2765 !(sc->ti_if_flags & IFF_PROMISC)) { 2766 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2767 TI_CMD_CODE_PROMISC_ENB, 0); 2768 } else if (ifp->if_flags & IFF_RUNNING && 2769 !(ifp->if_flags & IFF_PROMISC) && 2770 sc->ti_if_flags & IFF_PROMISC) { 2771 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2772 TI_CMD_CODE_PROMISC_DIS, 0); 2773 } else 2774 ti_init(sc); 2775 } else { 2776 if (ifp->if_flags & IFF_RUNNING) { 2777 ti_stop(sc); 2778 } 2779 } 2780 sc->ti_if_flags = ifp->if_flags; 2781 error = 0; 2782 break; 2783 case SIOCSIFMEDIA: 2784 case SIOCGIFMEDIA: 2785 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2786 break; 2787 default: 2788 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2789 break; 2790 2791 error = 0; 2792 2793 if (command == SIOCSIFCAP) 2794 ti_init(sc); 2795 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2796 ; 2797 else if (ifp->if_flags & IFF_RUNNING) 2798 ti_setmulti(sc); 2799 break; 2800 } 2801 2802 (void)splx(s); 2803 2804 return (error); 2805 } 2806 2807 static void 2808 ti_watchdog(struct ifnet *ifp) 2809 { 2810 struct ti_softc *sc; 2811 2812 sc = ifp->if_softc; 2813 2814 aprint_error_dev(&sc->sc_dev, "watchdog timeout -- resetting\n"); 2815 ti_stop(sc); 2816 ti_init(sc); 2817 2818 ifp->if_oerrors++; 2819 } 2820 2821 /* 2822 * Stop the adapter and free any mbufs allocated to the 2823 * RX and TX lists. 2824 */ 2825 static void 2826 ti_stop(struct ti_softc *sc) 2827 { 2828 struct ifnet *ifp; 2829 struct ti_cmd_desc cmd; 2830 2831 ifp = &sc->ethercom.ec_if; 2832 2833 /* Disable host interrupts. */ 2834 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2835 /* 2836 * Tell firmware we're shutting down. 2837 */ 2838 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2839 2840 /* Halt and reinitialize. */ 2841 ti_chipinit(sc); 2842 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2843 ti_chipinit(sc); 2844 2845 /* Free the RX lists. */ 2846 ti_free_rx_ring_std(sc); 2847 2848 /* Free jumbo RX list. */ 2849 ti_free_rx_ring_jumbo(sc); 2850 2851 /* Free mini RX list. */ 2852 ti_free_rx_ring_mini(sc); 2853 2854 /* Free TX buffers. */ 2855 ti_free_tx_ring(sc); 2856 2857 sc->ti_ev_prodidx.ti_idx = 0; 2858 sc->ti_return_prodidx.ti_idx = 0; 2859 sc->ti_tx_considx.ti_idx = 0; 2860 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2861 2862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2863 } 2864 2865 /* 2866 * Stop all chip I/O so that the kernel's probe routines don't 2867 * get confused by errant DMAs when rebooting. 2868 */ 2869 static void 2870 ti_shutdown(void *v) 2871 { 2872 struct ti_softc *sc = v; 2873 2874 ti_chipinit(sc); 2875 } 2876
Indexes created Fri Sep 26 20:09:58 GMT 2025