if_tl.c revision 1.10
1 /* $NetBSD: if_tl.c,v 1.10 1998/05/05 07:17:12 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include "bpfilter.h" 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <vm/vm.h> 84 #include <vm/vm_param.h> 85 #include <vm/vm_kern.h> 86 87 #if defined(__NetBSD__) 88 #include <net/if_ether.h> 89 #if defined(INET) 90 #include <netinet/if_inarp.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 #include <dev/i2c/i2c_bus.h> 100 #include <dev/i2c/i2c_eeprom.h> 101 #include <dev/mii/mii_adapter.h> 102 #include <dev/mii/mii_adapters_id.h> 103 #include <dev/pci/if_tlregs.h> 104 #endif /* __NetBSD__ */ 105 106 /* number of transmit/receive buffers */ 107 #ifndef TL_NBUF 108 #define TL_NBUF 10 109 #endif 110 111 /* number of seconds the link can be idle */ 112 #ifndef TL_IDLETIME 113 #define TL_IDLETIME 10 114 #endif 115 116 struct tl_softc { 117 struct device sc_dev; /* base device */ 118 bus_space_tag_t tl_bustag; 119 bus_space_handle_t tl_bushandle; /* CSR region handle */ 120 void* tl_ih; 121 struct ethercom tl_ec; 122 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 123 struct ifmedia tl_ifmedia; 124 u_int16_t tl_flags; 125 #define TL_IFACT 0x0001 /* chip has interface activity */ 126 u_int8_t tl_lasttx; /* we were without input this many seconds */ 127 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 128 mii_data_t mii; /* mii bus */ 129 struct Rx_list *Rx_list; /* Receive and transmit lists */ 130 struct Tx_list *Tx_list; 131 struct Rx_list *active_Rx, *last_Rx; 132 struct Tx_list *active_Tx, *last_Tx; 133 struct Tx_list *Free_Tx; 134 int opkt; /* used to detect link up/down for AUI/BNC */ 135 int stats_exesscoll; /* idem */ 136 #ifdef TL_PRIV_STATS 137 int ierr_overr; 138 int ierr_code; 139 int ierr_crc; 140 int ierr_nomem; 141 int oerr_underr; 142 int oerr_deffered; 143 int oerr_coll; 144 int oerr_multicoll; 145 int oerr_latecoll; 146 int oerr_exesscoll; 147 int oerr_carrloss; 148 int oerr_mcopy; 149 #endif 150 }; 151 #define tl_if tl_ec.ec_if 152 #define tl_bpf tl_if.if_bpf 153 154 typedef struct tl_softc tl_softc_t; 155 typedef u_long ioctl_cmd_t; 156 157 #define TL_HR_READ(sc, reg) \ 158 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 159 #define TL_HR_READ_BYTE(sc, reg) \ 160 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 161 #define TL_HR_WRITE(sc, reg, data) \ 162 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 163 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 164 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 165 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 166 167 #ifdef __BROKEN_INDIRECT_CONFIG 168 static int tl_pci_match __P((struct device *, void *, void *)); 169 #else 170 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 171 #endif 172 static void tl_pci_attach __P((struct device *, struct device *, void *)); 173 static int tl_intr __P((void *)); 174 175 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 176 static int tl_mediachange __P((struct ifnet *)); 177 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 178 static void tl_ifwatchdog __P((struct ifnet *)); 179 static void tl_shutdown __P((void*)); 180 181 static void tl_ifstart __P((struct ifnet *)); 182 static void tl_reset __P((tl_softc_t*)); 183 static int tl_init __P((tl_softc_t*)); 184 static void tl_restart __P((void *)); 185 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 186 static void tl_read_stats __P((tl_softc_t*)); 187 static void tl_ticks __P((void*)); 188 static int tl_multicast_hash __P((u_int8_t*)); 189 static void tl_addr_filter __P((tl_softc_t*)); 190 191 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 192 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 193 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 194 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 195 196 197 #if defined(TLDEBUG_RX) 198 static void ether_printheader __P((struct ether_header*)); 199 #endif 200 201 void tl_mii_set __P((void*, u_int8_t)); 202 void tl_mii_clr __P((void*, u_int8_t)); 203 int tl_mii_read __P((void*, u_int8_t)); 204 205 void tl_i2c_set __P((void*, u_int8_t)); 206 void tl_i2c_clr __P((void*, u_int8_t)); 207 int tl_i2c_read __P((void*, u_int8_t)); 208 209 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 210 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 211 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 212 static __inline void netsio_clr(sc, bits) 213 tl_softc_t* sc; 214 u_int8_t bits; 215 { 216 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 217 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 218 } 219 static __inline void netsio_set(sc, bits) 220 tl_softc_t* sc; 221 u_int8_t bits; 222 { 223 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 224 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 225 } 226 static __inline u_int8_t netsio_read(sc, bits) 227 tl_softc_t* sc; 228 u_int8_t bits; 229 { 230 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 231 } 232 233 struct cfattach tl_ca = { 234 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 235 }; 236 237 struct tl_product_desc { 238 u_int32_t tp_product; 239 u_int32_t tp_adapter; 240 int tp_flags; 241 const char *tp_desc; 242 }; 243 244 /* tp_flags */ 245 #define TPF_BROKEN_MEM 0x00000001 /* memory-mapped access is broken */ 246 247 const struct tl_product_desc tl_compaq_products[] = { 248 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 249 0, "Compaq Netelligent 10/100 TX" }, 250 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 251 0, "Compaq Netelligent 10 T" }, 252 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 253 0, "Compaq Integrated NetFlex 3/P" }, 254 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 255 0, "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 256 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 257 0, "Compaq Dual Port Netelligent 10/100 TX" }, 258 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 259 0, "Compaq Deskpro 4000 5233MMX" }, 260 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 261 0, "Compaq NetFlex 3/P w/ BNC" }, 262 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 263 0, "Compaq NetFlex 3/P" }, 264 { 0, 0, NULL }, 265 }; 266 267 const struct tl_product_desc tl_ti_products[] = { 268 /* 269 * Built-in Ethernet on the TI TravelMate 5000 270 * docking station; better product description? 271 * XXX Seems to have broken memory-mapped access. 272 */ 273 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 274 TPF_BROKEN_MEM, "Texas Instruments ThunderLAN" }, 275 { 0, 0, NULL }, 276 }; 277 278 struct tl_vendor_desc { 279 u_int32_t tv_vendor; 280 const struct tl_product_desc *tv_products; 281 }; 282 283 const struct tl_vendor_desc tl_vendors[] = { 284 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 285 { PCI_VENDOR_TI, tl_ti_products }, 286 { 0, NULL }, 287 }; 288 289 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 290 291 const struct tl_product_desc * 292 tl_lookup_product(id) 293 u_int32_t id; 294 { 295 const struct tl_product_desc *tp; 296 const struct tl_vendor_desc *tv; 297 298 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 299 if (PCI_VENDOR(id) == tv->tv_vendor) 300 break; 301 302 if ((tp = tv->tv_products) == NULL) 303 return (NULL); 304 305 for (; tp->tp_desc != NULL; tp++) 306 if (PCI_PRODUCT(id) == tp->tp_product) 307 break; 308 309 if (tp->tp_desc == NULL) 310 return (NULL); 311 312 return (tp); 313 } 314 315 static char *nullbuf = NULL; 316 317 static int 318 tl_pci_match(parent, match, aux) 319 struct device *parent; 320 #ifdef __BROKEN_INDIRECT_CONFIG 321 void *match; 322 #else 323 struct cfdata *match; 324 #endif 325 void *aux; 326 { 327 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 328 329 if (tl_lookup_product(pa->pa_id) != NULL) 330 return (1); 331 332 return (0); 333 } 334 335 static void 336 tl_pci_attach(parent, self, aux) 337 struct device * parent; 338 struct device * self; 339 void * aux; 340 { 341 tl_softc_t *sc = (tl_softc_t *)self; 342 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 343 const struct tl_product_desc *tp; 344 struct ifnet * const ifp = &sc->tl_if; 345 bus_space_tag_t iot, memt; 346 bus_space_handle_t ioh, memh; 347 pci_intr_handle_t intrhandle; 348 const char *intrstr; 349 int i, tmp, ioh_valid, memh_valid; 350 pcireg_t csr; 351 352 printf("\n"); 353 354 tp = tl_lookup_product(pa->pa_id); 355 if (tp == NULL) 356 panic("tl_pci_attach: impossible"); 357 358 /* Map the card space. */ 359 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 360 &iot, &ioh, NULL, NULL) == 0); 361 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 362 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 363 0, &memt, &memh, NULL, NULL) == 0); 364 365 if (memh_valid && (tp->tp_flags & TPF_BROKEN_MEM) == 0) { 366 sc->tl_bustag = memt; 367 sc->tl_bushandle = memh; 368 } else if (ioh_valid) { 369 sc->tl_bustag = iot; 370 sc->tl_bushandle = ioh; 371 } else { 372 printf("%s: unable to map device registers\n", 373 sc->sc_dev.dv_xname); 374 return; 375 } 376 377 /* Enable the device. */ 378 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 379 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 380 csr | PCI_COMMAND_MASTER_ENABLE); 381 382 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 383 sc->mii.adapter_id = tp->tp_adapter; 384 385 tl_reset(sc); 386 387 /* fill in the i2c struct */ 388 sc->i2cbus.adapter_softc = sc; 389 sc->i2cbus.set_bit = tl_i2c_set; 390 sc->i2cbus.clr_bit = tl_i2c_clr; 391 sc->i2cbus.read_bit = tl_i2c_read; 392 393 #ifdef TLDEBUG 394 printf("default values of INTreg: 0x%x\n", 395 tl_intreg_read(sc, TL_INT_Defaults)); 396 #endif 397 398 /* read mac addr */ 399 for (i=0; i<ETHER_ADDR_LEN; i++) { 400 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 401 if (tmp < 0) { 402 printf("%s: error reading Ethernet adress\n", 403 sc->sc_dev.dv_xname); 404 return; 405 } else { 406 sc->tl_enaddr[i] = tmp; 407 } 408 } 409 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 410 ether_sprintf(sc->tl_enaddr)); 411 412 /* Map and establish interrupts */ 413 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 414 pa->pa_intrline, &intrhandle)) { 415 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 416 return; 417 } 418 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 419 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 420 tl_intr, sc); 421 if (sc->tl_ih == NULL) { 422 printf("%s: couldn't establish interrupt", 423 sc->sc_dev.dv_xname); 424 if (intrstr != NULL) 425 printf(" at %s", intrstr); 426 printf("\n"); 427 return; 428 } 429 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 430 431 /* 432 * Add shutdown hook so that DMA is disabled prior to reboot. Not 433 * doing do could allow DMA to corrupt kernel memory during the 434 * reboot before the driver initializes. 435 */ 436 (void) shutdownhook_establish(tl_shutdown, sc); 437 438 sc->mii.adapter_softc = sc; 439 sc->mii.mii_setbit = tl_mii_set; 440 sc->mii.mii_clrbit = tl_mii_clr; 441 sc->mii.mii_readbit = tl_mii_read; 442 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 443 sc->mii.mii_writereg = NULL; 444 if (config_found(self, (void*)&sc->mii, mii_adapter_print) == NULL) { 445 return; 446 } 447 448 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 449 mii_media_add(&sc->tl_ifmedia, &sc->mii); 450 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 451 452 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 453 sc->tl_if.if_softc = sc; 454 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 455 ifp->if_ioctl = tl_ifioctl; 456 ifp->if_start = tl_ifstart; 457 ifp->if_watchdog = tl_ifwatchdog; 458 ifp->if_timer = 0; 459 if_attach(ifp); 460 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 461 #if NBPFILTER > 0 462 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 463 sizeof(struct ether_header)); 464 #endif 465 sc->mii.mii_media_active = IFM_NONE; 466 } 467 468 static void 469 tl_reset(sc) 470 tl_softc_t *sc; 471 { 472 int i; 473 474 /* read stats */ 475 if (sc->tl_if.if_flags & IFF_RUNNING) { 476 untimeout(tl_ticks, sc); 477 tl_read_stats(sc); 478 } 479 /* Reset adapter */ 480 TL_HR_WRITE(sc, TL_HOST_CMD, 481 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 482 DELAY(100000); 483 /* Disable interrupts */ 484 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 485 /* setup aregs & hash */ 486 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 487 tl_intreg_write(sc, i, 0); 488 #ifdef TLDEBUG_ADDR 489 printf("Areg & hash registers: \n"); 490 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 491 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 492 #endif 493 /* Setup NetConfig */ 494 tl_intreg_write(sc, TL_INT_NetConfig, 495 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 496 /* Bsize: accept default */ 497 /* TX commit in Acommit: accept default */ 498 /* Load Ld_tmr and Ld_thr */ 499 /* Ld_tmr = 3 */ 500 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 501 /* Ld_thr = 0 */ 502 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 503 /* Unreset MII */ 504 netsio_set(sc, TL_NETSIO_NMRST); 505 DELAY(100000); 506 sc->mii.mii_media_status &= ~IFM_ACTIVE; 507 sc->tl_flags = 0; 508 sc->opkt = 0; 509 sc->stats_exesscoll = 0; 510 } 511 512 static void tl_shutdown(v) 513 void *v; 514 { 515 tl_softc_t *sc = v; 516 struct Tx_list *Tx; 517 int i; 518 519 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 520 return; 521 /* disable interrupts */ 522 TL_HR_WRITE(sc, TL_HOST_CMD, 523 HOST_CMD_IntOff); 524 /* stop TX and RX channels */ 525 TL_HR_WRITE(sc, TL_HOST_CMD, 526 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 527 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 528 DELAY(100000); 529 530 /* stop statistics reading loop, read stats */ 531 untimeout(tl_ticks, sc); 532 tl_read_stats(sc); 533 534 /* deallocate memory allocations */ 535 for (i=0; i< TL_NBUF; i++) { 536 if (sc->Rx_list[i].m) 537 m_freem(sc->Rx_list[i].m); 538 sc->Rx_list[i].m = NULL; 539 } 540 free(sc->Rx_list, M_DEVBUF); 541 sc->Rx_list = NULL; 542 while ((Tx = sc->active_Tx) != NULL) { 543 Tx->hw_list.stat = 0; 544 m_freem(Tx->m); 545 sc->active_Tx = Tx->next; 546 Tx->next = sc->Free_Tx; 547 sc->Free_Tx = Tx; 548 } 549 sc->last_Tx = NULL; 550 free(sc->Tx_list, M_DEVBUF); 551 sc->Tx_list = NULL; 552 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 553 sc->mii.mii_media_status &= ~IFM_ACTIVE; 554 sc->tl_flags = 0; 555 } 556 557 static void tl_restart(v) 558 void *v; 559 { 560 tl_init(v); 561 } 562 563 static int tl_init(sc) 564 tl_softc_t *sc; 565 { 566 struct ifnet *ifp = &sc->tl_if; 567 int i, s; 568 569 s = splimp(); 570 /* cancel any pending IO */ 571 tl_shutdown(sc); 572 tl_reset(sc); 573 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 574 splx(s); 575 return 0; 576 } 577 /* Set various register to reasonable value */ 578 /* setup NetCmd in promisc mode if needed */ 579 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 580 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 581 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 582 /* Max receive size : MCLBYTES */ 583 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 584 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 585 (MCLBYTES >> 8) & 0xff); 586 587 /* init MAC addr */ 588 for (i = 0; i < ETHER_ADDR_LEN; i++) 589 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 590 /* add multicast filters */ 591 tl_addr_filter(sc); 592 #ifdef TLDEBUG_ADDR 593 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 594 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 595 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 596 #endif 597 598 /* Pre-allocate receivers mbuf, make the lists */ 599 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 600 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 601 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 602 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 603 sc->tl_if.if_flags &= ~IFF_UP; 604 splx(s); 605 return ENOMEM; 606 } 607 for (i=0; i< TL_NBUF; i++) { 608 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 609 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 610 sc->tl_if.if_flags &= ~IFF_UP; 611 splx(s); 612 return ENOMEM; 613 } 614 if (i > 0) { /* chain the list */ 615 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 616 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 617 #ifdef DIAGNOSTIC 618 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 619 printf("%s: physical addr 0x%x of list not properly aligned\n", 620 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 621 #endif 622 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 623 } 624 } 625 sc->Rx_list[TL_NBUF-1].next = NULL; 626 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 627 sc->Tx_list[TL_NBUF-1].next = NULL; 628 629 sc->active_Rx = &sc->Rx_list[0]; 630 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 631 sc->active_Tx = sc->last_Tx = NULL; 632 sc->Free_Tx = &sc->Tx_list[0]; 633 634 if (nullbuf == NULL) 635 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 636 if (nullbuf == NULL) { 637 printf("%s: can't allocate space for pad buffer\n", 638 sc->sc_dev.dv_xname); 639 sc->tl_if.if_flags &= ~IFF_UP; 640 splx(s); 641 return ENOMEM; 642 } 643 bzero(nullbuf, ETHER_MIN_TX); 644 645 /* set media if needed */ 646 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 647 mii_mediachg(&sc->mii); 648 } 649 650 /* start ticks calls */ 651 timeout(tl_ticks, sc, hz); 652 /* write adress of Rx list and enable interrupts */ 653 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 654 TL_HR_WRITE(sc, TL_HOST_CMD, 655 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 656 sc->tl_if.if_flags |= IFF_RUNNING; 657 sc->tl_if.if_flags &= ~IFF_OACTIVE; 658 return 0; 659 } 660 661 662 static u_int32_t 663 tl_intreg_read(sc, reg) 664 tl_softc_t *sc; 665 u_int32_t reg; 666 { 667 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 668 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 669 } 670 671 static u_int8_t 672 tl_intreg_read_byte(sc, reg) 673 tl_softc_t *sc; 674 u_int32_t reg; 675 { 676 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 677 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 678 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 679 } 680 681 static void 682 tl_intreg_write(sc, reg, val) 683 tl_softc_t *sc; 684 u_int32_t reg; 685 u_int32_t val; 686 { 687 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 688 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 689 } 690 691 static void 692 tl_intreg_write_byte(sc, reg, val) 693 tl_softc_t *sc; 694 u_int32_t reg; 695 u_int8_t val; 696 { 697 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 698 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 699 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 700 } 701 702 void tl_mii_set(v, bit) 703 void *v; 704 u_int8_t bit; 705 { 706 tl_softc_t *sc = v; 707 708 switch (bit) { 709 case MII_DATA: 710 netsio_set(sc, TL_NETSIO_MDATA); 711 break; 712 case MII_CLOCK: 713 netsio_set(sc, TL_NETSIO_MCLK); 714 break; 715 case MII_TXEN: 716 netsio_set(sc, TL_NETSIO_MTXEN); 717 break; 718 default: 719 printf("tl_mii_set: unknown bit %d\n", bit); 720 } 721 } 722 723 void tl_mii_clr(v, bit) 724 void *v; 725 u_int8_t bit; 726 { 727 tl_softc_t *sc = v; 728 729 switch (bit) { 730 case MII_DATA: 731 netsio_clr(sc, TL_NETSIO_MDATA); 732 break; 733 case MII_CLOCK: 734 netsio_clr(sc, TL_NETSIO_MCLK); 735 break; 736 case MII_TXEN: 737 netsio_clr(sc, TL_NETSIO_MTXEN); 738 break; 739 default: 740 printf("tl_mii_clr: unknown bit %d\n", bit); 741 } 742 return; 743 } 744 745 int tl_mii_read(v, bit) 746 void *v; 747 u_int8_t bit; 748 { 749 tl_softc_t *sc = v; 750 751 switch (bit) { 752 case MII_DATA: 753 return netsio_read(sc, TL_NETSIO_MDATA); 754 break; 755 case MII_CLOCK: 756 return netsio_read(sc, TL_NETSIO_MCLK); 757 break; 758 case MII_TXEN: 759 return netsio_read(sc, TL_NETSIO_MTXEN); 760 break; 761 default: 762 printf("tl_mii_read: unknown bit %d\n", bit); 763 return -1; 764 } 765 } 766 767 void tl_i2c_set(v, bit) 768 void *v; 769 u_int8_t bit; 770 { 771 tl_softc_t *sc = v; 772 773 switch (bit) { 774 case I2C_DATA: 775 netsio_set(sc, TL_NETSIO_EDATA); 776 break; 777 case I2C_CLOCK: 778 netsio_set(sc, TL_NETSIO_ECLOCK); 779 break; 780 case I2C_TXEN: 781 netsio_set(sc, TL_NETSIO_ETXEN); 782 break; 783 default: 784 printf("tl_i2c_set: unknown bit %d\n", bit); 785 } 786 return; 787 } 788 789 void tl_i2c_clr(v, bit) 790 void *v; 791 u_int8_t bit; 792 { 793 tl_softc_t *sc = v; 794 795 switch (bit) { 796 case I2C_DATA: 797 netsio_clr(sc, TL_NETSIO_EDATA); 798 break; 799 case I2C_CLOCK: 800 netsio_clr(sc, TL_NETSIO_ECLOCK); 801 break; 802 case I2C_TXEN: 803 netsio_clr(sc, TL_NETSIO_ETXEN); 804 break; 805 default: 806 printf("tl_i2c_clr: unknown bit %d\n", bit); 807 } 808 return; 809 } 810 811 int tl_i2c_read(v, bit) 812 void *v; 813 u_int8_t bit; 814 { 815 tl_softc_t *sc = v; 816 817 switch (bit) { 818 case I2C_DATA: 819 return netsio_read(sc, TL_NETSIO_EDATA); 820 break; 821 case I2C_CLOCK: 822 return netsio_read(sc, TL_NETSIO_ECLOCK); 823 break; 824 case I2C_TXEN: 825 return netsio_read(sc, TL_NETSIO_ETXEN); 826 break; 827 default: 828 printf("tl_i2c_read: unknown bit %d\n", bit); 829 return -1; 830 } 831 } 832 833 static int 834 tl_intr(v) 835 void *v; 836 { 837 tl_softc_t *sc = v; 838 struct ifnet *ifp = &sc->tl_if; 839 struct Rx_list *Rx; 840 struct Tx_list *Tx; 841 struct mbuf *m; 842 u_int32_t int_type, int_reg; 843 int ack = 0; 844 int size; 845 846 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 847 int_type = int_reg & TL_INTR_MASK; 848 if (int_type == 0) 849 return 0; 850 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 851 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 852 int_type, int_reg); 853 #endif 854 /* disable interrupts */ 855 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 856 switch(int_type & TL_INTR_MASK) { 857 case TL_INTR_RxEOF: 858 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 859 /* dequeue and requeue at end of list */ 860 ack++; 861 Rx = sc->active_Rx; 862 sc->active_Rx = Rx->next; 863 m = Rx->m; 864 size = Rx->hw_list.stat >> 16; 865 #ifdef TLDEBUG_RX 866 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 867 #endif 868 if (tl_add_RxBuff(Rx, m ) == 0) { 869 /* No new mbuf, reuse the same. This means that this packet 870 is lost */ 871 m = NULL; 872 #ifdef TL_PRIV_STATS 873 sc->ierr_nomem++; 874 #endif 875 #ifdef TLDEBUG 876 printf("%s: out of mbuf, lost input packet\n", 877 sc->sc_dev.dv_xname); 878 #endif 879 } 880 Rx->next = NULL; 881 Rx->hw_list.fwd = 0; 882 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 883 #ifdef DIAGNOSTIC 884 if (sc->last_Rx->hw_list.fwd & 0x7) 885 printf("%s: physical addr 0x%x of list not properly aligned\n", 886 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 887 #endif 888 sc->last_Rx->next = Rx; 889 sc->last_Rx = Rx; 890 891 /* deliver packet */ 892 if (m) { 893 struct ether_header *eh; 894 if (size < sizeof(struct ether_header)) { 895 m_freem(m); 896 continue; 897 } 898 m->m_pkthdr.rcvif = ifp; 899 m->m_pkthdr.len = m->m_len = 900 size - sizeof(struct ether_header); 901 eh = mtod(m, struct ether_header *); 902 #ifdef TLDEBUG_RX 903 printf("tl_intr: Rx packet:\n"); 904 ether_printheader(eh); 905 #endif 906 #if NBPFILTER > 0 907 if (ifp->if_bpf) { 908 bpf_tap(ifp->if_bpf, 909 mtod(m, caddr_t), 910 size); 911 /* 912 * Only pass this packet up 913 * if it is for us. 914 */ 915 if ((ifp->if_flags & IFF_PROMISC) && 916 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 917 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 918 sizeof(eh->ether_dhost)) != 0) { 919 m_freem(m); 920 continue; 921 } 922 } 923 #endif /* NBPFILTER > 0 */ 924 m->m_data += sizeof(struct ether_header); 925 ether_input(ifp, eh, m); 926 } 927 } 928 #ifdef TLDEBUG_RX 929 printf("TL_INTR_RxEOF: ack %d\n", ack); 930 #else 931 if (ack == 0) { 932 printf("%s: EOF intr without anything to read !\n", 933 sc->sc_dev.dv_xname); 934 tl_reset(sc); 935 /* shedule reinit of the board */ 936 timeout(tl_restart, sc, 1); 937 return(1); 938 } 939 #endif 940 break; 941 case TL_INTR_RxEOC: 942 ack++; 943 #ifdef TLDEBUG_RX 944 printf("TL_INTR_RxEOC: ack %d\n", ack); 945 #endif 946 #ifdef DIAGNOSTIC 947 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 948 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 949 sc->sc_dev.dv_xname); 950 return 0; 951 } else 952 #endif 953 { 954 /* write adress of Rx list and send Rx GO command, ack interrupt 955 and enable interrupts in one command */ 956 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 957 vtophys(&sc->active_Rx->hw_list)); 958 TL_HR_WRITE(sc, TL_HOST_CMD, 959 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 960 HOST_CMD_ACK | HOST_CMD_IntOn); 961 return 1; 962 } 963 case TL_INTR_TxEOF: 964 case TL_INTR_TxEOC: 965 while ((Tx = sc->active_Tx) != NULL) { 966 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 967 break; 968 ack++; 969 #ifdef TLDEBUG_TX 970 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 971 #endif 972 Tx->hw_list.stat = 0; 973 m_freem(Tx->m); 974 Tx->m = NULL; 975 sc->active_Tx = Tx->next; 976 if (sc->active_Tx == NULL) 977 sc->last_Tx = NULL; 978 Tx->next = sc->Free_Tx; 979 sc->Free_Tx = Tx; 980 } 981 /* if this was an EOC, ACK immediatly */ 982 if (int_type == TL_INTR_TxEOC) { 983 #ifdef TLDEBUG_TX 984 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 985 #endif 986 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 987 HOST_CMD_IntOn); 988 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 989 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 990 vtophys(&sc->active_Tx->hw_list)); 991 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 992 } 993 sc->tl_if.if_timer = 0; 994 if (sc->tl_if.if_snd.ifq_head != NULL) 995 tl_ifstart(&sc->tl_if); 996 return 1; 997 } 998 #ifdef TLDEBUG 999 else { 1000 printf("TL_INTR_TxEOF: ack %d\n", ack); 1001 } 1002 #endif 1003 sc->tl_if.if_timer = 0; 1004 if (sc->tl_if.if_snd.ifq_head != NULL) 1005 tl_ifstart(&sc->tl_if); 1006 break; 1007 case TL_INTR_Stat: 1008 ack++; 1009 #ifdef TLDEBUG 1010 printf("TL_INTR_Stat: ack %d\n", ack); 1011 #endif 1012 tl_read_stats(sc); 1013 break; 1014 case TL_INTR_Adc: 1015 if (int_reg & TL_INTVec_MASK) { 1016 /* adapter check conditions */ 1017 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1018 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1019 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1020 tl_reset(sc); 1021 /* shedule reinit of the board */ 1022 timeout(tl_restart, sc, 1); 1023 return(1); 1024 } else { 1025 u_int8_t netstat; 1026 /* Network status */ 1027 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1028 printf("%s: network status, NetSts=%x\n", 1029 sc->sc_dev.dv_xname, netstat); 1030 /* Ack interrupts */ 1031 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1032 ack++; 1033 } 1034 break; 1035 default: 1036 printf("%s: unhandled interrupt code %x!\n", 1037 sc->sc_dev.dv_xname, int_type); 1038 ack++; 1039 } 1040 1041 if (ack) { 1042 /* Ack the interrupt and enable interrupts */ 1043 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1044 HOST_CMD_IntOn); 1045 return 1; 1046 } 1047 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1048 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1049 return 0; 1050 } 1051 1052 static int 1053 tl_ifioctl(ifp, cmd, data) 1054 struct ifnet *ifp; 1055 ioctl_cmd_t cmd; 1056 caddr_t data; 1057 { 1058 struct tl_softc *sc = ifp->if_softc; 1059 struct ifreq *ifr = (struct ifreq *)data; 1060 int s, error; 1061 1062 s = splimp(); 1063 switch(cmd) { 1064 case SIOCSIFADDR: { 1065 struct ifaddr *ifa = (struct ifaddr *)data; 1066 sc->tl_if.if_flags |= IFF_UP; 1067 if ((error = tl_init(sc)) != NULL) { 1068 sc->tl_if.if_flags &= ~IFF_UP; 1069 break; 1070 } 1071 switch (ifa->ifa_addr->sa_family) { 1072 #ifdef INET 1073 case AF_INET: 1074 arp_ifinit(ifp, ifa); 1075 break; 1076 #endif 1077 #ifdef NS 1078 case AF_NS: { 1079 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1080 1081 if (ns_nullhost(*ina)) 1082 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1083 else 1084 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1085 ifp->if_addrlen); 1086 break; 1087 } 1088 #endif 1089 default: 1090 break; 1091 } 1092 break; 1093 } 1094 case SIOCSIFFLAGS: 1095 { 1096 u_int8_t reg; 1097 /* 1098 * If interface is marked up and not running, then start it. 1099 * If it is marked down and running, stop it. 1100 */ 1101 if (ifp->if_flags & IFF_UP) { 1102 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1103 error = tl_init(sc); 1104 /* all flags have been handled by init */ 1105 break; 1106 } 1107 error = 0; 1108 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1109 if (ifp->if_flags & IFF_PROMISC) 1110 reg |= TL_NETCOMMAND_CAF; 1111 else 1112 reg &= ~TL_NETCOMMAND_CAF; 1113 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1114 #ifdef TL_PRIV_STATS 1115 if (ifp->if_flags & IFF_LINK0) { 1116 ifp->if_flags &= ~IFF_LINK0; 1117 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1118 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1119 printf(" %4d RX code error\n", sc->ierr_code); 1120 printf(" %4d RX crc error\n", sc->ierr_crc); 1121 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1122 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1123 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1124 printf(" %4d TX single collisions\n", sc->oerr_coll); 1125 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1126 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1127 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1128 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1129 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1130 } 1131 #endif 1132 } else { 1133 if (ifp->if_flags & IFF_RUNNING) 1134 tl_shutdown(sc); 1135 error = 0; 1136 } 1137 break; 1138 } 1139 case SIOCADDMULTI: 1140 case SIOCDELMULTI: 1141 /* 1142 * Update multicast listeners 1143 */ 1144 if (cmd == SIOCADDMULTI) 1145 error = ether_addmulti(ifr, &sc->tl_ec); 1146 else 1147 error = ether_delmulti(ifr, &sc->tl_ec); 1148 if (error == ENETRESET) { 1149 tl_addr_filter(sc); 1150 error = 0; 1151 } 1152 break; 1153 case SIOCSIFMEDIA: 1154 case SIOCGIFMEDIA: 1155 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1156 break; 1157 default: 1158 error = EINVAL; 1159 } 1160 splx(s); 1161 return error; 1162 } 1163 1164 static void 1165 tl_ifstart(ifp) 1166 struct ifnet *ifp; 1167 { 1168 tl_softc_t *sc = ifp->if_softc; 1169 struct mbuf *m, *mb_head; 1170 struct Tx_list *Tx; 1171 int segment, size; 1172 1173 txloop: 1174 /* If we don't have more space ... */ 1175 if (sc->Free_Tx == NULL) { 1176 #ifdef TLDEBUG 1177 printf("tl_ifstart: No free TX list\n"); 1178 #endif 1179 return; 1180 } 1181 /* Grab a paquet for output */ 1182 IF_DEQUEUE(&ifp->if_snd, mb_head); 1183 if (mb_head == NULL) { 1184 #ifdef TLDEBUG_TX 1185 printf("tl_ifstart: nothing to send\n"); 1186 #endif 1187 return; 1188 } 1189 Tx = sc->Free_Tx; 1190 sc->Free_Tx = Tx->next; 1191 /* 1192 * Go through each of the mbufs in the chain and initialize 1193 * the transmit list descriptors with the physical address 1194 * and size of the mbuf. 1195 */ 1196 tbdinit: 1197 bzero(Tx, sizeof(struct Tx_list)); 1198 Tx->m = mb_head; 1199 size = 0; 1200 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1201 if (m->m_len != 0) { 1202 if (segment == TL_NSEG) 1203 break; 1204 size += m->m_len; 1205 Tx->hw_list.seg[segment].data_addr = 1206 vtophys(mtod(m, vm_offset_t)); 1207 Tx->hw_list.seg[segment].data_count = m->m_len; 1208 segment++; 1209 } 1210 } 1211 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1212 /* 1213 * We ran out of segments, or we will. We have to recopy this mbuf 1214 * chain first. 1215 */ 1216 struct mbuf *mn; 1217 #ifdef TLDEBUG_TX 1218 printf("tl_ifstart: need to copy mbuf\n"); 1219 #endif 1220 #ifdef TL_PRIV_STATS 1221 sc->oerr_mcopy++; 1222 #endif 1223 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1224 if (mn == NULL) { 1225 m_freem(mb_head); 1226 goto bad; 1227 } 1228 if (mb_head->m_pkthdr.len > MHLEN) { 1229 MCLGET(mn, M_DONTWAIT); 1230 if ((mn->m_flags & M_EXT) == 0) { 1231 m_freem(mn); 1232 m_freem(mb_head); 1233 goto bad; 1234 } 1235 } 1236 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1237 mtod(mn, caddr_t)); 1238 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1239 m_freem(mb_head); 1240 mb_head = mn; 1241 goto tbdinit; 1242 } 1243 /* We are at end of mbuf chain. check the size and 1244 * see if it needs to be extended 1245 */ 1246 if (size < ETHER_MIN_TX) { 1247 #ifdef DIAGNOSTIC 1248 if (segment >= TL_NSEG) { 1249 panic("tl_ifstart: to much segmets (%d)\n", segment); 1250 } 1251 #endif 1252 /* 1253 * add the nullbuf in the seg 1254 */ 1255 Tx->hw_list.seg[segment].data_count = 1256 ETHER_MIN_TX - size; 1257 Tx->hw_list.seg[segment].data_addr = 1258 vtophys(nullbuf); 1259 size = ETHER_MIN_TX; 1260 segment++; 1261 } 1262 /* The list is done, finish the list init */ 1263 Tx->hw_list.seg[segment-1].data_count |= 1264 TL_LAST_SEG; 1265 Tx->hw_list.stat = (size << 16) | 0x3000; 1266 #ifdef TLDEBUG_TX 1267 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1268 Tx->hw_list.stat); 1269 #if 0 1270 for(segment = 0; segment < TL_NSEG; segment++) { 1271 printf(" seg %d addr 0x%x len 0x%x\n", 1272 segment, 1273 Tx->hw_list.seg[segment].data_addr, 1274 Tx->hw_list.seg[segment].data_count); 1275 } 1276 #endif 1277 #endif 1278 sc->opkt++; 1279 if (sc->active_Tx == NULL) { 1280 sc->active_Tx = sc->last_Tx = Tx; 1281 #ifdef TLDEBUG_TX 1282 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1283 vtophys(&Tx->hw_list)); 1284 #endif 1285 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1286 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1287 } else { 1288 #ifdef TLDEBUG_TX 1289 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1290 vtophys(&Tx->hw_list)); 1291 #endif 1292 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1293 sc->last_Tx->next = Tx; 1294 sc->last_Tx = Tx; 1295 #ifdef DIAGNOSTIC 1296 if (sc->last_Tx->hw_list.fwd & 0x7) 1297 printf("%s: physical addr 0x%x of list not properly aligned\n", 1298 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1299 #endif 1300 } 1301 #if NBPFILTER > 0 1302 /* Pass packet to bpf if there is a listener */ 1303 if (ifp->if_bpf) 1304 bpf_mtap(ifp->if_bpf, mb_head); 1305 #endif 1306 /* Set a 5 second timer just in case we don't hear from the card again. */ 1307 ifp->if_timer = 5; 1308 1309 goto txloop; 1310 bad: 1311 #ifdef TLDEBUG 1312 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1313 #endif 1314 Tx->next = sc->Free_Tx; 1315 sc->Free_Tx = Tx; 1316 return; 1317 } 1318 1319 static void 1320 tl_ifwatchdog(ifp) 1321 struct ifnet *ifp; 1322 { 1323 tl_softc_t *sc = ifp->if_softc; 1324 1325 if ((ifp->if_flags & IFF_RUNNING) == 0) 1326 return; 1327 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1328 ifp->if_oerrors++; 1329 tl_init(sc); 1330 } 1331 1332 static int 1333 tl_mediachange(ifp) 1334 struct ifnet *ifp; 1335 { 1336 1337 tl_softc_t *sc = ifp->if_softc; 1338 int err; 1339 u_int32_t reg; 1340 int oldmedia; 1341 #ifdef TLDEBUG 1342 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1343 #endif 1344 oldmedia = sc->mii.mii_media_active; 1345 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1346 if ((err = mii_mediachg(&sc->mii)) != 0) 1347 sc->mii.mii_media_active = oldmedia; 1348 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1349 if (sc->mii.mii_media_active & IFM_FDX) 1350 reg |= TL_NETCOMMAND_DUPLEX; 1351 else 1352 reg &= ~TL_NETCOMMAND_DUPLEX; 1353 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1354 return err; 1355 } 1356 1357 static void 1358 tl_mediastatus(ifp, ifmr) 1359 struct ifnet *ifp; 1360 struct ifmediareq *ifmr; 1361 { 1362 tl_softc_t *sc = ifp->if_softc; 1363 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1364 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1365 if (sc->tl_flags & TL_IFACT) 1366 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1367 else 1368 sc->mii.mii_media_status = IFM_AVALID; 1369 else 1370 mii_pollstat(&sc->mii); 1371 1372 ifmr->ifm_active = sc->mii.mii_media_active; 1373 ifmr->ifm_status = sc->mii.mii_media_status; 1374 } 1375 1376 static int tl_add_RxBuff(Rx, oldm) 1377 struct Rx_list *Rx; 1378 struct mbuf *oldm; 1379 { 1380 struct mbuf *m; 1381 1382 MGETHDR(m, M_DONTWAIT, MT_DATA); 1383 if (m != NULL) { 1384 MCLGET(m, M_DONTWAIT); 1385 if ((m->m_flags & M_EXT) == 0) { 1386 m_freem(m); 1387 if (oldm == NULL) 1388 return 0; 1389 m = oldm; 1390 m->m_data = m->m_ext.ext_buf; 1391 } 1392 } else { 1393 if (oldm == NULL) 1394 return 0; 1395 m = oldm; 1396 m->m_data = m->m_ext.ext_buf; 1397 } 1398 /* 1399 * Move the data pointer up so that the incoming data packet 1400 * will be 32-bit aligned. 1401 */ 1402 m->m_data += 2; 1403 1404 /* (re)init the Rx_list struct */ 1405 1406 Rx->m = m; 1407 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1408 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1409 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1410 return (m != oldm); 1411 } 1412 1413 static void tl_ticks(v) 1414 void *v; 1415 { 1416 tl_softc_t *sc = v; 1417 1418 tl_read_stats(sc); 1419 if (sc->opkt > 0) { 1420 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1421 if (sc->tl_flags & TL_IFACT) /* only print once */ 1422 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1423 sc->tl_flags &= ~TL_IFACT; 1424 } else 1425 sc->tl_flags |= TL_IFACT; 1426 sc->oerr_exesscoll = sc->opkt = 0; 1427 sc->tl_lasttx = 0; 1428 } else { 1429 sc->tl_lasttx++; 1430 if (sc->tl_lasttx >= TL_IDLETIME) { 1431 /* 1432 * No TX activity in the last TL_IDLETIME seconds. 1433 * sends a LLC Class1 TEST pkt 1434 */ 1435 struct mbuf *m; 1436 int s; 1437 MGETHDR(m, M_DONTWAIT, MT_DATA); 1438 if (m != NULL) { 1439 #ifdef TLDEBUG 1440 printf("tl_ticks: sending LLC test pkt\n"); 1441 #endif 1442 bcopy(sc->tl_enaddr, 1443 mtod(m, struct ether_header *)->ether_dhost, 6); 1444 bcopy(sc->tl_enaddr, 1445 mtod(m, struct ether_header *)->ether_shost, 6); 1446 mtod(m, struct ether_header *)->ether_type = htons(3); 1447 mtod(m, unsigned char *)[14] = 0; 1448 mtod(m, unsigned char *)[15] = 0; 1449 mtod(m, unsigned char *)[16] = 0xE3; 1450 /* LLC Class1 TEST (no poll) */ 1451 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1452 s = splnet(); 1453 IF_PREPEND(&sc->tl_if.if_snd, m); 1454 tl_ifstart(&sc->tl_if); 1455 splx(s); 1456 } 1457 } 1458 } 1459 1460 /* read statistics every seconds */ 1461 timeout(tl_ticks, v, hz); 1462 } 1463 1464 static void 1465 tl_read_stats(sc) 1466 tl_softc_t *sc; 1467 { 1468 u_int32_t reg; 1469 int ierr_overr; 1470 int ierr_code; 1471 int ierr_crc; 1472 int oerr_underr; 1473 int oerr_deffered; 1474 int oerr_coll; 1475 int oerr_multicoll; 1476 int oerr_exesscoll; 1477 int oerr_latecoll; 1478 int oerr_carrloss; 1479 struct ifnet *ifp = &sc->tl_if; 1480 1481 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1482 ifp->if_opackets += reg & 0x00ffffff; 1483 oerr_underr = reg >> 24; 1484 1485 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1486 ifp->if_ipackets += reg & 0x00ffffff; 1487 ierr_overr = reg >> 24; 1488 1489 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1490 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1491 ierr_code = (reg & TL_FERR_CODE) >> 24; 1492 oerr_deffered = (reg & TL_FERR_DEF); 1493 1494 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1495 oerr_multicoll = (reg & TL_COL_MULTI); 1496 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1497 1498 reg = tl_intreg_read(sc, TL_INT_LERR); 1499 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1500 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1501 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1502 1503 1504 sc->stats_exesscoll += oerr_exesscoll; 1505 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1506 oerr_carrloss; 1507 ifp->if_collisions += oerr_coll + oerr_multicoll; 1508 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1509 1510 if (ierr_overr) 1511 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1512 if (oerr_underr) 1513 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1514 #ifdef TL_PRIV_STATS 1515 sc->ierr_overr += ierr_overr; 1516 sc->ierr_code += ierr_code; 1517 sc->ierr_crc += ierr_crc; 1518 sc->oerr_underr += oerr_underr; 1519 sc->oerr_deffered += oerr_deffered; 1520 sc->oerr_coll += oerr_coll; 1521 sc->oerr_multicoll += oerr_multicoll; 1522 sc->oerr_exesscoll += oerr_exesscoll; 1523 sc->oerr_latecoll += oerr_latecoll; 1524 sc->oerr_carrloss += oerr_carrloss; 1525 #endif 1526 } 1527 1528 static void tl_addr_filter(sc) 1529 tl_softc_t *sc; 1530 { 1531 struct ether_multistep step; 1532 struct ether_multi *enm; 1533 u_int32_t hash[2] = {0, 0}; 1534 int i; 1535 1536 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1537 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1538 while (enm != NULL) { 1539 #ifdef TLDEBUG 1540 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1541 #endif 1542 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1543 i = tl_multicast_hash(enm->enm_addrlo); 1544 hash[i/32] |= 1 << (i%32); 1545 } else { 1546 hash[0] = hash[1] = 0xffffffff; 1547 sc->tl_if.if_flags |= IFF_ALLMULTI; 1548 break; 1549 } 1550 ETHER_NEXT_MULTI(step, enm); 1551 } 1552 #ifdef TLDEBUG 1553 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1554 #endif 1555 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1556 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1557 } 1558 1559 static int tl_multicast_hash(a) 1560 u_int8_t *a; 1561 { 1562 int hash; 1563 1564 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1565 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1566 1567 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1568 DA(a,36), DA(a,42)); 1569 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1570 DA(a,37), DA(a,43)) << 1; 1571 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1572 DA(a,38), DA(a,44)) << 2; 1573 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1574 DA(a,39), DA(a,45)) << 3; 1575 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1576 DA(a,40), DA(a,46)) << 4; 1577 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1578 DA(a,41), DA(a,47)) << 5; 1579 1580 return hash; 1581 } 1582 1583 #if defined(TLDEBUG_RX) 1584 void ether_printheader(eh) 1585 struct ether_header *eh; 1586 { 1587 u_char *c = (char*)eh; 1588 int i; 1589 for (i=0; i<sizeof(struct ether_header); i++) 1590 printf("%x ", (u_int)c[i]); 1591 printf("\n"); 1592 } 1593 #endif 1594
Indexes created Wed Sep 24 05:09:52 GMT 2025