if_tl.c revision 1.105
1 /* $NetBSD: if_tl.c,v 1.105 2016/07/07 06:55:41 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Texas Instruments ThunderLAN ethernet controller 29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 30 * available from www.ti.com 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.105 2016/07/07 06:55:41 msaitoh Exp $"); 35 36 #undef TLDEBUG 37 #define TL_PRIV_STATS 38 #undef TLDEBUG_RX 39 #undef TLDEBUG_TX 40 #undef TLDEBUG_ADDR 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 68 #include <sys/rndsource.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #endif 76 77 78 #if defined(__NetBSD__) 79 #include <net/if_ether.h> 80 #if defined(INET) 81 #include <netinet/if_inarp.h> 82 #endif 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/i2c/i2cvar.h> 92 #include <dev/i2c/i2c_bitbang.h> 93 #include <dev/i2c/at24cxxvar.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/mii/tlphyvar.h> 99 100 #include <dev/pci/if_tlregs.h> 101 #include <dev/pci/if_tlvar.h> 102 #endif /* __NetBSD__ */ 103 104 /* number of transmit/receive buffers */ 105 #ifndef TL_NBUF 106 #define TL_NBUF 32 107 #endif 108 109 static int tl_pci_match(device_t, cfdata_t, void *); 110 static void tl_pci_attach(device_t, device_t, void *); 111 static int tl_intr(void *); 112 113 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 114 static int tl_mediachange(struct ifnet *); 115 static void tl_ifwatchdog(struct ifnet *); 116 static bool tl_shutdown(device_t, int); 117 118 static void tl_ifstart(struct ifnet *); 119 static void tl_reset(tl_softc_t *); 120 static int tl_init(struct ifnet *); 121 static void tl_stop(struct ifnet *, int); 122 static void tl_restart(void *); 123 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 124 static void tl_read_stats(tl_softc_t *); 125 static void tl_ticks(void *); 126 static int tl_multicast_hash(uint8_t *); 127 static void tl_addr_filter(tl_softc_t *); 128 129 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 130 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 131 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 132 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 133 134 void tl_mii_sync(struct tl_softc *); 135 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 136 137 138 #if defined(TLDEBUG_RX) 139 static void ether_printheader(struct ether_header *); 140 #endif 141 142 int tl_mii_read(device_t, int, int); 143 void tl_mii_write(device_t, int, int, int); 144 145 void tl_statchg(struct ifnet *); 146 147 /* I2C glue */ 148 static int tl_i2c_acquire_bus(void *, int); 149 static void tl_i2c_release_bus(void *, int); 150 static int tl_i2c_send_start(void *, int); 151 static int tl_i2c_send_stop(void *, int); 152 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 153 static int tl_i2c_read_byte(void *, uint8_t *, int); 154 static int tl_i2c_write_byte(void *, uint8_t, int); 155 156 /* I2C bit-bang glue */ 157 static void tl_i2cbb_set_bits(void *, uint32_t); 158 static void tl_i2cbb_set_dir(void *, uint32_t); 159 static uint32_t tl_i2cbb_read(void *); 160 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 161 tl_i2cbb_set_bits, 162 tl_i2cbb_set_dir, 163 tl_i2cbb_read, 164 { 165 TL_NETSIO_EDATA, /* SDA */ 166 TL_NETSIO_ECLOCK, /* SCL */ 167 TL_NETSIO_ETXEN, /* SDA is output */ 168 0, /* SDA is input */ 169 } 170 }; 171 172 static inline void netsio_clr(tl_softc_t *, uint8_t); 173 static inline void netsio_set(tl_softc_t *, uint8_t); 174 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 175 176 static inline void 177 netsio_clr(tl_softc_t *sc, uint8_t bits) 178 { 179 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 184 static inline void 185 netsio_set(tl_softc_t *sc, uint8_t bits) 186 { 187 188 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 189 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 190 } 191 192 static inline uint8_t 193 netsio_read(tl_softc_t *sc, uint8_t bits) 194 { 195 196 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 197 } 198 199 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 200 tl_pci_match, tl_pci_attach, NULL, NULL); 201 202 static const struct tl_product_desc tl_compaq_products[] = { 203 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 204 "Compaq Netelligent 10/100 TX" }, 205 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 206 "Integrated Compaq Netelligent 10/100 TX" }, 207 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 208 "Compaq Netelligent 10 T" }, 209 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 210 "Compaq Netelligent 10 T/2 UTP/Coax" }, 211 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 212 "Compaq Integrated NetFlex 3/P" }, 213 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 214 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 216 "Compaq Dual Port Netelligent 10/100 TX" }, 217 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 218 "Compaq Deskpro 4000 5233MMX" }, 219 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 220 "Compaq NetFlex 3/P w/ BNC" }, 221 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 222 "Compaq NetFlex 3/P" }, 223 { 0, 0, NULL }, 224 }; 225 226 static const struct tl_product_desc tl_ti_products[] = { 227 /* 228 * Built-in Ethernet on the TI TravelMate 5000 229 * docking station; better product description? 230 */ 231 { PCI_PRODUCT_TI_TLAN, 0, 232 "Texas Instruments ThunderLAN" }, 233 { 0, 0, NULL }, 234 }; 235 236 struct tl_vendor_desc { 237 uint32_t tv_vendor; 238 const struct tl_product_desc *tv_products; 239 }; 240 241 const struct tl_vendor_desc tl_vendors[] = { 242 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 243 { PCI_VENDOR_TI, tl_ti_products }, 244 { 0, NULL }, 245 }; 246 247 static const struct tl_product_desc *tl_lookup_product(uint32_t); 248 249 static const struct tl_product_desc * 250 tl_lookup_product(uint32_t id) 251 { 252 const struct tl_product_desc *tp; 253 const struct tl_vendor_desc *tv; 254 255 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 256 if (PCI_VENDOR(id) == tv->tv_vendor) 257 break; 258 259 if ((tp = tv->tv_products) == NULL) 260 return NULL; 261 262 for (; tp->tp_desc != NULL; tp++) 263 if (PCI_PRODUCT(id) == tp->tp_product) 264 break; 265 266 if (tp->tp_desc == NULL) 267 return NULL; 268 269 return tp; 270 } 271 272 static int 273 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 276 277 if (tl_lookup_product(pa->pa_id) != NULL) 278 return 1; 279 280 return 0; 281 } 282 283 static void 284 tl_pci_attach(device_t parent, device_t self, void *aux) 285 { 286 tl_softc_t *sc = device_private(self); 287 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 288 const struct tl_product_desc *tp; 289 struct ifnet * const ifp = &sc->tl_if; 290 bus_space_tag_t iot, memt; 291 bus_space_handle_t ioh, memh; 292 pci_intr_handle_t intrhandle; 293 const char *intrstr; 294 int ioh_valid, memh_valid; 295 int reg_io, reg_mem; 296 pcireg_t reg10, reg14; 297 pcireg_t csr; 298 char intrbuf[PCI_INTRSTR_LEN]; 299 300 sc->sc_dev = self; 301 aprint_normal("\n"); 302 303 callout_init(&sc->tl_tick_ch, 0); 304 callout_init(&sc->tl_restart_ch, 0); 305 306 tp = tl_lookup_product(pa->pa_id); 307 if (tp == NULL) 308 panic("%s: impossible", __func__); 309 sc->tl_product = tp; 310 311 /* 312 * Map the card space. First we have to find the I/O and MEM 313 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 314 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 315 * The ThunderLAN manual is not consistent about this either (there 316 * are both cases in code examples). 317 */ 318 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 319 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 320 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 321 reg_io = 0x10; 322 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 323 reg_io = 0x14; 324 else 325 reg_io = 0; 326 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 327 reg_mem = 0x10; 328 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 329 reg_mem = 0x14; 330 else 331 reg_mem = 0; 332 333 if (reg_io != 0) 334 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 335 0, &iot, &ioh, NULL, NULL) == 0); 336 else 337 ioh_valid = 0; 338 if (reg_mem != 0) 339 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 340 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 341 0, &memt, &memh, NULL, NULL) == 0); 342 else 343 memh_valid = 0; 344 345 if (ioh_valid) { 346 sc->tl_bustag = iot; 347 sc->tl_bushandle = ioh; 348 } else if (memh_valid) { 349 sc->tl_bustag = memt; 350 sc->tl_bushandle = memh; 351 } else { 352 aprint_error_dev(self, "unable to map device registers\n"); 353 return; 354 } 355 sc->tl_dmatag = pa->pa_dmat; 356 357 /* Enable the device. */ 358 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 359 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 360 csr | PCI_COMMAND_MASTER_ENABLE); 361 362 aprint_normal_dev(self, "%s\n", tp->tp_desc); 363 364 tl_reset(sc); 365 366 /* fill in the i2c tag */ 367 sc->sc_i2c.ic_cookie = sc; 368 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 369 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 370 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 371 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 372 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 373 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 374 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 375 376 #ifdef TLDEBUG 377 aprint_debug_dev(self, "default values of INTreg: 0x%x\n", 378 tl_intreg_read(sc, TL_INT_Defaults)); 379 #endif 380 381 /* read mac addr */ 382 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 383 sc->tl_enaddr, ETHER_ADDR_LEN)) { 384 aprint_error_dev(self, "error reading Ethernet address\n"); 385 return; 386 } 387 aprint_normal_dev(self, "Ethernet address %s\n", 388 ether_sprintf(sc->tl_enaddr)); 389 390 /* Map and establish interrupts */ 391 if (pci_intr_map(pa, &intrhandle)) { 392 aprint_error_dev(self, "couldn't map interrupt\n"); 393 return; 394 } 395 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 396 sizeof(intrbuf)); 397 sc->tl_if.if_softc = sc; 398 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 399 tl_intr, sc); 400 if (sc->tl_ih == NULL) { 401 aprint_error_dev(self, "couldn't establish interrupt"); 402 if (intrstr != NULL) 403 aprint_error(" at %s", intrstr); 404 aprint_error("\n"); 405 return; 406 } 407 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 408 409 /* init these pointers, so that tl_shutdown won't try to read them */ 410 sc->Rx_list = NULL; 411 sc->Tx_list = NULL; 412 413 /* allocate DMA-safe memory for control structs */ 414 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 415 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 416 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 417 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 418 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 419 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 420 return; 421 } 422 423 /* 424 * Initialize our media structures and probe the MII. 425 * 426 * Note that we don't care about the media instance. We 427 * are expecting to have multiple PHYs on the 10/100 cards, 428 * and on those cards we exclude the internal PHY from providing 429 * 10baseT. By ignoring the instance, it allows us to not have 430 * to specify it on the command line when switching media. 431 */ 432 sc->tl_mii.mii_ifp = ifp; 433 sc->tl_mii.mii_readreg = tl_mii_read; 434 sc->tl_mii.mii_writereg = tl_mii_write; 435 sc->tl_mii.mii_statchg = tl_statchg; 436 sc->tl_ec.ec_mii = &sc->tl_mii; 437 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 438 ether_mediastatus); 439 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 440 MII_OFFSET_ANY, 0); 441 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 442 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 444 } else 445 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 446 447 /* 448 * We can support 802.1Q VLAN-sized frames. 449 */ 450 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 451 452 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 453 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 454 ifp->if_ioctl = tl_ifioctl; 455 ifp->if_start = tl_ifstart; 456 ifp->if_watchdog = tl_ifwatchdog; 457 ifp->if_init = tl_init; 458 ifp->if_stop = tl_stop; 459 ifp->if_timer = 0; 460 IFQ_SET_READY(&ifp->if_snd); 461 if_attach(ifp); 462 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 463 464 /* 465 * Add shutdown hook so that DMA is disabled prior to reboot. 466 * Not doing reboot before the driver initializes. 467 */ 468 if (pmf_device_register1(self, NULL, NULL, tl_shutdown)) 469 pmf_class_network_register(self, ifp); 470 else 471 aprint_error_dev(self, "couldn't establish power handler\n"); 472 473 rnd_attach_source(&sc->rnd_source, device_xname(self), 474 RND_TYPE_NET, RND_FLAG_DEFAULT); 475 } 476 477 static void 478 tl_reset(tl_softc_t *sc) 479 { 480 int i; 481 482 /* read stats */ 483 if (sc->tl_if.if_flags & IFF_RUNNING) { 484 callout_stop(&sc->tl_tick_ch); 485 tl_read_stats(sc); 486 } 487 /* Reset adapter */ 488 TL_HR_WRITE(sc, TL_HOST_CMD, 489 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 490 DELAY(100000); 491 /* Disable interrupts */ 492 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 493 /* setup aregs & hash */ 494 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 495 tl_intreg_write(sc, i, 0); 496 #ifdef TLDEBUG_ADDR 497 printf("Areg & hash registers: \n"); 498 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 499 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 500 #endif 501 /* Setup NetConfig */ 502 tl_intreg_write(sc, TL_INT_NetConfig, 503 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 504 /* Bsize: accept default */ 505 /* TX commit in Acommit: accept default */ 506 /* Load Ld_tmr and Ld_thr */ 507 /* Ld_tmr = 3 */ 508 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 509 /* Ld_thr = 0 */ 510 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 511 /* Unreset MII */ 512 netsio_set(sc, TL_NETSIO_NMRST); 513 DELAY(100000); 514 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 515 } 516 517 static bool 518 tl_shutdown(device_t self, int howto) 519 { 520 tl_softc_t *sc = device_private(self); 521 struct ifnet *ifp = &sc->tl_if; 522 523 tl_stop(ifp, 1); 524 525 return true; 526 } 527 528 static void 529 tl_stop(struct ifnet *ifp, int disable) 530 { 531 tl_softc_t *sc = ifp->if_softc; 532 struct Tx_list *Tx; 533 int i; 534 535 if ((ifp->if_flags & IFF_RUNNING) == 0) 536 return; 537 /* disable interrupts */ 538 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 539 /* stop TX and RX channels */ 540 TL_HR_WRITE(sc, TL_HOST_CMD, 541 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 542 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 543 DELAY(100000); 544 545 /* stop statistics reading loop, read stats */ 546 callout_stop(&sc->tl_tick_ch); 547 tl_read_stats(sc); 548 549 /* Down the MII. */ 550 mii_down(&sc->tl_mii); 551 552 /* deallocate memory allocations */ 553 if (sc->Rx_list) { 554 for (i = 0; i< TL_NBUF; i++) { 555 if (sc->Rx_list[i].m) { 556 bus_dmamap_unload(sc->tl_dmatag, 557 sc->Rx_list[i].m_dmamap); 558 m_freem(sc->Rx_list[i].m); 559 } 560 bus_dmamap_destroy(sc->tl_dmatag, 561 sc->Rx_list[i].m_dmamap); 562 sc->Rx_list[i].m = NULL; 563 } 564 free(sc->Rx_list, M_DEVBUF); 565 sc->Rx_list = NULL; 566 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 567 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 568 sc->hw_Rx_list = NULL; 569 while ((Tx = sc->active_Tx) != NULL) { 570 Tx->hw_list->stat = 0; 571 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 572 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 573 m_freem(Tx->m); 574 sc->active_Tx = Tx->next; 575 Tx->next = sc->Free_Tx; 576 sc->Free_Tx = Tx; 577 } 578 sc->last_Tx = NULL; 579 free(sc->Tx_list, M_DEVBUF); 580 sc->Tx_list = NULL; 581 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 582 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 583 sc->hw_Tx_list = NULL; 584 } 585 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 586 ifp->if_timer = 0; 587 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 588 } 589 590 static void 591 tl_restart(void *v) 592 { 593 594 tl_init(v); 595 } 596 597 static int 598 tl_init(struct ifnet *ifp) 599 { 600 tl_softc_t *sc = ifp->if_softc; 601 int i, s, error; 602 bus_size_t boundary; 603 prop_number_t prop_boundary; 604 const char *errstring; 605 char *nullbuf; 606 607 s = splnet(); 608 /* cancel any pending IO */ 609 tl_stop(ifp, 1); 610 tl_reset(sc); 611 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 612 splx(s); 613 return 0; 614 } 615 /* Set various register to reasonable value */ 616 /* setup NetCmd in promisc mode if needed */ 617 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 618 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 619 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 620 /* Max receive size : MCLBYTES */ 621 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 622 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 623 (MCLBYTES >> 8) & 0xff); 624 625 /* init MAC addr */ 626 for (i = 0; i < ETHER_ADDR_LEN; i++) 627 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 628 /* add multicast filters */ 629 tl_addr_filter(sc); 630 #ifdef TLDEBUG_ADDR 631 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 632 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 633 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 634 #endif 635 636 /* Pre-allocate receivers mbuf, make the lists */ 637 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 638 M_NOWAIT|M_ZERO); 639 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 640 M_NOWAIT|M_ZERO); 641 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 642 errstring = "out of memory for lists"; 643 error = ENOMEM; 644 goto bad; 645 } 646 647 /* 648 * Some boards (Set Engineering GFE) do not permit DMA transfers 649 * across page boundaries. 650 */ 651 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 652 "tl-dma-page-boundary"); 653 if (prop_boundary != NULL) { 654 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 655 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 656 } else { 657 boundary = 0; 658 } 659 660 error = bus_dmamap_create(sc->tl_dmatag, 661 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 662 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 663 &sc->Rx_dmamap); 664 if (error == 0) 665 error = bus_dmamap_create(sc->tl_dmatag, 666 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 667 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 668 BUS_DMA_WAITOK, &sc->Tx_dmamap); 669 if (error == 0) 670 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 671 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 672 &sc->null_dmamap); 673 if (error) { 674 errstring = "can't allocate DMA maps for lists"; 675 goto bad; 676 } 677 memset(sc->ctrl, 0, PAGE_SIZE); 678 sc->hw_Rx_list = (void *)sc->ctrl; 679 sc->hw_Tx_list = 680 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 681 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 682 sizeof(struct tl_Tx_list) * TL_NBUF; 683 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 684 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 685 BUS_DMA_WAITOK); 686 if (error == 0) 687 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 688 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 689 BUS_DMA_WAITOK); 690 if (error == 0) 691 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 692 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 693 if (error) { 694 errstring = "can't DMA map DMA memory for lists"; 695 goto bad; 696 } 697 for (i = 0; i < TL_NBUF; i++) { 698 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 699 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 700 &sc->Rx_list[i].m_dmamap); 701 if (error == 0) { 702 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 703 TL_NSEG, MCLBYTES, boundary, 704 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 705 &sc->Tx_list[i].m_dmamap); 706 } 707 if (error) { 708 errstring = "can't allocate DMA maps for mbufs"; 709 goto bad; 710 } 711 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 712 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 713 + sizeof(struct tl_Rx_list) * i; 714 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 715 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 716 + sizeof(struct tl_Tx_list) * i; 717 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 718 errstring = "out of mbuf for receive list"; 719 error = ENOMEM; 720 goto bad; 721 } 722 if (i > 0) { /* chain the list */ 723 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 724 sc->hw_Rx_list[i - 1].fwd = 725 htole32(sc->Rx_list[i].hw_listaddr); 726 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 727 } 728 } 729 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 730 sc->Rx_list[TL_NBUF - 1].next = NULL; 731 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 732 sc->Tx_list[TL_NBUF - 1].next = NULL; 733 734 sc->active_Rx = &sc->Rx_list[0]; 735 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 736 sc->active_Tx = sc->last_Tx = NULL; 737 sc->Free_Tx = &sc->Tx_list[0]; 738 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 739 sizeof(struct tl_Rx_list) * TL_NBUF, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 742 sizeof(struct tl_Tx_list) * TL_NBUF, 743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 745 BUS_DMASYNC_PREWRITE); 746 747 /* set media */ 748 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 749 error = 0; 750 else if (error != 0) { 751 errstring = "could not set media"; 752 goto bad; 753 } 754 755 /* start ticks calls */ 756 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 757 /* write address of Rx list and enable interrupts */ 758 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 759 TL_HR_WRITE(sc, TL_HOST_CMD, 760 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 761 sc->tl_if.if_flags |= IFF_RUNNING; 762 sc->tl_if.if_flags &= ~IFF_OACTIVE; 763 splx(s); 764 return 0; 765 bad: 766 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 767 splx(s); 768 return error; 769 } 770 771 772 static uint32_t 773 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 774 { 775 776 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 777 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 778 } 779 780 static uint8_t 781 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 782 { 783 784 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 785 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 786 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 787 } 788 789 static void 790 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 791 { 792 793 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 794 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 795 } 796 797 static void 798 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 799 { 800 801 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 802 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 803 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 804 } 805 806 void 807 tl_mii_sync(struct tl_softc *sc) 808 { 809 int i; 810 811 netsio_clr(sc, TL_NETSIO_MTXEN); 812 for (i = 0; i < 32; i++) { 813 netsio_clr(sc, TL_NETSIO_MCLK); 814 netsio_set(sc, TL_NETSIO_MCLK); 815 } 816 } 817 818 void 819 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 820 { 821 int i; 822 823 netsio_set(sc, TL_NETSIO_MTXEN); 824 for (i = 1 << (nbits - 1); i; i = i >> 1) { 825 netsio_clr(sc, TL_NETSIO_MCLK); 826 netsio_read(sc, TL_NETSIO_MCLK); 827 if (data & i) 828 netsio_set(sc, TL_NETSIO_MDATA); 829 else 830 netsio_clr(sc, TL_NETSIO_MDATA); 831 netsio_set(sc, TL_NETSIO_MCLK); 832 netsio_read(sc, TL_NETSIO_MCLK); 833 } 834 } 835 836 int 837 tl_mii_read(device_t self, int phy, int reg) 838 { 839 struct tl_softc *sc = device_private(self); 840 int val = 0, i, err; 841 842 /* 843 * Read the PHY register by manually driving the MII control lines. 844 */ 845 846 tl_mii_sync(sc); 847 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 848 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 849 tl_mii_sendbits(sc, phy, 5); 850 tl_mii_sendbits(sc, reg, 5); 851 852 netsio_clr(sc, TL_NETSIO_MTXEN); 853 netsio_clr(sc, TL_NETSIO_MCLK); 854 netsio_set(sc, TL_NETSIO_MCLK); 855 netsio_clr(sc, TL_NETSIO_MCLK); 856 857 err = netsio_read(sc, TL_NETSIO_MDATA); 858 netsio_set(sc, TL_NETSIO_MCLK); 859 860 /* Even if an error occurs, must still clock out the cycle. */ 861 for (i = 0; i < 16; i++) { 862 val <<= 1; 863 netsio_clr(sc, TL_NETSIO_MCLK); 864 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 865 val |= 1; 866 netsio_set(sc, TL_NETSIO_MCLK); 867 } 868 netsio_clr(sc, TL_NETSIO_MCLK); 869 netsio_set(sc, TL_NETSIO_MCLK); 870 871 return err ? 0 : val; 872 } 873 874 void 875 tl_mii_write(device_t self, int phy, int reg, int val) 876 { 877 struct tl_softc *sc = device_private(self); 878 879 /* 880 * Write the PHY register by manually driving the MII control lines. 881 */ 882 883 tl_mii_sync(sc); 884 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 885 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 886 tl_mii_sendbits(sc, phy, 5); 887 tl_mii_sendbits(sc, reg, 5); 888 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 889 tl_mii_sendbits(sc, val, 16); 890 891 netsio_clr(sc, TL_NETSIO_MCLK); 892 netsio_set(sc, TL_NETSIO_MCLK); 893 } 894 895 void 896 tl_statchg(struct ifnet *ifp) 897 { 898 tl_softc_t *sc = ifp->if_softc; 899 uint32_t reg; 900 901 #ifdef TLDEBUG 902 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 903 #endif 904 905 /* 906 * We must keep the ThunderLAN and the PHY in sync as 907 * to the status of full-duplex! 908 */ 909 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 910 if (sc->tl_mii.mii_media_active & IFM_FDX) 911 reg |= TL_NETCOMMAND_DUPLEX; 912 else 913 reg &= ~TL_NETCOMMAND_DUPLEX; 914 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 915 } 916 917 /********** I2C glue **********/ 918 919 static int 920 tl_i2c_acquire_bus(void *cookie, int flags) 921 { 922 923 /* private bus */ 924 return 0; 925 } 926 927 static void 928 tl_i2c_release_bus(void *cookie, int flags) 929 { 930 931 /* private bus */ 932 } 933 934 static int 935 tl_i2c_send_start(void *cookie, int flags) 936 { 937 938 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 939 } 940 941 static int 942 tl_i2c_send_stop(void *cookie, int flags) 943 { 944 945 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 946 } 947 948 static int 949 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 950 { 951 952 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 953 } 954 955 static int 956 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 957 { 958 959 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 960 } 961 962 static int 963 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 964 { 965 966 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 967 } 968 969 /********** I2C bit-bang glue **********/ 970 971 static void 972 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 973 { 974 struct tl_softc *sc = cookie; 975 uint8_t reg; 976 977 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 978 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 979 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 980 } 981 982 static void 983 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 984 { 985 struct tl_softc *sc = cookie; 986 uint8_t reg; 987 988 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 989 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 990 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 991 } 992 993 static uint32_t 994 tl_i2cbb_read(void *cookie) 995 { 996 997 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 998 } 999 1000 /********** End of I2C stuff **********/ 1001 1002 static int 1003 tl_intr(void *v) 1004 { 1005 tl_softc_t *sc = v; 1006 struct ifnet *ifp = &sc->tl_if; 1007 struct Rx_list *Rx; 1008 struct Tx_list *Tx; 1009 struct mbuf *m; 1010 uint32_t int_type, int_reg; 1011 int ack = 0; 1012 int size; 1013 1014 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1015 int_type = int_reg & TL_INTR_MASK; 1016 if (int_type == 0) 1017 return 0; 1018 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1019 printf("%s: interrupt type %x, intr_reg %x\n", 1020 device_xname(sc->sc_dev), int_type, int_reg); 1021 #endif 1022 /* disable interrupts */ 1023 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1024 switch(int_type & TL_INTR_MASK) { 1025 case TL_INTR_RxEOF: 1026 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1027 sizeof(struct tl_Rx_list) * TL_NBUF, 1028 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1029 while(le32toh(sc->active_Rx->hw_list->stat) & 1030 TL_RX_CSTAT_CPLT) { 1031 /* dequeue and requeue at end of list */ 1032 ack++; 1033 Rx = sc->active_Rx; 1034 sc->active_Rx = Rx->next; 1035 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1036 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1037 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1038 m = Rx->m; 1039 size = le32toh(Rx->hw_list->stat) >> 16; 1040 #ifdef TLDEBUG_RX 1041 printf("%s: RX list complete, Rx %p, size=%d\n", 1042 __func__, Rx, size); 1043 #endif 1044 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1045 /* 1046 * No new mbuf, reuse the same. This means 1047 * that this packet 1048 * is lost 1049 */ 1050 m = NULL; 1051 #ifdef TL_PRIV_STATS 1052 sc->ierr_nomem++; 1053 #endif 1054 #ifdef TLDEBUG 1055 printf("%s: out of mbuf, lost input packet\n", 1056 device_xname(sc->sc_dev)); 1057 #endif 1058 } 1059 Rx->next = NULL; 1060 Rx->hw_list->fwd = 0; 1061 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1062 sc->last_Rx->next = Rx; 1063 sc->last_Rx = Rx; 1064 1065 /* deliver packet */ 1066 if (m) { 1067 if (size < sizeof(struct ether_header)) { 1068 m_freem(m); 1069 continue; 1070 } 1071 m_set_rcvif(m, ifp); 1072 m->m_pkthdr.len = m->m_len = size; 1073 #ifdef TLDEBUG_RX 1074 { 1075 struct ether_header *eh = 1076 mtod(m, struct ether_header *); 1077 printf("%s: Rx packet:\n", __func__); 1078 ether_printheader(eh); 1079 } 1080 #endif 1081 bpf_mtap(ifp, m); 1082 if_percpuq_enqueue(ifp->if_percpuq, m); 1083 } 1084 } 1085 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1086 sizeof(struct tl_Rx_list) * TL_NBUF, 1087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1088 #ifdef TLDEBUG_RX 1089 printf("TL_INTR_RxEOF: ack %d\n", ack); 1090 #else 1091 if (ack == 0) { 1092 printf("%s: EOF intr without anything to read !\n", 1093 device_xname(sc->sc_dev)); 1094 tl_reset(sc); 1095 /* schedule reinit of the board */ 1096 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1097 return 1; 1098 } 1099 #endif 1100 break; 1101 case TL_INTR_RxEOC: 1102 ack++; 1103 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1104 sizeof(struct tl_Rx_list) * TL_NBUF, 1105 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1106 #ifdef TLDEBUG_RX 1107 printf("TL_INTR_RxEOC: ack %d\n", ack); 1108 #endif 1109 #ifdef DIAGNOSTIC 1110 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1111 printf("%s: Rx EOC interrupt and active Tx list not " 1112 "cleared\n", device_xname(sc->sc_dev)); 1113 return 0; 1114 } else 1115 #endif 1116 { 1117 /* 1118 * write address of Rx list and send Rx GO command, ack 1119 * interrupt and enable interrupts in one command 1120 */ 1121 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1122 TL_HR_WRITE(sc, TL_HOST_CMD, 1123 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1124 HOST_CMD_ACK | HOST_CMD_IntOn); 1125 return 1; 1126 } 1127 case TL_INTR_TxEOF: 1128 case TL_INTR_TxEOC: 1129 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1130 sizeof(struct tl_Tx_list) * TL_NBUF, 1131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1132 while ((Tx = sc->active_Tx) != NULL) { 1133 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1134 break; 1135 ack++; 1136 #ifdef TLDEBUG_TX 1137 printf("TL_INTR_TxEOC: list 0x%x done\n", 1138 (int)Tx->hw_listaddr); 1139 #endif 1140 Tx->hw_list->stat = 0; 1141 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1142 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1144 m_freem(Tx->m); 1145 Tx->m = NULL; 1146 sc->active_Tx = Tx->next; 1147 if (sc->active_Tx == NULL) 1148 sc->last_Tx = NULL; 1149 Tx->next = sc->Free_Tx; 1150 sc->Free_Tx = Tx; 1151 } 1152 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1153 sizeof(struct tl_Tx_list) * TL_NBUF, 1154 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1155 /* if this was an EOC, ACK immediatly */ 1156 if (ack) 1157 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1158 if (int_type == TL_INTR_TxEOC) { 1159 #ifdef TLDEBUG_TX 1160 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1161 ack); 1162 #endif 1163 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1164 HOST_CMD_ACK | HOST_CMD_IntOn); 1165 if (sc->active_Tx != NULL) { 1166 /* needs a Tx go command */ 1167 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1168 sc->active_Tx->hw_listaddr); 1169 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1170 } 1171 sc->tl_if.if_timer = 0; 1172 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1173 tl_ifstart(&sc->tl_if); 1174 return 1; 1175 } 1176 #ifdef TLDEBUG 1177 else { 1178 printf("TL_INTR_TxEOF: ack %d\n", ack); 1179 } 1180 #endif 1181 sc->tl_if.if_timer = 0; 1182 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1183 tl_ifstart(&sc->tl_if); 1184 break; 1185 case TL_INTR_Stat: 1186 ack++; 1187 #ifdef TLDEBUG 1188 printf("TL_INTR_Stat: ack %d\n", ack); 1189 #endif 1190 tl_read_stats(sc); 1191 break; 1192 case TL_INTR_Adc: 1193 if (int_reg & TL_INTVec_MASK) { 1194 /* adapter check conditions */ 1195 printf("%s: check condition, intvect=0x%x, " 1196 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1197 int_reg & TL_INTVec_MASK, 1198 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1199 tl_reset(sc); 1200 /* schedule reinit of the board */ 1201 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1202 return 1; 1203 } else { 1204 uint8_t netstat; 1205 /* Network status */ 1206 netstat = 1207 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1208 printf("%s: network status, NetSts=%x\n", 1209 device_xname(sc->sc_dev), netstat); 1210 /* Ack interrupts */ 1211 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1212 netstat); 1213 ack++; 1214 } 1215 break; 1216 default: 1217 printf("%s: unhandled interrupt code %x!\n", 1218 device_xname(sc->sc_dev), int_type); 1219 ack++; 1220 } 1221 1222 if (ack) { 1223 /* Ack the interrupt and enable interrupts */ 1224 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1225 HOST_CMD_IntOn); 1226 rnd_add_uint32(&sc->rnd_source, int_reg); 1227 return 1; 1228 } 1229 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1230 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1231 return 0; 1232 } 1233 1234 static int 1235 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1236 { 1237 struct tl_softc *sc = ifp->if_softc; 1238 int s, error; 1239 1240 s = splnet(); 1241 error = ether_ioctl(ifp, cmd, data); 1242 if (error == ENETRESET) { 1243 if (ifp->if_flags & IFF_RUNNING) 1244 tl_addr_filter(sc); 1245 error = 0; 1246 } 1247 splx(s); 1248 return error; 1249 } 1250 1251 static void 1252 tl_ifstart(struct ifnet *ifp) 1253 { 1254 tl_softc_t *sc = ifp->if_softc; 1255 struct mbuf *mb_head; 1256 struct Tx_list *Tx; 1257 int segment, size; 1258 int again, error; 1259 1260 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1261 return; 1262 txloop: 1263 /* If we don't have more space ... */ 1264 if (sc->Free_Tx == NULL) { 1265 #ifdef TLDEBUG 1266 printf("%s: No free TX list\n", __func__); 1267 #endif 1268 sc->tl_if.if_flags |= IFF_OACTIVE; 1269 return; 1270 } 1271 /* Grab a paquet for output */ 1272 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1273 if (mb_head == NULL) { 1274 #ifdef TLDEBUG_TX 1275 printf("%s: nothing to send\n", __func__); 1276 #endif 1277 return; 1278 } 1279 Tx = sc->Free_Tx; 1280 sc->Free_Tx = Tx->next; 1281 Tx->next = NULL; 1282 again = 0; 1283 /* 1284 * Go through each of the mbufs in the chain and initialize 1285 * the transmit list descriptors with the physical address 1286 * and size of the mbuf. 1287 */ 1288 tbdinit: 1289 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1290 Tx->m = mb_head; 1291 size = mb_head->m_pkthdr.len; 1292 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1293 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1294 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1295 struct mbuf *mn; 1296 /* 1297 * We ran out of segments, or we will. We have to recopy this 1298 * mbuf chain first. 1299 */ 1300 if (error == 0) 1301 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1302 if (again) { 1303 /* already copyed, can't do much more */ 1304 m_freem(mb_head); 1305 goto bad; 1306 } 1307 again = 1; 1308 #ifdef TLDEBUG_TX 1309 printf("%s: need to copy mbuf\n", __func__); 1310 #endif 1311 #ifdef TL_PRIV_STATS 1312 sc->oerr_mcopy++; 1313 #endif 1314 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1315 if (mn == NULL) { 1316 m_freem(mb_head); 1317 goto bad; 1318 } 1319 if (mb_head->m_pkthdr.len > MHLEN) { 1320 MCLGET(mn, M_DONTWAIT); 1321 if ((mn->m_flags & M_EXT) == 0) { 1322 m_freem(mn); 1323 m_freem(mb_head); 1324 goto bad; 1325 } 1326 } 1327 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1328 mtod(mn, void *)); 1329 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1330 m_freem(mb_head); 1331 mb_head = mn; 1332 goto tbdinit; 1333 } 1334 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1335 Tx->hw_list->seg[segment].data_addr = 1336 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1337 Tx->hw_list->seg[segment].data_count = 1338 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1339 } 1340 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1341 Tx->m_dmamap->dm_mapsize, 1342 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1343 /* We are at end of mbuf chain. check the size and 1344 * see if it needs to be extended 1345 */ 1346 if (size < ETHER_MIN_TX) { 1347 #ifdef DIAGNOSTIC 1348 if (segment >= TL_NSEG) { 1349 panic("%s: to much segmets (%d)", __func__, segment); 1350 } 1351 #endif 1352 /* 1353 * add the nullbuf in the seg 1354 */ 1355 Tx->hw_list->seg[segment].data_count = 1356 htole32(ETHER_MIN_TX - size); 1357 Tx->hw_list->seg[segment].data_addr = 1358 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1359 size = ETHER_MIN_TX; 1360 segment++; 1361 } 1362 /* The list is done, finish the list init */ 1363 Tx->hw_list->seg[segment - 1].data_count |= 1364 htole32(TL_LAST_SEG); 1365 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1366 #ifdef TLDEBUG_TX 1367 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1368 le32toh(Tx->hw_list->stat)); 1369 #if 0 1370 for (segment = 0; segment < TL_NSEG; segment++) { 1371 printf(" seg %d addr 0x%x len 0x%x\n", 1372 segment, 1373 le32toh(Tx->hw_list->seg[segment].data_addr), 1374 le32toh(Tx->hw_list->seg[segment].data_count)); 1375 } 1376 #endif 1377 #endif 1378 if (sc->active_Tx == NULL) { 1379 sc->active_Tx = sc->last_Tx = Tx; 1380 #ifdef TLDEBUG_TX 1381 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1382 (int)Tx->hw_listaddr); 1383 #endif 1384 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1385 sizeof(struct tl_Tx_list) * TL_NBUF, 1386 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1387 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1388 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1389 } else { 1390 #ifdef TLDEBUG_TX 1391 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1392 (int)Tx->hw_listaddr); 1393 #endif 1394 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1395 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1396 sizeof(struct tl_Tx_list) * TL_NBUF, 1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1398 sc->last_Tx->next = Tx; 1399 sc->last_Tx = Tx; 1400 #ifdef DIAGNOSTIC 1401 if (sc->last_Tx->hw_list->fwd & 0x7) 1402 printf("%s: physical addr 0x%x of list not properly " 1403 "aligned\n", 1404 device_xname(sc->sc_dev), 1405 sc->last_Rx->hw_list->fwd); 1406 #endif 1407 } 1408 /* Pass packet to bpf if there is a listener */ 1409 bpf_mtap(ifp, mb_head); 1410 /* 1411 * Set a 5 second timer just in case we don't hear from the card again. 1412 */ 1413 ifp->if_timer = 5; 1414 goto txloop; 1415 bad: 1416 #ifdef TLDEBUG 1417 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1418 #endif 1419 Tx->next = sc->Free_Tx; 1420 sc->Free_Tx = Tx; 1421 } 1422 1423 static void 1424 tl_ifwatchdog(struct ifnet *ifp) 1425 { 1426 tl_softc_t *sc = ifp->if_softc; 1427 1428 if ((ifp->if_flags & IFF_RUNNING) == 0) 1429 return; 1430 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1431 ifp->if_oerrors++; 1432 tl_init(ifp); 1433 } 1434 1435 static int 1436 tl_mediachange(struct ifnet *ifp) 1437 { 1438 1439 if (ifp->if_flags & IFF_UP) 1440 tl_init(ifp); 1441 return 0; 1442 } 1443 1444 static int 1445 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1446 { 1447 struct mbuf *m; 1448 int error; 1449 1450 MGETHDR(m, M_DONTWAIT, MT_DATA); 1451 if (m != NULL) { 1452 MCLGET(m, M_DONTWAIT); 1453 if ((m->m_flags & M_EXT) == 0) { 1454 m_freem(m); 1455 if (oldm == NULL) 1456 return 0; 1457 m = oldm; 1458 m->m_data = m->m_ext.ext_buf; 1459 } 1460 } else { 1461 if (oldm == NULL) 1462 return 0; 1463 m = oldm; 1464 m->m_data = m->m_ext.ext_buf; 1465 } 1466 1467 /* (re)init the Rx_list struct */ 1468 1469 Rx->m = m; 1470 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1471 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1472 printf("%s: bus_dmamap_load() failed (error %d) for " 1473 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1474 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1475 m_freem(m); 1476 Rx->m = NULL; 1477 return 0; 1478 } 1479 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1480 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1481 /* 1482 * Move the data pointer up so that the incoming data packet 1483 * will be 32-bit aligned. 1484 */ 1485 m->m_data += 2; 1486 1487 Rx->hw_list->stat = 1488 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1489 Rx->hw_list->seg.data_count = 1490 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1491 Rx->hw_list->seg.data_addr = 1492 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1493 return (m != oldm); 1494 } 1495 1496 static void 1497 tl_ticks(void *v) 1498 { 1499 tl_softc_t *sc = v; 1500 1501 tl_read_stats(sc); 1502 1503 /* Tick the MII. */ 1504 mii_tick(&sc->tl_mii); 1505 1506 /* read statistics every seconds */ 1507 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1508 } 1509 1510 static void 1511 tl_read_stats(tl_softc_t *sc) 1512 { 1513 uint32_t reg; 1514 int ierr_overr; 1515 int ierr_code; 1516 int ierr_crc; 1517 int oerr_underr; 1518 int oerr_deferred; 1519 int oerr_coll; 1520 int oerr_multicoll; 1521 int oerr_exesscoll; 1522 int oerr_latecoll; 1523 int oerr_carrloss; 1524 struct ifnet *ifp = &sc->tl_if; 1525 1526 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1527 ifp->if_opackets += reg & 0x00ffffff; 1528 oerr_underr = reg >> 24; 1529 1530 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1531 ifp->if_ipackets += reg & 0x00ffffff; 1532 ierr_overr = reg >> 24; 1533 1534 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1535 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1536 ierr_code = (reg & TL_FERR_CODE) >> 24; 1537 oerr_deferred = (reg & TL_FERR_DEF); 1538 1539 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1540 oerr_multicoll = (reg & TL_COL_MULTI); 1541 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1542 1543 reg = tl_intreg_read(sc, TL_INT_LERR); 1544 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1545 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1546 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1547 1548 1549 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1550 oerr_carrloss; 1551 ifp->if_collisions += oerr_coll + oerr_multicoll; 1552 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1553 1554 if (ierr_overr) 1555 printf("%s: receiver ring buffer overrun\n", 1556 device_xname(sc->sc_dev)); 1557 if (oerr_underr) 1558 printf("%s: transmit buffer underrun\n", 1559 device_xname(sc->sc_dev)); 1560 #ifdef TL_PRIV_STATS 1561 sc->ierr_overr += ierr_overr; 1562 sc->ierr_code += ierr_code; 1563 sc->ierr_crc += ierr_crc; 1564 sc->oerr_underr += oerr_underr; 1565 sc->oerr_deferred += oerr_deferred; 1566 sc->oerr_coll += oerr_coll; 1567 sc->oerr_multicoll += oerr_multicoll; 1568 sc->oerr_exesscoll += oerr_exesscoll; 1569 sc->oerr_latecoll += oerr_latecoll; 1570 sc->oerr_carrloss += oerr_carrloss; 1571 #endif 1572 } 1573 1574 static void 1575 tl_addr_filter(tl_softc_t *sc) 1576 { 1577 struct ether_multistep step; 1578 struct ether_multi *enm; 1579 uint32_t hash[2] = {0, 0}; 1580 int i; 1581 1582 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1583 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1584 while (enm != NULL) { 1585 #ifdef TLDEBUG 1586 printf("%s: addrs %s %s\n", __func__, 1587 ether_sprintf(enm->enm_addrlo), 1588 ether_sprintf(enm->enm_addrhi)); 1589 #endif 1590 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1591 i = tl_multicast_hash(enm->enm_addrlo); 1592 hash[i / 32] |= 1 << (i%32); 1593 } else { 1594 hash[0] = hash[1] = 0xffffffff; 1595 sc->tl_if.if_flags |= IFF_ALLMULTI; 1596 break; 1597 } 1598 ETHER_NEXT_MULTI(step, enm); 1599 } 1600 #ifdef TLDEBUG 1601 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1602 #endif 1603 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1604 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1605 } 1606 1607 static int 1608 tl_multicast_hash(uint8_t *a) 1609 { 1610 int hash; 1611 1612 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1613 #define xor8(a,b,c,d,e,f,g,h) \ 1614 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1615 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1616 1617 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1618 DA(a,36), DA(a,42)); 1619 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1620 DA(a,37), DA(a,43)) << 1; 1621 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1622 DA(a,38), DA(a,44)) << 2; 1623 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1624 DA(a,39), DA(a,45)) << 3; 1625 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1626 DA(a,40), DA(a,46)) << 4; 1627 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1628 DA(a,41), DA(a,47)) << 5; 1629 1630 return hash; 1631 } 1632 1633 #if defined(TLDEBUG_RX) 1634 void 1635 ether_printheader(struct ether_header *eh) 1636 { 1637 uint8_t *c = (uint8_t *)eh; 1638 int i; 1639 1640 for (i = 0; i < sizeof(struct ether_header); i++) 1641 printf("%02x ", (u_int)c[i]); 1642 printf("\n"); 1643 } 1644 #endif 1645
Indexes created Thu Sep 25 16:09:42 GMT 2025