if_tl.c revision 1.109
1 /* $NetBSD: if_tl.c,v 1.109 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Texas Instruments ThunderLAN ethernet controller 29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 30 * available from www.ti.com 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.109 2018/06/26 06:48:01 msaitoh Exp $"); 35 36 #undef TLDEBUG 37 #define TL_PRIV_STATS 38 #undef TLDEBUG_RX 39 #undef TLDEBUG_TX 40 #undef TLDEBUG_ADDR 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 #include <net/bpf.h> 65 66 #include <sys/rndsource.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/in_var.h> 72 #include <netinet/ip.h> 73 #endif 74 75 76 #if defined(__NetBSD__) 77 #include <net/if_ether.h> 78 #if defined(INET) 79 #include <netinet/if_inarp.h> 80 #endif 81 82 #include <sys/bus.h> 83 #include <sys/intr.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pcidevs.h> 88 89 #include <dev/i2c/i2cvar.h> 90 #include <dev/i2c/i2c_bitbang.h> 91 #include <dev/i2c/at24cxxvar.h> 92 93 #include <dev/mii/mii.h> 94 #include <dev/mii/miivar.h> 95 96 #include <dev/mii/tlphyvar.h> 97 98 #include <dev/pci/if_tlregs.h> 99 #include <dev/pci/if_tlvar.h> 100 #endif /* __NetBSD__ */ 101 102 /* number of transmit/receive buffers */ 103 #ifndef TL_NBUF 104 #define TL_NBUF 32 105 #endif 106 107 static int tl_pci_match(device_t, cfdata_t, void *); 108 static void tl_pci_attach(device_t, device_t, void *); 109 static int tl_intr(void *); 110 111 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 112 static int tl_mediachange(struct ifnet *); 113 static void tl_ifwatchdog(struct ifnet *); 114 static bool tl_shutdown(device_t, int); 115 116 static void tl_ifstart(struct ifnet *); 117 static void tl_reset(tl_softc_t *); 118 static int tl_init(struct ifnet *); 119 static void tl_stop(struct ifnet *, int); 120 static void tl_restart(void *); 121 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 122 static void tl_read_stats(tl_softc_t *); 123 static void tl_ticks(void *); 124 static int tl_multicast_hash(uint8_t *); 125 static void tl_addr_filter(tl_softc_t *); 126 127 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 128 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 129 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 130 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 131 132 void tl_mii_sync(struct tl_softc *); 133 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 134 135 136 #if defined(TLDEBUG_RX) 137 static void ether_printheader(struct ether_header *); 138 #endif 139 140 int tl_mii_read(device_t, int, int); 141 void tl_mii_write(device_t, int, int, int); 142 143 void tl_statchg(struct ifnet *); 144 145 /* I2C glue */ 146 static int tl_i2c_acquire_bus(void *, int); 147 static void tl_i2c_release_bus(void *, int); 148 static int tl_i2c_send_start(void *, int); 149 static int tl_i2c_send_stop(void *, int); 150 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 151 static int tl_i2c_read_byte(void *, uint8_t *, int); 152 static int tl_i2c_write_byte(void *, uint8_t, int); 153 154 /* I2C bit-bang glue */ 155 static void tl_i2cbb_set_bits(void *, uint32_t); 156 static void tl_i2cbb_set_dir(void *, uint32_t); 157 static uint32_t tl_i2cbb_read(void *); 158 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 159 tl_i2cbb_set_bits, 160 tl_i2cbb_set_dir, 161 tl_i2cbb_read, 162 { 163 TL_NETSIO_EDATA, /* SDA */ 164 TL_NETSIO_ECLOCK, /* SCL */ 165 TL_NETSIO_ETXEN, /* SDA is output */ 166 0, /* SDA is input */ 167 } 168 }; 169 170 static inline void netsio_clr(tl_softc_t *, uint8_t); 171 static inline void netsio_set(tl_softc_t *, uint8_t); 172 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 173 174 static inline void 175 netsio_clr(tl_softc_t *sc, uint8_t bits) 176 { 177 178 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 179 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 180 } 181 182 static inline void 183 netsio_set(tl_softc_t *sc, uint8_t bits) 184 { 185 186 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 187 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 188 } 189 190 static inline uint8_t 191 netsio_read(tl_softc_t *sc, uint8_t bits) 192 { 193 194 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 195 } 196 197 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 198 tl_pci_match, tl_pci_attach, NULL, NULL); 199 200 static const struct tl_product_desc tl_compaq_products[] = { 201 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 202 "Compaq Netelligent 10/100 TX" }, 203 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 204 "Integrated Compaq Netelligent 10/100 TX" }, 205 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 206 "Compaq Netelligent 10 T" }, 207 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 208 "Compaq Netelligent 10 T/2 UTP/Coax" }, 209 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 210 "Compaq Integrated NetFlex 3/P" }, 211 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 212 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 213 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 214 "Compaq Dual Port Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 216 "Compaq Deskpro 4000 5233MMX" }, 217 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 218 "Compaq NetFlex 3/P w/ BNC" }, 219 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 220 "Compaq NetFlex 3/P" }, 221 { 0, 0, NULL }, 222 }; 223 224 static const struct tl_product_desc tl_ti_products[] = { 225 /* 226 * Built-in Ethernet on the TI TravelMate 5000 227 * docking station; better product description? 228 */ 229 { PCI_PRODUCT_TI_TLAN, 0, 230 "Texas Instruments ThunderLAN" }, 231 { 0, 0, NULL }, 232 }; 233 234 struct tl_vendor_desc { 235 uint32_t tv_vendor; 236 const struct tl_product_desc *tv_products; 237 }; 238 239 const struct tl_vendor_desc tl_vendors[] = { 240 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 241 { PCI_VENDOR_TI, tl_ti_products }, 242 { 0, NULL }, 243 }; 244 245 static const struct tl_product_desc *tl_lookup_product(uint32_t); 246 247 static const struct tl_product_desc * 248 tl_lookup_product(uint32_t id) 249 { 250 const struct tl_product_desc *tp; 251 const struct tl_vendor_desc *tv; 252 253 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 254 if (PCI_VENDOR(id) == tv->tv_vendor) 255 break; 256 257 if ((tp = tv->tv_products) == NULL) 258 return NULL; 259 260 for (; tp->tp_desc != NULL; tp++) 261 if (PCI_PRODUCT(id) == tp->tp_product) 262 break; 263 264 if (tp->tp_desc == NULL) 265 return NULL; 266 267 return tp; 268 } 269 270 static int 271 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 272 { 273 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 274 275 if (tl_lookup_product(pa->pa_id) != NULL) 276 return 1; 277 278 return 0; 279 } 280 281 static void 282 tl_pci_attach(device_t parent, device_t self, void *aux) 283 { 284 tl_softc_t *sc = device_private(self); 285 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 286 const struct tl_product_desc *tp; 287 struct ifnet * const ifp = &sc->tl_if; 288 bus_space_tag_t iot, memt; 289 bus_space_handle_t ioh, memh; 290 pci_intr_handle_t intrhandle; 291 const char *intrstr; 292 int ioh_valid, memh_valid; 293 int reg_io, reg_mem; 294 pcireg_t reg10, reg14; 295 pcireg_t csr; 296 char intrbuf[PCI_INTRSTR_LEN]; 297 298 sc->sc_dev = self; 299 aprint_normal("\n"); 300 301 callout_init(&sc->tl_tick_ch, 0); 302 callout_init(&sc->tl_restart_ch, 0); 303 304 tp = tl_lookup_product(pa->pa_id); 305 if (tp == NULL) 306 panic("%s: impossible", __func__); 307 sc->tl_product = tp; 308 309 /* 310 * Map the card space. First we have to find the I/O and MEM 311 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 312 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 313 * The ThunderLAN manual is not consistent about this either (there 314 * are both cases in code examples). 315 */ 316 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 317 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 318 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 319 reg_io = 0x10; 320 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 321 reg_io = 0x14; 322 else 323 reg_io = 0; 324 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 325 reg_mem = 0x10; 326 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 327 reg_mem = 0x14; 328 else 329 reg_mem = 0; 330 331 if (reg_io != 0) 332 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 333 0, &iot, &ioh, NULL, NULL) == 0); 334 else 335 ioh_valid = 0; 336 if (reg_mem != 0) 337 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 338 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 339 0, &memt, &memh, NULL, NULL) == 0); 340 else 341 memh_valid = 0; 342 343 if (ioh_valid) { 344 sc->tl_bustag = iot; 345 sc->tl_bushandle = ioh; 346 } else if (memh_valid) { 347 sc->tl_bustag = memt; 348 sc->tl_bushandle = memh; 349 } else { 350 aprint_error_dev(self, "unable to map device registers\n"); 351 return; 352 } 353 sc->tl_dmatag = pa->pa_dmat; 354 355 /* Enable the device. */ 356 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 357 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 358 csr | PCI_COMMAND_MASTER_ENABLE); 359 360 aprint_normal_dev(self, "%s\n", tp->tp_desc); 361 362 tl_reset(sc); 363 364 /* fill in the i2c tag */ 365 sc->sc_i2c.ic_cookie = sc; 366 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 367 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 368 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 369 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 370 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 371 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 372 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 373 374 #ifdef TLDEBUG 375 aprint_debug_dev(self, "default values of INTreg: 0x%x\n", 376 tl_intreg_read(sc, TL_INT_Defaults)); 377 #endif 378 379 /* read mac addr */ 380 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 381 sc->tl_enaddr, ETHER_ADDR_LEN)) { 382 aprint_error_dev(self, "error reading Ethernet address\n"); 383 return; 384 } 385 aprint_normal_dev(self, "Ethernet address %s\n", 386 ether_sprintf(sc->tl_enaddr)); 387 388 /* Map and establish interrupts */ 389 if (pci_intr_map(pa, &intrhandle)) { 390 aprint_error_dev(self, "couldn't map interrupt\n"); 391 return; 392 } 393 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 394 sizeof(intrbuf)); 395 sc->tl_if.if_softc = sc; 396 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 397 tl_intr, sc); 398 if (sc->tl_ih == NULL) { 399 aprint_error_dev(self, "couldn't establish interrupt"); 400 if (intrstr != NULL) 401 aprint_error(" at %s", intrstr); 402 aprint_error("\n"); 403 return; 404 } 405 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 406 407 /* init these pointers, so that tl_shutdown won't try to read them */ 408 sc->Rx_list = NULL; 409 sc->Tx_list = NULL; 410 411 /* allocate DMA-safe memory for control structs */ 412 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 413 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 414 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 415 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 416 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 417 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 418 return; 419 } 420 421 /* 422 * Initialize our media structures and probe the MII. 423 * 424 * Note that we don't care about the media instance. We 425 * are expecting to have multiple PHYs on the 10/100 cards, 426 * and on those cards we exclude the internal PHY from providing 427 * 10baseT. By ignoring the instance, it allows us to not have 428 * to specify it on the command line when switching media. 429 */ 430 sc->tl_mii.mii_ifp = ifp; 431 sc->tl_mii.mii_readreg = tl_mii_read; 432 sc->tl_mii.mii_writereg = tl_mii_write; 433 sc->tl_mii.mii_statchg = tl_statchg; 434 sc->tl_ec.ec_mii = &sc->tl_mii; 435 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 436 ether_mediastatus); 437 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 438 MII_OFFSET_ANY, 0); 439 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 440 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 441 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 442 } else 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = tl_ifioctl; 453 ifp->if_start = tl_ifstart; 454 ifp->if_watchdog = tl_ifwatchdog; 455 ifp->if_init = tl_init; 456 ifp->if_stop = tl_stop; 457 ifp->if_timer = 0; 458 IFQ_SET_READY(&ifp->if_snd); 459 if_attach(ifp); 460 if_deferred_start_init(ifp, NULL); 461 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 462 463 /* 464 * Add shutdown hook so that DMA is disabled prior to reboot. 465 * Not doing reboot before the driver initializes. 466 */ 467 if (pmf_device_register1(self, NULL, NULL, tl_shutdown)) 468 pmf_class_network_register(self, ifp); 469 else 470 aprint_error_dev(self, "couldn't establish power handler\n"); 471 472 rnd_attach_source(&sc->rnd_source, device_xname(self), 473 RND_TYPE_NET, RND_FLAG_DEFAULT); 474 } 475 476 static void 477 tl_reset(tl_softc_t *sc) 478 { 479 int i; 480 481 /* read stats */ 482 if (sc->tl_if.if_flags & IFF_RUNNING) { 483 callout_stop(&sc->tl_tick_ch); 484 tl_read_stats(sc); 485 } 486 /* Reset adapter */ 487 TL_HR_WRITE(sc, TL_HOST_CMD, 488 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 489 DELAY(100000); 490 /* Disable interrupts */ 491 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 492 /* setup aregs & hash */ 493 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 494 tl_intreg_write(sc, i, 0); 495 #ifdef TLDEBUG_ADDR 496 printf("Areg & hash registers: \n"); 497 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 498 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 499 #endif 500 /* Setup NetConfig */ 501 tl_intreg_write(sc, TL_INT_NetConfig, 502 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 503 /* Bsize: accept default */ 504 /* TX commit in Acommit: accept default */ 505 /* Load Ld_tmr and Ld_thr */ 506 /* Ld_tmr = 3 */ 507 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 508 /* Ld_thr = 0 */ 509 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 510 /* Unreset MII */ 511 netsio_set(sc, TL_NETSIO_NMRST); 512 DELAY(100000); 513 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 514 } 515 516 static bool 517 tl_shutdown(device_t self, int howto) 518 { 519 tl_softc_t *sc = device_private(self); 520 struct ifnet *ifp = &sc->tl_if; 521 522 tl_stop(ifp, 1); 523 524 return true; 525 } 526 527 static void 528 tl_stop(struct ifnet *ifp, int disable) 529 { 530 tl_softc_t *sc = ifp->if_softc; 531 struct Tx_list *Tx; 532 int i; 533 534 if ((ifp->if_flags & IFF_RUNNING) == 0) 535 return; 536 /* disable interrupts */ 537 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 538 /* stop TX and RX channels */ 539 TL_HR_WRITE(sc, TL_HOST_CMD, 540 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 541 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 542 DELAY(100000); 543 544 /* stop statistics reading loop, read stats */ 545 callout_stop(&sc->tl_tick_ch); 546 tl_read_stats(sc); 547 548 /* Down the MII. */ 549 mii_down(&sc->tl_mii); 550 551 /* deallocate memory allocations */ 552 if (sc->Rx_list) { 553 for (i = 0; i< TL_NBUF; i++) { 554 if (sc->Rx_list[i].m) { 555 bus_dmamap_unload(sc->tl_dmatag, 556 sc->Rx_list[i].m_dmamap); 557 m_freem(sc->Rx_list[i].m); 558 } 559 bus_dmamap_destroy(sc->tl_dmatag, 560 sc->Rx_list[i].m_dmamap); 561 sc->Rx_list[i].m = NULL; 562 } 563 free(sc->Rx_list, M_DEVBUF); 564 sc->Rx_list = NULL; 565 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 566 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 567 sc->hw_Rx_list = NULL; 568 while ((Tx = sc->active_Tx) != NULL) { 569 Tx->hw_list->stat = 0; 570 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 571 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 572 m_freem(Tx->m); 573 sc->active_Tx = Tx->next; 574 Tx->next = sc->Free_Tx; 575 sc->Free_Tx = Tx; 576 } 577 sc->last_Tx = NULL; 578 free(sc->Tx_list, M_DEVBUF); 579 sc->Tx_list = NULL; 580 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 581 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 582 sc->hw_Tx_list = NULL; 583 } 584 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 585 ifp->if_timer = 0; 586 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 587 } 588 589 static void 590 tl_restart(void *v) 591 { 592 593 tl_init(v); 594 } 595 596 static int 597 tl_init(struct ifnet *ifp) 598 { 599 tl_softc_t *sc = ifp->if_softc; 600 int i, s, error; 601 bus_size_t boundary; 602 prop_number_t prop_boundary; 603 const char *errstring; 604 char *nullbuf; 605 606 s = splnet(); 607 /* cancel any pending IO */ 608 tl_stop(ifp, 1); 609 tl_reset(sc); 610 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 611 splx(s); 612 return 0; 613 } 614 /* Set various register to reasonable value */ 615 /* setup NetCmd in promisc mode if needed */ 616 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 617 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 618 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 619 /* Max receive size : MCLBYTES */ 620 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 621 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 622 (MCLBYTES >> 8) & 0xff); 623 624 /* init MAC addr */ 625 for (i = 0; i < ETHER_ADDR_LEN; i++) 626 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 627 /* add multicast filters */ 628 tl_addr_filter(sc); 629 #ifdef TLDEBUG_ADDR 630 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 631 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 632 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 633 #endif 634 635 /* Pre-allocate receivers mbuf, make the lists */ 636 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 637 M_NOWAIT|M_ZERO); 638 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 639 M_NOWAIT|M_ZERO); 640 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 641 errstring = "out of memory for lists"; 642 error = ENOMEM; 643 goto bad; 644 } 645 646 /* 647 * Some boards (Set Engineering GFE) do not permit DMA transfers 648 * across page boundaries. 649 */ 650 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 651 "tl-dma-page-boundary"); 652 if (prop_boundary != NULL) { 653 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 654 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 655 } else { 656 boundary = 0; 657 } 658 659 error = bus_dmamap_create(sc->tl_dmatag, 660 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 661 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 662 &sc->Rx_dmamap); 663 if (error == 0) 664 error = bus_dmamap_create(sc->tl_dmatag, 665 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 666 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 667 BUS_DMA_WAITOK, &sc->Tx_dmamap); 668 if (error == 0) 669 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 670 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 671 &sc->null_dmamap); 672 if (error) { 673 errstring = "can't allocate DMA maps for lists"; 674 goto bad; 675 } 676 memset(sc->ctrl, 0, PAGE_SIZE); 677 sc->hw_Rx_list = (void *)sc->ctrl; 678 sc->hw_Tx_list = 679 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 680 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 681 sizeof(struct tl_Tx_list) * TL_NBUF; 682 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 683 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 684 BUS_DMA_WAITOK); 685 if (error == 0) 686 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 687 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 688 BUS_DMA_WAITOK); 689 if (error == 0) 690 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 691 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 692 if (error) { 693 errstring = "can't DMA map DMA memory for lists"; 694 goto bad; 695 } 696 for (i = 0; i < TL_NBUF; i++) { 697 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 698 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 699 &sc->Rx_list[i].m_dmamap); 700 if (error == 0) { 701 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 702 TL_NSEG, MCLBYTES, boundary, 703 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 704 &sc->Tx_list[i].m_dmamap); 705 } 706 if (error) { 707 errstring = "can't allocate DMA maps for mbufs"; 708 goto bad; 709 } 710 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 711 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 712 + sizeof(struct tl_Rx_list) * i; 713 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 714 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 715 + sizeof(struct tl_Tx_list) * i; 716 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 717 errstring = "out of mbuf for receive list"; 718 error = ENOMEM; 719 goto bad; 720 } 721 if (i > 0) { /* chain the list */ 722 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 723 sc->hw_Rx_list[i - 1].fwd = 724 htole32(sc->Rx_list[i].hw_listaddr); 725 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 726 } 727 } 728 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 729 sc->Rx_list[TL_NBUF - 1].next = NULL; 730 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 731 sc->Tx_list[TL_NBUF - 1].next = NULL; 732 733 sc->active_Rx = &sc->Rx_list[0]; 734 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 735 sc->active_Tx = sc->last_Tx = NULL; 736 sc->Free_Tx = &sc->Tx_list[0]; 737 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 738 sizeof(struct tl_Rx_list) * TL_NBUF, 739 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 740 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 741 sizeof(struct tl_Tx_list) * TL_NBUF, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 744 BUS_DMASYNC_PREWRITE); 745 746 /* set media */ 747 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 748 error = 0; 749 else if (error != 0) { 750 errstring = "could not set media"; 751 goto bad; 752 } 753 754 /* start ticks calls */ 755 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 756 /* write address of Rx list and enable interrupts */ 757 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 758 TL_HR_WRITE(sc, TL_HOST_CMD, 759 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 760 sc->tl_if.if_flags |= IFF_RUNNING; 761 sc->tl_if.if_flags &= ~IFF_OACTIVE; 762 splx(s); 763 return 0; 764 bad: 765 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 766 splx(s); 767 return error; 768 } 769 770 771 static uint32_t 772 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 773 { 774 775 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 776 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 777 } 778 779 static uint8_t 780 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 781 { 782 783 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 784 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 785 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 786 } 787 788 static void 789 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 790 { 791 792 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 793 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 794 } 795 796 static void 797 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 798 { 799 800 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 801 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 802 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 803 } 804 805 void 806 tl_mii_sync(struct tl_softc *sc) 807 { 808 int i; 809 810 netsio_clr(sc, TL_NETSIO_MTXEN); 811 for (i = 0; i < 32; i++) { 812 netsio_clr(sc, TL_NETSIO_MCLK); 813 netsio_set(sc, TL_NETSIO_MCLK); 814 } 815 } 816 817 void 818 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 819 { 820 int i; 821 822 netsio_set(sc, TL_NETSIO_MTXEN); 823 for (i = 1 << (nbits - 1); i; i = i >> 1) { 824 netsio_clr(sc, TL_NETSIO_MCLK); 825 netsio_read(sc, TL_NETSIO_MCLK); 826 if (data & i) 827 netsio_set(sc, TL_NETSIO_MDATA); 828 else 829 netsio_clr(sc, TL_NETSIO_MDATA); 830 netsio_set(sc, TL_NETSIO_MCLK); 831 netsio_read(sc, TL_NETSIO_MCLK); 832 } 833 } 834 835 int 836 tl_mii_read(device_t self, int phy, int reg) 837 { 838 struct tl_softc *sc = device_private(self); 839 int val = 0, i, err; 840 841 /* 842 * Read the PHY register by manually driving the MII control lines. 843 */ 844 845 tl_mii_sync(sc); 846 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 847 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 848 tl_mii_sendbits(sc, phy, 5); 849 tl_mii_sendbits(sc, reg, 5); 850 851 netsio_clr(sc, TL_NETSIO_MTXEN); 852 netsio_clr(sc, TL_NETSIO_MCLK); 853 netsio_set(sc, TL_NETSIO_MCLK); 854 netsio_clr(sc, TL_NETSIO_MCLK); 855 856 err = netsio_read(sc, TL_NETSIO_MDATA); 857 netsio_set(sc, TL_NETSIO_MCLK); 858 859 /* Even if an error occurs, must still clock out the cycle. */ 860 for (i = 0; i < 16; i++) { 861 val <<= 1; 862 netsio_clr(sc, TL_NETSIO_MCLK); 863 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 864 val |= 1; 865 netsio_set(sc, TL_NETSIO_MCLK); 866 } 867 netsio_clr(sc, TL_NETSIO_MCLK); 868 netsio_set(sc, TL_NETSIO_MCLK); 869 870 return err ? 0 : val; 871 } 872 873 void 874 tl_mii_write(device_t self, int phy, int reg, int val) 875 { 876 struct tl_softc *sc = device_private(self); 877 878 /* 879 * Write the PHY register by manually driving the MII control lines. 880 */ 881 882 tl_mii_sync(sc); 883 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 884 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 885 tl_mii_sendbits(sc, phy, 5); 886 tl_mii_sendbits(sc, reg, 5); 887 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 888 tl_mii_sendbits(sc, val, 16); 889 890 netsio_clr(sc, TL_NETSIO_MCLK); 891 netsio_set(sc, TL_NETSIO_MCLK); 892 } 893 894 void 895 tl_statchg(struct ifnet *ifp) 896 { 897 tl_softc_t *sc = ifp->if_softc; 898 uint32_t reg; 899 900 #ifdef TLDEBUG 901 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 902 #endif 903 904 /* 905 * We must keep the ThunderLAN and the PHY in sync as 906 * to the status of full-duplex! 907 */ 908 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 909 if (sc->tl_mii.mii_media_active & IFM_FDX) 910 reg |= TL_NETCOMMAND_DUPLEX; 911 else 912 reg &= ~TL_NETCOMMAND_DUPLEX; 913 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 914 } 915 916 /********** I2C glue **********/ 917 918 static int 919 tl_i2c_acquire_bus(void *cookie, int flags) 920 { 921 922 /* private bus */ 923 return 0; 924 } 925 926 static void 927 tl_i2c_release_bus(void *cookie, int flags) 928 { 929 930 /* private bus */ 931 } 932 933 static int 934 tl_i2c_send_start(void *cookie, int flags) 935 { 936 937 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 938 } 939 940 static int 941 tl_i2c_send_stop(void *cookie, int flags) 942 { 943 944 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 945 } 946 947 static int 948 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 949 { 950 951 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 952 } 953 954 static int 955 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 956 { 957 958 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 959 } 960 961 static int 962 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 963 { 964 965 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 966 } 967 968 /********** I2C bit-bang glue **********/ 969 970 static void 971 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 972 { 973 struct tl_softc *sc = cookie; 974 uint8_t reg; 975 976 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 977 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 978 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 979 } 980 981 static void 982 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 983 { 984 struct tl_softc *sc = cookie; 985 uint8_t reg; 986 987 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 988 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 989 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 990 } 991 992 static uint32_t 993 tl_i2cbb_read(void *cookie) 994 { 995 996 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 997 } 998 999 /********** End of I2C stuff **********/ 1000 1001 static int 1002 tl_intr(void *v) 1003 { 1004 tl_softc_t *sc = v; 1005 struct ifnet *ifp = &sc->tl_if; 1006 struct Rx_list *Rx; 1007 struct Tx_list *Tx; 1008 struct mbuf *m; 1009 uint32_t int_type, int_reg; 1010 int ack = 0; 1011 int size; 1012 1013 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1014 int_type = int_reg & TL_INTR_MASK; 1015 if (int_type == 0) 1016 return 0; 1017 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1018 printf("%s: interrupt type %x, intr_reg %x\n", 1019 device_xname(sc->sc_dev), int_type, int_reg); 1020 #endif 1021 /* disable interrupts */ 1022 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1023 switch(int_type & TL_INTR_MASK) { 1024 case TL_INTR_RxEOF: 1025 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1026 sizeof(struct tl_Rx_list) * TL_NBUF, 1027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1028 while(le32toh(sc->active_Rx->hw_list->stat) & 1029 TL_RX_CSTAT_CPLT) { 1030 /* dequeue and requeue at end of list */ 1031 ack++; 1032 Rx = sc->active_Rx; 1033 sc->active_Rx = Rx->next; 1034 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1035 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1036 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1037 m = Rx->m; 1038 size = le32toh(Rx->hw_list->stat) >> 16; 1039 #ifdef TLDEBUG_RX 1040 printf("%s: RX list complete, Rx %p, size=%d\n", 1041 __func__, Rx, size); 1042 #endif 1043 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1044 /* 1045 * No new mbuf, reuse the same. This means 1046 * that this packet 1047 * is lost 1048 */ 1049 m = NULL; 1050 #ifdef TL_PRIV_STATS 1051 sc->ierr_nomem++; 1052 #endif 1053 #ifdef TLDEBUG 1054 printf("%s: out of mbuf, lost input packet\n", 1055 device_xname(sc->sc_dev)); 1056 #endif 1057 } 1058 Rx->next = NULL; 1059 Rx->hw_list->fwd = 0; 1060 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1061 sc->last_Rx->next = Rx; 1062 sc->last_Rx = Rx; 1063 1064 /* deliver packet */ 1065 if (m) { 1066 if (size < sizeof(struct ether_header)) { 1067 m_freem(m); 1068 continue; 1069 } 1070 m_set_rcvif(m, ifp); 1071 m->m_pkthdr.len = m->m_len = size; 1072 #ifdef TLDEBUG_RX 1073 { 1074 struct ether_header *eh = 1075 mtod(m, struct ether_header *); 1076 printf("%s: Rx packet:\n", __func__); 1077 ether_printheader(eh); 1078 } 1079 #endif 1080 if_percpuq_enqueue(ifp->if_percpuq, m); 1081 } 1082 } 1083 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1084 sizeof(struct tl_Rx_list) * TL_NBUF, 1085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1086 #ifdef TLDEBUG_RX 1087 printf("TL_INTR_RxEOF: ack %d\n", ack); 1088 #else 1089 if (ack == 0) { 1090 printf("%s: EOF intr without anything to read !\n", 1091 device_xname(sc->sc_dev)); 1092 tl_reset(sc); 1093 /* schedule reinit of the board */ 1094 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1095 return 1; 1096 } 1097 #endif 1098 break; 1099 case TL_INTR_RxEOC: 1100 ack++; 1101 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1102 sizeof(struct tl_Rx_list) * TL_NBUF, 1103 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1104 #ifdef TLDEBUG_RX 1105 printf("TL_INTR_RxEOC: ack %d\n", ack); 1106 #endif 1107 #ifdef DIAGNOSTIC 1108 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1109 printf("%s: Rx EOC interrupt and active Tx list not " 1110 "cleared\n", device_xname(sc->sc_dev)); 1111 return 0; 1112 } else 1113 #endif 1114 { 1115 /* 1116 * write address of Rx list and send Rx GO command, ack 1117 * interrupt and enable interrupts in one command 1118 */ 1119 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1120 TL_HR_WRITE(sc, TL_HOST_CMD, 1121 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1122 HOST_CMD_ACK | HOST_CMD_IntOn); 1123 return 1; 1124 } 1125 case TL_INTR_TxEOF: 1126 case TL_INTR_TxEOC: 1127 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1128 sizeof(struct tl_Tx_list) * TL_NBUF, 1129 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1130 while ((Tx = sc->active_Tx) != NULL) { 1131 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1132 break; 1133 ack++; 1134 #ifdef TLDEBUG_TX 1135 printf("TL_INTR_TxEOC: list 0x%x done\n", 1136 (int)Tx->hw_listaddr); 1137 #endif 1138 Tx->hw_list->stat = 0; 1139 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1140 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1142 m_freem(Tx->m); 1143 Tx->m = NULL; 1144 sc->active_Tx = Tx->next; 1145 if (sc->active_Tx == NULL) 1146 sc->last_Tx = NULL; 1147 Tx->next = sc->Free_Tx; 1148 sc->Free_Tx = Tx; 1149 } 1150 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1151 sizeof(struct tl_Tx_list) * TL_NBUF, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 /* if this was an EOC, ACK immediatly */ 1154 if (ack) 1155 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1156 if (int_type == TL_INTR_TxEOC) { 1157 #ifdef TLDEBUG_TX 1158 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1159 ack); 1160 #endif 1161 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1162 HOST_CMD_ACK | HOST_CMD_IntOn); 1163 if (sc->active_Tx != NULL) { 1164 /* needs a Tx go command */ 1165 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1166 sc->active_Tx->hw_listaddr); 1167 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1168 } 1169 sc->tl_if.if_timer = 0; 1170 if_schedule_deferred_start(&sc->tl_if); 1171 return 1; 1172 } 1173 #ifdef TLDEBUG 1174 else { 1175 printf("TL_INTR_TxEOF: ack %d\n", ack); 1176 } 1177 #endif 1178 sc->tl_if.if_timer = 0; 1179 if_schedule_deferred_start(&sc->tl_if); 1180 break; 1181 case TL_INTR_Stat: 1182 ack++; 1183 #ifdef TLDEBUG 1184 printf("TL_INTR_Stat: ack %d\n", ack); 1185 #endif 1186 tl_read_stats(sc); 1187 break; 1188 case TL_INTR_Adc: 1189 if (int_reg & TL_INTVec_MASK) { 1190 /* adapter check conditions */ 1191 printf("%s: check condition, intvect=0x%x, " 1192 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1193 int_reg & TL_INTVec_MASK, 1194 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1195 tl_reset(sc); 1196 /* schedule reinit of the board */ 1197 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1198 return 1; 1199 } else { 1200 uint8_t netstat; 1201 /* Network status */ 1202 netstat = 1203 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1204 printf("%s: network status, NetSts=%x\n", 1205 device_xname(sc->sc_dev), netstat); 1206 /* Ack interrupts */ 1207 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1208 netstat); 1209 ack++; 1210 } 1211 break; 1212 default: 1213 printf("%s: unhandled interrupt code %x!\n", 1214 device_xname(sc->sc_dev), int_type); 1215 ack++; 1216 } 1217 1218 if (ack) { 1219 /* Ack the interrupt and enable interrupts */ 1220 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1221 HOST_CMD_IntOn); 1222 rnd_add_uint32(&sc->rnd_source, int_reg); 1223 return 1; 1224 } 1225 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1226 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1227 return 0; 1228 } 1229 1230 static int 1231 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1232 { 1233 struct tl_softc *sc = ifp->if_softc; 1234 int s, error; 1235 1236 s = splnet(); 1237 error = ether_ioctl(ifp, cmd, data); 1238 if (error == ENETRESET) { 1239 if (ifp->if_flags & IFF_RUNNING) 1240 tl_addr_filter(sc); 1241 error = 0; 1242 } 1243 splx(s); 1244 return error; 1245 } 1246 1247 static void 1248 tl_ifstart(struct ifnet *ifp) 1249 { 1250 tl_softc_t *sc = ifp->if_softc; 1251 struct mbuf *mb_head; 1252 struct Tx_list *Tx; 1253 int segment, size; 1254 int again, error; 1255 1256 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1257 return; 1258 txloop: 1259 /* If we don't have more space ... */ 1260 if (sc->Free_Tx == NULL) { 1261 #ifdef TLDEBUG 1262 printf("%s: No free TX list\n", __func__); 1263 #endif 1264 sc->tl_if.if_flags |= IFF_OACTIVE; 1265 return; 1266 } 1267 /* Grab a paquet for output */ 1268 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1269 if (mb_head == NULL) { 1270 #ifdef TLDEBUG_TX 1271 printf("%s: nothing to send\n", __func__); 1272 #endif 1273 return; 1274 } 1275 Tx = sc->Free_Tx; 1276 sc->Free_Tx = Tx->next; 1277 Tx->next = NULL; 1278 again = 0; 1279 /* 1280 * Go through each of the mbufs in the chain and initialize 1281 * the transmit list descriptors with the physical address 1282 * and size of the mbuf. 1283 */ 1284 tbdinit: 1285 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1286 Tx->m = mb_head; 1287 size = mb_head->m_pkthdr.len; 1288 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1289 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1290 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1291 struct mbuf *mn; 1292 /* 1293 * We ran out of segments, or we will. We have to recopy this 1294 * mbuf chain first. 1295 */ 1296 if (error == 0) 1297 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1298 if (again) { 1299 /* already copyed, can't do much more */ 1300 m_freem(mb_head); 1301 goto bad; 1302 } 1303 again = 1; 1304 #ifdef TLDEBUG_TX 1305 printf("%s: need to copy mbuf\n", __func__); 1306 #endif 1307 #ifdef TL_PRIV_STATS 1308 sc->oerr_mcopy++; 1309 #endif 1310 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1311 if (mn == NULL) { 1312 m_freem(mb_head); 1313 goto bad; 1314 } 1315 if (mb_head->m_pkthdr.len > MHLEN) { 1316 MCLGET(mn, M_DONTWAIT); 1317 if ((mn->m_flags & M_EXT) == 0) { 1318 m_freem(mn); 1319 m_freem(mb_head); 1320 goto bad; 1321 } 1322 } 1323 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1324 mtod(mn, void *)); 1325 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1326 m_freem(mb_head); 1327 mb_head = mn; 1328 goto tbdinit; 1329 } 1330 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1331 Tx->hw_list->seg[segment].data_addr = 1332 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1333 Tx->hw_list->seg[segment].data_count = 1334 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1335 } 1336 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1337 Tx->m_dmamap->dm_mapsize, 1338 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1339 /* We are at end of mbuf chain. check the size and 1340 * see if it needs to be extended 1341 */ 1342 if (size < ETHER_MIN_TX) { 1343 #ifdef DIAGNOSTIC 1344 if (segment >= TL_NSEG) { 1345 panic("%s: to much segmets (%d)", __func__, segment); 1346 } 1347 #endif 1348 /* 1349 * add the nullbuf in the seg 1350 */ 1351 Tx->hw_list->seg[segment].data_count = 1352 htole32(ETHER_MIN_TX - size); 1353 Tx->hw_list->seg[segment].data_addr = 1354 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1355 size = ETHER_MIN_TX; 1356 segment++; 1357 } 1358 /* The list is done, finish the list init */ 1359 Tx->hw_list->seg[segment - 1].data_count |= 1360 htole32(TL_LAST_SEG); 1361 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1362 #ifdef TLDEBUG_TX 1363 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1364 le32toh(Tx->hw_list->stat)); 1365 #if 0 1366 for (segment = 0; segment < TL_NSEG; segment++) { 1367 printf(" seg %d addr 0x%x len 0x%x\n", 1368 segment, 1369 le32toh(Tx->hw_list->seg[segment].data_addr), 1370 le32toh(Tx->hw_list->seg[segment].data_count)); 1371 } 1372 #endif 1373 #endif 1374 if (sc->active_Tx == NULL) { 1375 sc->active_Tx = sc->last_Tx = Tx; 1376 #ifdef TLDEBUG_TX 1377 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1378 (int)Tx->hw_listaddr); 1379 #endif 1380 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1381 sizeof(struct tl_Tx_list) * TL_NBUF, 1382 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1383 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1384 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1385 } else { 1386 #ifdef TLDEBUG_TX 1387 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1388 (int)Tx->hw_listaddr); 1389 #endif 1390 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1391 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1392 sizeof(struct tl_Tx_list) * TL_NBUF, 1393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1394 sc->last_Tx->next = Tx; 1395 sc->last_Tx = Tx; 1396 #ifdef DIAGNOSTIC 1397 if (sc->last_Tx->hw_list->fwd & 0x7) 1398 printf("%s: physical addr 0x%x of list not properly " 1399 "aligned\n", 1400 device_xname(sc->sc_dev), 1401 sc->last_Rx->hw_list->fwd); 1402 #endif 1403 } 1404 /* Pass packet to bpf if there is a listener */ 1405 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1406 /* 1407 * Set a 5 second timer just in case we don't hear from the card again. 1408 */ 1409 ifp->if_timer = 5; 1410 goto txloop; 1411 bad: 1412 #ifdef TLDEBUG 1413 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1414 #endif 1415 Tx->next = sc->Free_Tx; 1416 sc->Free_Tx = Tx; 1417 } 1418 1419 static void 1420 tl_ifwatchdog(struct ifnet *ifp) 1421 { 1422 tl_softc_t *sc = ifp->if_softc; 1423 1424 if ((ifp->if_flags & IFF_RUNNING) == 0) 1425 return; 1426 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1427 ifp->if_oerrors++; 1428 tl_init(ifp); 1429 } 1430 1431 static int 1432 tl_mediachange(struct ifnet *ifp) 1433 { 1434 1435 if (ifp->if_flags & IFF_UP) 1436 tl_init(ifp); 1437 return 0; 1438 } 1439 1440 static int 1441 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1442 { 1443 struct mbuf *m; 1444 int error; 1445 1446 MGETHDR(m, M_DONTWAIT, MT_DATA); 1447 if (m != NULL) { 1448 MCLGET(m, M_DONTWAIT); 1449 if ((m->m_flags & M_EXT) == 0) { 1450 m_freem(m); 1451 if (oldm == NULL) 1452 return 0; 1453 m = oldm; 1454 m->m_data = m->m_ext.ext_buf; 1455 } 1456 } else { 1457 if (oldm == NULL) 1458 return 0; 1459 m = oldm; 1460 m->m_data = m->m_ext.ext_buf; 1461 } 1462 1463 /* (re)init the Rx_list struct */ 1464 1465 Rx->m = m; 1466 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1467 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1468 printf("%s: bus_dmamap_load() failed (error %d) for " 1469 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1470 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1471 m_freem(m); 1472 Rx->m = NULL; 1473 return 0; 1474 } 1475 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1476 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1477 /* 1478 * Move the data pointer up so that the incoming data packet 1479 * will be 32-bit aligned. 1480 */ 1481 m->m_data += 2; 1482 1483 Rx->hw_list->stat = 1484 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1485 Rx->hw_list->seg.data_count = 1486 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1487 Rx->hw_list->seg.data_addr = 1488 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1489 return (m != oldm); 1490 } 1491 1492 static void 1493 tl_ticks(void *v) 1494 { 1495 tl_softc_t *sc = v; 1496 1497 tl_read_stats(sc); 1498 1499 /* Tick the MII. */ 1500 mii_tick(&sc->tl_mii); 1501 1502 /* read statistics every seconds */ 1503 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1504 } 1505 1506 static void 1507 tl_read_stats(tl_softc_t *sc) 1508 { 1509 uint32_t reg; 1510 int ierr_overr; 1511 int ierr_code; 1512 int ierr_crc; 1513 int oerr_underr; 1514 int oerr_deferred; 1515 int oerr_coll; 1516 int oerr_multicoll; 1517 int oerr_exesscoll; 1518 int oerr_latecoll; 1519 int oerr_carrloss; 1520 struct ifnet *ifp = &sc->tl_if; 1521 1522 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1523 ifp->if_opackets += reg & 0x00ffffff; 1524 oerr_underr = reg >> 24; 1525 1526 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1527 ifp->if_ipackets += reg & 0x00ffffff; 1528 ierr_overr = reg >> 24; 1529 1530 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1531 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1532 ierr_code = (reg & TL_FERR_CODE) >> 24; 1533 oerr_deferred = (reg & TL_FERR_DEF); 1534 1535 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1536 oerr_multicoll = (reg & TL_COL_MULTI); 1537 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1538 1539 reg = tl_intreg_read(sc, TL_INT_LERR); 1540 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1541 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1542 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1543 1544 1545 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1546 oerr_carrloss; 1547 ifp->if_collisions += oerr_coll + oerr_multicoll; 1548 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1549 1550 if (ierr_overr) 1551 printf("%s: receiver ring buffer overrun\n", 1552 device_xname(sc->sc_dev)); 1553 if (oerr_underr) 1554 printf("%s: transmit buffer underrun\n", 1555 device_xname(sc->sc_dev)); 1556 #ifdef TL_PRIV_STATS 1557 sc->ierr_overr += ierr_overr; 1558 sc->ierr_code += ierr_code; 1559 sc->ierr_crc += ierr_crc; 1560 sc->oerr_underr += oerr_underr; 1561 sc->oerr_deferred += oerr_deferred; 1562 sc->oerr_coll += oerr_coll; 1563 sc->oerr_multicoll += oerr_multicoll; 1564 sc->oerr_exesscoll += oerr_exesscoll; 1565 sc->oerr_latecoll += oerr_latecoll; 1566 sc->oerr_carrloss += oerr_carrloss; 1567 #endif 1568 } 1569 1570 static void 1571 tl_addr_filter(tl_softc_t *sc) 1572 { 1573 struct ether_multistep step; 1574 struct ether_multi *enm; 1575 uint32_t hash[2] = {0, 0}; 1576 int i; 1577 1578 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1579 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1580 while (enm != NULL) { 1581 #ifdef TLDEBUG 1582 printf("%s: addrs %s %s\n", __func__, 1583 ether_sprintf(enm->enm_addrlo), 1584 ether_sprintf(enm->enm_addrhi)); 1585 #endif 1586 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1587 i = tl_multicast_hash(enm->enm_addrlo); 1588 hash[i / 32] |= 1 << (i%32); 1589 } else { 1590 hash[0] = hash[1] = 0xffffffff; 1591 sc->tl_if.if_flags |= IFF_ALLMULTI; 1592 break; 1593 } 1594 ETHER_NEXT_MULTI(step, enm); 1595 } 1596 #ifdef TLDEBUG 1597 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1598 #endif 1599 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1600 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1601 } 1602 1603 static int 1604 tl_multicast_hash(uint8_t *a) 1605 { 1606 int hash; 1607 1608 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1609 #define xor8(a,b,c,d,e,f,g,h) \ 1610 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1611 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1612 1613 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1614 DA(a,36), DA(a,42)); 1615 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1616 DA(a,37), DA(a,43)) << 1; 1617 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1618 DA(a,38), DA(a,44)) << 2; 1619 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1620 DA(a,39), DA(a,45)) << 3; 1621 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1622 DA(a,40), DA(a,46)) << 4; 1623 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1624 DA(a,41), DA(a,47)) << 5; 1625 1626 return hash; 1627 } 1628 1629 #if defined(TLDEBUG_RX) 1630 void 1631 ether_printheader(struct ether_header *eh) 1632 { 1633 uint8_t *c = (uint8_t *)eh; 1634 int i; 1635 1636 for (i = 0; i < sizeof(struct ether_header); i++) 1637 printf("%02x ", (u_int)c[i]); 1638 printf("\n"); 1639 } 1640 #endif 1641
Indexes created Fri Sep 26 20:09:58 GMT 2025