if_tl.c revision 1.11
1 /* $NetBSD: if_tl.c,v 1.11 1998/06/08 06:55:56 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include "bpfilter.h" 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <vm/vm.h> 84 #include <vm/vm_param.h> 85 #include <vm/vm_kern.h> 86 87 #if defined(__NetBSD__) 88 #include <net/if_ether.h> 89 #if defined(INET) 90 #include <netinet/if_inarp.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 #include <dev/i2c/i2c_bus.h> 100 #include <dev/i2c/i2c_eeprom.h> 101 #include <dev/mii/mii_adapter.h> 102 #include <dev/mii/mii_adapters_id.h> 103 #include <dev/pci/if_tlregs.h> 104 #endif /* __NetBSD__ */ 105 106 /* number of transmit/receive buffers */ 107 #ifndef TL_NBUF 108 #define TL_NBUF 10 109 #endif 110 111 /* number of seconds the link can be idle */ 112 #ifndef TL_IDLETIME 113 #define TL_IDLETIME 10 114 #endif 115 116 struct tl_softc { 117 struct device sc_dev; /* base device */ 118 bus_space_tag_t tl_bustag; 119 bus_space_handle_t tl_bushandle; /* CSR region handle */ 120 void* tl_ih; 121 struct ethercom tl_ec; 122 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 123 struct ifmedia tl_ifmedia; 124 u_int16_t tl_flags; 125 #define TL_IFACT 0x0001 /* chip has interface activity */ 126 u_int8_t tl_lasttx; /* we were without input this many seconds */ 127 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 128 mii_data_t mii; /* mii bus */ 129 struct Rx_list *Rx_list; /* Receive and transmit lists */ 130 struct Tx_list *Tx_list; 131 struct Rx_list *active_Rx, *last_Rx; 132 struct Tx_list *active_Tx, *last_Tx; 133 struct Tx_list *Free_Tx; 134 int opkt; /* used to detect link up/down for AUI/BNC */ 135 int stats_exesscoll; /* idem */ 136 #ifdef TL_PRIV_STATS 137 int ierr_overr; 138 int ierr_code; 139 int ierr_crc; 140 int ierr_nomem; 141 int oerr_underr; 142 int oerr_deffered; 143 int oerr_coll; 144 int oerr_multicoll; 145 int oerr_latecoll; 146 int oerr_exesscoll; 147 int oerr_carrloss; 148 int oerr_mcopy; 149 #endif 150 }; 151 #define tl_if tl_ec.ec_if 152 #define tl_bpf tl_if.if_bpf 153 154 typedef struct tl_softc tl_softc_t; 155 typedef u_long ioctl_cmd_t; 156 157 #define TL_HR_READ(sc, reg) \ 158 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 159 #define TL_HR_READ_BYTE(sc, reg) \ 160 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 161 #define TL_HR_WRITE(sc, reg, data) \ 162 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 163 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 164 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 165 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 166 167 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 168 static void tl_pci_attach __P((struct device *, struct device *, void *)); 169 static int tl_intr __P((void *)); 170 171 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 172 static int tl_mediachange __P((struct ifnet *)); 173 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 174 static void tl_ifwatchdog __P((struct ifnet *)); 175 static void tl_shutdown __P((void*)); 176 177 static void tl_ifstart __P((struct ifnet *)); 178 static void tl_reset __P((tl_softc_t*)); 179 static int tl_init __P((tl_softc_t*)); 180 static void tl_restart __P((void *)); 181 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 182 static void tl_read_stats __P((tl_softc_t*)); 183 static void tl_ticks __P((void*)); 184 static int tl_multicast_hash __P((u_int8_t*)); 185 static void tl_addr_filter __P((tl_softc_t*)); 186 187 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 188 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 189 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 190 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 191 192 193 #if defined(TLDEBUG_RX) 194 static void ether_printheader __P((struct ether_header*)); 195 #endif 196 197 void tl_mii_set __P((void*, u_int8_t)); 198 void tl_mii_clr __P((void*, u_int8_t)); 199 int tl_mii_read __P((void*, u_int8_t)); 200 201 void tl_i2c_set __P((void*, u_int8_t)); 202 void tl_i2c_clr __P((void*, u_int8_t)); 203 int tl_i2c_read __P((void*, u_int8_t)); 204 205 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 206 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 207 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 208 static __inline void netsio_clr(sc, bits) 209 tl_softc_t* sc; 210 u_int8_t bits; 211 { 212 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 213 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 214 } 215 static __inline void netsio_set(sc, bits) 216 tl_softc_t* sc; 217 u_int8_t bits; 218 { 219 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 220 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 221 } 222 static __inline u_int8_t netsio_read(sc, bits) 223 tl_softc_t* sc; 224 u_int8_t bits; 225 { 226 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 227 } 228 229 struct cfattach tl_ca = { 230 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 231 }; 232 233 struct tl_product_desc { 234 u_int32_t tp_product; 235 u_int32_t tp_adapter; 236 int tp_flags; 237 const char *tp_desc; 238 }; 239 240 /* tp_flags */ 241 #define TPF_BROKEN_MEM 0x00000001 /* memory-mapped access is broken */ 242 243 const struct tl_product_desc tl_compaq_products[] = { 244 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 245 0, "Compaq Netelligent 10/100 TX" }, 246 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 247 0, "Compaq Netelligent 10 T" }, 248 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 249 0, "Compaq Integrated NetFlex 3/P" }, 250 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 251 0, "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 252 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 253 0, "Compaq Dual Port Netelligent 10/100 TX" }, 254 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 255 0, "Compaq Deskpro 4000 5233MMX" }, 256 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 257 0, "Compaq NetFlex 3/P w/ BNC" }, 258 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 259 0, "Compaq NetFlex 3/P" }, 260 { 0, 0, NULL }, 261 }; 262 263 const struct tl_product_desc tl_ti_products[] = { 264 /* 265 * Built-in Ethernet on the TI TravelMate 5000 266 * docking station; better product description? 267 * XXX Seems to have broken memory-mapped access. 268 */ 269 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 270 TPF_BROKEN_MEM, "Texas Instruments ThunderLAN" }, 271 { 0, 0, NULL }, 272 }; 273 274 struct tl_vendor_desc { 275 u_int32_t tv_vendor; 276 const struct tl_product_desc *tv_products; 277 }; 278 279 const struct tl_vendor_desc tl_vendors[] = { 280 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 281 { PCI_VENDOR_TI, tl_ti_products }, 282 { 0, NULL }, 283 }; 284 285 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 286 287 const struct tl_product_desc * 288 tl_lookup_product(id) 289 u_int32_t id; 290 { 291 const struct tl_product_desc *tp; 292 const struct tl_vendor_desc *tv; 293 294 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 295 if (PCI_VENDOR(id) == tv->tv_vendor) 296 break; 297 298 if ((tp = tv->tv_products) == NULL) 299 return (NULL); 300 301 for (; tp->tp_desc != NULL; tp++) 302 if (PCI_PRODUCT(id) == tp->tp_product) 303 break; 304 305 if (tp->tp_desc == NULL) 306 return (NULL); 307 308 return (tp); 309 } 310 311 static char *nullbuf = NULL; 312 313 static int 314 tl_pci_match(parent, match, aux) 315 struct device *parent; 316 struct cfdata *match; 317 void *aux; 318 { 319 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 320 321 if (tl_lookup_product(pa->pa_id) != NULL) 322 return (1); 323 324 return (0); 325 } 326 327 static void 328 tl_pci_attach(parent, self, aux) 329 struct device * parent; 330 struct device * self; 331 void * aux; 332 { 333 tl_softc_t *sc = (tl_softc_t *)self; 334 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 335 const struct tl_product_desc *tp; 336 struct ifnet * const ifp = &sc->tl_if; 337 bus_space_tag_t iot, memt; 338 bus_space_handle_t ioh, memh; 339 pci_intr_handle_t intrhandle; 340 const char *intrstr; 341 int i, tmp, ioh_valid, memh_valid; 342 pcireg_t csr; 343 344 printf("\n"); 345 346 tp = tl_lookup_product(pa->pa_id); 347 if (tp == NULL) 348 panic("tl_pci_attach: impossible"); 349 350 /* Map the card space. */ 351 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 352 &iot, &ioh, NULL, NULL) == 0); 353 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 354 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 355 0, &memt, &memh, NULL, NULL) == 0); 356 357 if (memh_valid && (tp->tp_flags & TPF_BROKEN_MEM) == 0) { 358 sc->tl_bustag = memt; 359 sc->tl_bushandle = memh; 360 } else if (ioh_valid) { 361 sc->tl_bustag = iot; 362 sc->tl_bushandle = ioh; 363 } else { 364 printf("%s: unable to map device registers\n", 365 sc->sc_dev.dv_xname); 366 return; 367 } 368 369 /* Enable the device. */ 370 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 371 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 372 csr | PCI_COMMAND_MASTER_ENABLE); 373 374 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 375 sc->mii.adapter_id = tp->tp_adapter; 376 377 tl_reset(sc); 378 379 /* fill in the i2c struct */ 380 sc->i2cbus.adapter_softc = sc; 381 sc->i2cbus.set_bit = tl_i2c_set; 382 sc->i2cbus.clr_bit = tl_i2c_clr; 383 sc->i2cbus.read_bit = tl_i2c_read; 384 385 #ifdef TLDEBUG 386 printf("default values of INTreg: 0x%x\n", 387 tl_intreg_read(sc, TL_INT_Defaults)); 388 #endif 389 390 /* read mac addr */ 391 for (i=0; i<ETHER_ADDR_LEN; i++) { 392 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 393 if (tmp < 0) { 394 printf("%s: error reading Ethernet adress\n", 395 sc->sc_dev.dv_xname); 396 return; 397 } else { 398 sc->tl_enaddr[i] = tmp; 399 } 400 } 401 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 402 ether_sprintf(sc->tl_enaddr)); 403 404 /* Map and establish interrupts */ 405 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 406 pa->pa_intrline, &intrhandle)) { 407 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 408 return; 409 } 410 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 411 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 412 tl_intr, sc); 413 if (sc->tl_ih == NULL) { 414 printf("%s: couldn't establish interrupt", 415 sc->sc_dev.dv_xname); 416 if (intrstr != NULL) 417 printf(" at %s", intrstr); 418 printf("\n"); 419 return; 420 } 421 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 422 423 /* 424 * Add shutdown hook so that DMA is disabled prior to reboot. Not 425 * doing do could allow DMA to corrupt kernel memory during the 426 * reboot before the driver initializes. 427 */ 428 (void) shutdownhook_establish(tl_shutdown, sc); 429 430 sc->mii.adapter_softc = sc; 431 sc->mii.mii_setbit = tl_mii_set; 432 sc->mii.mii_clrbit = tl_mii_clr; 433 sc->mii.mii_readbit = tl_mii_read; 434 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 435 sc->mii.mii_writereg = NULL; 436 if (config_found(self, (void*)&sc->mii, mii_adapter_print) == NULL) { 437 return; 438 } 439 440 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 441 mii_media_add(&sc->tl_ifmedia, &sc->mii); 442 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 443 444 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 445 sc->tl_if.if_softc = sc; 446 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 447 ifp->if_ioctl = tl_ifioctl; 448 ifp->if_start = tl_ifstart; 449 ifp->if_watchdog = tl_ifwatchdog; 450 ifp->if_timer = 0; 451 if_attach(ifp); 452 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 453 #if NBPFILTER > 0 454 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 455 sizeof(struct ether_header)); 456 #endif 457 sc->mii.mii_media_active = IFM_NONE; 458 } 459 460 static void 461 tl_reset(sc) 462 tl_softc_t *sc; 463 { 464 int i; 465 466 /* read stats */ 467 if (sc->tl_if.if_flags & IFF_RUNNING) { 468 untimeout(tl_ticks, sc); 469 tl_read_stats(sc); 470 } 471 /* Reset adapter */ 472 TL_HR_WRITE(sc, TL_HOST_CMD, 473 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 474 DELAY(100000); 475 /* Disable interrupts */ 476 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 477 /* setup aregs & hash */ 478 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 479 tl_intreg_write(sc, i, 0); 480 #ifdef TLDEBUG_ADDR 481 printf("Areg & hash registers: \n"); 482 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 483 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 484 #endif 485 /* Setup NetConfig */ 486 tl_intreg_write(sc, TL_INT_NetConfig, 487 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 488 /* Bsize: accept default */ 489 /* TX commit in Acommit: accept default */ 490 /* Load Ld_tmr and Ld_thr */ 491 /* Ld_tmr = 3 */ 492 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 493 /* Ld_thr = 0 */ 494 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 495 /* Unreset MII */ 496 netsio_set(sc, TL_NETSIO_NMRST); 497 DELAY(100000); 498 sc->mii.mii_media_status &= ~IFM_ACTIVE; 499 sc->tl_flags = 0; 500 sc->opkt = 0; 501 sc->stats_exesscoll = 0; 502 } 503 504 static void tl_shutdown(v) 505 void *v; 506 { 507 tl_softc_t *sc = v; 508 struct Tx_list *Tx; 509 int i; 510 511 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 512 return; 513 /* disable interrupts */ 514 TL_HR_WRITE(sc, TL_HOST_CMD, 515 HOST_CMD_IntOff); 516 /* stop TX and RX channels */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 518 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 519 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 520 DELAY(100000); 521 522 /* stop statistics reading loop, read stats */ 523 untimeout(tl_ticks, sc); 524 tl_read_stats(sc); 525 526 /* deallocate memory allocations */ 527 for (i=0; i< TL_NBUF; i++) { 528 if (sc->Rx_list[i].m) 529 m_freem(sc->Rx_list[i].m); 530 sc->Rx_list[i].m = NULL; 531 } 532 free(sc->Rx_list, M_DEVBUF); 533 sc->Rx_list = NULL; 534 while ((Tx = sc->active_Tx) != NULL) { 535 Tx->hw_list.stat = 0; 536 m_freem(Tx->m); 537 sc->active_Tx = Tx->next; 538 Tx->next = sc->Free_Tx; 539 sc->Free_Tx = Tx; 540 } 541 sc->last_Tx = NULL; 542 free(sc->Tx_list, M_DEVBUF); 543 sc->Tx_list = NULL; 544 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 545 sc->mii.mii_media_status &= ~IFM_ACTIVE; 546 sc->tl_flags = 0; 547 } 548 549 static void tl_restart(v) 550 void *v; 551 { 552 tl_init(v); 553 } 554 555 static int tl_init(sc) 556 tl_softc_t *sc; 557 { 558 struct ifnet *ifp = &sc->tl_if; 559 int i, s; 560 561 s = splimp(); 562 /* cancel any pending IO */ 563 tl_shutdown(sc); 564 tl_reset(sc); 565 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 566 splx(s); 567 return 0; 568 } 569 /* Set various register to reasonable value */ 570 /* setup NetCmd in promisc mode if needed */ 571 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 572 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 573 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 574 /* Max receive size : MCLBYTES */ 575 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 576 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 577 (MCLBYTES >> 8) & 0xff); 578 579 /* init MAC addr */ 580 for (i = 0; i < ETHER_ADDR_LEN; i++) 581 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 582 /* add multicast filters */ 583 tl_addr_filter(sc); 584 #ifdef TLDEBUG_ADDR 585 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 586 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 587 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 588 #endif 589 590 /* Pre-allocate receivers mbuf, make the lists */ 591 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 592 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 593 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 594 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 595 sc->tl_if.if_flags &= ~IFF_UP; 596 splx(s); 597 return ENOMEM; 598 } 599 for (i=0; i< TL_NBUF; i++) { 600 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 601 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 602 sc->tl_if.if_flags &= ~IFF_UP; 603 splx(s); 604 return ENOMEM; 605 } 606 if (i > 0) { /* chain the list */ 607 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 608 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 609 #ifdef DIAGNOSTIC 610 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 611 printf("%s: physical addr 0x%x of list not properly aligned\n", 612 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 613 #endif 614 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 615 } 616 } 617 sc->Rx_list[TL_NBUF-1].next = NULL; 618 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 619 sc->Tx_list[TL_NBUF-1].next = NULL; 620 621 sc->active_Rx = &sc->Rx_list[0]; 622 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 623 sc->active_Tx = sc->last_Tx = NULL; 624 sc->Free_Tx = &sc->Tx_list[0]; 625 626 if (nullbuf == NULL) 627 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 628 if (nullbuf == NULL) { 629 printf("%s: can't allocate space for pad buffer\n", 630 sc->sc_dev.dv_xname); 631 sc->tl_if.if_flags &= ~IFF_UP; 632 splx(s); 633 return ENOMEM; 634 } 635 bzero(nullbuf, ETHER_MIN_TX); 636 637 /* set media if needed */ 638 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 639 mii_mediachg(&sc->mii); 640 } 641 642 /* start ticks calls */ 643 timeout(tl_ticks, sc, hz); 644 /* write adress of Rx list and enable interrupts */ 645 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 646 TL_HR_WRITE(sc, TL_HOST_CMD, 647 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 648 sc->tl_if.if_flags |= IFF_RUNNING; 649 sc->tl_if.if_flags &= ~IFF_OACTIVE; 650 return 0; 651 } 652 653 654 static u_int32_t 655 tl_intreg_read(sc, reg) 656 tl_softc_t *sc; 657 u_int32_t reg; 658 { 659 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 660 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 661 } 662 663 static u_int8_t 664 tl_intreg_read_byte(sc, reg) 665 tl_softc_t *sc; 666 u_int32_t reg; 667 { 668 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 669 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 670 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 671 } 672 673 static void 674 tl_intreg_write(sc, reg, val) 675 tl_softc_t *sc; 676 u_int32_t reg; 677 u_int32_t val; 678 { 679 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 680 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 681 } 682 683 static void 684 tl_intreg_write_byte(sc, reg, val) 685 tl_softc_t *sc; 686 u_int32_t reg; 687 u_int8_t val; 688 { 689 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 690 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 691 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 692 } 693 694 void tl_mii_set(v, bit) 695 void *v; 696 u_int8_t bit; 697 { 698 tl_softc_t *sc = v; 699 700 switch (bit) { 701 case MII_DATA: 702 netsio_set(sc, TL_NETSIO_MDATA); 703 break; 704 case MII_CLOCK: 705 netsio_set(sc, TL_NETSIO_MCLK); 706 break; 707 case MII_TXEN: 708 netsio_set(sc, TL_NETSIO_MTXEN); 709 break; 710 default: 711 printf("tl_mii_set: unknown bit %d\n", bit); 712 } 713 } 714 715 void tl_mii_clr(v, bit) 716 void *v; 717 u_int8_t bit; 718 { 719 tl_softc_t *sc = v; 720 721 switch (bit) { 722 case MII_DATA: 723 netsio_clr(sc, TL_NETSIO_MDATA); 724 break; 725 case MII_CLOCK: 726 netsio_clr(sc, TL_NETSIO_MCLK); 727 break; 728 case MII_TXEN: 729 netsio_clr(sc, TL_NETSIO_MTXEN); 730 break; 731 default: 732 printf("tl_mii_clr: unknown bit %d\n", bit); 733 } 734 return; 735 } 736 737 int tl_mii_read(v, bit) 738 void *v; 739 u_int8_t bit; 740 { 741 tl_softc_t *sc = v; 742 743 switch (bit) { 744 case MII_DATA: 745 return netsio_read(sc, TL_NETSIO_MDATA); 746 break; 747 case MII_CLOCK: 748 return netsio_read(sc, TL_NETSIO_MCLK); 749 break; 750 case MII_TXEN: 751 return netsio_read(sc, TL_NETSIO_MTXEN); 752 break; 753 default: 754 printf("tl_mii_read: unknown bit %d\n", bit); 755 return -1; 756 } 757 } 758 759 void tl_i2c_set(v, bit) 760 void *v; 761 u_int8_t bit; 762 { 763 tl_softc_t *sc = v; 764 765 switch (bit) { 766 case I2C_DATA: 767 netsio_set(sc, TL_NETSIO_EDATA); 768 break; 769 case I2C_CLOCK: 770 netsio_set(sc, TL_NETSIO_ECLOCK); 771 break; 772 case I2C_TXEN: 773 netsio_set(sc, TL_NETSIO_ETXEN); 774 break; 775 default: 776 printf("tl_i2c_set: unknown bit %d\n", bit); 777 } 778 return; 779 } 780 781 void tl_i2c_clr(v, bit) 782 void *v; 783 u_int8_t bit; 784 { 785 tl_softc_t *sc = v; 786 787 switch (bit) { 788 case I2C_DATA: 789 netsio_clr(sc, TL_NETSIO_EDATA); 790 break; 791 case I2C_CLOCK: 792 netsio_clr(sc, TL_NETSIO_ECLOCK); 793 break; 794 case I2C_TXEN: 795 netsio_clr(sc, TL_NETSIO_ETXEN); 796 break; 797 default: 798 printf("tl_i2c_clr: unknown bit %d\n", bit); 799 } 800 return; 801 } 802 803 int tl_i2c_read(v, bit) 804 void *v; 805 u_int8_t bit; 806 { 807 tl_softc_t *sc = v; 808 809 switch (bit) { 810 case I2C_DATA: 811 return netsio_read(sc, TL_NETSIO_EDATA); 812 break; 813 case I2C_CLOCK: 814 return netsio_read(sc, TL_NETSIO_ECLOCK); 815 break; 816 case I2C_TXEN: 817 return netsio_read(sc, TL_NETSIO_ETXEN); 818 break; 819 default: 820 printf("tl_i2c_read: unknown bit %d\n", bit); 821 return -1; 822 } 823 } 824 825 static int 826 tl_intr(v) 827 void *v; 828 { 829 tl_softc_t *sc = v; 830 struct ifnet *ifp = &sc->tl_if; 831 struct Rx_list *Rx; 832 struct Tx_list *Tx; 833 struct mbuf *m; 834 u_int32_t int_type, int_reg; 835 int ack = 0; 836 int size; 837 838 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 839 int_type = int_reg & TL_INTR_MASK; 840 if (int_type == 0) 841 return 0; 842 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 843 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 844 int_type, int_reg); 845 #endif 846 /* disable interrupts */ 847 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 848 switch(int_type & TL_INTR_MASK) { 849 case TL_INTR_RxEOF: 850 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 851 /* dequeue and requeue at end of list */ 852 ack++; 853 Rx = sc->active_Rx; 854 sc->active_Rx = Rx->next; 855 m = Rx->m; 856 size = Rx->hw_list.stat >> 16; 857 #ifdef TLDEBUG_RX 858 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 859 #endif 860 if (tl_add_RxBuff(Rx, m ) == 0) { 861 /* No new mbuf, reuse the same. This means that this packet 862 is lost */ 863 m = NULL; 864 #ifdef TL_PRIV_STATS 865 sc->ierr_nomem++; 866 #endif 867 #ifdef TLDEBUG 868 printf("%s: out of mbuf, lost input packet\n", 869 sc->sc_dev.dv_xname); 870 #endif 871 } 872 Rx->next = NULL; 873 Rx->hw_list.fwd = 0; 874 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 875 #ifdef DIAGNOSTIC 876 if (sc->last_Rx->hw_list.fwd & 0x7) 877 printf("%s: physical addr 0x%x of list not properly aligned\n", 878 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 879 #endif 880 sc->last_Rx->next = Rx; 881 sc->last_Rx = Rx; 882 883 /* deliver packet */ 884 if (m) { 885 struct ether_header *eh; 886 if (size < sizeof(struct ether_header)) { 887 m_freem(m); 888 continue; 889 } 890 m->m_pkthdr.rcvif = ifp; 891 m->m_pkthdr.len = m->m_len = 892 size - sizeof(struct ether_header); 893 eh = mtod(m, struct ether_header *); 894 #ifdef TLDEBUG_RX 895 printf("tl_intr: Rx packet:\n"); 896 ether_printheader(eh); 897 #endif 898 #if NBPFILTER > 0 899 if (ifp->if_bpf) { 900 bpf_tap(ifp->if_bpf, 901 mtod(m, caddr_t), 902 size); 903 /* 904 * Only pass this packet up 905 * if it is for us. 906 */ 907 if ((ifp->if_flags & IFF_PROMISC) && 908 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 909 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 910 sizeof(eh->ether_dhost)) != 0) { 911 m_freem(m); 912 continue; 913 } 914 } 915 #endif /* NBPFILTER > 0 */ 916 m->m_data += sizeof(struct ether_header); 917 ether_input(ifp, eh, m); 918 } 919 } 920 #ifdef TLDEBUG_RX 921 printf("TL_INTR_RxEOF: ack %d\n", ack); 922 #else 923 if (ack == 0) { 924 printf("%s: EOF intr without anything to read !\n", 925 sc->sc_dev.dv_xname); 926 tl_reset(sc); 927 /* shedule reinit of the board */ 928 timeout(tl_restart, sc, 1); 929 return(1); 930 } 931 #endif 932 break; 933 case TL_INTR_RxEOC: 934 ack++; 935 #ifdef TLDEBUG_RX 936 printf("TL_INTR_RxEOC: ack %d\n", ack); 937 #endif 938 #ifdef DIAGNOSTIC 939 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 940 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 941 sc->sc_dev.dv_xname); 942 return 0; 943 } else 944 #endif 945 { 946 /* write adress of Rx list and send Rx GO command, ack interrupt 947 and enable interrupts in one command */ 948 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 949 vtophys(&sc->active_Rx->hw_list)); 950 TL_HR_WRITE(sc, TL_HOST_CMD, 951 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 952 HOST_CMD_ACK | HOST_CMD_IntOn); 953 return 1; 954 } 955 case TL_INTR_TxEOF: 956 case TL_INTR_TxEOC: 957 while ((Tx = sc->active_Tx) != NULL) { 958 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 959 break; 960 ack++; 961 #ifdef TLDEBUG_TX 962 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 963 #endif 964 Tx->hw_list.stat = 0; 965 m_freem(Tx->m); 966 Tx->m = NULL; 967 sc->active_Tx = Tx->next; 968 if (sc->active_Tx == NULL) 969 sc->last_Tx = NULL; 970 Tx->next = sc->Free_Tx; 971 sc->Free_Tx = Tx; 972 } 973 /* if this was an EOC, ACK immediatly */ 974 if (int_type == TL_INTR_TxEOC) { 975 #ifdef TLDEBUG_TX 976 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 977 #endif 978 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 979 HOST_CMD_IntOn); 980 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 981 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 982 vtophys(&sc->active_Tx->hw_list)); 983 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 984 } 985 sc->tl_if.if_timer = 0; 986 if (sc->tl_if.if_snd.ifq_head != NULL) 987 tl_ifstart(&sc->tl_if); 988 return 1; 989 } 990 #ifdef TLDEBUG 991 else { 992 printf("TL_INTR_TxEOF: ack %d\n", ack); 993 } 994 #endif 995 sc->tl_if.if_timer = 0; 996 if (sc->tl_if.if_snd.ifq_head != NULL) 997 tl_ifstart(&sc->tl_if); 998 break; 999 case TL_INTR_Stat: 1000 ack++; 1001 #ifdef TLDEBUG 1002 printf("TL_INTR_Stat: ack %d\n", ack); 1003 #endif 1004 tl_read_stats(sc); 1005 break; 1006 case TL_INTR_Adc: 1007 if (int_reg & TL_INTVec_MASK) { 1008 /* adapter check conditions */ 1009 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1010 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1011 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1012 tl_reset(sc); 1013 /* shedule reinit of the board */ 1014 timeout(tl_restart, sc, 1); 1015 return(1); 1016 } else { 1017 u_int8_t netstat; 1018 /* Network status */ 1019 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1020 printf("%s: network status, NetSts=%x\n", 1021 sc->sc_dev.dv_xname, netstat); 1022 /* Ack interrupts */ 1023 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1024 ack++; 1025 } 1026 break; 1027 default: 1028 printf("%s: unhandled interrupt code %x!\n", 1029 sc->sc_dev.dv_xname, int_type); 1030 ack++; 1031 } 1032 1033 if (ack) { 1034 /* Ack the interrupt and enable interrupts */ 1035 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1036 HOST_CMD_IntOn); 1037 return 1; 1038 } 1039 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1040 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1041 return 0; 1042 } 1043 1044 static int 1045 tl_ifioctl(ifp, cmd, data) 1046 struct ifnet *ifp; 1047 ioctl_cmd_t cmd; 1048 caddr_t data; 1049 { 1050 struct tl_softc *sc = ifp->if_softc; 1051 struct ifreq *ifr = (struct ifreq *)data; 1052 int s, error; 1053 1054 s = splimp(); 1055 switch(cmd) { 1056 case SIOCSIFADDR: { 1057 struct ifaddr *ifa = (struct ifaddr *)data; 1058 sc->tl_if.if_flags |= IFF_UP; 1059 if ((error = tl_init(sc)) != NULL) { 1060 sc->tl_if.if_flags &= ~IFF_UP; 1061 break; 1062 } 1063 switch (ifa->ifa_addr->sa_family) { 1064 #ifdef INET 1065 case AF_INET: 1066 arp_ifinit(ifp, ifa); 1067 break; 1068 #endif 1069 #ifdef NS 1070 case AF_NS: { 1071 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1072 1073 if (ns_nullhost(*ina)) 1074 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1075 else 1076 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1077 ifp->if_addrlen); 1078 break; 1079 } 1080 #endif 1081 default: 1082 break; 1083 } 1084 break; 1085 } 1086 case SIOCSIFFLAGS: 1087 { 1088 u_int8_t reg; 1089 /* 1090 * If interface is marked up and not running, then start it. 1091 * If it is marked down and running, stop it. 1092 */ 1093 if (ifp->if_flags & IFF_UP) { 1094 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1095 error = tl_init(sc); 1096 /* all flags have been handled by init */ 1097 break; 1098 } 1099 error = 0; 1100 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1101 if (ifp->if_flags & IFF_PROMISC) 1102 reg |= TL_NETCOMMAND_CAF; 1103 else 1104 reg &= ~TL_NETCOMMAND_CAF; 1105 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1106 #ifdef TL_PRIV_STATS 1107 if (ifp->if_flags & IFF_LINK0) { 1108 ifp->if_flags &= ~IFF_LINK0; 1109 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1110 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1111 printf(" %4d RX code error\n", sc->ierr_code); 1112 printf(" %4d RX crc error\n", sc->ierr_crc); 1113 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1114 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1115 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1116 printf(" %4d TX single collisions\n", sc->oerr_coll); 1117 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1118 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1119 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1120 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1121 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1122 } 1123 #endif 1124 } else { 1125 if (ifp->if_flags & IFF_RUNNING) 1126 tl_shutdown(sc); 1127 error = 0; 1128 } 1129 break; 1130 } 1131 case SIOCADDMULTI: 1132 case SIOCDELMULTI: 1133 /* 1134 * Update multicast listeners 1135 */ 1136 if (cmd == SIOCADDMULTI) 1137 error = ether_addmulti(ifr, &sc->tl_ec); 1138 else 1139 error = ether_delmulti(ifr, &sc->tl_ec); 1140 if (error == ENETRESET) { 1141 tl_addr_filter(sc); 1142 error = 0; 1143 } 1144 break; 1145 case SIOCSIFMEDIA: 1146 case SIOCGIFMEDIA: 1147 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1148 break; 1149 default: 1150 error = EINVAL; 1151 } 1152 splx(s); 1153 return error; 1154 } 1155 1156 static void 1157 tl_ifstart(ifp) 1158 struct ifnet *ifp; 1159 { 1160 tl_softc_t *sc = ifp->if_softc; 1161 struct mbuf *m, *mb_head; 1162 struct Tx_list *Tx; 1163 int segment, size; 1164 1165 txloop: 1166 /* If we don't have more space ... */ 1167 if (sc->Free_Tx == NULL) { 1168 #ifdef TLDEBUG 1169 printf("tl_ifstart: No free TX list\n"); 1170 #endif 1171 return; 1172 } 1173 /* Grab a paquet for output */ 1174 IF_DEQUEUE(&ifp->if_snd, mb_head); 1175 if (mb_head == NULL) { 1176 #ifdef TLDEBUG_TX 1177 printf("tl_ifstart: nothing to send\n"); 1178 #endif 1179 return; 1180 } 1181 Tx = sc->Free_Tx; 1182 sc->Free_Tx = Tx->next; 1183 /* 1184 * Go through each of the mbufs in the chain and initialize 1185 * the transmit list descriptors with the physical address 1186 * and size of the mbuf. 1187 */ 1188 tbdinit: 1189 bzero(Tx, sizeof(struct Tx_list)); 1190 Tx->m = mb_head; 1191 size = 0; 1192 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1193 if (m->m_len != 0) { 1194 if (segment == TL_NSEG) 1195 break; 1196 size += m->m_len; 1197 Tx->hw_list.seg[segment].data_addr = 1198 vtophys(mtod(m, vm_offset_t)); 1199 Tx->hw_list.seg[segment].data_count = m->m_len; 1200 segment++; 1201 } 1202 } 1203 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1204 /* 1205 * We ran out of segments, or we will. We have to recopy this mbuf 1206 * chain first. 1207 */ 1208 struct mbuf *mn; 1209 #ifdef TLDEBUG_TX 1210 printf("tl_ifstart: need to copy mbuf\n"); 1211 #endif 1212 #ifdef TL_PRIV_STATS 1213 sc->oerr_mcopy++; 1214 #endif 1215 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1216 if (mn == NULL) { 1217 m_freem(mb_head); 1218 goto bad; 1219 } 1220 if (mb_head->m_pkthdr.len > MHLEN) { 1221 MCLGET(mn, M_DONTWAIT); 1222 if ((mn->m_flags & M_EXT) == 0) { 1223 m_freem(mn); 1224 m_freem(mb_head); 1225 goto bad; 1226 } 1227 } 1228 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1229 mtod(mn, caddr_t)); 1230 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1231 m_freem(mb_head); 1232 mb_head = mn; 1233 goto tbdinit; 1234 } 1235 /* We are at end of mbuf chain. check the size and 1236 * see if it needs to be extended 1237 */ 1238 if (size < ETHER_MIN_TX) { 1239 #ifdef DIAGNOSTIC 1240 if (segment >= TL_NSEG) { 1241 panic("tl_ifstart: to much segmets (%d)\n", segment); 1242 } 1243 #endif 1244 /* 1245 * add the nullbuf in the seg 1246 */ 1247 Tx->hw_list.seg[segment].data_count = 1248 ETHER_MIN_TX - size; 1249 Tx->hw_list.seg[segment].data_addr = 1250 vtophys(nullbuf); 1251 size = ETHER_MIN_TX; 1252 segment++; 1253 } 1254 /* The list is done, finish the list init */ 1255 Tx->hw_list.seg[segment-1].data_count |= 1256 TL_LAST_SEG; 1257 Tx->hw_list.stat = (size << 16) | 0x3000; 1258 #ifdef TLDEBUG_TX 1259 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1260 Tx->hw_list.stat); 1261 #if 0 1262 for(segment = 0; segment < TL_NSEG; segment++) { 1263 printf(" seg %d addr 0x%x len 0x%x\n", 1264 segment, 1265 Tx->hw_list.seg[segment].data_addr, 1266 Tx->hw_list.seg[segment].data_count); 1267 } 1268 #endif 1269 #endif 1270 sc->opkt++; 1271 if (sc->active_Tx == NULL) { 1272 sc->active_Tx = sc->last_Tx = Tx; 1273 #ifdef TLDEBUG_TX 1274 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1275 vtophys(&Tx->hw_list)); 1276 #endif 1277 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1278 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1279 } else { 1280 #ifdef TLDEBUG_TX 1281 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1282 vtophys(&Tx->hw_list)); 1283 #endif 1284 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1285 sc->last_Tx->next = Tx; 1286 sc->last_Tx = Tx; 1287 #ifdef DIAGNOSTIC 1288 if (sc->last_Tx->hw_list.fwd & 0x7) 1289 printf("%s: physical addr 0x%x of list not properly aligned\n", 1290 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1291 #endif 1292 } 1293 #if NBPFILTER > 0 1294 /* Pass packet to bpf if there is a listener */ 1295 if (ifp->if_bpf) 1296 bpf_mtap(ifp->if_bpf, mb_head); 1297 #endif 1298 /* Set a 5 second timer just in case we don't hear from the card again. */ 1299 ifp->if_timer = 5; 1300 1301 goto txloop; 1302 bad: 1303 #ifdef TLDEBUG 1304 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1305 #endif 1306 Tx->next = sc->Free_Tx; 1307 sc->Free_Tx = Tx; 1308 return; 1309 } 1310 1311 static void 1312 tl_ifwatchdog(ifp) 1313 struct ifnet *ifp; 1314 { 1315 tl_softc_t *sc = ifp->if_softc; 1316 1317 if ((ifp->if_flags & IFF_RUNNING) == 0) 1318 return; 1319 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1320 ifp->if_oerrors++; 1321 tl_init(sc); 1322 } 1323 1324 static int 1325 tl_mediachange(ifp) 1326 struct ifnet *ifp; 1327 { 1328 1329 tl_softc_t *sc = ifp->if_softc; 1330 int err; 1331 u_int32_t reg; 1332 int oldmedia; 1333 #ifdef TLDEBUG 1334 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1335 #endif 1336 oldmedia = sc->mii.mii_media_active; 1337 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1338 if ((err = mii_mediachg(&sc->mii)) != 0) 1339 sc->mii.mii_media_active = oldmedia; 1340 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1341 if (sc->mii.mii_media_active & IFM_FDX) 1342 reg |= TL_NETCOMMAND_DUPLEX; 1343 else 1344 reg &= ~TL_NETCOMMAND_DUPLEX; 1345 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1346 return err; 1347 } 1348 1349 static void 1350 tl_mediastatus(ifp, ifmr) 1351 struct ifnet *ifp; 1352 struct ifmediareq *ifmr; 1353 { 1354 tl_softc_t *sc = ifp->if_softc; 1355 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1356 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1357 if (sc->tl_flags & TL_IFACT) 1358 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1359 else 1360 sc->mii.mii_media_status = IFM_AVALID; 1361 else 1362 mii_pollstat(&sc->mii); 1363 1364 ifmr->ifm_active = sc->mii.mii_media_active; 1365 ifmr->ifm_status = sc->mii.mii_media_status; 1366 } 1367 1368 static int tl_add_RxBuff(Rx, oldm) 1369 struct Rx_list *Rx; 1370 struct mbuf *oldm; 1371 { 1372 struct mbuf *m; 1373 1374 MGETHDR(m, M_DONTWAIT, MT_DATA); 1375 if (m != NULL) { 1376 MCLGET(m, M_DONTWAIT); 1377 if ((m->m_flags & M_EXT) == 0) { 1378 m_freem(m); 1379 if (oldm == NULL) 1380 return 0; 1381 m = oldm; 1382 m->m_data = m->m_ext.ext_buf; 1383 } 1384 } else { 1385 if (oldm == NULL) 1386 return 0; 1387 m = oldm; 1388 m->m_data = m->m_ext.ext_buf; 1389 } 1390 /* 1391 * Move the data pointer up so that the incoming data packet 1392 * will be 32-bit aligned. 1393 */ 1394 m->m_data += 2; 1395 1396 /* (re)init the Rx_list struct */ 1397 1398 Rx->m = m; 1399 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1400 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1401 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1402 return (m != oldm); 1403 } 1404 1405 static void tl_ticks(v) 1406 void *v; 1407 { 1408 tl_softc_t *sc = v; 1409 1410 tl_read_stats(sc); 1411 if (sc->opkt > 0) { 1412 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1413 if (sc->tl_flags & TL_IFACT) /* only print once */ 1414 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1415 sc->tl_flags &= ~TL_IFACT; 1416 } else 1417 sc->tl_flags |= TL_IFACT; 1418 sc->oerr_exesscoll = sc->opkt = 0; 1419 sc->tl_lasttx = 0; 1420 } else { 1421 sc->tl_lasttx++; 1422 if (sc->tl_lasttx >= TL_IDLETIME) { 1423 /* 1424 * No TX activity in the last TL_IDLETIME seconds. 1425 * sends a LLC Class1 TEST pkt 1426 */ 1427 struct mbuf *m; 1428 int s; 1429 MGETHDR(m, M_DONTWAIT, MT_DATA); 1430 if (m != NULL) { 1431 #ifdef TLDEBUG 1432 printf("tl_ticks: sending LLC test pkt\n"); 1433 #endif 1434 bcopy(sc->tl_enaddr, 1435 mtod(m, struct ether_header *)->ether_dhost, 6); 1436 bcopy(sc->tl_enaddr, 1437 mtod(m, struct ether_header *)->ether_shost, 6); 1438 mtod(m, struct ether_header *)->ether_type = htons(3); 1439 mtod(m, unsigned char *)[14] = 0; 1440 mtod(m, unsigned char *)[15] = 0; 1441 mtod(m, unsigned char *)[16] = 0xE3; 1442 /* LLC Class1 TEST (no poll) */ 1443 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1444 s = splnet(); 1445 IF_PREPEND(&sc->tl_if.if_snd, m); 1446 tl_ifstart(&sc->tl_if); 1447 splx(s); 1448 } 1449 } 1450 } 1451 1452 /* read statistics every seconds */ 1453 timeout(tl_ticks, v, hz); 1454 } 1455 1456 static void 1457 tl_read_stats(sc) 1458 tl_softc_t *sc; 1459 { 1460 u_int32_t reg; 1461 int ierr_overr; 1462 int ierr_code; 1463 int ierr_crc; 1464 int oerr_underr; 1465 int oerr_deffered; 1466 int oerr_coll; 1467 int oerr_multicoll; 1468 int oerr_exesscoll; 1469 int oerr_latecoll; 1470 int oerr_carrloss; 1471 struct ifnet *ifp = &sc->tl_if; 1472 1473 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1474 ifp->if_opackets += reg & 0x00ffffff; 1475 oerr_underr = reg >> 24; 1476 1477 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1478 ifp->if_ipackets += reg & 0x00ffffff; 1479 ierr_overr = reg >> 24; 1480 1481 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1482 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1483 ierr_code = (reg & TL_FERR_CODE) >> 24; 1484 oerr_deffered = (reg & TL_FERR_DEF); 1485 1486 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1487 oerr_multicoll = (reg & TL_COL_MULTI); 1488 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1489 1490 reg = tl_intreg_read(sc, TL_INT_LERR); 1491 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1492 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1493 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1494 1495 1496 sc->stats_exesscoll += oerr_exesscoll; 1497 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1498 oerr_carrloss; 1499 ifp->if_collisions += oerr_coll + oerr_multicoll; 1500 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1501 1502 if (ierr_overr) 1503 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1504 if (oerr_underr) 1505 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1506 #ifdef TL_PRIV_STATS 1507 sc->ierr_overr += ierr_overr; 1508 sc->ierr_code += ierr_code; 1509 sc->ierr_crc += ierr_crc; 1510 sc->oerr_underr += oerr_underr; 1511 sc->oerr_deffered += oerr_deffered; 1512 sc->oerr_coll += oerr_coll; 1513 sc->oerr_multicoll += oerr_multicoll; 1514 sc->oerr_exesscoll += oerr_exesscoll; 1515 sc->oerr_latecoll += oerr_latecoll; 1516 sc->oerr_carrloss += oerr_carrloss; 1517 #endif 1518 } 1519 1520 static void tl_addr_filter(sc) 1521 tl_softc_t *sc; 1522 { 1523 struct ether_multistep step; 1524 struct ether_multi *enm; 1525 u_int32_t hash[2] = {0, 0}; 1526 int i; 1527 1528 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1529 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1530 while (enm != NULL) { 1531 #ifdef TLDEBUG 1532 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1533 #endif 1534 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1535 i = tl_multicast_hash(enm->enm_addrlo); 1536 hash[i/32] |= 1 << (i%32); 1537 } else { 1538 hash[0] = hash[1] = 0xffffffff; 1539 sc->tl_if.if_flags |= IFF_ALLMULTI; 1540 break; 1541 } 1542 ETHER_NEXT_MULTI(step, enm); 1543 } 1544 #ifdef TLDEBUG 1545 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1546 #endif 1547 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1548 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1549 } 1550 1551 static int tl_multicast_hash(a) 1552 u_int8_t *a; 1553 { 1554 int hash; 1555 1556 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1557 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1558 1559 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1560 DA(a,36), DA(a,42)); 1561 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1562 DA(a,37), DA(a,43)) << 1; 1563 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1564 DA(a,38), DA(a,44)) << 2; 1565 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1566 DA(a,39), DA(a,45)) << 3; 1567 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1568 DA(a,40), DA(a,46)) << 4; 1569 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1570 DA(a,41), DA(a,47)) << 5; 1571 1572 return hash; 1573 } 1574 1575 #if defined(TLDEBUG_RX) 1576 void ether_printheader(eh) 1577 struct ether_header *eh; 1578 { 1579 u_char *c = (char*)eh; 1580 int i; 1581 for (i=0; i<sizeof(struct ether_header); i++) 1582 printf("%x ", (u_int)c[i]); 1583 printf("\n"); 1584 } 1585 #endif 1586
Indexes created Tue Oct 21 06:10:07 GMT 2025