if_tl.c revision 1.115
1 /* $NetBSD: if_tl.c,v 1.115 2019/05/23 13:10:52 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Texas Instruments ThunderLAN ethernet controller 29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 30 * available from www.ti.com 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.115 2019/05/23 13:10:52 msaitoh Exp $"); 35 36 #undef TLDEBUG 37 #define TL_PRIV_STATS 38 #undef TLDEBUG_RX 39 #undef TLDEBUG_TX 40 #undef TLDEBUG_ADDR 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_dl.h> 60 #include <net/route.h> 61 #include <net/netisr.h> 62 #include <net/bpf.h> 63 64 #include <sys/rndsource.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #endif 72 73 74 #if defined(__NetBSD__) 75 #include <net/if_ether.h> 76 #if defined(INET) 77 #include <netinet/if_inarp.h> 78 #endif 79 80 #include <sys/bus.h> 81 #include <sys/intr.h> 82 83 #include <dev/pci/pcireg.h> 84 #include <dev/pci/pcivar.h> 85 #include <dev/pci/pcidevs.h> 86 87 #include <dev/i2c/i2cvar.h> 88 #include <dev/i2c/i2c_bitbang.h> 89 #include <dev/i2c/at24cxxvar.h> 90 91 #include <dev/mii/mii.h> 92 #include <dev/mii/miivar.h> 93 94 #include <dev/mii/tlphyvar.h> 95 96 #include <dev/pci/if_tlregs.h> 97 #include <dev/pci/if_tlvar.h> 98 #endif /* __NetBSD__ */ 99 100 /* number of transmit/receive buffers */ 101 #ifndef TL_NBUF 102 #define TL_NBUF 32 103 #endif 104 105 static int tl_pci_match(device_t, cfdata_t, void *); 106 static void tl_pci_attach(device_t, device_t, void *); 107 static int tl_intr(void *); 108 109 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 110 static int tl_mediachange(struct ifnet *); 111 static void tl_ifwatchdog(struct ifnet *); 112 static bool tl_shutdown(device_t, int); 113 114 static void tl_ifstart(struct ifnet *); 115 static void tl_reset(tl_softc_t *); 116 static int tl_init(struct ifnet *); 117 static void tl_stop(struct ifnet *, int); 118 static void tl_restart(void *); 119 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 120 static void tl_read_stats(tl_softc_t *); 121 static void tl_ticks(void *); 122 static int tl_multicast_hash(uint8_t *); 123 static void tl_addr_filter(tl_softc_t *); 124 125 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 126 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 127 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 128 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 129 130 void tl_mii_sync(struct tl_softc *); 131 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 132 133 134 #if defined(TLDEBUG_RX) 135 static void ether_printheader(struct ether_header *); 136 #endif 137 138 int tl_mii_read(device_t, int, int, uint16_t *); 139 int tl_mii_write(device_t, int, int, uint16_t); 140 141 void tl_statchg(struct ifnet *); 142 143 /* I2C glue */ 144 static int tl_i2c_acquire_bus(void *, int); 145 static void tl_i2c_release_bus(void *, int); 146 static int tl_i2c_send_start(void *, int); 147 static int tl_i2c_send_stop(void *, int); 148 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 149 static int tl_i2c_read_byte(void *, uint8_t *, int); 150 static int tl_i2c_write_byte(void *, uint8_t, int); 151 152 /* I2C bit-bang glue */ 153 static void tl_i2cbb_set_bits(void *, uint32_t); 154 static void tl_i2cbb_set_dir(void *, uint32_t); 155 static uint32_t tl_i2cbb_read(void *); 156 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 157 tl_i2cbb_set_bits, 158 tl_i2cbb_set_dir, 159 tl_i2cbb_read, 160 { 161 TL_NETSIO_EDATA, /* SDA */ 162 TL_NETSIO_ECLOCK, /* SCL */ 163 TL_NETSIO_ETXEN, /* SDA is output */ 164 0, /* SDA is input */ 165 } 166 }; 167 168 static inline void netsio_clr(tl_softc_t *, uint8_t); 169 static inline void netsio_set(tl_softc_t *, uint8_t); 170 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 171 172 static inline void 173 netsio_clr(tl_softc_t *sc, uint8_t bits) 174 { 175 176 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 177 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 178 } 179 180 static inline void 181 netsio_set(tl_softc_t *sc, uint8_t bits) 182 { 183 184 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 185 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 186 } 187 188 static inline uint8_t 189 netsio_read(tl_softc_t *sc, uint8_t bits) 190 { 191 192 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 193 } 194 195 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 196 tl_pci_match, tl_pci_attach, NULL, NULL); 197 198 static const struct tl_product_desc tl_compaq_products[] = { 199 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 200 "Compaq Netelligent 10/100 TX" }, 201 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 202 "Integrated Compaq Netelligent 10/100 TX" }, 203 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 204 "Compaq Netelligent 10 T" }, 205 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 206 "Compaq Netelligent 10 T/2 UTP/Coax" }, 207 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 208 "Compaq Integrated NetFlex 3/P" }, 209 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2 |TLPHY_MEDIA_NO_10_T, 210 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 211 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5 |TLPHY_MEDIA_NO_10_T, 212 "Compaq Dual Port Netelligent 10/100 TX" }, 213 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5 | TLPHY_MEDIA_NO_10_T, 214 "Compaq Deskpro 4000 5233MMX" }, 215 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 216 "Compaq NetFlex 3/P w/ BNC" }, 217 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 218 "Compaq NetFlex 3/P" }, 219 { 0, 0, NULL }, 220 }; 221 222 static const struct tl_product_desc tl_ti_products[] = { 223 /* 224 * Built-in Ethernet on the TI TravelMate 5000 225 * docking station; better product description? 226 */ 227 { PCI_PRODUCT_TI_TLAN, 0, 228 "Texas Instruments ThunderLAN" }, 229 { 0, 0, NULL }, 230 }; 231 232 struct tl_vendor_desc { 233 uint32_t tv_vendor; 234 const struct tl_product_desc *tv_products; 235 }; 236 237 const struct tl_vendor_desc tl_vendors[] = { 238 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 239 { PCI_VENDOR_TI, tl_ti_products }, 240 { 0, NULL }, 241 }; 242 243 static const struct tl_product_desc *tl_lookup_product(uint32_t); 244 245 static const struct tl_product_desc * 246 tl_lookup_product(uint32_t id) 247 { 248 const struct tl_product_desc *tp; 249 const struct tl_vendor_desc *tv; 250 251 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 252 if (PCI_VENDOR(id) == tv->tv_vendor) 253 break; 254 255 if ((tp = tv->tv_products) == NULL) 256 return NULL; 257 258 for (; tp->tp_desc != NULL; tp++) 259 if (PCI_PRODUCT(id) == tp->tp_product) 260 break; 261 262 if (tp->tp_desc == NULL) 263 return NULL; 264 265 return tp; 266 } 267 268 static int 269 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 270 { 271 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 272 273 if (tl_lookup_product(pa->pa_id) != NULL) 274 return 1; 275 276 return 0; 277 } 278 279 static void 280 tl_pci_attach(device_t parent, device_t self, void *aux) 281 { 282 tl_softc_t *sc = device_private(self); 283 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 284 const struct tl_product_desc *tp; 285 struct ifnet * const ifp = &sc->tl_if; 286 struct mii_data * const mii = &sc->tl_mii; 287 bus_space_tag_t iot, memt; 288 bus_space_handle_t ioh, memh; 289 pci_intr_handle_t intrhandle; 290 const char *intrstr; 291 int ioh_valid, memh_valid; 292 int reg_io, reg_mem; 293 pcireg_t reg10, reg14; 294 pcireg_t csr; 295 char intrbuf[PCI_INTRSTR_LEN]; 296 297 sc->sc_dev = self; 298 aprint_normal("\n"); 299 300 callout_init(&sc->tl_tick_ch, 0); 301 callout_init(&sc->tl_restart_ch, 0); 302 303 tp = tl_lookup_product(pa->pa_id); 304 if (tp == NULL) 305 panic("%s: impossible", __func__); 306 sc->tl_product = tp; 307 308 /* 309 * Map the card space. First we have to find the I/O and MEM 310 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 311 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 312 * The ThunderLAN manual is not consistent about this either (there 313 * are both cases in code examples). 314 */ 315 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 316 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 317 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 318 reg_io = 0x10; 319 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 320 reg_io = 0x14; 321 else 322 reg_io = 0; 323 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 324 reg_mem = 0x10; 325 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 326 reg_mem = 0x14; 327 else 328 reg_mem = 0; 329 330 if (reg_io != 0) 331 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 332 0, &iot, &ioh, NULL, NULL) == 0); 333 else 334 ioh_valid = 0; 335 if (reg_mem != 0) 336 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 337 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 338 0, &memt, &memh, NULL, NULL) == 0); 339 else 340 memh_valid = 0; 341 342 if (ioh_valid) { 343 sc->tl_bustag = iot; 344 sc->tl_bushandle = ioh; 345 } else if (memh_valid) { 346 sc->tl_bustag = memt; 347 sc->tl_bushandle = memh; 348 } else { 349 aprint_error_dev(self, "unable to map device registers\n"); 350 return; 351 } 352 sc->tl_dmatag = pa->pa_dmat; 353 354 /* Enable the device. */ 355 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 356 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 357 csr | PCI_COMMAND_MASTER_ENABLE); 358 359 aprint_normal_dev(self, "%s\n", tp->tp_desc); 360 361 tl_reset(sc); 362 363 /* fill in the i2c tag */ 364 sc->sc_i2c.ic_cookie = sc; 365 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 366 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 367 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 368 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 369 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 370 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 371 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 372 373 #ifdef TLDEBUG 374 aprint_debug_dev(self, "default values of INTreg: 0x%x\n", 375 tl_intreg_read(sc, TL_INT_Defaults)); 376 #endif 377 378 /* read mac addr */ 379 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 380 sc->tl_enaddr, ETHER_ADDR_LEN)) { 381 aprint_error_dev(self, "error reading Ethernet address\n"); 382 return; 383 } 384 aprint_normal_dev(self, "Ethernet address %s\n", 385 ether_sprintf(sc->tl_enaddr)); 386 387 /* Map and establish interrupts */ 388 if (pci_intr_map(pa, &intrhandle)) { 389 aprint_error_dev(self, "couldn't map interrupt\n"); 390 return; 391 } 392 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 393 sizeof(intrbuf)); 394 sc->tl_if.if_softc = sc; 395 sc->tl_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 396 tl_intr, sc, device_xname(self)); 397 if (sc->tl_ih == NULL) { 398 aprint_error_dev(self, "couldn't establish interrupt"); 399 if (intrstr != NULL) 400 aprint_error(" at %s", intrstr); 401 aprint_error("\n"); 402 return; 403 } 404 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 405 406 /* init these pointers, so that tl_shutdown won't try to read them */ 407 sc->Rx_list = NULL; 408 sc->Tx_list = NULL; 409 410 /* allocate DMA-safe memory for control structs */ 411 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 412 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 413 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 414 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 415 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 416 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 417 return; 418 } 419 420 /* 421 * Initialize our media structures and probe the MII. 422 * 423 * Note that we don't care about the media instance. We 424 * are expecting to have multiple PHYs on the 10/100 cards, 425 * and on those cards we exclude the internal PHY from providing 426 * 10baseT. By ignoring the instance, it allows us to not have 427 * to specify it on the command line when switching media. 428 */ 429 mii->mii_ifp = ifp; 430 mii->mii_readreg = tl_mii_read; 431 mii->mii_writereg = tl_mii_write; 432 mii->mii_statchg = tl_statchg; 433 sc->tl_ec.ec_mii = mii; 434 ifmedia_init(&mii->mii_media, IFM_IMASK, tl_mediachange, 435 ether_mediastatus); 436 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 437 if (LIST_FIRST(&mii->mii_phys) == NULL) { 438 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 439 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 440 } else 441 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 442 443 /* 444 * We can support 802.1Q VLAN-sized frames. 445 */ 446 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 447 448 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 449 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 450 ifp->if_ioctl = tl_ifioctl; 451 ifp->if_start = tl_ifstart; 452 ifp->if_watchdog = tl_ifwatchdog; 453 ifp->if_init = tl_init; 454 ifp->if_stop = tl_stop; 455 ifp->if_timer = 0; 456 IFQ_SET_READY(&ifp->if_snd); 457 if_attach(ifp); 458 if_deferred_start_init(ifp, NULL); 459 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 460 461 /* 462 * Add shutdown hook so that DMA is disabled prior to reboot. 463 * Not doing reboot before the driver initializes. 464 */ 465 if (pmf_device_register1(self, NULL, NULL, tl_shutdown)) 466 pmf_class_network_register(self, ifp); 467 else 468 aprint_error_dev(self, "couldn't establish power handler\n"); 469 470 rnd_attach_source(&sc->rnd_source, device_xname(self), 471 RND_TYPE_NET, RND_FLAG_DEFAULT); 472 } 473 474 static void 475 tl_reset(tl_softc_t *sc) 476 { 477 int i; 478 479 /* read stats */ 480 if (sc->tl_if.if_flags & IFF_RUNNING) { 481 callout_stop(&sc->tl_tick_ch); 482 tl_read_stats(sc); 483 } 484 /* Reset adapter */ 485 TL_HR_WRITE(sc, TL_HOST_CMD, 486 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 487 DELAY(100000); 488 /* Disable interrupts */ 489 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 490 /* setup aregs & hash */ 491 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 492 tl_intreg_write(sc, i, 0); 493 #ifdef TLDEBUG_ADDR 494 printf("Areg & hash registers: \n"); 495 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 496 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 497 #endif 498 /* Setup NetConfig */ 499 tl_intreg_write(sc, TL_INT_NetConfig, 500 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 501 /* Bsize: accept default */ 502 /* TX commit in Acommit: accept default */ 503 /* Load Ld_tmr and Ld_thr */ 504 /* Ld_tmr = 3 */ 505 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 506 /* Ld_thr = 0 */ 507 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 508 /* Unreset MII */ 509 netsio_set(sc, TL_NETSIO_NMRST); 510 DELAY(100000); 511 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 512 } 513 514 static bool 515 tl_shutdown(device_t self, int howto) 516 { 517 tl_softc_t *sc = device_private(self); 518 struct ifnet *ifp = &sc->tl_if; 519 520 tl_stop(ifp, 1); 521 522 return true; 523 } 524 525 static void 526 tl_stop(struct ifnet *ifp, int disable) 527 { 528 tl_softc_t *sc = ifp->if_softc; 529 struct Tx_list *Tx; 530 int i; 531 532 if ((ifp->if_flags & IFF_RUNNING) == 0) 533 return; 534 /* disable interrupts */ 535 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 536 /* stop TX and RX channels */ 537 TL_HR_WRITE(sc, TL_HOST_CMD, 538 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 539 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 540 DELAY(100000); 541 542 /* stop statistics reading loop, read stats */ 543 callout_stop(&sc->tl_tick_ch); 544 tl_read_stats(sc); 545 546 /* Down the MII. */ 547 mii_down(&sc->tl_mii); 548 549 /* deallocate memory allocations */ 550 if (sc->Rx_list) { 551 for (i = 0; i< TL_NBUF; i++) { 552 if (sc->Rx_list[i].m) { 553 bus_dmamap_unload(sc->tl_dmatag, 554 sc->Rx_list[i].m_dmamap); 555 m_freem(sc->Rx_list[i].m); 556 } 557 bus_dmamap_destroy(sc->tl_dmatag, 558 sc->Rx_list[i].m_dmamap); 559 sc->Rx_list[i].m = NULL; 560 } 561 free(sc->Rx_list, M_DEVBUF); 562 sc->Rx_list = NULL; 563 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 564 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 565 sc->hw_Rx_list = NULL; 566 while ((Tx = sc->active_Tx) != NULL) { 567 Tx->hw_list->stat = 0; 568 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 569 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 570 m_freem(Tx->m); 571 sc->active_Tx = Tx->next; 572 Tx->next = sc->Free_Tx; 573 sc->Free_Tx = Tx; 574 } 575 sc->last_Tx = NULL; 576 free(sc->Tx_list, M_DEVBUF); 577 sc->Tx_list = NULL; 578 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 579 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 580 sc->hw_Tx_list = NULL; 581 } 582 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 583 ifp->if_timer = 0; 584 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 585 } 586 587 static void 588 tl_restart(void *v) 589 { 590 591 tl_init(v); 592 } 593 594 static int 595 tl_init(struct ifnet *ifp) 596 { 597 tl_softc_t *sc = ifp->if_softc; 598 int i, s, error; 599 bus_size_t boundary; 600 prop_number_t prop_boundary; 601 const char *errstring; 602 char *nullbuf; 603 604 s = splnet(); 605 /* cancel any pending IO */ 606 tl_stop(ifp, 1); 607 tl_reset(sc); 608 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 609 splx(s); 610 return 0; 611 } 612 /* Set various register to reasonable value */ 613 /* setup NetCmd in promisc mode if needed */ 614 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 615 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 616 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 617 /* Max receive size : MCLBYTES */ 618 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 619 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 620 (MCLBYTES >> 8) & 0xff); 621 622 /* init MAC addr */ 623 for (i = 0; i < ETHER_ADDR_LEN; i++) 624 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 625 /* add multicast filters */ 626 tl_addr_filter(sc); 627 #ifdef TLDEBUG_ADDR 628 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 629 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 630 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 631 #endif 632 633 /* Pre-allocate receivers mbuf, make the lists */ 634 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 635 M_NOWAIT | M_ZERO); 636 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 637 M_NOWAIT | M_ZERO); 638 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 639 errstring = "out of memory for lists"; 640 error = ENOMEM; 641 goto bad; 642 } 643 644 /* 645 * Some boards (Set Engineering GFE) do not permit DMA transfers 646 * across page boundaries. 647 */ 648 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 649 "tl-dma-page-boundary"); 650 if (prop_boundary != NULL) { 651 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 652 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 653 } else { 654 boundary = 0; 655 } 656 657 error = bus_dmamap_create(sc->tl_dmatag, 658 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 659 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 660 &sc->Rx_dmamap); 661 if (error == 0) 662 error = bus_dmamap_create(sc->tl_dmatag, 663 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 664 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 665 BUS_DMA_WAITOK, &sc->Tx_dmamap); 666 if (error == 0) 667 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 668 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 669 &sc->null_dmamap); 670 if (error) { 671 errstring = "can't allocate DMA maps for lists"; 672 goto bad; 673 } 674 memset(sc->ctrl, 0, PAGE_SIZE); 675 sc->hw_Rx_list = (void *)sc->ctrl; 676 sc->hw_Tx_list = 677 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 678 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 679 sizeof(struct tl_Tx_list) * TL_NBUF; 680 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 681 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 682 BUS_DMA_WAITOK); 683 if (error == 0) 684 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 685 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 686 BUS_DMA_WAITOK); 687 if (error == 0) 688 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 689 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 690 if (error) { 691 errstring = "can't DMA map DMA memory for lists"; 692 goto bad; 693 } 694 for (i = 0; i < TL_NBUF; i++) { 695 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 696 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 697 &sc->Rx_list[i].m_dmamap); 698 if (error == 0) { 699 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 700 TL_NSEG, MCLBYTES, boundary, 701 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 702 &sc->Tx_list[i].m_dmamap); 703 } 704 if (error) { 705 errstring = "can't allocate DMA maps for mbufs"; 706 goto bad; 707 } 708 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 709 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 710 + sizeof(struct tl_Rx_list) * i; 711 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 712 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 713 + sizeof(struct tl_Tx_list) * i; 714 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 715 errstring = "out of mbuf for receive list"; 716 error = ENOMEM; 717 goto bad; 718 } 719 if (i > 0) { /* chain the list */ 720 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 721 sc->hw_Rx_list[i - 1].fwd = 722 htole32(sc->Rx_list[i].hw_listaddr); 723 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 724 } 725 } 726 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 727 sc->Rx_list[TL_NBUF - 1].next = NULL; 728 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 729 sc->Tx_list[TL_NBUF - 1].next = NULL; 730 731 sc->active_Rx = &sc->Rx_list[0]; 732 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 733 sc->active_Tx = sc->last_Tx = NULL; 734 sc->Free_Tx = &sc->Tx_list[0]; 735 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 736 sizeof(struct tl_Rx_list) * TL_NBUF, 737 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 738 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 739 sizeof(struct tl_Tx_list) * TL_NBUF, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 742 BUS_DMASYNC_PREWRITE); 743 744 /* set media */ 745 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 746 error = 0; 747 else if (error != 0) { 748 errstring = "could not set media"; 749 goto bad; 750 } 751 752 /* start ticks calls */ 753 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 754 /* write address of Rx list and enable interrupts */ 755 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 756 TL_HR_WRITE(sc, TL_HOST_CMD, 757 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 758 sc->tl_if.if_flags |= IFF_RUNNING; 759 sc->tl_if.if_flags &= ~IFF_OACTIVE; 760 splx(s); 761 return 0; 762 bad: 763 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 764 splx(s); 765 return error; 766 } 767 768 769 static uint32_t 770 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 771 { 772 773 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 774 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 775 } 776 777 static uint8_t 778 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 779 { 780 781 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 782 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 783 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 784 } 785 786 static void 787 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 788 { 789 790 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 791 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 792 } 793 794 static void 795 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 796 { 797 798 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 799 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 800 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 801 } 802 803 void 804 tl_mii_sync(struct tl_softc *sc) 805 { 806 int i; 807 808 netsio_clr(sc, TL_NETSIO_MTXEN); 809 for (i = 0; i < 32; i++) { 810 netsio_clr(sc, TL_NETSIO_MCLK); 811 netsio_set(sc, TL_NETSIO_MCLK); 812 } 813 } 814 815 void 816 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 817 { 818 int i; 819 820 netsio_set(sc, TL_NETSIO_MTXEN); 821 for (i = 1 << (nbits - 1); i; i = i >> 1) { 822 netsio_clr(sc, TL_NETSIO_MCLK); 823 netsio_read(sc, TL_NETSIO_MCLK); 824 if (data & i) 825 netsio_set(sc, TL_NETSIO_MDATA); 826 else 827 netsio_clr(sc, TL_NETSIO_MDATA); 828 netsio_set(sc, TL_NETSIO_MCLK); 829 netsio_read(sc, TL_NETSIO_MCLK); 830 } 831 } 832 833 int 834 tl_mii_read(device_t self, int phy, int reg, uint16_t *val) 835 { 836 struct tl_softc *sc = device_private(self); 837 uint16_t data = 0; 838 int i, err; 839 840 /* 841 * Read the PHY register by manually driving the MII control lines. 842 */ 843 844 tl_mii_sync(sc); 845 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 846 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 847 tl_mii_sendbits(sc, phy, 5); 848 tl_mii_sendbits(sc, reg, 5); 849 850 netsio_clr(sc, TL_NETSIO_MTXEN); 851 netsio_clr(sc, TL_NETSIO_MCLK); 852 netsio_set(sc, TL_NETSIO_MCLK); 853 netsio_clr(sc, TL_NETSIO_MCLK); 854 855 err = netsio_read(sc, TL_NETSIO_MDATA); 856 netsio_set(sc, TL_NETSIO_MCLK); 857 858 /* Even if an error occurs, must still clock out the cycle. */ 859 for (i = 0; i < 16; i++) { 860 data <<= 1; 861 netsio_clr(sc, TL_NETSIO_MCLK); 862 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 863 data |= 1; 864 netsio_set(sc, TL_NETSIO_MCLK); 865 } 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 netsio_set(sc, TL_NETSIO_MCLK); 868 869 *val = data; 870 return err; 871 } 872 873 int 874 tl_mii_write(device_t self, int phy, int reg, uint16_t val) 875 { 876 struct tl_softc *sc = device_private(self); 877 878 /* 879 * Write the PHY register by manually driving the MII control lines. 880 */ 881 882 tl_mii_sync(sc); 883 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 884 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 885 tl_mii_sendbits(sc, phy, 5); 886 tl_mii_sendbits(sc, reg, 5); 887 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 888 tl_mii_sendbits(sc, val, 16); 889 890 netsio_clr(sc, TL_NETSIO_MCLK); 891 netsio_set(sc, TL_NETSIO_MCLK); 892 893 return 0; 894 } 895 896 void 897 tl_statchg(struct ifnet *ifp) 898 { 899 tl_softc_t *sc = ifp->if_softc; 900 uint32_t reg; 901 902 #ifdef TLDEBUG 903 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 904 #endif 905 906 /* 907 * We must keep the ThunderLAN and the PHY in sync as 908 * to the status of full-duplex! 909 */ 910 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 911 if (sc->tl_mii.mii_media_active & IFM_FDX) 912 reg |= TL_NETCOMMAND_DUPLEX; 913 else 914 reg &= ~TL_NETCOMMAND_DUPLEX; 915 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 916 } 917 918 /********** I2C glue **********/ 919 920 static int 921 tl_i2c_acquire_bus(void *cookie, int flags) 922 { 923 924 /* private bus */ 925 return 0; 926 } 927 928 static void 929 tl_i2c_release_bus(void *cookie, int flags) 930 { 931 932 /* private bus */ 933 } 934 935 static int 936 tl_i2c_send_start(void *cookie, int flags) 937 { 938 939 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 940 } 941 942 static int 943 tl_i2c_send_stop(void *cookie, int flags) 944 { 945 946 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 947 } 948 949 static int 950 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 951 { 952 953 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 954 } 955 956 static int 957 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 958 { 959 960 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 961 } 962 963 static int 964 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 965 { 966 967 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 968 } 969 970 /********** I2C bit-bang glue **********/ 971 972 static void 973 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 974 { 975 struct tl_softc *sc = cookie; 976 uint8_t reg; 977 978 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 979 reg = (reg & ~(TL_NETSIO_EDATA | TL_NETSIO_ECLOCK)) | bits; 980 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 981 } 982 983 static void 984 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 985 { 986 struct tl_softc *sc = cookie; 987 uint8_t reg; 988 989 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 990 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 991 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 992 } 993 994 static uint32_t 995 tl_i2cbb_read(void *cookie) 996 { 997 998 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 999 } 1000 1001 /********** End of I2C stuff **********/ 1002 1003 static int 1004 tl_intr(void *v) 1005 { 1006 tl_softc_t *sc = v; 1007 struct ifnet *ifp = &sc->tl_if; 1008 struct Rx_list *Rx; 1009 struct Tx_list *Tx; 1010 struct mbuf *m; 1011 uint32_t int_type, int_reg; 1012 int ack = 0; 1013 int size; 1014 1015 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1016 int_type = int_reg & TL_INTR_MASK; 1017 if (int_type == 0) 1018 return 0; 1019 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1020 printf("%s: interrupt type %x, intr_reg %x\n", 1021 device_xname(sc->sc_dev), int_type, int_reg); 1022 #endif 1023 /* disable interrupts */ 1024 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1025 switch (int_type & TL_INTR_MASK) { 1026 case TL_INTR_RxEOF: 1027 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1028 sizeof(struct tl_Rx_list) * TL_NBUF, 1029 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1030 while (le32toh(sc->active_Rx->hw_list->stat) & 1031 TL_RX_CSTAT_CPLT) { 1032 /* dequeue and requeue at end of list */ 1033 ack++; 1034 Rx = sc->active_Rx; 1035 sc->active_Rx = Rx->next; 1036 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1037 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1038 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1039 m = Rx->m; 1040 size = le32toh(Rx->hw_list->stat) >> 16; 1041 #ifdef TLDEBUG_RX 1042 printf("%s: RX list complete, Rx %p, size=%d\n", 1043 __func__, Rx, size); 1044 #endif 1045 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1046 /* 1047 * No new mbuf, reuse the same. This means 1048 * that this packet 1049 * is lost 1050 */ 1051 m = NULL; 1052 #ifdef TL_PRIV_STATS 1053 sc->ierr_nomem++; 1054 #endif 1055 #ifdef TLDEBUG 1056 printf("%s: out of mbuf, lost input packet\n", 1057 device_xname(sc->sc_dev)); 1058 #endif 1059 } 1060 Rx->next = NULL; 1061 Rx->hw_list->fwd = 0; 1062 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1063 sc->last_Rx->next = Rx; 1064 sc->last_Rx = Rx; 1065 1066 /* deliver packet */ 1067 if (m) { 1068 if (size < sizeof(struct ether_header)) { 1069 m_freem(m); 1070 continue; 1071 } 1072 m_set_rcvif(m, ifp); 1073 m->m_pkthdr.len = m->m_len = size; 1074 #ifdef TLDEBUG_RX 1075 { 1076 struct ether_header *eh = 1077 mtod(m, struct ether_header *); 1078 printf("%s: Rx packet:\n", __func__); 1079 ether_printheader(eh); 1080 } 1081 #endif 1082 if_percpuq_enqueue(ifp->if_percpuq, m); 1083 } 1084 } 1085 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1086 sizeof(struct tl_Rx_list) * TL_NBUF, 1087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1088 #ifdef TLDEBUG_RX 1089 printf("TL_INTR_RxEOF: ack %d\n", ack); 1090 #else 1091 if (ack == 0) { 1092 printf("%s: EOF intr without anything to read !\n", 1093 device_xname(sc->sc_dev)); 1094 tl_reset(sc); 1095 /* schedule reinit of the board */ 1096 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1097 return 1; 1098 } 1099 #endif 1100 break; 1101 case TL_INTR_RxEOC: 1102 ack++; 1103 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1104 sizeof(struct tl_Rx_list) * TL_NBUF, 1105 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1106 #ifdef TLDEBUG_RX 1107 printf("TL_INTR_RxEOC: ack %d\n", ack); 1108 #endif 1109 #ifdef DIAGNOSTIC 1110 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1111 printf("%s: Rx EOC interrupt and active Tx list not " 1112 "cleared\n", device_xname(sc->sc_dev)); 1113 return 0; 1114 } else 1115 #endif 1116 { 1117 /* 1118 * write address of Rx list and send Rx GO command, ack 1119 * interrupt and enable interrupts in one command 1120 */ 1121 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1122 TL_HR_WRITE(sc, TL_HOST_CMD, 1123 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1124 HOST_CMD_ACK | HOST_CMD_IntOn); 1125 return 1; 1126 } 1127 case TL_INTR_TxEOF: 1128 case TL_INTR_TxEOC: 1129 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1130 sizeof(struct tl_Tx_list) * TL_NBUF, 1131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1132 while ((Tx = sc->active_Tx) != NULL) { 1133 if ((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) 1134 == 0) 1135 break; 1136 ack++; 1137 #ifdef TLDEBUG_TX 1138 printf("TL_INTR_TxEOC: list 0x%x done\n", 1139 (int)Tx->hw_listaddr); 1140 #endif 1141 Tx->hw_list->stat = 0; 1142 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1143 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1144 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1145 m_freem(Tx->m); 1146 Tx->m = NULL; 1147 sc->active_Tx = Tx->next; 1148 if (sc->active_Tx == NULL) 1149 sc->last_Tx = NULL; 1150 Tx->next = sc->Free_Tx; 1151 sc->Free_Tx = Tx; 1152 } 1153 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1154 sizeof(struct tl_Tx_list) * TL_NBUF, 1155 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1156 /* if this was an EOC, ACK immediatly */ 1157 if (ack) 1158 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1159 if (int_type == TL_INTR_TxEOC) { 1160 #ifdef TLDEBUG_TX 1161 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1162 ack); 1163 #endif 1164 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1165 HOST_CMD_ACK | HOST_CMD_IntOn); 1166 if (sc->active_Tx != NULL) { 1167 /* needs a Tx go command */ 1168 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1169 sc->active_Tx->hw_listaddr); 1170 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1171 } 1172 sc->tl_if.if_timer = 0; 1173 if_schedule_deferred_start(&sc->tl_if); 1174 return 1; 1175 } 1176 #ifdef TLDEBUG 1177 else { 1178 printf("TL_INTR_TxEOF: ack %d\n", ack); 1179 } 1180 #endif 1181 sc->tl_if.if_timer = 0; 1182 if_schedule_deferred_start(&sc->tl_if); 1183 break; 1184 case TL_INTR_Stat: 1185 ack++; 1186 #ifdef TLDEBUG 1187 printf("TL_INTR_Stat: ack %d\n", ack); 1188 #endif 1189 tl_read_stats(sc); 1190 break; 1191 case TL_INTR_Adc: 1192 if (int_reg & TL_INTVec_MASK) { 1193 /* adapter check conditions */ 1194 printf("%s: check condition, intvect=0x%x, " 1195 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1196 int_reg & TL_INTVec_MASK, 1197 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1198 tl_reset(sc); 1199 /* schedule reinit of the board */ 1200 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1201 return 1; 1202 } else { 1203 uint8_t netstat; 1204 /* Network status */ 1205 netstat = 1206 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1207 printf("%s: network status, NetSts=%x\n", 1208 device_xname(sc->sc_dev), netstat); 1209 /* Ack interrupts */ 1210 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1211 netstat); 1212 ack++; 1213 } 1214 break; 1215 default: 1216 printf("%s: unhandled interrupt code %x!\n", 1217 device_xname(sc->sc_dev), int_type); 1218 ack++; 1219 } 1220 1221 if (ack) { 1222 /* Ack the interrupt and enable interrupts */ 1223 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1224 HOST_CMD_IntOn); 1225 rnd_add_uint32(&sc->rnd_source, int_reg); 1226 return 1; 1227 } 1228 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1229 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1230 return 0; 1231 } 1232 1233 static int 1234 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1235 { 1236 struct tl_softc *sc = ifp->if_softc; 1237 int s, error; 1238 1239 s = splnet(); 1240 error = ether_ioctl(ifp, cmd, data); 1241 if (error == ENETRESET) { 1242 if (ifp->if_flags & IFF_RUNNING) 1243 tl_addr_filter(sc); 1244 error = 0; 1245 } 1246 splx(s); 1247 return error; 1248 } 1249 1250 static void 1251 tl_ifstart(struct ifnet *ifp) 1252 { 1253 tl_softc_t *sc = ifp->if_softc; 1254 struct mbuf *mb_head; 1255 struct Tx_list *Tx; 1256 int segment, size; 1257 int again, error; 1258 1259 if ((sc->tl_if.if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1260 return; 1261 txloop: 1262 /* If we don't have more space ... */ 1263 if (sc->Free_Tx == NULL) { 1264 #ifdef TLDEBUG 1265 printf("%s: No free TX list\n", __func__); 1266 #endif 1267 sc->tl_if.if_flags |= IFF_OACTIVE; 1268 return; 1269 } 1270 /* Grab a paquet for output */ 1271 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1272 if (mb_head == NULL) { 1273 #ifdef TLDEBUG_TX 1274 printf("%s: nothing to send\n", __func__); 1275 #endif 1276 return; 1277 } 1278 Tx = sc->Free_Tx; 1279 sc->Free_Tx = Tx->next; 1280 Tx->next = NULL; 1281 again = 0; 1282 /* 1283 * Go through each of the mbufs in the chain and initialize 1284 * the transmit list descriptors with the physical address 1285 * and size of the mbuf. 1286 */ 1287 tbdinit: 1288 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1289 Tx->m = mb_head; 1290 size = mb_head->m_pkthdr.len; 1291 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1292 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1293 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1294 struct mbuf *mn; 1295 /* 1296 * We ran out of segments, or we will. We have to recopy this 1297 * mbuf chain first. 1298 */ 1299 if (error == 0) 1300 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1301 if (again) { 1302 /* already copyed, can't do much more */ 1303 m_freem(mb_head); 1304 goto bad; 1305 } 1306 again = 1; 1307 #ifdef TLDEBUG_TX 1308 printf("%s: need to copy mbuf\n", __func__); 1309 #endif 1310 #ifdef TL_PRIV_STATS 1311 sc->oerr_mcopy++; 1312 #endif 1313 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1314 if (mn == NULL) { 1315 m_freem(mb_head); 1316 goto bad; 1317 } 1318 if (mb_head->m_pkthdr.len > MHLEN) { 1319 MCLGET(mn, M_DONTWAIT); 1320 if ((mn->m_flags & M_EXT) == 0) { 1321 m_freem(mn); 1322 m_freem(mb_head); 1323 goto bad; 1324 } 1325 } 1326 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1327 mtod(mn, void *)); 1328 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1329 m_freem(mb_head); 1330 mb_head = mn; 1331 goto tbdinit; 1332 } 1333 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1334 Tx->hw_list->seg[segment].data_addr = 1335 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1336 Tx->hw_list->seg[segment].data_count = 1337 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1338 } 1339 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1340 Tx->m_dmamap->dm_mapsize, 1341 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1342 /* We are at end of mbuf chain. check the size and 1343 * see if it needs to be extended 1344 */ 1345 if (size < ETHER_MIN_TX) { 1346 #ifdef DIAGNOSTIC 1347 if (segment >= TL_NSEG) { 1348 panic("%s: to much segmets (%d)", __func__, segment); 1349 } 1350 #endif 1351 /* 1352 * add the nullbuf in the seg 1353 */ 1354 Tx->hw_list->seg[segment].data_count = 1355 htole32(ETHER_MIN_TX - size); 1356 Tx->hw_list->seg[segment].data_addr = 1357 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1358 size = ETHER_MIN_TX; 1359 segment++; 1360 } 1361 /* The list is done, finish the list init */ 1362 Tx->hw_list->seg[segment - 1].data_count |= 1363 htole32(TL_LAST_SEG); 1364 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1365 #ifdef TLDEBUG_TX 1366 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1367 le32toh(Tx->hw_list->stat)); 1368 #if 0 1369 for (segment = 0; segment < TL_NSEG; segment++) { 1370 printf(" seg %d addr 0x%x len 0x%x\n", 1371 segment, 1372 le32toh(Tx->hw_list->seg[segment].data_addr), 1373 le32toh(Tx->hw_list->seg[segment].data_count)); 1374 } 1375 #endif 1376 #endif 1377 if (sc->active_Tx == NULL) { 1378 sc->active_Tx = sc->last_Tx = Tx; 1379 #ifdef TLDEBUG_TX 1380 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1381 (int)Tx->hw_listaddr); 1382 #endif 1383 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1384 sizeof(struct tl_Tx_list) * TL_NBUF, 1385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1386 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1387 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1388 } else { 1389 #ifdef TLDEBUG_TX 1390 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1391 (int)Tx->hw_listaddr); 1392 #endif 1393 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1394 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1395 sizeof(struct tl_Tx_list) * TL_NBUF, 1396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1397 sc->last_Tx->next = Tx; 1398 sc->last_Tx = Tx; 1399 #ifdef DIAGNOSTIC 1400 if (sc->last_Tx->hw_list->fwd & 0x7) 1401 printf("%s: physical addr 0x%x of list not properly " 1402 "aligned\n", 1403 device_xname(sc->sc_dev), 1404 sc->last_Rx->hw_list->fwd); 1405 #endif 1406 } 1407 /* Pass packet to bpf if there is a listener */ 1408 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1409 /* 1410 * Set a 5 second timer just in case we don't hear from the card again. 1411 */ 1412 ifp->if_timer = 5; 1413 goto txloop; 1414 bad: 1415 #ifdef TLDEBUG 1416 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1417 #endif 1418 Tx->next = sc->Free_Tx; 1419 sc->Free_Tx = Tx; 1420 } 1421 1422 static void 1423 tl_ifwatchdog(struct ifnet *ifp) 1424 { 1425 tl_softc_t *sc = ifp->if_softc; 1426 1427 if ((ifp->if_flags & IFF_RUNNING) == 0) 1428 return; 1429 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1430 ifp->if_oerrors++; 1431 tl_init(ifp); 1432 } 1433 1434 static int 1435 tl_mediachange(struct ifnet *ifp) 1436 { 1437 1438 if (ifp->if_flags & IFF_UP) 1439 tl_init(ifp); 1440 return 0; 1441 } 1442 1443 static int 1444 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1445 { 1446 struct mbuf *m; 1447 int error; 1448 1449 MGETHDR(m, M_DONTWAIT, MT_DATA); 1450 if (m != NULL) { 1451 MCLGET(m, M_DONTWAIT); 1452 if ((m->m_flags & M_EXT) == 0) { 1453 m_freem(m); 1454 if (oldm == NULL) 1455 return 0; 1456 m = oldm; 1457 m->m_data = m->m_ext.ext_buf; 1458 } 1459 } else { 1460 if (oldm == NULL) 1461 return 0; 1462 m = oldm; 1463 m->m_data = m->m_ext.ext_buf; 1464 } 1465 1466 /* (re)init the Rx_list struct */ 1467 1468 Rx->m = m; 1469 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1470 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1471 printf("%s: bus_dmamap_load() failed (error %d) for " 1472 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1473 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1474 m_freem(m); 1475 Rx->m = NULL; 1476 return 0; 1477 } 1478 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1479 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1480 /* 1481 * Move the data pointer up so that the incoming data packet 1482 * will be 32-bit aligned. 1483 */ 1484 m->m_data += 2; 1485 1486 Rx->hw_list->stat = 1487 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1488 Rx->hw_list->seg.data_count = 1489 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1490 Rx->hw_list->seg.data_addr = 1491 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1492 return (m != oldm); 1493 } 1494 1495 static void 1496 tl_ticks(void *v) 1497 { 1498 tl_softc_t *sc = v; 1499 1500 tl_read_stats(sc); 1501 1502 /* Tick the MII. */ 1503 mii_tick(&sc->tl_mii); 1504 1505 /* read statistics every seconds */ 1506 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1507 } 1508 1509 static void 1510 tl_read_stats(tl_softc_t *sc) 1511 { 1512 uint32_t reg; 1513 int ierr_overr; 1514 int ierr_code; 1515 int ierr_crc; 1516 int oerr_underr; 1517 int oerr_deferred; 1518 int oerr_coll; 1519 int oerr_multicoll; 1520 int oerr_exesscoll; 1521 int oerr_latecoll; 1522 int oerr_carrloss; 1523 struct ifnet *ifp = &sc->tl_if; 1524 1525 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1526 ifp->if_opackets += reg & 0x00ffffff; 1527 oerr_underr = reg >> 24; 1528 1529 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1530 ifp->if_ipackets += reg & 0x00ffffff; 1531 ierr_overr = reg >> 24; 1532 1533 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1534 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1535 ierr_code = (reg & TL_FERR_CODE) >> 24; 1536 oerr_deferred = (reg & TL_FERR_DEF); 1537 1538 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1539 oerr_multicoll = (reg & TL_COL_MULTI); 1540 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1541 1542 reg = tl_intreg_read(sc, TL_INT_LERR); 1543 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1544 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1545 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1546 1547 1548 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1549 oerr_carrloss; 1550 ifp->if_collisions += oerr_coll + oerr_multicoll; 1551 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1552 1553 if (ierr_overr) 1554 printf("%s: receiver ring buffer overrun\n", 1555 device_xname(sc->sc_dev)); 1556 if (oerr_underr) 1557 printf("%s: transmit buffer underrun\n", 1558 device_xname(sc->sc_dev)); 1559 #ifdef TL_PRIV_STATS 1560 sc->ierr_overr += ierr_overr; 1561 sc->ierr_code += ierr_code; 1562 sc->ierr_crc += ierr_crc; 1563 sc->oerr_underr += oerr_underr; 1564 sc->oerr_deferred += oerr_deferred; 1565 sc->oerr_coll += oerr_coll; 1566 sc->oerr_multicoll += oerr_multicoll; 1567 sc->oerr_exesscoll += oerr_exesscoll; 1568 sc->oerr_latecoll += oerr_latecoll; 1569 sc->oerr_carrloss += oerr_carrloss; 1570 #endif 1571 } 1572 1573 static void 1574 tl_addr_filter(tl_softc_t *sc) 1575 { 1576 struct ether_multistep step; 1577 struct ether_multi *enm; 1578 uint32_t hash[2] = {0, 0}; 1579 int i; 1580 1581 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1582 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1583 while (enm != NULL) { 1584 #ifdef TLDEBUG 1585 printf("%s: addrs %s %s\n", __func__, 1586 ether_sprintf(enm->enm_addrlo), 1587 ether_sprintf(enm->enm_addrhi)); 1588 #endif 1589 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1590 i = tl_multicast_hash(enm->enm_addrlo); 1591 hash[i / 32] |= 1 << (i%32); 1592 } else { 1593 hash[0] = hash[1] = 0xffffffff; 1594 sc->tl_if.if_flags |= IFF_ALLMULTI; 1595 break; 1596 } 1597 ETHER_NEXT_MULTI(step, enm); 1598 } 1599 #ifdef TLDEBUG 1600 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1601 #endif 1602 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1603 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1604 } 1605 1606 static int 1607 tl_multicast_hash(uint8_t *a) 1608 { 1609 int hash; 1610 1611 #define DA(addr, bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1612 #define xor8(a, b, c, d, e, f, g, h) \ 1613 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1614 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1615 1616 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1617 DA(a,36), DA(a,42)); 1618 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1619 DA(a,37), DA(a,43)) << 1; 1620 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1621 DA(a,38), DA(a,44)) << 2; 1622 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1623 DA(a,39), DA(a,45)) << 3; 1624 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1625 DA(a,40), DA(a,46)) << 4; 1626 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1627 DA(a,41), DA(a,47)) << 5; 1628 1629 return hash; 1630 } 1631 1632 #if defined(TLDEBUG_RX) 1633 void 1634 ether_printheader(struct ether_header *eh) 1635 { 1636 uint8_t *c = (uint8_t *)eh; 1637 int i; 1638 1639 for (i = 0; i < sizeof(struct ether_header); i++) 1640 printf("%02x ", (u_int)c[i]); 1641 printf("\n"); 1642 } 1643 #endif 1644
Indexes created Wed Sep 24 05:09:52 GMT 2025