if_tl.c revision 1.12
1 /* $NetBSD: if_tl.c,v 1.12 1998/07/05 00:51:24 jonathan Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/mbuf.h> 49 #include <sys/protosw.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 56 #include <sys/device.h> 57 58 #include <net/if.h> 59 #if defined(SIOCSIFMEDIA) 60 #include <net/if_media.h> 61 #endif 62 #include <net/if_types.h> 63 #include <net/if_dl.h> 64 #include <net/route.h> 65 #include <net/netisr.h> 66 67 #include "bpfilter.h" 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #include <net/bpfdesc.h> 71 #endif 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #endif 79 80 #ifdef NS 81 #include <netns/ns.h> 82 #include <netns/ns_if.h> 83 #endif 84 85 #include <vm/vm.h> 86 #include <vm/vm_param.h> 87 #include <vm/vm_kern.h> 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #if defined(INET) 92 #include <netinet/if_inarp.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <dev/pci/pcidevs.h> 101 #include <dev/i2c/i2c_bus.h> 102 #include <dev/i2c/i2c_eeprom.h> 103 #include <dev/mii/mii_adapter.h> 104 #include <dev/mii/mii_adapters_id.h> 105 #include <dev/pci/if_tlregs.h> 106 #endif /* __NetBSD__ */ 107 108 /* number of transmit/receive buffers */ 109 #ifndef TL_NBUF 110 #define TL_NBUF 10 111 #endif 112 113 /* number of seconds the link can be idle */ 114 #ifndef TL_IDLETIME 115 #define TL_IDLETIME 10 116 #endif 117 118 struct tl_softc { 119 struct device sc_dev; /* base device */ 120 bus_space_tag_t tl_bustag; 121 bus_space_handle_t tl_bushandle; /* CSR region handle */ 122 void* tl_ih; 123 struct ethercom tl_ec; 124 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 125 struct ifmedia tl_ifmedia; 126 u_int16_t tl_flags; 127 #define TL_IFACT 0x0001 /* chip has interface activity */ 128 u_int8_t tl_lasttx; /* we were without input this many seconds */ 129 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 130 mii_data_t mii; /* mii bus */ 131 struct Rx_list *Rx_list; /* Receive and transmit lists */ 132 struct Tx_list *Tx_list; 133 struct Rx_list *active_Rx, *last_Rx; 134 struct Tx_list *active_Tx, *last_Tx; 135 struct Tx_list *Free_Tx; 136 int opkt; /* used to detect link up/down for AUI/BNC */ 137 int stats_exesscoll; /* idem */ 138 #ifdef TL_PRIV_STATS 139 int ierr_overr; 140 int ierr_code; 141 int ierr_crc; 142 int ierr_nomem; 143 int oerr_underr; 144 int oerr_deffered; 145 int oerr_coll; 146 int oerr_multicoll; 147 int oerr_latecoll; 148 int oerr_exesscoll; 149 int oerr_carrloss; 150 int oerr_mcopy; 151 #endif 152 }; 153 #define tl_if tl_ec.ec_if 154 #define tl_bpf tl_if.if_bpf 155 156 typedef struct tl_softc tl_softc_t; 157 typedef u_long ioctl_cmd_t; 158 159 #define TL_HR_READ(sc, reg) \ 160 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 161 #define TL_HR_READ_BYTE(sc, reg) \ 162 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 163 #define TL_HR_WRITE(sc, reg, data) \ 164 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 165 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 166 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 167 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 168 169 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 170 static void tl_pci_attach __P((struct device *, struct device *, void *)); 171 static int tl_intr __P((void *)); 172 173 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 174 static int tl_mediachange __P((struct ifnet *)); 175 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 176 static void tl_ifwatchdog __P((struct ifnet *)); 177 static void tl_shutdown __P((void*)); 178 179 static void tl_ifstart __P((struct ifnet *)); 180 static void tl_reset __P((tl_softc_t*)); 181 static int tl_init __P((tl_softc_t*)); 182 static void tl_restart __P((void *)); 183 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 184 static void tl_read_stats __P((tl_softc_t*)); 185 static void tl_ticks __P((void*)); 186 static int tl_multicast_hash __P((u_int8_t*)); 187 static void tl_addr_filter __P((tl_softc_t*)); 188 189 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 190 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 191 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 192 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 193 194 195 #if defined(TLDEBUG_RX) 196 static void ether_printheader __P((struct ether_header*)); 197 #endif 198 199 void tl_mii_set __P((void*, u_int8_t)); 200 void tl_mii_clr __P((void*, u_int8_t)); 201 int tl_mii_read __P((void*, u_int8_t)); 202 203 void tl_i2c_set __P((void*, u_int8_t)); 204 void tl_i2c_clr __P((void*, u_int8_t)); 205 int tl_i2c_read __P((void*, u_int8_t)); 206 207 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 208 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 209 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 210 static __inline void netsio_clr(sc, bits) 211 tl_softc_t* sc; 212 u_int8_t bits; 213 { 214 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 215 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 216 } 217 static __inline void netsio_set(sc, bits) 218 tl_softc_t* sc; 219 u_int8_t bits; 220 { 221 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 222 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 223 } 224 static __inline u_int8_t netsio_read(sc, bits) 225 tl_softc_t* sc; 226 u_int8_t bits; 227 { 228 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 229 } 230 231 struct cfattach tl_ca = { 232 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 233 }; 234 235 struct tl_product_desc { 236 u_int32_t tp_product; 237 u_int32_t tp_adapter; 238 int tp_flags; 239 const char *tp_desc; 240 }; 241 242 /* tp_flags */ 243 #define TPF_BROKEN_MEM 0x00000001 /* memory-mapped access is broken */ 244 245 const struct tl_product_desc tl_compaq_products[] = { 246 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 247 0, "Compaq Netelligent 10/100 TX" }, 248 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 249 0, "Compaq Netelligent 10 T" }, 250 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 251 0, "Compaq Integrated NetFlex 3/P" }, 252 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 253 0, "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 254 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 255 0, "Compaq Dual Port Netelligent 10/100 TX" }, 256 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 257 0, "Compaq Deskpro 4000 5233MMX" }, 258 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 259 0, "Compaq NetFlex 3/P w/ BNC" }, 260 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 261 0, "Compaq NetFlex 3/P" }, 262 { 0, 0, NULL }, 263 }; 264 265 const struct tl_product_desc tl_ti_products[] = { 266 /* 267 * Built-in Ethernet on the TI TravelMate 5000 268 * docking station; better product description? 269 * XXX Seems to have broken memory-mapped access. 270 */ 271 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 272 TPF_BROKEN_MEM, "Texas Instruments ThunderLAN" }, 273 { 0, 0, NULL }, 274 }; 275 276 struct tl_vendor_desc { 277 u_int32_t tv_vendor; 278 const struct tl_product_desc *tv_products; 279 }; 280 281 const struct tl_vendor_desc tl_vendors[] = { 282 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 283 { PCI_VENDOR_TI, tl_ti_products }, 284 { 0, NULL }, 285 }; 286 287 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 288 289 const struct tl_product_desc * 290 tl_lookup_product(id) 291 u_int32_t id; 292 { 293 const struct tl_product_desc *tp; 294 const struct tl_vendor_desc *tv; 295 296 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 297 if (PCI_VENDOR(id) == tv->tv_vendor) 298 break; 299 300 if ((tp = tv->tv_products) == NULL) 301 return (NULL); 302 303 for (; tp->tp_desc != NULL; tp++) 304 if (PCI_PRODUCT(id) == tp->tp_product) 305 break; 306 307 if (tp->tp_desc == NULL) 308 return (NULL); 309 310 return (tp); 311 } 312 313 static char *nullbuf = NULL; 314 315 static int 316 tl_pci_match(parent, match, aux) 317 struct device *parent; 318 struct cfdata *match; 319 void *aux; 320 { 321 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 322 323 if (tl_lookup_product(pa->pa_id) != NULL) 324 return (1); 325 326 return (0); 327 } 328 329 static void 330 tl_pci_attach(parent, self, aux) 331 struct device * parent; 332 struct device * self; 333 void * aux; 334 { 335 tl_softc_t *sc = (tl_softc_t *)self; 336 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 337 const struct tl_product_desc *tp; 338 struct ifnet * const ifp = &sc->tl_if; 339 bus_space_tag_t iot, memt; 340 bus_space_handle_t ioh, memh; 341 pci_intr_handle_t intrhandle; 342 const char *intrstr; 343 int i, tmp, ioh_valid, memh_valid; 344 pcireg_t csr; 345 346 printf("\n"); 347 348 tp = tl_lookup_product(pa->pa_id); 349 if (tp == NULL) 350 panic("tl_pci_attach: impossible"); 351 352 /* Map the card space. */ 353 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 354 &iot, &ioh, NULL, NULL) == 0); 355 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 356 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 357 0, &memt, &memh, NULL, NULL) == 0); 358 359 if (memh_valid && (tp->tp_flags & TPF_BROKEN_MEM) == 0) { 360 sc->tl_bustag = memt; 361 sc->tl_bushandle = memh; 362 } else if (ioh_valid) { 363 sc->tl_bustag = iot; 364 sc->tl_bushandle = ioh; 365 } else { 366 printf("%s: unable to map device registers\n", 367 sc->sc_dev.dv_xname); 368 return; 369 } 370 371 /* Enable the device. */ 372 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 373 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 374 csr | PCI_COMMAND_MASTER_ENABLE); 375 376 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 377 sc->mii.adapter_id = tp->tp_adapter; 378 379 tl_reset(sc); 380 381 /* fill in the i2c struct */ 382 sc->i2cbus.adapter_softc = sc; 383 sc->i2cbus.set_bit = tl_i2c_set; 384 sc->i2cbus.clr_bit = tl_i2c_clr; 385 sc->i2cbus.read_bit = tl_i2c_read; 386 387 #ifdef TLDEBUG 388 printf("default values of INTreg: 0x%x\n", 389 tl_intreg_read(sc, TL_INT_Defaults)); 390 #endif 391 392 /* read mac addr */ 393 for (i=0; i<ETHER_ADDR_LEN; i++) { 394 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 395 if (tmp < 0) { 396 printf("%s: error reading Ethernet adress\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } else { 400 sc->tl_enaddr[i] = tmp; 401 } 402 } 403 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 404 ether_sprintf(sc->tl_enaddr)); 405 406 /* Map and establish interrupts */ 407 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 408 pa->pa_intrline, &intrhandle)) { 409 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 410 return; 411 } 412 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 413 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 414 tl_intr, sc); 415 if (sc->tl_ih == NULL) { 416 printf("%s: couldn't establish interrupt", 417 sc->sc_dev.dv_xname); 418 if (intrstr != NULL) 419 printf(" at %s", intrstr); 420 printf("\n"); 421 return; 422 } 423 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 424 425 /* 426 * Add shutdown hook so that DMA is disabled prior to reboot. Not 427 * doing do could allow DMA to corrupt kernel memory during the 428 * reboot before the driver initializes. 429 */ 430 (void) shutdownhook_establish(tl_shutdown, sc); 431 432 sc->mii.adapter_softc = sc; 433 sc->mii.mii_setbit = tl_mii_set; 434 sc->mii.mii_clrbit = tl_mii_clr; 435 sc->mii.mii_readbit = tl_mii_read; 436 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 437 sc->mii.mii_writereg = NULL; 438 if (config_found(self, (void*)&sc->mii, mii_adapter_print) == NULL) { 439 return; 440 } 441 442 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 443 mii_media_add(&sc->tl_ifmedia, &sc->mii); 444 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 445 446 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 447 sc->tl_if.if_softc = sc; 448 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 449 ifp->if_ioctl = tl_ifioctl; 450 ifp->if_start = tl_ifstart; 451 ifp->if_watchdog = tl_ifwatchdog; 452 ifp->if_timer = 0; 453 if_attach(ifp); 454 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 455 #if NBPFILTER > 0 456 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 457 sizeof(struct ether_header)); 458 #endif 459 sc->mii.mii_media_active = IFM_NONE; 460 } 461 462 static void 463 tl_reset(sc) 464 tl_softc_t *sc; 465 { 466 int i; 467 468 /* read stats */ 469 if (sc->tl_if.if_flags & IFF_RUNNING) { 470 untimeout(tl_ticks, sc); 471 tl_read_stats(sc); 472 } 473 /* Reset adapter */ 474 TL_HR_WRITE(sc, TL_HOST_CMD, 475 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 476 DELAY(100000); 477 /* Disable interrupts */ 478 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 479 /* setup aregs & hash */ 480 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 481 tl_intreg_write(sc, i, 0); 482 #ifdef TLDEBUG_ADDR 483 printf("Areg & hash registers: \n"); 484 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 485 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 486 #endif 487 /* Setup NetConfig */ 488 tl_intreg_write(sc, TL_INT_NetConfig, 489 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 490 /* Bsize: accept default */ 491 /* TX commit in Acommit: accept default */ 492 /* Load Ld_tmr and Ld_thr */ 493 /* Ld_tmr = 3 */ 494 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 495 /* Ld_thr = 0 */ 496 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 497 /* Unreset MII */ 498 netsio_set(sc, TL_NETSIO_NMRST); 499 DELAY(100000); 500 sc->mii.mii_media_status &= ~IFM_ACTIVE; 501 sc->tl_flags = 0; 502 sc->opkt = 0; 503 sc->stats_exesscoll = 0; 504 } 505 506 static void tl_shutdown(v) 507 void *v; 508 { 509 tl_softc_t *sc = v; 510 struct Tx_list *Tx; 511 int i; 512 513 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 514 return; 515 /* disable interrupts */ 516 TL_HR_WRITE(sc, TL_HOST_CMD, 517 HOST_CMD_IntOff); 518 /* stop TX and RX channels */ 519 TL_HR_WRITE(sc, TL_HOST_CMD, 520 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 521 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 522 DELAY(100000); 523 524 /* stop statistics reading loop, read stats */ 525 untimeout(tl_ticks, sc); 526 tl_read_stats(sc); 527 528 /* deallocate memory allocations */ 529 for (i=0; i< TL_NBUF; i++) { 530 if (sc->Rx_list[i].m) 531 m_freem(sc->Rx_list[i].m); 532 sc->Rx_list[i].m = NULL; 533 } 534 free(sc->Rx_list, M_DEVBUF); 535 sc->Rx_list = NULL; 536 while ((Tx = sc->active_Tx) != NULL) { 537 Tx->hw_list.stat = 0; 538 m_freem(Tx->m); 539 sc->active_Tx = Tx->next; 540 Tx->next = sc->Free_Tx; 541 sc->Free_Tx = Tx; 542 } 543 sc->last_Tx = NULL; 544 free(sc->Tx_list, M_DEVBUF); 545 sc->Tx_list = NULL; 546 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 547 sc->mii.mii_media_status &= ~IFM_ACTIVE; 548 sc->tl_flags = 0; 549 } 550 551 static void tl_restart(v) 552 void *v; 553 { 554 tl_init(v); 555 } 556 557 static int tl_init(sc) 558 tl_softc_t *sc; 559 { 560 struct ifnet *ifp = &sc->tl_if; 561 int i, s; 562 563 s = splimp(); 564 /* cancel any pending IO */ 565 tl_shutdown(sc); 566 tl_reset(sc); 567 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 568 splx(s); 569 return 0; 570 } 571 /* Set various register to reasonable value */ 572 /* setup NetCmd in promisc mode if needed */ 573 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 574 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 575 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 576 /* Max receive size : MCLBYTES */ 577 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 578 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 579 (MCLBYTES >> 8) & 0xff); 580 581 /* init MAC addr */ 582 for (i = 0; i < ETHER_ADDR_LEN; i++) 583 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 584 /* add multicast filters */ 585 tl_addr_filter(sc); 586 #ifdef TLDEBUG_ADDR 587 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 588 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 589 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 590 #endif 591 592 /* Pre-allocate receivers mbuf, make the lists */ 593 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 594 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 595 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 596 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 597 sc->tl_if.if_flags &= ~IFF_UP; 598 splx(s); 599 return ENOMEM; 600 } 601 for (i=0; i< TL_NBUF; i++) { 602 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 603 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 604 sc->tl_if.if_flags &= ~IFF_UP; 605 splx(s); 606 return ENOMEM; 607 } 608 if (i > 0) { /* chain the list */ 609 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 610 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 611 #ifdef DIAGNOSTIC 612 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 613 printf("%s: physical addr 0x%x of list not properly aligned\n", 614 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 615 #endif 616 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 617 } 618 } 619 sc->Rx_list[TL_NBUF-1].next = NULL; 620 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 621 sc->Tx_list[TL_NBUF-1].next = NULL; 622 623 sc->active_Rx = &sc->Rx_list[0]; 624 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 625 sc->active_Tx = sc->last_Tx = NULL; 626 sc->Free_Tx = &sc->Tx_list[0]; 627 628 if (nullbuf == NULL) 629 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 630 if (nullbuf == NULL) { 631 printf("%s: can't allocate space for pad buffer\n", 632 sc->sc_dev.dv_xname); 633 sc->tl_if.if_flags &= ~IFF_UP; 634 splx(s); 635 return ENOMEM; 636 } 637 bzero(nullbuf, ETHER_MIN_TX); 638 639 /* set media if needed */ 640 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 641 mii_mediachg(&sc->mii); 642 } 643 644 /* start ticks calls */ 645 timeout(tl_ticks, sc, hz); 646 /* write adress of Rx list and enable interrupts */ 647 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 648 TL_HR_WRITE(sc, TL_HOST_CMD, 649 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 650 sc->tl_if.if_flags |= IFF_RUNNING; 651 sc->tl_if.if_flags &= ~IFF_OACTIVE; 652 return 0; 653 } 654 655 656 static u_int32_t 657 tl_intreg_read(sc, reg) 658 tl_softc_t *sc; 659 u_int32_t reg; 660 { 661 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 662 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 663 } 664 665 static u_int8_t 666 tl_intreg_read_byte(sc, reg) 667 tl_softc_t *sc; 668 u_int32_t reg; 669 { 670 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 671 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 672 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 673 } 674 675 static void 676 tl_intreg_write(sc, reg, val) 677 tl_softc_t *sc; 678 u_int32_t reg; 679 u_int32_t val; 680 { 681 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 682 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 683 } 684 685 static void 686 tl_intreg_write_byte(sc, reg, val) 687 tl_softc_t *sc; 688 u_int32_t reg; 689 u_int8_t val; 690 { 691 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 692 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 693 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 694 } 695 696 void tl_mii_set(v, bit) 697 void *v; 698 u_int8_t bit; 699 { 700 tl_softc_t *sc = v; 701 702 switch (bit) { 703 case MII_DATA: 704 netsio_set(sc, TL_NETSIO_MDATA); 705 break; 706 case MII_CLOCK: 707 netsio_set(sc, TL_NETSIO_MCLK); 708 break; 709 case MII_TXEN: 710 netsio_set(sc, TL_NETSIO_MTXEN); 711 break; 712 default: 713 printf("tl_mii_set: unknown bit %d\n", bit); 714 } 715 } 716 717 void tl_mii_clr(v, bit) 718 void *v; 719 u_int8_t bit; 720 { 721 tl_softc_t *sc = v; 722 723 switch (bit) { 724 case MII_DATA: 725 netsio_clr(sc, TL_NETSIO_MDATA); 726 break; 727 case MII_CLOCK: 728 netsio_clr(sc, TL_NETSIO_MCLK); 729 break; 730 case MII_TXEN: 731 netsio_clr(sc, TL_NETSIO_MTXEN); 732 break; 733 default: 734 printf("tl_mii_clr: unknown bit %d\n", bit); 735 } 736 return; 737 } 738 739 int tl_mii_read(v, bit) 740 void *v; 741 u_int8_t bit; 742 { 743 tl_softc_t *sc = v; 744 745 switch (bit) { 746 case MII_DATA: 747 return netsio_read(sc, TL_NETSIO_MDATA); 748 break; 749 case MII_CLOCK: 750 return netsio_read(sc, TL_NETSIO_MCLK); 751 break; 752 case MII_TXEN: 753 return netsio_read(sc, TL_NETSIO_MTXEN); 754 break; 755 default: 756 printf("tl_mii_read: unknown bit %d\n", bit); 757 return -1; 758 } 759 } 760 761 void tl_i2c_set(v, bit) 762 void *v; 763 u_int8_t bit; 764 { 765 tl_softc_t *sc = v; 766 767 switch (bit) { 768 case I2C_DATA: 769 netsio_set(sc, TL_NETSIO_EDATA); 770 break; 771 case I2C_CLOCK: 772 netsio_set(sc, TL_NETSIO_ECLOCK); 773 break; 774 case I2C_TXEN: 775 netsio_set(sc, TL_NETSIO_ETXEN); 776 break; 777 default: 778 printf("tl_i2c_set: unknown bit %d\n", bit); 779 } 780 return; 781 } 782 783 void tl_i2c_clr(v, bit) 784 void *v; 785 u_int8_t bit; 786 { 787 tl_softc_t *sc = v; 788 789 switch (bit) { 790 case I2C_DATA: 791 netsio_clr(sc, TL_NETSIO_EDATA); 792 break; 793 case I2C_CLOCK: 794 netsio_clr(sc, TL_NETSIO_ECLOCK); 795 break; 796 case I2C_TXEN: 797 netsio_clr(sc, TL_NETSIO_ETXEN); 798 break; 799 default: 800 printf("tl_i2c_clr: unknown bit %d\n", bit); 801 } 802 return; 803 } 804 805 int tl_i2c_read(v, bit) 806 void *v; 807 u_int8_t bit; 808 { 809 tl_softc_t *sc = v; 810 811 switch (bit) { 812 case I2C_DATA: 813 return netsio_read(sc, TL_NETSIO_EDATA); 814 break; 815 case I2C_CLOCK: 816 return netsio_read(sc, TL_NETSIO_ECLOCK); 817 break; 818 case I2C_TXEN: 819 return netsio_read(sc, TL_NETSIO_ETXEN); 820 break; 821 default: 822 printf("tl_i2c_read: unknown bit %d\n", bit); 823 return -1; 824 } 825 } 826 827 static int 828 tl_intr(v) 829 void *v; 830 { 831 tl_softc_t *sc = v; 832 struct ifnet *ifp = &sc->tl_if; 833 struct Rx_list *Rx; 834 struct Tx_list *Tx; 835 struct mbuf *m; 836 u_int32_t int_type, int_reg; 837 int ack = 0; 838 int size; 839 840 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 841 int_type = int_reg & TL_INTR_MASK; 842 if (int_type == 0) 843 return 0; 844 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 845 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 846 int_type, int_reg); 847 #endif 848 /* disable interrupts */ 849 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 850 switch(int_type & TL_INTR_MASK) { 851 case TL_INTR_RxEOF: 852 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 853 /* dequeue and requeue at end of list */ 854 ack++; 855 Rx = sc->active_Rx; 856 sc->active_Rx = Rx->next; 857 m = Rx->m; 858 size = Rx->hw_list.stat >> 16; 859 #ifdef TLDEBUG_RX 860 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 861 #endif 862 if (tl_add_RxBuff(Rx, m ) == 0) { 863 /* No new mbuf, reuse the same. This means that this packet 864 is lost */ 865 m = NULL; 866 #ifdef TL_PRIV_STATS 867 sc->ierr_nomem++; 868 #endif 869 #ifdef TLDEBUG 870 printf("%s: out of mbuf, lost input packet\n", 871 sc->sc_dev.dv_xname); 872 #endif 873 } 874 Rx->next = NULL; 875 Rx->hw_list.fwd = 0; 876 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 877 #ifdef DIAGNOSTIC 878 if (sc->last_Rx->hw_list.fwd & 0x7) 879 printf("%s: physical addr 0x%x of list not properly aligned\n", 880 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 881 #endif 882 sc->last_Rx->next = Rx; 883 sc->last_Rx = Rx; 884 885 /* deliver packet */ 886 if (m) { 887 struct ether_header *eh; 888 if (size < sizeof(struct ether_header)) { 889 m_freem(m); 890 continue; 891 } 892 m->m_pkthdr.rcvif = ifp; 893 m->m_pkthdr.len = m->m_len = 894 size - sizeof(struct ether_header); 895 eh = mtod(m, struct ether_header *); 896 #ifdef TLDEBUG_RX 897 printf("tl_intr: Rx packet:\n"); 898 ether_printheader(eh); 899 #endif 900 #if NBPFILTER > 0 901 if (ifp->if_bpf) { 902 bpf_tap(ifp->if_bpf, 903 mtod(m, caddr_t), 904 size); 905 /* 906 * Only pass this packet up 907 * if it is for us. 908 */ 909 if ((ifp->if_flags & IFF_PROMISC) && 910 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 911 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 912 sizeof(eh->ether_dhost)) != 0) { 913 m_freem(m); 914 continue; 915 } 916 } 917 #endif /* NBPFILTER > 0 */ 918 m->m_data += sizeof(struct ether_header); 919 ether_input(ifp, eh, m); 920 } 921 } 922 #ifdef TLDEBUG_RX 923 printf("TL_INTR_RxEOF: ack %d\n", ack); 924 #else 925 if (ack == 0) { 926 printf("%s: EOF intr without anything to read !\n", 927 sc->sc_dev.dv_xname); 928 tl_reset(sc); 929 /* shedule reinit of the board */ 930 timeout(tl_restart, sc, 1); 931 return(1); 932 } 933 #endif 934 break; 935 case TL_INTR_RxEOC: 936 ack++; 937 #ifdef TLDEBUG_RX 938 printf("TL_INTR_RxEOC: ack %d\n", ack); 939 #endif 940 #ifdef DIAGNOSTIC 941 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 942 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 943 sc->sc_dev.dv_xname); 944 return 0; 945 } else 946 #endif 947 { 948 /* write adress of Rx list and send Rx GO command, ack interrupt 949 and enable interrupts in one command */ 950 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 951 vtophys(&sc->active_Rx->hw_list)); 952 TL_HR_WRITE(sc, TL_HOST_CMD, 953 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 954 HOST_CMD_ACK | HOST_CMD_IntOn); 955 return 1; 956 } 957 case TL_INTR_TxEOF: 958 case TL_INTR_TxEOC: 959 while ((Tx = sc->active_Tx) != NULL) { 960 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 961 break; 962 ack++; 963 #ifdef TLDEBUG_TX 964 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 965 #endif 966 Tx->hw_list.stat = 0; 967 m_freem(Tx->m); 968 Tx->m = NULL; 969 sc->active_Tx = Tx->next; 970 if (sc->active_Tx == NULL) 971 sc->last_Tx = NULL; 972 Tx->next = sc->Free_Tx; 973 sc->Free_Tx = Tx; 974 } 975 /* if this was an EOC, ACK immediatly */ 976 if (int_type == TL_INTR_TxEOC) { 977 #ifdef TLDEBUG_TX 978 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 979 #endif 980 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 981 HOST_CMD_IntOn); 982 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 983 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 984 vtophys(&sc->active_Tx->hw_list)); 985 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 986 } 987 sc->tl_if.if_timer = 0; 988 if (sc->tl_if.if_snd.ifq_head != NULL) 989 tl_ifstart(&sc->tl_if); 990 return 1; 991 } 992 #ifdef TLDEBUG 993 else { 994 printf("TL_INTR_TxEOF: ack %d\n", ack); 995 } 996 #endif 997 sc->tl_if.if_timer = 0; 998 if (sc->tl_if.if_snd.ifq_head != NULL) 999 tl_ifstart(&sc->tl_if); 1000 break; 1001 case TL_INTR_Stat: 1002 ack++; 1003 #ifdef TLDEBUG 1004 printf("TL_INTR_Stat: ack %d\n", ack); 1005 #endif 1006 tl_read_stats(sc); 1007 break; 1008 case TL_INTR_Adc: 1009 if (int_reg & TL_INTVec_MASK) { 1010 /* adapter check conditions */ 1011 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1012 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1013 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1014 tl_reset(sc); 1015 /* shedule reinit of the board */ 1016 timeout(tl_restart, sc, 1); 1017 return(1); 1018 } else { 1019 u_int8_t netstat; 1020 /* Network status */ 1021 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1022 printf("%s: network status, NetSts=%x\n", 1023 sc->sc_dev.dv_xname, netstat); 1024 /* Ack interrupts */ 1025 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1026 ack++; 1027 } 1028 break; 1029 default: 1030 printf("%s: unhandled interrupt code %x!\n", 1031 sc->sc_dev.dv_xname, int_type); 1032 ack++; 1033 } 1034 1035 if (ack) { 1036 /* Ack the interrupt and enable interrupts */ 1037 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1038 HOST_CMD_IntOn); 1039 return 1; 1040 } 1041 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1042 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1043 return 0; 1044 } 1045 1046 static int 1047 tl_ifioctl(ifp, cmd, data) 1048 struct ifnet *ifp; 1049 ioctl_cmd_t cmd; 1050 caddr_t data; 1051 { 1052 struct tl_softc *sc = ifp->if_softc; 1053 struct ifreq *ifr = (struct ifreq *)data; 1054 int s, error; 1055 1056 s = splimp(); 1057 switch(cmd) { 1058 case SIOCSIFADDR: { 1059 struct ifaddr *ifa = (struct ifaddr *)data; 1060 sc->tl_if.if_flags |= IFF_UP; 1061 if ((error = tl_init(sc)) != NULL) { 1062 sc->tl_if.if_flags &= ~IFF_UP; 1063 break; 1064 } 1065 switch (ifa->ifa_addr->sa_family) { 1066 #ifdef INET 1067 case AF_INET: 1068 arp_ifinit(ifp, ifa); 1069 break; 1070 #endif 1071 #ifdef NS 1072 case AF_NS: { 1073 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1074 1075 if (ns_nullhost(*ina)) 1076 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1077 else 1078 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1079 ifp->if_addrlen); 1080 break; 1081 } 1082 #endif 1083 default: 1084 break; 1085 } 1086 break; 1087 } 1088 case SIOCSIFFLAGS: 1089 { 1090 u_int8_t reg; 1091 /* 1092 * If interface is marked up and not running, then start it. 1093 * If it is marked down and running, stop it. 1094 */ 1095 if (ifp->if_flags & IFF_UP) { 1096 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1097 error = tl_init(sc); 1098 /* all flags have been handled by init */ 1099 break; 1100 } 1101 error = 0; 1102 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1103 if (ifp->if_flags & IFF_PROMISC) 1104 reg |= TL_NETCOMMAND_CAF; 1105 else 1106 reg &= ~TL_NETCOMMAND_CAF; 1107 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1108 #ifdef TL_PRIV_STATS 1109 if (ifp->if_flags & IFF_LINK0) { 1110 ifp->if_flags &= ~IFF_LINK0; 1111 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1112 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1113 printf(" %4d RX code error\n", sc->ierr_code); 1114 printf(" %4d RX crc error\n", sc->ierr_crc); 1115 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1116 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1117 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1118 printf(" %4d TX single collisions\n", sc->oerr_coll); 1119 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1120 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1121 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1122 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1123 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1124 } 1125 #endif 1126 } else { 1127 if (ifp->if_flags & IFF_RUNNING) 1128 tl_shutdown(sc); 1129 error = 0; 1130 } 1131 break; 1132 } 1133 case SIOCADDMULTI: 1134 case SIOCDELMULTI: 1135 /* 1136 * Update multicast listeners 1137 */ 1138 if (cmd == SIOCADDMULTI) 1139 error = ether_addmulti(ifr, &sc->tl_ec); 1140 else 1141 error = ether_delmulti(ifr, &sc->tl_ec); 1142 if (error == ENETRESET) { 1143 tl_addr_filter(sc); 1144 error = 0; 1145 } 1146 break; 1147 case SIOCSIFMEDIA: 1148 case SIOCGIFMEDIA: 1149 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1150 break; 1151 default: 1152 error = EINVAL; 1153 } 1154 splx(s); 1155 return error; 1156 } 1157 1158 static void 1159 tl_ifstart(ifp) 1160 struct ifnet *ifp; 1161 { 1162 tl_softc_t *sc = ifp->if_softc; 1163 struct mbuf *m, *mb_head; 1164 struct Tx_list *Tx; 1165 int segment, size; 1166 1167 txloop: 1168 /* If we don't have more space ... */ 1169 if (sc->Free_Tx == NULL) { 1170 #ifdef TLDEBUG 1171 printf("tl_ifstart: No free TX list\n"); 1172 #endif 1173 return; 1174 } 1175 /* Grab a paquet for output */ 1176 IF_DEQUEUE(&ifp->if_snd, mb_head); 1177 if (mb_head == NULL) { 1178 #ifdef TLDEBUG_TX 1179 printf("tl_ifstart: nothing to send\n"); 1180 #endif 1181 return; 1182 } 1183 Tx = sc->Free_Tx; 1184 sc->Free_Tx = Tx->next; 1185 /* 1186 * Go through each of the mbufs in the chain and initialize 1187 * the transmit list descriptors with the physical address 1188 * and size of the mbuf. 1189 */ 1190 tbdinit: 1191 bzero(Tx, sizeof(struct Tx_list)); 1192 Tx->m = mb_head; 1193 size = 0; 1194 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1195 if (m->m_len != 0) { 1196 if (segment == TL_NSEG) 1197 break; 1198 size += m->m_len; 1199 Tx->hw_list.seg[segment].data_addr = 1200 vtophys(mtod(m, vm_offset_t)); 1201 Tx->hw_list.seg[segment].data_count = m->m_len; 1202 segment++; 1203 } 1204 } 1205 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1206 /* 1207 * We ran out of segments, or we will. We have to recopy this mbuf 1208 * chain first. 1209 */ 1210 struct mbuf *mn; 1211 #ifdef TLDEBUG_TX 1212 printf("tl_ifstart: need to copy mbuf\n"); 1213 #endif 1214 #ifdef TL_PRIV_STATS 1215 sc->oerr_mcopy++; 1216 #endif 1217 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1218 if (mn == NULL) { 1219 m_freem(mb_head); 1220 goto bad; 1221 } 1222 if (mb_head->m_pkthdr.len > MHLEN) { 1223 MCLGET(mn, M_DONTWAIT); 1224 if ((mn->m_flags & M_EXT) == 0) { 1225 m_freem(mn); 1226 m_freem(mb_head); 1227 goto bad; 1228 } 1229 } 1230 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1231 mtod(mn, caddr_t)); 1232 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1233 m_freem(mb_head); 1234 mb_head = mn; 1235 goto tbdinit; 1236 } 1237 /* We are at end of mbuf chain. check the size and 1238 * see if it needs to be extended 1239 */ 1240 if (size < ETHER_MIN_TX) { 1241 #ifdef DIAGNOSTIC 1242 if (segment >= TL_NSEG) { 1243 panic("tl_ifstart: to much segmets (%d)\n", segment); 1244 } 1245 #endif 1246 /* 1247 * add the nullbuf in the seg 1248 */ 1249 Tx->hw_list.seg[segment].data_count = 1250 ETHER_MIN_TX - size; 1251 Tx->hw_list.seg[segment].data_addr = 1252 vtophys(nullbuf); 1253 size = ETHER_MIN_TX; 1254 segment++; 1255 } 1256 /* The list is done, finish the list init */ 1257 Tx->hw_list.seg[segment-1].data_count |= 1258 TL_LAST_SEG; 1259 Tx->hw_list.stat = (size << 16) | 0x3000; 1260 #ifdef TLDEBUG_TX 1261 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1262 Tx->hw_list.stat); 1263 #if 0 1264 for(segment = 0; segment < TL_NSEG; segment++) { 1265 printf(" seg %d addr 0x%x len 0x%x\n", 1266 segment, 1267 Tx->hw_list.seg[segment].data_addr, 1268 Tx->hw_list.seg[segment].data_count); 1269 } 1270 #endif 1271 #endif 1272 sc->opkt++; 1273 if (sc->active_Tx == NULL) { 1274 sc->active_Tx = sc->last_Tx = Tx; 1275 #ifdef TLDEBUG_TX 1276 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1277 vtophys(&Tx->hw_list)); 1278 #endif 1279 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1280 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1281 } else { 1282 #ifdef TLDEBUG_TX 1283 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1284 vtophys(&Tx->hw_list)); 1285 #endif 1286 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1287 sc->last_Tx->next = Tx; 1288 sc->last_Tx = Tx; 1289 #ifdef DIAGNOSTIC 1290 if (sc->last_Tx->hw_list.fwd & 0x7) 1291 printf("%s: physical addr 0x%x of list not properly aligned\n", 1292 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1293 #endif 1294 } 1295 #if NBPFILTER > 0 1296 /* Pass packet to bpf if there is a listener */ 1297 if (ifp->if_bpf) 1298 bpf_mtap(ifp->if_bpf, mb_head); 1299 #endif 1300 /* Set a 5 second timer just in case we don't hear from the card again. */ 1301 ifp->if_timer = 5; 1302 1303 goto txloop; 1304 bad: 1305 #ifdef TLDEBUG 1306 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1307 #endif 1308 Tx->next = sc->Free_Tx; 1309 sc->Free_Tx = Tx; 1310 return; 1311 } 1312 1313 static void 1314 tl_ifwatchdog(ifp) 1315 struct ifnet *ifp; 1316 { 1317 tl_softc_t *sc = ifp->if_softc; 1318 1319 if ((ifp->if_flags & IFF_RUNNING) == 0) 1320 return; 1321 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1322 ifp->if_oerrors++; 1323 tl_init(sc); 1324 } 1325 1326 static int 1327 tl_mediachange(ifp) 1328 struct ifnet *ifp; 1329 { 1330 1331 tl_softc_t *sc = ifp->if_softc; 1332 int err; 1333 u_int32_t reg; 1334 int oldmedia; 1335 #ifdef TLDEBUG 1336 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1337 #endif 1338 oldmedia = sc->mii.mii_media_active; 1339 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1340 if ((err = mii_mediachg(&sc->mii)) != 0) 1341 sc->mii.mii_media_active = oldmedia; 1342 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1343 if (sc->mii.mii_media_active & IFM_FDX) 1344 reg |= TL_NETCOMMAND_DUPLEX; 1345 else 1346 reg &= ~TL_NETCOMMAND_DUPLEX; 1347 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1348 return err; 1349 } 1350 1351 static void 1352 tl_mediastatus(ifp, ifmr) 1353 struct ifnet *ifp; 1354 struct ifmediareq *ifmr; 1355 { 1356 tl_softc_t *sc = ifp->if_softc; 1357 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1358 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1359 if (sc->tl_flags & TL_IFACT) 1360 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1361 else 1362 sc->mii.mii_media_status = IFM_AVALID; 1363 else 1364 mii_pollstat(&sc->mii); 1365 1366 ifmr->ifm_active = sc->mii.mii_media_active; 1367 ifmr->ifm_status = sc->mii.mii_media_status; 1368 } 1369 1370 static int tl_add_RxBuff(Rx, oldm) 1371 struct Rx_list *Rx; 1372 struct mbuf *oldm; 1373 { 1374 struct mbuf *m; 1375 1376 MGETHDR(m, M_DONTWAIT, MT_DATA); 1377 if (m != NULL) { 1378 MCLGET(m, M_DONTWAIT); 1379 if ((m->m_flags & M_EXT) == 0) { 1380 m_freem(m); 1381 if (oldm == NULL) 1382 return 0; 1383 m = oldm; 1384 m->m_data = m->m_ext.ext_buf; 1385 } 1386 } else { 1387 if (oldm == NULL) 1388 return 0; 1389 m = oldm; 1390 m->m_data = m->m_ext.ext_buf; 1391 } 1392 /* 1393 * Move the data pointer up so that the incoming data packet 1394 * will be 32-bit aligned. 1395 */ 1396 m->m_data += 2; 1397 1398 /* (re)init the Rx_list struct */ 1399 1400 Rx->m = m; 1401 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1402 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1403 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1404 return (m != oldm); 1405 } 1406 1407 static void tl_ticks(v) 1408 void *v; 1409 { 1410 tl_softc_t *sc = v; 1411 1412 tl_read_stats(sc); 1413 if (sc->opkt > 0) { 1414 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1415 if (sc->tl_flags & TL_IFACT) /* only print once */ 1416 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1417 sc->tl_flags &= ~TL_IFACT; 1418 } else 1419 sc->tl_flags |= TL_IFACT; 1420 sc->oerr_exesscoll = sc->opkt = 0; 1421 sc->tl_lasttx = 0; 1422 } else { 1423 sc->tl_lasttx++; 1424 if (sc->tl_lasttx >= TL_IDLETIME) { 1425 /* 1426 * No TX activity in the last TL_IDLETIME seconds. 1427 * sends a LLC Class1 TEST pkt 1428 */ 1429 struct mbuf *m; 1430 int s; 1431 MGETHDR(m, M_DONTWAIT, MT_DATA); 1432 if (m != NULL) { 1433 #ifdef TLDEBUG 1434 printf("tl_ticks: sending LLC test pkt\n"); 1435 #endif 1436 bcopy(sc->tl_enaddr, 1437 mtod(m, struct ether_header *)->ether_dhost, 6); 1438 bcopy(sc->tl_enaddr, 1439 mtod(m, struct ether_header *)->ether_shost, 6); 1440 mtod(m, struct ether_header *)->ether_type = htons(3); 1441 mtod(m, unsigned char *)[14] = 0; 1442 mtod(m, unsigned char *)[15] = 0; 1443 mtod(m, unsigned char *)[16] = 0xE3; 1444 /* LLC Class1 TEST (no poll) */ 1445 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1446 s = splnet(); 1447 IF_PREPEND(&sc->tl_if.if_snd, m); 1448 tl_ifstart(&sc->tl_if); 1449 splx(s); 1450 } 1451 } 1452 } 1453 1454 /* read statistics every seconds */ 1455 timeout(tl_ticks, v, hz); 1456 } 1457 1458 static void 1459 tl_read_stats(sc) 1460 tl_softc_t *sc; 1461 { 1462 u_int32_t reg; 1463 int ierr_overr; 1464 int ierr_code; 1465 int ierr_crc; 1466 int oerr_underr; 1467 int oerr_deffered; 1468 int oerr_coll; 1469 int oerr_multicoll; 1470 int oerr_exesscoll; 1471 int oerr_latecoll; 1472 int oerr_carrloss; 1473 struct ifnet *ifp = &sc->tl_if; 1474 1475 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1476 ifp->if_opackets += reg & 0x00ffffff; 1477 oerr_underr = reg >> 24; 1478 1479 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1480 ifp->if_ipackets += reg & 0x00ffffff; 1481 ierr_overr = reg >> 24; 1482 1483 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1484 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1485 ierr_code = (reg & TL_FERR_CODE) >> 24; 1486 oerr_deffered = (reg & TL_FERR_DEF); 1487 1488 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1489 oerr_multicoll = (reg & TL_COL_MULTI); 1490 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1491 1492 reg = tl_intreg_read(sc, TL_INT_LERR); 1493 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1494 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1495 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1496 1497 1498 sc->stats_exesscoll += oerr_exesscoll; 1499 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1500 oerr_carrloss; 1501 ifp->if_collisions += oerr_coll + oerr_multicoll; 1502 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1503 1504 if (ierr_overr) 1505 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1506 if (oerr_underr) 1507 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1508 #ifdef TL_PRIV_STATS 1509 sc->ierr_overr += ierr_overr; 1510 sc->ierr_code += ierr_code; 1511 sc->ierr_crc += ierr_crc; 1512 sc->oerr_underr += oerr_underr; 1513 sc->oerr_deffered += oerr_deffered; 1514 sc->oerr_coll += oerr_coll; 1515 sc->oerr_multicoll += oerr_multicoll; 1516 sc->oerr_exesscoll += oerr_exesscoll; 1517 sc->oerr_latecoll += oerr_latecoll; 1518 sc->oerr_carrloss += oerr_carrloss; 1519 #endif 1520 } 1521 1522 static void tl_addr_filter(sc) 1523 tl_softc_t *sc; 1524 { 1525 struct ether_multistep step; 1526 struct ether_multi *enm; 1527 u_int32_t hash[2] = {0, 0}; 1528 int i; 1529 1530 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1531 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1532 while (enm != NULL) { 1533 #ifdef TLDEBUG 1534 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1535 #endif 1536 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1537 i = tl_multicast_hash(enm->enm_addrlo); 1538 hash[i/32] |= 1 << (i%32); 1539 } else { 1540 hash[0] = hash[1] = 0xffffffff; 1541 sc->tl_if.if_flags |= IFF_ALLMULTI; 1542 break; 1543 } 1544 ETHER_NEXT_MULTI(step, enm); 1545 } 1546 #ifdef TLDEBUG 1547 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1548 #endif 1549 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1550 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1551 } 1552 1553 static int tl_multicast_hash(a) 1554 u_int8_t *a; 1555 { 1556 int hash; 1557 1558 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1559 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1560 1561 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1562 DA(a,36), DA(a,42)); 1563 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1564 DA(a,37), DA(a,43)) << 1; 1565 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1566 DA(a,38), DA(a,44)) << 2; 1567 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1568 DA(a,39), DA(a,45)) << 3; 1569 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1570 DA(a,40), DA(a,46)) << 4; 1571 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1572 DA(a,41), DA(a,47)) << 5; 1573 1574 return hash; 1575 } 1576 1577 #if defined(TLDEBUG_RX) 1578 void ether_printheader(eh) 1579 struct ether_header *eh; 1580 { 1581 u_char *c = (char*)eh; 1582 int i; 1583 for (i=0; i<sizeof(struct ether_header); i++) 1584 printf("%x ", (u_int)c[i]); 1585 printf("\n"); 1586 } 1587 #endif 1588
Indexes created Thu Sep 25 16:09:42 GMT 2025