if_tl.c revision 1.14
1 /* $NetBSD: if_tl.c,v 1.14 1998/08/08 23:51:42 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 #include <dev/i2c/i2c_bus.h> 103 #include <dev/i2c/i2c_eeprom.h> 104 #include <dev/mii/mii_adapter.h> 105 #include <dev/mii/mii_adapters_id.h> 106 #include <dev/pci/if_tlregs.h> 107 #endif /* __NetBSD__ */ 108 109 /* number of transmit/receive buffers */ 110 #ifndef TL_NBUF 111 #define TL_NBUF 10 112 #endif 113 114 /* number of seconds the link can be idle */ 115 #ifndef TL_IDLETIME 116 #define TL_IDLETIME 10 117 #endif 118 119 struct tl_softc { 120 struct device sc_dev; /* base device */ 121 bus_space_tag_t tl_bustag; 122 bus_space_handle_t tl_bushandle; /* CSR region handle */ 123 void* tl_ih; 124 struct ethercom tl_ec; 125 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 126 struct ifmedia tl_ifmedia; 127 u_int16_t tl_flags; 128 #define TL_IFACT 0x0001 /* chip has interface activity */ 129 u_int8_t tl_lasttx; /* we were without input this many seconds */ 130 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 131 mii_data_t mii; /* mii bus */ 132 struct Rx_list *Rx_list; /* Receive and transmit lists */ 133 struct Tx_list *Tx_list; 134 struct Rx_list *active_Rx, *last_Rx; 135 struct Tx_list *active_Tx, *last_Tx; 136 struct Tx_list *Free_Tx; 137 int opkt; /* used to detect link up/down for AUI/BNC */ 138 int stats_exesscoll; /* idem */ 139 #ifdef TL_PRIV_STATS 140 int ierr_overr; 141 int ierr_code; 142 int ierr_crc; 143 int ierr_nomem; 144 int oerr_underr; 145 int oerr_deffered; 146 int oerr_coll; 147 int oerr_multicoll; 148 int oerr_latecoll; 149 int oerr_exesscoll; 150 int oerr_carrloss; 151 int oerr_mcopy; 152 #endif 153 }; 154 #define tl_if tl_ec.ec_if 155 #define tl_bpf tl_if.if_bpf 156 157 typedef struct tl_softc tl_softc_t; 158 typedef u_long ioctl_cmd_t; 159 160 #define TL_HR_READ(sc, reg) \ 161 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 162 #define TL_HR_READ_BYTE(sc, reg) \ 163 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 164 #define TL_HR_WRITE(sc, reg, data) \ 165 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 166 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 167 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 168 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 169 170 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 171 static void tl_pci_attach __P((struct device *, struct device *, void *)); 172 static int tl_intr __P((void *)); 173 174 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 175 static int tl_mediachange __P((struct ifnet *)); 176 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 177 static void tl_ifwatchdog __P((struct ifnet *)); 178 static void tl_shutdown __P((void*)); 179 180 static void tl_ifstart __P((struct ifnet *)); 181 static void tl_reset __P((tl_softc_t*)); 182 static int tl_init __P((tl_softc_t*)); 183 static void tl_restart __P((void *)); 184 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 185 static void tl_read_stats __P((tl_softc_t*)); 186 static void tl_ticks __P((void*)); 187 static int tl_multicast_hash __P((u_int8_t*)); 188 static void tl_addr_filter __P((tl_softc_t*)); 189 190 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 191 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 192 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 193 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 194 195 196 #if defined(TLDEBUG_RX) 197 static void ether_printheader __P((struct ether_header*)); 198 #endif 199 200 void tl_mii_set __P((void*, u_int8_t)); 201 void tl_mii_clr __P((void*, u_int8_t)); 202 int tl_mii_read __P((void*, u_int8_t)); 203 204 void tl_i2c_set __P((void*, u_int8_t)); 205 void tl_i2c_clr __P((void*, u_int8_t)); 206 int tl_i2c_read __P((void*, u_int8_t)); 207 208 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 209 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 210 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 211 static __inline void netsio_clr(sc, bits) 212 tl_softc_t* sc; 213 u_int8_t bits; 214 { 215 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 216 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 217 } 218 static __inline void netsio_set(sc, bits) 219 tl_softc_t* sc; 220 u_int8_t bits; 221 { 222 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 223 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 224 } 225 static __inline u_int8_t netsio_read(sc, bits) 226 tl_softc_t* sc; 227 u_int8_t bits; 228 { 229 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 230 } 231 232 struct cfattach tl_ca = { 233 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 234 }; 235 236 struct tl_product_desc { 237 u_int32_t tp_product; 238 u_int32_t tp_adapter; 239 int tp_flags; 240 const char *tp_desc; 241 }; 242 243 /* tp_flags */ 244 #define TPF_BROKEN_MEM 0x00000001 /* memory-mapped access is broken */ 245 246 const struct tl_product_desc tl_compaq_products[] = { 247 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 248 0, "Compaq Netelligent 10/100 TX" }, 249 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 250 0, "Compaq Netelligent 10 T" }, 251 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 252 0, "Compaq Integrated NetFlex 3/P" }, 253 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 254 0, "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 255 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 256 0, "Compaq Dual Port Netelligent 10/100 TX" }, 257 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 258 0, "Compaq Deskpro 4000 5233MMX" }, 259 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 260 0, "Compaq NetFlex 3/P w/ BNC" }, 261 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 262 0, "Compaq NetFlex 3/P" }, 263 { 0, 0, NULL }, 264 }; 265 266 const struct tl_product_desc tl_ti_products[] = { 267 /* 268 * Built-in Ethernet on the TI TravelMate 5000 269 * docking station; better product description? 270 * XXX Seems to have broken memory-mapped access. 271 */ 272 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 273 TPF_BROKEN_MEM, "Texas Instruments ThunderLAN" }, 274 { 0, 0, NULL }, 275 }; 276 277 struct tl_vendor_desc { 278 u_int32_t tv_vendor; 279 const struct tl_product_desc *tv_products; 280 }; 281 282 const struct tl_vendor_desc tl_vendors[] = { 283 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 284 { PCI_VENDOR_TI, tl_ti_products }, 285 { 0, NULL }, 286 }; 287 288 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 289 290 const struct tl_product_desc * 291 tl_lookup_product(id) 292 u_int32_t id; 293 { 294 const struct tl_product_desc *tp; 295 const struct tl_vendor_desc *tv; 296 297 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 298 if (PCI_VENDOR(id) == tv->tv_vendor) 299 break; 300 301 if ((tp = tv->tv_products) == NULL) 302 return (NULL); 303 304 for (; tp->tp_desc != NULL; tp++) 305 if (PCI_PRODUCT(id) == tp->tp_product) 306 break; 307 308 if (tp->tp_desc == NULL) 309 return (NULL); 310 311 return (tp); 312 } 313 314 static char *nullbuf = NULL; 315 316 static int 317 tl_pci_match(parent, match, aux) 318 struct device *parent; 319 struct cfdata *match; 320 void *aux; 321 { 322 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 323 324 if (tl_lookup_product(pa->pa_id) != NULL) 325 return (1); 326 327 return (0); 328 } 329 330 static void 331 tl_pci_attach(parent, self, aux) 332 struct device * parent; 333 struct device * self; 334 void * aux; 335 { 336 tl_softc_t *sc = (tl_softc_t *)self; 337 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 338 const struct tl_product_desc *tp; 339 struct ifnet * const ifp = &sc->tl_if; 340 bus_space_tag_t iot, memt; 341 bus_space_handle_t ioh, memh; 342 pci_intr_handle_t intrhandle; 343 const char *intrstr; 344 int i, tmp, ioh_valid, memh_valid; 345 pcireg_t csr; 346 347 printf("\n"); 348 349 tp = tl_lookup_product(pa->pa_id); 350 if (tp == NULL) 351 panic("tl_pci_attach: impossible"); 352 353 /* Map the card space. */ 354 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 355 &iot, &ioh, NULL, NULL) == 0); 356 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 357 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 358 0, &memt, &memh, NULL, NULL) == 0); 359 360 if (memh_valid && (tp->tp_flags & TPF_BROKEN_MEM) == 0) { 361 sc->tl_bustag = memt; 362 sc->tl_bushandle = memh; 363 } else if (ioh_valid) { 364 sc->tl_bustag = iot; 365 sc->tl_bushandle = ioh; 366 } else { 367 printf("%s: unable to map device registers\n", 368 sc->sc_dev.dv_xname); 369 return; 370 } 371 372 /* Enable the device. */ 373 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 374 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 375 csr | PCI_COMMAND_MASTER_ENABLE); 376 377 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 378 sc->mii.adapter_id = tp->tp_adapter; 379 380 tl_reset(sc); 381 382 /* fill in the i2c struct */ 383 sc->i2cbus.adapter_softc = sc; 384 sc->i2cbus.set_bit = tl_i2c_set; 385 sc->i2cbus.clr_bit = tl_i2c_clr; 386 sc->i2cbus.read_bit = tl_i2c_read; 387 388 #ifdef TLDEBUG 389 printf("default values of INTreg: 0x%x\n", 390 tl_intreg_read(sc, TL_INT_Defaults)); 391 #endif 392 393 /* read mac addr */ 394 for (i=0; i<ETHER_ADDR_LEN; i++) { 395 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 396 if (tmp < 0) { 397 printf("%s: error reading Ethernet adress\n", 398 sc->sc_dev.dv_xname); 399 return; 400 } else { 401 sc->tl_enaddr[i] = tmp; 402 } 403 } 404 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 405 ether_sprintf(sc->tl_enaddr)); 406 407 /* Map and establish interrupts */ 408 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 409 pa->pa_intrline, &intrhandle)) { 410 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 411 return; 412 } 413 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 414 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 415 tl_intr, sc); 416 if (sc->tl_ih == NULL) { 417 printf("%s: couldn't establish interrupt", 418 sc->sc_dev.dv_xname); 419 if (intrstr != NULL) 420 printf(" at %s", intrstr); 421 printf("\n"); 422 return; 423 } 424 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 425 426 /* 427 * Add shutdown hook so that DMA is disabled prior to reboot. Not 428 * doing do could allow DMA to corrupt kernel memory during the 429 * reboot before the driver initializes. 430 */ 431 (void) shutdownhook_establish(tl_shutdown, sc); 432 433 sc->mii.adapter_softc = sc; 434 sc->mii.mii_setbit = tl_mii_set; 435 sc->mii.mii_clrbit = tl_mii_clr; 436 sc->mii.mii_readbit = tl_mii_read; 437 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 438 sc->mii.mii_writereg = NULL; 439 if (config_found(self, (void*)&sc->mii, mii_adapter_print) == NULL) { 440 return; 441 } 442 443 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 444 mii_media_add(&sc->tl_ifmedia, &sc->mii); 445 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 446 447 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 448 sc->tl_if.if_softc = sc; 449 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 450 ifp->if_ioctl = tl_ifioctl; 451 ifp->if_start = tl_ifstart; 452 ifp->if_watchdog = tl_ifwatchdog; 453 ifp->if_timer = 0; 454 if_attach(ifp); 455 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 456 #if NBPFILTER > 0 457 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 458 sizeof(struct ether_header)); 459 #endif 460 sc->mii.mii_media_active = IFM_NONE; 461 } 462 463 static void 464 tl_reset(sc) 465 tl_softc_t *sc; 466 { 467 int i; 468 469 /* read stats */ 470 if (sc->tl_if.if_flags & IFF_RUNNING) { 471 untimeout(tl_ticks, sc); 472 tl_read_stats(sc); 473 } 474 /* Reset adapter */ 475 TL_HR_WRITE(sc, TL_HOST_CMD, 476 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 477 DELAY(100000); 478 /* Disable interrupts */ 479 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 480 /* setup aregs & hash */ 481 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 482 tl_intreg_write(sc, i, 0); 483 #ifdef TLDEBUG_ADDR 484 printf("Areg & hash registers: \n"); 485 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 486 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 487 #endif 488 /* Setup NetConfig */ 489 tl_intreg_write(sc, TL_INT_NetConfig, 490 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 491 /* Bsize: accept default */ 492 /* TX commit in Acommit: accept default */ 493 /* Load Ld_tmr and Ld_thr */ 494 /* Ld_tmr = 3 */ 495 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 496 /* Ld_thr = 0 */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 498 /* Unreset MII */ 499 netsio_set(sc, TL_NETSIO_NMRST); 500 DELAY(100000); 501 sc->mii.mii_media_status &= ~IFM_ACTIVE; 502 sc->tl_flags = 0; 503 sc->opkt = 0; 504 sc->stats_exesscoll = 0; 505 } 506 507 static void tl_shutdown(v) 508 void *v; 509 { 510 tl_softc_t *sc = v; 511 struct Tx_list *Tx; 512 int i; 513 514 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 515 return; 516 /* disable interrupts */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 518 HOST_CMD_IntOff); 519 /* stop TX and RX channels */ 520 TL_HR_WRITE(sc, TL_HOST_CMD, 521 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 522 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 523 DELAY(100000); 524 525 /* stop statistics reading loop, read stats */ 526 untimeout(tl_ticks, sc); 527 tl_read_stats(sc); 528 529 /* deallocate memory allocations */ 530 for (i=0; i< TL_NBUF; i++) { 531 if (sc->Rx_list[i].m) 532 m_freem(sc->Rx_list[i].m); 533 sc->Rx_list[i].m = NULL; 534 } 535 free(sc->Rx_list, M_DEVBUF); 536 sc->Rx_list = NULL; 537 while ((Tx = sc->active_Tx) != NULL) { 538 Tx->hw_list.stat = 0; 539 m_freem(Tx->m); 540 sc->active_Tx = Tx->next; 541 Tx->next = sc->Free_Tx; 542 sc->Free_Tx = Tx; 543 } 544 sc->last_Tx = NULL; 545 free(sc->Tx_list, M_DEVBUF); 546 sc->Tx_list = NULL; 547 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 548 sc->mii.mii_media_status &= ~IFM_ACTIVE; 549 sc->tl_flags = 0; 550 } 551 552 static void tl_restart(v) 553 void *v; 554 { 555 tl_init(v); 556 } 557 558 static int tl_init(sc) 559 tl_softc_t *sc; 560 { 561 struct ifnet *ifp = &sc->tl_if; 562 int i, s; 563 564 s = splnet(); 565 /* cancel any pending IO */ 566 tl_shutdown(sc); 567 tl_reset(sc); 568 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 569 splx(s); 570 return 0; 571 } 572 /* Set various register to reasonable value */ 573 /* setup NetCmd in promisc mode if needed */ 574 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 575 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 576 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 577 /* Max receive size : MCLBYTES */ 578 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 579 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 580 (MCLBYTES >> 8) & 0xff); 581 582 /* init MAC addr */ 583 for (i = 0; i < ETHER_ADDR_LEN; i++) 584 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 585 /* add multicast filters */ 586 tl_addr_filter(sc); 587 #ifdef TLDEBUG_ADDR 588 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 589 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 590 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 591 #endif 592 593 /* Pre-allocate receivers mbuf, make the lists */ 594 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 595 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 596 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 597 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 598 sc->tl_if.if_flags &= ~IFF_UP; 599 splx(s); 600 return ENOMEM; 601 } 602 for (i=0; i< TL_NBUF; i++) { 603 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 604 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 605 sc->tl_if.if_flags &= ~IFF_UP; 606 splx(s); 607 return ENOMEM; 608 } 609 if (i > 0) { /* chain the list */ 610 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 611 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 612 #ifdef DIAGNOSTIC 613 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 614 printf("%s: physical addr 0x%x of list not properly aligned\n", 615 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 616 #endif 617 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 618 } 619 } 620 sc->Rx_list[TL_NBUF-1].next = NULL; 621 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 622 sc->Tx_list[TL_NBUF-1].next = NULL; 623 624 sc->active_Rx = &sc->Rx_list[0]; 625 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 626 sc->active_Tx = sc->last_Tx = NULL; 627 sc->Free_Tx = &sc->Tx_list[0]; 628 629 if (nullbuf == NULL) 630 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 631 if (nullbuf == NULL) { 632 printf("%s: can't allocate space for pad buffer\n", 633 sc->sc_dev.dv_xname); 634 sc->tl_if.if_flags &= ~IFF_UP; 635 splx(s); 636 return ENOMEM; 637 } 638 bzero(nullbuf, ETHER_MIN_TX); 639 640 /* set media if needed */ 641 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 642 mii_mediachg(&sc->mii); 643 } 644 645 /* start ticks calls */ 646 timeout(tl_ticks, sc, hz); 647 /* write adress of Rx list and enable interrupts */ 648 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 649 TL_HR_WRITE(sc, TL_HOST_CMD, 650 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 651 sc->tl_if.if_flags |= IFF_RUNNING; 652 sc->tl_if.if_flags &= ~IFF_OACTIVE; 653 return 0; 654 } 655 656 657 static u_int32_t 658 tl_intreg_read(sc, reg) 659 tl_softc_t *sc; 660 u_int32_t reg; 661 { 662 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 663 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 664 } 665 666 static u_int8_t 667 tl_intreg_read_byte(sc, reg) 668 tl_softc_t *sc; 669 u_int32_t reg; 670 { 671 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 672 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 673 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 674 } 675 676 static void 677 tl_intreg_write(sc, reg, val) 678 tl_softc_t *sc; 679 u_int32_t reg; 680 u_int32_t val; 681 { 682 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 683 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 684 } 685 686 static void 687 tl_intreg_write_byte(sc, reg, val) 688 tl_softc_t *sc; 689 u_int32_t reg; 690 u_int8_t val; 691 { 692 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 693 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 694 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 695 } 696 697 void tl_mii_set(v, bit) 698 void *v; 699 u_int8_t bit; 700 { 701 tl_softc_t *sc = v; 702 703 switch (bit) { 704 case MII_DATA: 705 netsio_set(sc, TL_NETSIO_MDATA); 706 break; 707 case MII_CLOCK: 708 netsio_set(sc, TL_NETSIO_MCLK); 709 break; 710 case MII_TXEN: 711 netsio_set(sc, TL_NETSIO_MTXEN); 712 break; 713 default: 714 printf("tl_mii_set: unknown bit %d\n", bit); 715 } 716 } 717 718 void tl_mii_clr(v, bit) 719 void *v; 720 u_int8_t bit; 721 { 722 tl_softc_t *sc = v; 723 724 switch (bit) { 725 case MII_DATA: 726 netsio_clr(sc, TL_NETSIO_MDATA); 727 break; 728 case MII_CLOCK: 729 netsio_clr(sc, TL_NETSIO_MCLK); 730 break; 731 case MII_TXEN: 732 netsio_clr(sc, TL_NETSIO_MTXEN); 733 break; 734 default: 735 printf("tl_mii_clr: unknown bit %d\n", bit); 736 } 737 return; 738 } 739 740 int tl_mii_read(v, bit) 741 void *v; 742 u_int8_t bit; 743 { 744 tl_softc_t *sc = v; 745 746 switch (bit) { 747 case MII_DATA: 748 return netsio_read(sc, TL_NETSIO_MDATA); 749 break; 750 case MII_CLOCK: 751 return netsio_read(sc, TL_NETSIO_MCLK); 752 break; 753 case MII_TXEN: 754 return netsio_read(sc, TL_NETSIO_MTXEN); 755 break; 756 default: 757 printf("tl_mii_read: unknown bit %d\n", bit); 758 return -1; 759 } 760 } 761 762 void tl_i2c_set(v, bit) 763 void *v; 764 u_int8_t bit; 765 { 766 tl_softc_t *sc = v; 767 768 switch (bit) { 769 case I2C_DATA: 770 netsio_set(sc, TL_NETSIO_EDATA); 771 break; 772 case I2C_CLOCK: 773 netsio_set(sc, TL_NETSIO_ECLOCK); 774 break; 775 case I2C_TXEN: 776 netsio_set(sc, TL_NETSIO_ETXEN); 777 break; 778 default: 779 printf("tl_i2c_set: unknown bit %d\n", bit); 780 } 781 return; 782 } 783 784 void tl_i2c_clr(v, bit) 785 void *v; 786 u_int8_t bit; 787 { 788 tl_softc_t *sc = v; 789 790 switch (bit) { 791 case I2C_DATA: 792 netsio_clr(sc, TL_NETSIO_EDATA); 793 break; 794 case I2C_CLOCK: 795 netsio_clr(sc, TL_NETSIO_ECLOCK); 796 break; 797 case I2C_TXEN: 798 netsio_clr(sc, TL_NETSIO_ETXEN); 799 break; 800 default: 801 printf("tl_i2c_clr: unknown bit %d\n", bit); 802 } 803 return; 804 } 805 806 int tl_i2c_read(v, bit) 807 void *v; 808 u_int8_t bit; 809 { 810 tl_softc_t *sc = v; 811 812 switch (bit) { 813 case I2C_DATA: 814 return netsio_read(sc, TL_NETSIO_EDATA); 815 break; 816 case I2C_CLOCK: 817 return netsio_read(sc, TL_NETSIO_ECLOCK); 818 break; 819 case I2C_TXEN: 820 return netsio_read(sc, TL_NETSIO_ETXEN); 821 break; 822 default: 823 printf("tl_i2c_read: unknown bit %d\n", bit); 824 return -1; 825 } 826 } 827 828 static int 829 tl_intr(v) 830 void *v; 831 { 832 tl_softc_t *sc = v; 833 struct ifnet *ifp = &sc->tl_if; 834 struct Rx_list *Rx; 835 struct Tx_list *Tx; 836 struct mbuf *m; 837 u_int32_t int_type, int_reg; 838 int ack = 0; 839 int size; 840 841 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 842 int_type = int_reg & TL_INTR_MASK; 843 if (int_type == 0) 844 return 0; 845 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 846 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 847 int_type, int_reg); 848 #endif 849 /* disable interrupts */ 850 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 851 switch(int_type & TL_INTR_MASK) { 852 case TL_INTR_RxEOF: 853 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 854 /* dequeue and requeue at end of list */ 855 ack++; 856 Rx = sc->active_Rx; 857 sc->active_Rx = Rx->next; 858 m = Rx->m; 859 size = Rx->hw_list.stat >> 16; 860 #ifdef TLDEBUG_RX 861 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 862 #endif 863 if (tl_add_RxBuff(Rx, m ) == 0) { 864 /* No new mbuf, reuse the same. This means that this packet 865 is lost */ 866 m = NULL; 867 #ifdef TL_PRIV_STATS 868 sc->ierr_nomem++; 869 #endif 870 #ifdef TLDEBUG 871 printf("%s: out of mbuf, lost input packet\n", 872 sc->sc_dev.dv_xname); 873 #endif 874 } 875 Rx->next = NULL; 876 Rx->hw_list.fwd = 0; 877 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 878 #ifdef DIAGNOSTIC 879 if (sc->last_Rx->hw_list.fwd & 0x7) 880 printf("%s: physical addr 0x%x of list not properly aligned\n", 881 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 882 #endif 883 sc->last_Rx->next = Rx; 884 sc->last_Rx = Rx; 885 886 /* deliver packet */ 887 if (m) { 888 struct ether_header *eh; 889 if (size < sizeof(struct ether_header)) { 890 m_freem(m); 891 continue; 892 } 893 m->m_pkthdr.rcvif = ifp; 894 m->m_pkthdr.len = m->m_len = 895 size - sizeof(struct ether_header); 896 eh = mtod(m, struct ether_header *); 897 #ifdef TLDEBUG_RX 898 printf("tl_intr: Rx packet:\n"); 899 ether_printheader(eh); 900 #endif 901 #if NBPFILTER > 0 902 if (ifp->if_bpf) { 903 bpf_tap(ifp->if_bpf, 904 mtod(m, caddr_t), 905 size); 906 /* 907 * Only pass this packet up 908 * if it is for us. 909 */ 910 if ((ifp->if_flags & IFF_PROMISC) && 911 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 912 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 913 sizeof(eh->ether_dhost)) != 0) { 914 m_freem(m); 915 continue; 916 } 917 } 918 #endif /* NBPFILTER > 0 */ 919 m->m_data += sizeof(struct ether_header); 920 ether_input(ifp, eh, m); 921 } 922 } 923 #ifdef TLDEBUG_RX 924 printf("TL_INTR_RxEOF: ack %d\n", ack); 925 #else 926 if (ack == 0) { 927 printf("%s: EOF intr without anything to read !\n", 928 sc->sc_dev.dv_xname); 929 tl_reset(sc); 930 /* shedule reinit of the board */ 931 timeout(tl_restart, sc, 1); 932 return(1); 933 } 934 #endif 935 break; 936 case TL_INTR_RxEOC: 937 ack++; 938 #ifdef TLDEBUG_RX 939 printf("TL_INTR_RxEOC: ack %d\n", ack); 940 #endif 941 #ifdef DIAGNOSTIC 942 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 943 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 944 sc->sc_dev.dv_xname); 945 return 0; 946 } else 947 #endif 948 { 949 /* write adress of Rx list and send Rx GO command, ack interrupt 950 and enable interrupts in one command */ 951 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 952 vtophys(&sc->active_Rx->hw_list)); 953 TL_HR_WRITE(sc, TL_HOST_CMD, 954 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 955 HOST_CMD_ACK | HOST_CMD_IntOn); 956 return 1; 957 } 958 case TL_INTR_TxEOF: 959 case TL_INTR_TxEOC: 960 while ((Tx = sc->active_Tx) != NULL) { 961 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 962 break; 963 ack++; 964 #ifdef TLDEBUG_TX 965 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 966 #endif 967 Tx->hw_list.stat = 0; 968 m_freem(Tx->m); 969 Tx->m = NULL; 970 sc->active_Tx = Tx->next; 971 if (sc->active_Tx == NULL) 972 sc->last_Tx = NULL; 973 Tx->next = sc->Free_Tx; 974 sc->Free_Tx = Tx; 975 } 976 /* if this was an EOC, ACK immediatly */ 977 if (int_type == TL_INTR_TxEOC) { 978 #ifdef TLDEBUG_TX 979 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 980 #endif 981 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 982 HOST_CMD_IntOn); 983 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 984 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 985 vtophys(&sc->active_Tx->hw_list)); 986 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 987 } 988 sc->tl_if.if_timer = 0; 989 if (sc->tl_if.if_snd.ifq_head != NULL) 990 tl_ifstart(&sc->tl_if); 991 return 1; 992 } 993 #ifdef TLDEBUG 994 else { 995 printf("TL_INTR_TxEOF: ack %d\n", ack); 996 } 997 #endif 998 sc->tl_if.if_timer = 0; 999 if (sc->tl_if.if_snd.ifq_head != NULL) 1000 tl_ifstart(&sc->tl_if); 1001 break; 1002 case TL_INTR_Stat: 1003 ack++; 1004 #ifdef TLDEBUG 1005 printf("TL_INTR_Stat: ack %d\n", ack); 1006 #endif 1007 tl_read_stats(sc); 1008 break; 1009 case TL_INTR_Adc: 1010 if (int_reg & TL_INTVec_MASK) { 1011 /* adapter check conditions */ 1012 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1013 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1014 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1015 tl_reset(sc); 1016 /* shedule reinit of the board */ 1017 timeout(tl_restart, sc, 1); 1018 return(1); 1019 } else { 1020 u_int8_t netstat; 1021 /* Network status */ 1022 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1023 printf("%s: network status, NetSts=%x\n", 1024 sc->sc_dev.dv_xname, netstat); 1025 /* Ack interrupts */ 1026 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1027 ack++; 1028 } 1029 break; 1030 default: 1031 printf("%s: unhandled interrupt code %x!\n", 1032 sc->sc_dev.dv_xname, int_type); 1033 ack++; 1034 } 1035 1036 if (ack) { 1037 /* Ack the interrupt and enable interrupts */ 1038 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1039 HOST_CMD_IntOn); 1040 return 1; 1041 } 1042 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1043 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1044 return 0; 1045 } 1046 1047 static int 1048 tl_ifioctl(ifp, cmd, data) 1049 struct ifnet *ifp; 1050 ioctl_cmd_t cmd; 1051 caddr_t data; 1052 { 1053 struct tl_softc *sc = ifp->if_softc; 1054 struct ifreq *ifr = (struct ifreq *)data; 1055 int s, error; 1056 1057 s = splnet(); 1058 switch(cmd) { 1059 case SIOCSIFADDR: { 1060 struct ifaddr *ifa = (struct ifaddr *)data; 1061 sc->tl_if.if_flags |= IFF_UP; 1062 if ((error = tl_init(sc)) != NULL) { 1063 sc->tl_if.if_flags &= ~IFF_UP; 1064 break; 1065 } 1066 switch (ifa->ifa_addr->sa_family) { 1067 #ifdef INET 1068 case AF_INET: 1069 arp_ifinit(ifp, ifa); 1070 break; 1071 #endif 1072 #ifdef NS 1073 case AF_NS: { 1074 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1075 1076 if (ns_nullhost(*ina)) 1077 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1078 else 1079 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1080 ifp->if_addrlen); 1081 break; 1082 } 1083 #endif 1084 default: 1085 break; 1086 } 1087 break; 1088 } 1089 case SIOCSIFFLAGS: 1090 { 1091 u_int8_t reg; 1092 /* 1093 * If interface is marked up and not running, then start it. 1094 * If it is marked down and running, stop it. 1095 */ 1096 if (ifp->if_flags & IFF_UP) { 1097 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1098 error = tl_init(sc); 1099 /* all flags have been handled by init */ 1100 break; 1101 } 1102 error = 0; 1103 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1104 if (ifp->if_flags & IFF_PROMISC) 1105 reg |= TL_NETCOMMAND_CAF; 1106 else 1107 reg &= ~TL_NETCOMMAND_CAF; 1108 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1109 #ifdef TL_PRIV_STATS 1110 if (ifp->if_flags & IFF_LINK0) { 1111 ifp->if_flags &= ~IFF_LINK0; 1112 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1113 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1114 printf(" %4d RX code error\n", sc->ierr_code); 1115 printf(" %4d RX crc error\n", sc->ierr_crc); 1116 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1117 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1118 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1119 printf(" %4d TX single collisions\n", sc->oerr_coll); 1120 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1121 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1122 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1123 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1124 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1125 } 1126 #endif 1127 } else { 1128 if (ifp->if_flags & IFF_RUNNING) 1129 tl_shutdown(sc); 1130 error = 0; 1131 } 1132 break; 1133 } 1134 case SIOCADDMULTI: 1135 case SIOCDELMULTI: 1136 /* 1137 * Update multicast listeners 1138 */ 1139 if (cmd == SIOCADDMULTI) 1140 error = ether_addmulti(ifr, &sc->tl_ec); 1141 else 1142 error = ether_delmulti(ifr, &sc->tl_ec); 1143 if (error == ENETRESET) { 1144 tl_addr_filter(sc); 1145 error = 0; 1146 } 1147 break; 1148 case SIOCSIFMEDIA: 1149 case SIOCGIFMEDIA: 1150 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1151 break; 1152 default: 1153 error = EINVAL; 1154 } 1155 splx(s); 1156 return error; 1157 } 1158 1159 static void 1160 tl_ifstart(ifp) 1161 struct ifnet *ifp; 1162 { 1163 tl_softc_t *sc = ifp->if_softc; 1164 struct mbuf *m, *mb_head; 1165 struct Tx_list *Tx; 1166 int segment, size; 1167 1168 txloop: 1169 /* If we don't have more space ... */ 1170 if (sc->Free_Tx == NULL) { 1171 #ifdef TLDEBUG 1172 printf("tl_ifstart: No free TX list\n"); 1173 #endif 1174 return; 1175 } 1176 /* Grab a paquet for output */ 1177 IF_DEQUEUE(&ifp->if_snd, mb_head); 1178 if (mb_head == NULL) { 1179 #ifdef TLDEBUG_TX 1180 printf("tl_ifstart: nothing to send\n"); 1181 #endif 1182 return; 1183 } 1184 Tx = sc->Free_Tx; 1185 sc->Free_Tx = Tx->next; 1186 /* 1187 * Go through each of the mbufs in the chain and initialize 1188 * the transmit list descriptors with the physical address 1189 * and size of the mbuf. 1190 */ 1191 tbdinit: 1192 bzero(Tx, sizeof(struct Tx_list)); 1193 Tx->m = mb_head; 1194 size = 0; 1195 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1196 if (m->m_len != 0) { 1197 if (segment == TL_NSEG) 1198 break; 1199 size += m->m_len; 1200 Tx->hw_list.seg[segment].data_addr = 1201 vtophys(mtod(m, vm_offset_t)); 1202 Tx->hw_list.seg[segment].data_count = m->m_len; 1203 segment++; 1204 } 1205 } 1206 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1207 /* 1208 * We ran out of segments, or we will. We have to recopy this mbuf 1209 * chain first. 1210 */ 1211 struct mbuf *mn; 1212 #ifdef TLDEBUG_TX 1213 printf("tl_ifstart: need to copy mbuf\n"); 1214 #endif 1215 #ifdef TL_PRIV_STATS 1216 sc->oerr_mcopy++; 1217 #endif 1218 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1219 if (mn == NULL) { 1220 m_freem(mb_head); 1221 goto bad; 1222 } 1223 if (mb_head->m_pkthdr.len > MHLEN) { 1224 MCLGET(mn, M_DONTWAIT); 1225 if ((mn->m_flags & M_EXT) == 0) { 1226 m_freem(mn); 1227 m_freem(mb_head); 1228 goto bad; 1229 } 1230 } 1231 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1232 mtod(mn, caddr_t)); 1233 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1234 m_freem(mb_head); 1235 mb_head = mn; 1236 goto tbdinit; 1237 } 1238 /* We are at end of mbuf chain. check the size and 1239 * see if it needs to be extended 1240 */ 1241 if (size < ETHER_MIN_TX) { 1242 #ifdef DIAGNOSTIC 1243 if (segment >= TL_NSEG) { 1244 panic("tl_ifstart: to much segmets (%d)\n", segment); 1245 } 1246 #endif 1247 /* 1248 * add the nullbuf in the seg 1249 */ 1250 Tx->hw_list.seg[segment].data_count = 1251 ETHER_MIN_TX - size; 1252 Tx->hw_list.seg[segment].data_addr = 1253 vtophys(nullbuf); 1254 size = ETHER_MIN_TX; 1255 segment++; 1256 } 1257 /* The list is done, finish the list init */ 1258 Tx->hw_list.seg[segment-1].data_count |= 1259 TL_LAST_SEG; 1260 Tx->hw_list.stat = (size << 16) | 0x3000; 1261 #ifdef TLDEBUG_TX 1262 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1263 Tx->hw_list.stat); 1264 #if 0 1265 for(segment = 0; segment < TL_NSEG; segment++) { 1266 printf(" seg %d addr 0x%x len 0x%x\n", 1267 segment, 1268 Tx->hw_list.seg[segment].data_addr, 1269 Tx->hw_list.seg[segment].data_count); 1270 } 1271 #endif 1272 #endif 1273 sc->opkt++; 1274 if (sc->active_Tx == NULL) { 1275 sc->active_Tx = sc->last_Tx = Tx; 1276 #ifdef TLDEBUG_TX 1277 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1278 vtophys(&Tx->hw_list)); 1279 #endif 1280 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1281 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1282 } else { 1283 #ifdef TLDEBUG_TX 1284 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1285 vtophys(&Tx->hw_list)); 1286 #endif 1287 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1288 sc->last_Tx->next = Tx; 1289 sc->last_Tx = Tx; 1290 #ifdef DIAGNOSTIC 1291 if (sc->last_Tx->hw_list.fwd & 0x7) 1292 printf("%s: physical addr 0x%x of list not properly aligned\n", 1293 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1294 #endif 1295 } 1296 #if NBPFILTER > 0 1297 /* Pass packet to bpf if there is a listener */ 1298 if (ifp->if_bpf) 1299 bpf_mtap(ifp->if_bpf, mb_head); 1300 #endif 1301 /* Set a 5 second timer just in case we don't hear from the card again. */ 1302 ifp->if_timer = 5; 1303 1304 goto txloop; 1305 bad: 1306 #ifdef TLDEBUG 1307 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1308 #endif 1309 Tx->next = sc->Free_Tx; 1310 sc->Free_Tx = Tx; 1311 return; 1312 } 1313 1314 static void 1315 tl_ifwatchdog(ifp) 1316 struct ifnet *ifp; 1317 { 1318 tl_softc_t *sc = ifp->if_softc; 1319 1320 if ((ifp->if_flags & IFF_RUNNING) == 0) 1321 return; 1322 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1323 ifp->if_oerrors++; 1324 tl_init(sc); 1325 } 1326 1327 static int 1328 tl_mediachange(ifp) 1329 struct ifnet *ifp; 1330 { 1331 1332 tl_softc_t *sc = ifp->if_softc; 1333 int err; 1334 u_int32_t reg; 1335 int oldmedia; 1336 #ifdef TLDEBUG 1337 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1338 #endif 1339 oldmedia = sc->mii.mii_media_active; 1340 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1341 if ((err = mii_mediachg(&sc->mii)) != 0) 1342 sc->mii.mii_media_active = oldmedia; 1343 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1344 if (sc->mii.mii_media_active & IFM_FDX) 1345 reg |= TL_NETCOMMAND_DUPLEX; 1346 else 1347 reg &= ~TL_NETCOMMAND_DUPLEX; 1348 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1349 return err; 1350 } 1351 1352 static void 1353 tl_mediastatus(ifp, ifmr) 1354 struct ifnet *ifp; 1355 struct ifmediareq *ifmr; 1356 { 1357 tl_softc_t *sc = ifp->if_softc; 1358 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1359 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1360 if (sc->tl_flags & TL_IFACT) 1361 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1362 else 1363 sc->mii.mii_media_status = IFM_AVALID; 1364 else 1365 mii_pollstat(&sc->mii); 1366 1367 ifmr->ifm_active = sc->mii.mii_media_active; 1368 ifmr->ifm_status = sc->mii.mii_media_status; 1369 } 1370 1371 static int tl_add_RxBuff(Rx, oldm) 1372 struct Rx_list *Rx; 1373 struct mbuf *oldm; 1374 { 1375 struct mbuf *m; 1376 1377 MGETHDR(m, M_DONTWAIT, MT_DATA); 1378 if (m != NULL) { 1379 MCLGET(m, M_DONTWAIT); 1380 if ((m->m_flags & M_EXT) == 0) { 1381 m_freem(m); 1382 if (oldm == NULL) 1383 return 0; 1384 m = oldm; 1385 m->m_data = m->m_ext.ext_buf; 1386 } 1387 } else { 1388 if (oldm == NULL) 1389 return 0; 1390 m = oldm; 1391 m->m_data = m->m_ext.ext_buf; 1392 } 1393 /* 1394 * Move the data pointer up so that the incoming data packet 1395 * will be 32-bit aligned. 1396 */ 1397 m->m_data += 2; 1398 1399 /* (re)init the Rx_list struct */ 1400 1401 Rx->m = m; 1402 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1403 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1404 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1405 return (m != oldm); 1406 } 1407 1408 static void tl_ticks(v) 1409 void *v; 1410 { 1411 tl_softc_t *sc = v; 1412 1413 tl_read_stats(sc); 1414 if (sc->opkt > 0) { 1415 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1416 if (sc->tl_flags & TL_IFACT) /* only print once */ 1417 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1418 sc->tl_flags &= ~TL_IFACT; 1419 } else 1420 sc->tl_flags |= TL_IFACT; 1421 sc->oerr_exesscoll = sc->opkt = 0; 1422 sc->tl_lasttx = 0; 1423 } else { 1424 sc->tl_lasttx++; 1425 if (sc->tl_lasttx >= TL_IDLETIME) { 1426 /* 1427 * No TX activity in the last TL_IDLETIME seconds. 1428 * sends a LLC Class1 TEST pkt 1429 */ 1430 struct mbuf *m; 1431 int s; 1432 MGETHDR(m, M_DONTWAIT, MT_DATA); 1433 if (m != NULL) { 1434 #ifdef TLDEBUG 1435 printf("tl_ticks: sending LLC test pkt\n"); 1436 #endif 1437 bcopy(sc->tl_enaddr, 1438 mtod(m, struct ether_header *)->ether_dhost, 6); 1439 bcopy(sc->tl_enaddr, 1440 mtod(m, struct ether_header *)->ether_shost, 6); 1441 mtod(m, struct ether_header *)->ether_type = htons(3); 1442 mtod(m, unsigned char *)[14] = 0; 1443 mtod(m, unsigned char *)[15] = 0; 1444 mtod(m, unsigned char *)[16] = 0xE3; 1445 /* LLC Class1 TEST (no poll) */ 1446 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1447 s = splnet(); 1448 IF_PREPEND(&sc->tl_if.if_snd, m); 1449 tl_ifstart(&sc->tl_if); 1450 splx(s); 1451 } 1452 } 1453 } 1454 1455 /* read statistics every seconds */ 1456 timeout(tl_ticks, v, hz); 1457 } 1458 1459 static void 1460 tl_read_stats(sc) 1461 tl_softc_t *sc; 1462 { 1463 u_int32_t reg; 1464 int ierr_overr; 1465 int ierr_code; 1466 int ierr_crc; 1467 int oerr_underr; 1468 int oerr_deffered; 1469 int oerr_coll; 1470 int oerr_multicoll; 1471 int oerr_exesscoll; 1472 int oerr_latecoll; 1473 int oerr_carrloss; 1474 struct ifnet *ifp = &sc->tl_if; 1475 1476 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1477 ifp->if_opackets += reg & 0x00ffffff; 1478 oerr_underr = reg >> 24; 1479 1480 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1481 ifp->if_ipackets += reg & 0x00ffffff; 1482 ierr_overr = reg >> 24; 1483 1484 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1485 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1486 ierr_code = (reg & TL_FERR_CODE) >> 24; 1487 oerr_deffered = (reg & TL_FERR_DEF); 1488 1489 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1490 oerr_multicoll = (reg & TL_COL_MULTI); 1491 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1492 1493 reg = tl_intreg_read(sc, TL_INT_LERR); 1494 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1495 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1496 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1497 1498 1499 sc->stats_exesscoll += oerr_exesscoll; 1500 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1501 oerr_carrloss; 1502 ifp->if_collisions += oerr_coll + oerr_multicoll; 1503 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1504 1505 if (ierr_overr) 1506 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1507 if (oerr_underr) 1508 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1509 #ifdef TL_PRIV_STATS 1510 sc->ierr_overr += ierr_overr; 1511 sc->ierr_code += ierr_code; 1512 sc->ierr_crc += ierr_crc; 1513 sc->oerr_underr += oerr_underr; 1514 sc->oerr_deffered += oerr_deffered; 1515 sc->oerr_coll += oerr_coll; 1516 sc->oerr_multicoll += oerr_multicoll; 1517 sc->oerr_exesscoll += oerr_exesscoll; 1518 sc->oerr_latecoll += oerr_latecoll; 1519 sc->oerr_carrloss += oerr_carrloss; 1520 #endif 1521 } 1522 1523 static void tl_addr_filter(sc) 1524 tl_softc_t *sc; 1525 { 1526 struct ether_multistep step; 1527 struct ether_multi *enm; 1528 u_int32_t hash[2] = {0, 0}; 1529 int i; 1530 1531 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1532 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1533 while (enm != NULL) { 1534 #ifdef TLDEBUG 1535 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1536 #endif 1537 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1538 i = tl_multicast_hash(enm->enm_addrlo); 1539 hash[i/32] |= 1 << (i%32); 1540 } else { 1541 hash[0] = hash[1] = 0xffffffff; 1542 sc->tl_if.if_flags |= IFF_ALLMULTI; 1543 break; 1544 } 1545 ETHER_NEXT_MULTI(step, enm); 1546 } 1547 #ifdef TLDEBUG 1548 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1549 #endif 1550 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1551 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1552 } 1553 1554 static int tl_multicast_hash(a) 1555 u_int8_t *a; 1556 { 1557 int hash; 1558 1559 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1560 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1561 1562 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1563 DA(a,36), DA(a,42)); 1564 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1565 DA(a,37), DA(a,43)) << 1; 1566 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1567 DA(a,38), DA(a,44)) << 2; 1568 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1569 DA(a,39), DA(a,45)) << 3; 1570 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1571 DA(a,40), DA(a,46)) << 4; 1572 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1573 DA(a,41), DA(a,47)) << 5; 1574 1575 return hash; 1576 } 1577 1578 #if defined(TLDEBUG_RX) 1579 void ether_printheader(eh) 1580 struct ether_header *eh; 1581 { 1582 u_char *c = (char*)eh; 1583 int i; 1584 for (i=0; i<sizeof(struct ether_header); i++) 1585 printf("%x ", (u_int)c[i]); 1586 printf("\n"); 1587 } 1588 #endif 1589
Indexes created Tue Sep 23 14:10:03 GMT 2025