if_tl.c revision 1.17
1 /* $NetBSD: if_tl.c,v 1.17 1998/08/15 16:49:33 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 #if defined(__NetBSD__) && defined(__alpha__) 116 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 117 #undef vtophys 118 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va)) 119 #endif 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 10 124 #endif 125 126 /* number of seconds the link can be idle */ 127 #ifndef TL_IDLETIME 128 #define TL_IDLETIME 10 129 #endif 130 131 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 132 static void tl_pci_attach __P((struct device *, struct device *, void *)); 133 static int tl_intr __P((void *)); 134 135 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 136 static int tl_mediachange __P((struct ifnet *)); 137 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 138 static void tl_ifwatchdog __P((struct ifnet *)); 139 static void tl_shutdown __P((void*)); 140 141 static void tl_ifstart __P((struct ifnet *)); 142 static void tl_reset __P((tl_softc_t*)); 143 static int tl_init __P((tl_softc_t*)); 144 static void tl_restart __P((void *)); 145 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 146 static void tl_read_stats __P((tl_softc_t*)); 147 static void tl_ticks __P((void*)); 148 static int tl_multicast_hash __P((u_int8_t*)); 149 static void tl_addr_filter __P((tl_softc_t*)); 150 151 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 152 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 153 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 154 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 155 156 void tl_mii_sync __P((struct tl_softc *)); 157 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 158 159 160 #if defined(TLDEBUG_RX) 161 static void ether_printheader __P((struct ether_header*)); 162 #endif 163 164 int tl_mii_read __P((struct device *, int, int)); 165 void tl_mii_write __P((struct device *, int, int, int)); 166 167 void tl_statchg __P((struct device *)); 168 169 void tl_i2c_set __P((void*, u_int8_t)); 170 void tl_i2c_clr __P((void*, u_int8_t)); 171 int tl_i2c_read __P((void*, u_int8_t)); 172 173 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 174 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 175 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 176 static __inline void netsio_clr(sc, bits) 177 tl_softc_t* sc; 178 u_int8_t bits; 179 { 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 static __inline void netsio_set(sc, bits) 184 tl_softc_t* sc; 185 u_int8_t bits; 186 { 187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 189 } 190 static __inline u_int8_t netsio_read(sc, bits) 191 tl_softc_t* sc; 192 u_int8_t bits; 193 { 194 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 195 } 196 197 struct cfattach tl_ca = { 198 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 199 }; 200 201 const struct tl_product_desc tl_compaq_products[] = { 202 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 203 0, "Compaq Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 205 0, "Compaq Netelligent 10 T" }, 206 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 207 0, "Compaq Integrated NetFlex 3/P" }, 208 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 209 0, "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 211 0, "Compaq Dual Port Netelligent 10/100 TX" }, 212 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 213 0, "Compaq Deskpro 4000 5233MMX" }, 214 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 215 0, "Compaq NetFlex 3/P w/ BNC" }, 216 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 217 0, "Compaq NetFlex 3/P" }, 218 { 0, 0, NULL }, 219 }; 220 221 const struct tl_product_desc tl_ti_products[] = { 222 /* 223 * Built-in Ethernet on the TI TravelMate 5000 224 * docking station; better product description? 225 * XXX Seems to have broken memory-mapped access. 226 */ 227 { PCI_PRODUCT_TI_TLAN, 0, 228 TPF_BROKEN_MEM, "Texas Instruments ThunderLAN" }, 229 { 0, 0, NULL }, 230 }; 231 232 struct tl_vendor_desc { 233 u_int32_t tv_vendor; 234 const struct tl_product_desc *tv_products; 235 }; 236 237 const struct tl_vendor_desc tl_vendors[] = { 238 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 239 { PCI_VENDOR_TI, tl_ti_products }, 240 { 0, NULL }, 241 }; 242 243 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 244 245 const struct tl_product_desc * 246 tl_lookup_product(id) 247 u_int32_t id; 248 { 249 const struct tl_product_desc *tp; 250 const struct tl_vendor_desc *tv; 251 252 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 253 if (PCI_VENDOR(id) == tv->tv_vendor) 254 break; 255 256 if ((tp = tv->tv_products) == NULL) 257 return (NULL); 258 259 for (; tp->tp_desc != NULL; tp++) 260 if (PCI_PRODUCT(id) == tp->tp_product) 261 break; 262 263 if (tp->tp_desc == NULL) 264 return (NULL); 265 266 return (tp); 267 } 268 269 static char *nullbuf = NULL; 270 271 static int 272 tl_pci_match(parent, match, aux) 273 struct device *parent; 274 struct cfdata *match; 275 void *aux; 276 { 277 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 278 279 if (tl_lookup_product(pa->pa_id) != NULL) 280 return (1); 281 282 return (0); 283 } 284 285 static void 286 tl_pci_attach(parent, self, aux) 287 struct device * parent; 288 struct device * self; 289 void * aux; 290 { 291 tl_softc_t *sc = (tl_softc_t *)self; 292 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 293 const struct tl_product_desc *tp; 294 struct ifnet * const ifp = &sc->tl_if; 295 bus_space_tag_t iot, memt; 296 bus_space_handle_t ioh, memh; 297 pci_intr_handle_t intrhandle; 298 const char *intrstr; 299 int i, tmp, ioh_valid, memh_valid; 300 pcireg_t csr; 301 302 printf("\n"); 303 304 tp = tl_lookup_product(pa->pa_id); 305 if (tp == NULL) 306 panic("tl_pci_attach: impossible"); 307 sc->tl_product = tp; 308 309 /* Map the card space. */ 310 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 311 &iot, &ioh, NULL, NULL) == 0); 312 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 313 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 314 0, &memt, &memh, NULL, NULL) == 0); 315 316 if (memh_valid && (tp->tp_flags & TPF_BROKEN_MEM) == 0) { 317 sc->tl_bustag = memt; 318 sc->tl_bushandle = memh; 319 } else if (ioh_valid) { 320 sc->tl_bustag = iot; 321 sc->tl_bushandle = ioh; 322 } else { 323 printf("%s: unable to map device registers\n", 324 sc->sc_dev.dv_xname); 325 return; 326 } 327 328 /* Enable the device. */ 329 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 330 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 331 csr | PCI_COMMAND_MASTER_ENABLE); 332 333 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 334 335 tl_reset(sc); 336 337 /* fill in the i2c struct */ 338 sc->i2cbus.adapter_softc = sc; 339 sc->i2cbus.set_bit = tl_i2c_set; 340 sc->i2cbus.clr_bit = tl_i2c_clr; 341 sc->i2cbus.read_bit = tl_i2c_read; 342 343 #ifdef TLDEBUG 344 printf("default values of INTreg: 0x%x\n", 345 tl_intreg_read(sc, TL_INT_Defaults)); 346 #endif 347 348 /* read mac addr */ 349 for (i=0; i<ETHER_ADDR_LEN; i++) { 350 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 351 if (tmp < 0) { 352 printf("%s: error reading Ethernet adress\n", 353 sc->sc_dev.dv_xname); 354 return; 355 } else { 356 sc->tl_enaddr[i] = tmp; 357 } 358 } 359 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 360 ether_sprintf(sc->tl_enaddr)); 361 362 /* Map and establish interrupts */ 363 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 364 pa->pa_intrline, &intrhandle)) { 365 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 366 return; 367 } 368 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 369 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 370 tl_intr, sc); 371 if (sc->tl_ih == NULL) { 372 printf("%s: couldn't establish interrupt", 373 sc->sc_dev.dv_xname); 374 if (intrstr != NULL) 375 printf(" at %s", intrstr); 376 printf("\n"); 377 return; 378 } 379 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 380 381 /* 382 * Add shutdown hook so that DMA is disabled prior to reboot. Not 383 * doing do could allow DMA to corrupt kernel memory during the 384 * reboot before the driver initializes. 385 */ 386 (void) shutdownhook_establish(tl_shutdown, sc); 387 388 /* 389 * Initialize our media structures and probe the MII. 390 * 391 * Note that we don't care about the media instance. We 392 * are expecting to have multiple PHYs on the 10/100 cards, 393 * and on those cards we exclude the internal PHY from providing 394 * 10baseT. By ignoring the instance, it allows us to not have 395 * to specify it on the command line when switching media. 396 */ 397 sc->tl_mii.mii_ifp = ifp; 398 sc->tl_mii.mii_readreg = tl_mii_read; 399 sc->tl_mii.mii_writereg = tl_mii_write; 400 sc->tl_mii.mii_statchg = tl_statchg; 401 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 402 tl_mediastatus); 403 mii_phy_probe(self, &sc->tl_mii, 0xffffffff); 404 #ifndef notyet /* XXX XXX XXX */ 405 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 406 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 407 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 408 } else 409 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 410 #else 411 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 412 #endif 413 414 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 415 sc->tl_if.if_softc = sc; 416 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 417 ifp->if_ioctl = tl_ifioctl; 418 ifp->if_start = tl_ifstart; 419 ifp->if_watchdog = tl_ifwatchdog; 420 ifp->if_timer = 0; 421 if_attach(ifp); 422 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 423 #if NBPFILTER > 0 424 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 425 sizeof(struct ether_header)); 426 #endif 427 } 428 429 static void 430 tl_reset(sc) 431 tl_softc_t *sc; 432 { 433 int i; 434 435 /* read stats */ 436 if (sc->tl_if.if_flags & IFF_RUNNING) { 437 untimeout(tl_ticks, sc); 438 tl_read_stats(sc); 439 } 440 /* Reset adapter */ 441 TL_HR_WRITE(sc, TL_HOST_CMD, 442 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 443 DELAY(100000); 444 /* Disable interrupts */ 445 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 446 /* setup aregs & hash */ 447 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 448 tl_intreg_write(sc, i, 0); 449 #ifdef TLDEBUG_ADDR 450 printf("Areg & hash registers: \n"); 451 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 452 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 453 #endif 454 /* Setup NetConfig */ 455 tl_intreg_write(sc, TL_INT_NetConfig, 456 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 457 /* Bsize: accept default */ 458 /* TX commit in Acommit: accept default */ 459 /* Load Ld_tmr and Ld_thr */ 460 /* Ld_tmr = 3 */ 461 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 462 /* Ld_thr = 0 */ 463 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 464 /* Unreset MII */ 465 netsio_set(sc, TL_NETSIO_NMRST); 466 DELAY(100000); 467 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 468 sc->tl_flags = 0; 469 sc->opkt = 0; 470 sc->stats_exesscoll = 0; 471 } 472 473 static void tl_shutdown(v) 474 void *v; 475 { 476 tl_softc_t *sc = v; 477 struct Tx_list *Tx; 478 int i; 479 480 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 481 return; 482 /* disable interrupts */ 483 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 484 /* stop TX and RX channels */ 485 TL_HR_WRITE(sc, TL_HOST_CMD, 486 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 487 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 488 DELAY(100000); 489 490 /* stop statistics reading loop, read stats */ 491 untimeout(tl_ticks, sc); 492 tl_read_stats(sc); 493 494 /* deallocate memory allocations */ 495 for (i=0; i< TL_NBUF; i++) { 496 if (sc->Rx_list[i].m) 497 m_freem(sc->Rx_list[i].m); 498 sc->Rx_list[i].m = NULL; 499 } 500 free(sc->Rx_list, M_DEVBUF); 501 sc->Rx_list = NULL; 502 while ((Tx = sc->active_Tx) != NULL) { 503 Tx->hw_list.stat = 0; 504 m_freem(Tx->m); 505 sc->active_Tx = Tx->next; 506 Tx->next = sc->Free_Tx; 507 sc->Free_Tx = Tx; 508 } 509 sc->last_Tx = NULL; 510 free(sc->Tx_list, M_DEVBUF); 511 sc->Tx_list = NULL; 512 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 513 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 514 sc->tl_flags = 0; 515 } 516 517 static void tl_restart(v) 518 void *v; 519 { 520 tl_init(v); 521 } 522 523 static int tl_init(sc) 524 tl_softc_t *sc; 525 { 526 struct ifnet *ifp = &sc->tl_if; 527 int i, s; 528 529 s = splnet(); 530 /* cancel any pending IO */ 531 tl_shutdown(sc); 532 tl_reset(sc); 533 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 534 splx(s); 535 return 0; 536 } 537 /* Set various register to reasonable value */ 538 /* setup NetCmd in promisc mode if needed */ 539 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 540 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 541 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 542 /* Max receive size : MCLBYTES */ 543 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 544 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 545 (MCLBYTES >> 8) & 0xff); 546 547 /* init MAC addr */ 548 for (i = 0; i < ETHER_ADDR_LEN; i++) 549 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 550 /* add multicast filters */ 551 tl_addr_filter(sc); 552 #ifdef TLDEBUG_ADDR 553 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 554 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 555 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 556 #endif 557 558 /* Pre-allocate receivers mbuf, make the lists */ 559 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 560 M_NOWAIT); 561 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 562 M_NOWAIT); 563 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 564 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 565 sc->tl_if.if_flags &= ~IFF_UP; 566 splx(s); 567 return ENOMEM; 568 } 569 for (i=0; i< TL_NBUF; i++) { 570 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 571 printf("%s: out of mbuf for receive list\n", 572 sc->sc_dev.dv_xname); 573 sc->tl_if.if_flags &= ~IFF_UP; 574 splx(s); 575 return ENOMEM; 576 } 577 if (i > 0) { /* chain the list */ 578 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 579 sc->Rx_list[i-1].hw_list.fwd = 580 vtophys(&sc->Rx_list[i].hw_list); 581 #ifdef DIAGNOSTIC 582 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 583 printf("%s: physical addr 0x%x of list not " 584 "properly aligned\n", 585 sc->sc_dev.dv_xname, 586 sc->Rx_list[i-1].hw_list.fwd); 587 #endif 588 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 589 } 590 } 591 sc->Rx_list[TL_NBUF-1].next = NULL; 592 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 593 sc->Tx_list[TL_NBUF-1].next = NULL; 594 595 sc->active_Rx = &sc->Rx_list[0]; 596 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 597 sc->active_Tx = sc->last_Tx = NULL; 598 sc->Free_Tx = &sc->Tx_list[0]; 599 600 if (nullbuf == NULL) 601 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 602 if (nullbuf == NULL) { 603 printf("%s: can't allocate space for pad buffer\n", 604 sc->sc_dev.dv_xname); 605 sc->tl_if.if_flags &= ~IFF_UP; 606 splx(s); 607 return ENOMEM; 608 } 609 bzero(nullbuf, ETHER_MIN_TX); 610 611 /* set media */ 612 mii_mediachg(&sc->tl_mii); 613 614 /* start ticks calls */ 615 timeout(tl_ticks, sc, hz); 616 /* write adress of Rx list and enable interrupts */ 617 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 618 TL_HR_WRITE(sc, TL_HOST_CMD, 619 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 620 sc->tl_if.if_flags |= IFF_RUNNING; 621 sc->tl_if.if_flags &= ~IFF_OACTIVE; 622 return 0; 623 } 624 625 626 static u_int32_t 627 tl_intreg_read(sc, reg) 628 tl_softc_t *sc; 629 u_int32_t reg; 630 { 631 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 632 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 633 } 634 635 static u_int8_t 636 tl_intreg_read_byte(sc, reg) 637 tl_softc_t *sc; 638 u_int32_t reg; 639 { 640 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 641 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 642 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 643 } 644 645 static void 646 tl_intreg_write(sc, reg, val) 647 tl_softc_t *sc; 648 u_int32_t reg; 649 u_int32_t val; 650 { 651 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 652 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 653 } 654 655 static void 656 tl_intreg_write_byte(sc, reg, val) 657 tl_softc_t *sc; 658 u_int32_t reg; 659 u_int8_t val; 660 { 661 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 662 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 663 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 664 } 665 666 void 667 tl_mii_sync(sc) 668 struct tl_softc *sc; 669 { 670 int i; 671 672 netsio_clr(sc, TL_NETSIO_MTXEN); 673 for (i = 0; i < 32; i++) { 674 netsio_clr(sc, TL_NETSIO_MCLK); 675 netsio_set(sc, TL_NETSIO_MCLK); 676 } 677 } 678 679 void 680 tl_mii_sendbits(sc, data, nbits) 681 struct tl_softc *sc; 682 u_int32_t data; 683 int nbits; 684 { 685 int i; 686 687 netsio_set(sc, TL_NETSIO_MTXEN); 688 for (i = 1 << (nbits - 1); i; i = i >> 1) { 689 netsio_clr(sc, TL_NETSIO_MCLK); 690 netsio_read(sc, TL_NETSIO_MCLK); 691 if (data & i) 692 netsio_set(sc, TL_NETSIO_MDATA); 693 else 694 netsio_clr(sc, TL_NETSIO_MDATA); 695 netsio_set(sc, TL_NETSIO_MCLK); 696 netsio_read(sc, TL_NETSIO_MCLK); 697 } 698 } 699 700 int 701 tl_mii_read(self, phy, reg) 702 struct device *self; 703 int phy, reg; 704 { 705 struct tl_softc *sc = (struct tl_softc *)self; 706 int val = 0, i, err; 707 708 /* 709 * Read the PHY register by manually driving the MII control lines. 710 */ 711 712 tl_mii_sync(sc); 713 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 714 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 715 tl_mii_sendbits(sc, phy, 5); 716 tl_mii_sendbits(sc, reg, 5); 717 718 netsio_clr(sc, TL_NETSIO_MTXEN); 719 netsio_clr(sc, TL_NETSIO_MCLK); 720 netsio_set(sc, TL_NETSIO_MCLK); 721 netsio_clr(sc, TL_NETSIO_MCLK); 722 723 err = netsio_read(sc, TL_NETSIO_MDATA); 724 netsio_set(sc, TL_NETSIO_MCLK); 725 726 /* Even if an error occurs, must still clock out the cycle. */ 727 for (i = 0; i < 16; i++) { 728 val <<= 1; 729 netsio_clr(sc, TL_NETSIO_MCLK); 730 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 731 val |= 1; 732 netsio_set(sc, TL_NETSIO_MCLK); 733 } 734 netsio_clr(sc, TL_NETSIO_MCLK); 735 netsio_set(sc, TL_NETSIO_MCLK); 736 737 return (err ? 0 : val); 738 } 739 740 void 741 tl_mii_write(self, phy, reg, val) 742 struct device *self; 743 int phy, reg, val; 744 { 745 struct tl_softc *sc = (struct tl_softc *)self; 746 747 /* 748 * Write the PHY register by manually driving the MII control lines. 749 */ 750 751 tl_mii_sync(sc); 752 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 753 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 754 tl_mii_sendbits(sc, phy, 5); 755 tl_mii_sendbits(sc, reg, 5); 756 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 757 tl_mii_sendbits(sc, val, 16); 758 759 netsio_clr(sc, TL_NETSIO_MCLK); 760 netsio_set(sc, TL_NETSIO_MCLK); 761 } 762 763 void 764 tl_statchg(self) 765 struct device *self; 766 { 767 tl_softc_t *sc = (struct tl_softc *)self; 768 u_int32_t reg; 769 770 #ifdef TLDEBUG 771 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 772 #endif 773 774 /* 775 * We must keep the ThunderLAN and the PHY in sync as 776 * to the status of full-duplex! 777 */ 778 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 779 if (sc->tl_mii.mii_media_active & IFM_FDX) 780 reg |= TL_NETCOMMAND_DUPLEX; 781 else 782 reg &= ~TL_NETCOMMAND_DUPLEX; 783 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 784 785 /* XXX Update ifp->if_baudrate */ 786 } 787 788 void tl_i2c_set(v, bit) 789 void *v; 790 u_int8_t bit; 791 { 792 tl_softc_t *sc = v; 793 794 switch (bit) { 795 case I2C_DATA: 796 netsio_set(sc, TL_NETSIO_EDATA); 797 break; 798 case I2C_CLOCK: 799 netsio_set(sc, TL_NETSIO_ECLOCK); 800 break; 801 case I2C_TXEN: 802 netsio_set(sc, TL_NETSIO_ETXEN); 803 break; 804 default: 805 printf("tl_i2c_set: unknown bit %d\n", bit); 806 } 807 return; 808 } 809 810 void tl_i2c_clr(v, bit) 811 void *v; 812 u_int8_t bit; 813 { 814 tl_softc_t *sc = v; 815 816 switch (bit) { 817 case I2C_DATA: 818 netsio_clr(sc, TL_NETSIO_EDATA); 819 break; 820 case I2C_CLOCK: 821 netsio_clr(sc, TL_NETSIO_ECLOCK); 822 break; 823 case I2C_TXEN: 824 netsio_clr(sc, TL_NETSIO_ETXEN); 825 break; 826 default: 827 printf("tl_i2c_clr: unknown bit %d\n", bit); 828 } 829 return; 830 } 831 832 int tl_i2c_read(v, bit) 833 void *v; 834 u_int8_t bit; 835 { 836 tl_softc_t *sc = v; 837 838 switch (bit) { 839 case I2C_DATA: 840 return netsio_read(sc, TL_NETSIO_EDATA); 841 break; 842 case I2C_CLOCK: 843 return netsio_read(sc, TL_NETSIO_ECLOCK); 844 break; 845 case I2C_TXEN: 846 return netsio_read(sc, TL_NETSIO_ETXEN); 847 break; 848 default: 849 printf("tl_i2c_read: unknown bit %d\n", bit); 850 return -1; 851 } 852 } 853 854 static int 855 tl_intr(v) 856 void *v; 857 { 858 tl_softc_t *sc = v; 859 struct ifnet *ifp = &sc->tl_if; 860 struct Rx_list *Rx; 861 struct Tx_list *Tx; 862 struct mbuf *m; 863 u_int32_t int_type, int_reg; 864 int ack = 0; 865 int size; 866 867 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 868 int_type = int_reg & TL_INTR_MASK; 869 if (int_type == 0) 870 return 0; 871 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 872 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 873 int_type, int_reg); 874 #endif 875 /* disable interrupts */ 876 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 877 switch(int_type & TL_INTR_MASK) { 878 case TL_INTR_RxEOF: 879 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 880 /* dequeue and requeue at end of list */ 881 ack++; 882 Rx = sc->active_Rx; 883 sc->active_Rx = Rx->next; 884 m = Rx->m; 885 size = Rx->hw_list.stat >> 16; 886 #ifdef TLDEBUG_RX 887 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 888 Rx, size); 889 #endif 890 if (tl_add_RxBuff(Rx, m ) == 0) { 891 /* 892 * No new mbuf, reuse the same. This means 893 * that this packet 894 * is lost 895 */ 896 m = NULL; 897 #ifdef TL_PRIV_STATS 898 sc->ierr_nomem++; 899 #endif 900 #ifdef TLDEBUG 901 printf("%s: out of mbuf, lost input packet\n", 902 sc->sc_dev.dv_xname); 903 #endif 904 } 905 Rx->next = NULL; 906 Rx->hw_list.fwd = 0; 907 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 908 #ifdef DIAGNOSTIC 909 if (sc->last_Rx->hw_list.fwd & 0x7) 910 printf("%s: physical addr 0x%x of list not " 911 "properly aligned\n", 912 sc->sc_dev.dv_xname, 913 sc->last_Rx->hw_list.fwd); 914 #endif 915 sc->last_Rx->next = Rx; 916 sc->last_Rx = Rx; 917 918 /* deliver packet */ 919 if (m) { 920 struct ether_header *eh; 921 if (size < sizeof(struct ether_header)) { 922 m_freem(m); 923 continue; 924 } 925 m->m_pkthdr.rcvif = ifp; 926 m->m_pkthdr.len = m->m_len = 927 size - sizeof(struct ether_header); 928 eh = mtod(m, struct ether_header *); 929 #ifdef TLDEBUG_RX 930 printf("tl_intr: Rx packet:\n"); 931 ether_printheader(eh); 932 #endif 933 #if NBPFILTER > 0 934 if (ifp->if_bpf) { 935 bpf_tap(ifp->if_bpf, 936 mtod(m, caddr_t), size); 937 /* 938 * Only pass this packet up 939 * if it is for us. 940 */ 941 if ((ifp->if_flags & IFF_PROMISC) && 942 /* !mcast and !bcast */ 943 (eh->ether_dhost[0] & 1) == 0 && 944 bcmp(eh->ether_dhost, 945 LLADDR(ifp->if_sadl), 946 sizeof(eh->ether_dhost)) != 0) { 947 m_freem(m); 948 continue; 949 } 950 } 951 #endif /* NBPFILTER > 0 */ 952 m->m_data += sizeof(struct ether_header); 953 ether_input(ifp, eh, m); 954 } 955 } 956 #ifdef TLDEBUG_RX 957 printf("TL_INTR_RxEOF: ack %d\n", ack); 958 #else 959 if (ack == 0) { 960 printf("%s: EOF intr without anything to read !\n", 961 sc->sc_dev.dv_xname); 962 tl_reset(sc); 963 /* shedule reinit of the board */ 964 timeout(tl_restart, sc, 1); 965 return(1); 966 } 967 #endif 968 break; 969 case TL_INTR_RxEOC: 970 ack++; 971 #ifdef TLDEBUG_RX 972 printf("TL_INTR_RxEOC: ack %d\n", ack); 973 #endif 974 #ifdef DIAGNOSTIC 975 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 976 printf("%s: Rx EOC interrupt and active Rx list not " 977 "cleared\n", sc->sc_dev.dv_xname); 978 return 0; 979 } else 980 #endif 981 { 982 /* 983 * write adress of Rx list and send Rx GO command, ack 984 * interrupt and enable interrupts in one command 985 */ 986 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 987 vtophys(&sc->active_Rx->hw_list)); 988 TL_HR_WRITE(sc, TL_HOST_CMD, 989 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 990 HOST_CMD_ACK | HOST_CMD_IntOn); 991 return 1; 992 } 993 case TL_INTR_TxEOF: 994 case TL_INTR_TxEOC: 995 while ((Tx = sc->active_Tx) != NULL) { 996 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 997 break; 998 ack++; 999 #ifdef TLDEBUG_TX 1000 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1001 vtophys(&Tx->hw_list)); 1002 #endif 1003 Tx->hw_list.stat = 0; 1004 m_freem(Tx->m); 1005 Tx->m = NULL; 1006 sc->active_Tx = Tx->next; 1007 if (sc->active_Tx == NULL) 1008 sc->last_Tx = NULL; 1009 Tx->next = sc->Free_Tx; 1010 sc->Free_Tx = Tx; 1011 } 1012 /* if this was an EOC, ACK immediatly */ 1013 if (int_type == TL_INTR_TxEOC) { 1014 #ifdef TLDEBUG_TX 1015 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1016 ack); 1017 #endif 1018 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1019 HOST_CMD_ACK | HOST_CMD_IntOn); 1020 if ( sc->active_Tx != NULL) { 1021 /* needs a Tx go command */ 1022 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1023 vtophys(&sc->active_Tx->hw_list)); 1024 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1025 } 1026 sc->tl_if.if_timer = 0; 1027 if (sc->tl_if.if_snd.ifq_head != NULL) 1028 tl_ifstart(&sc->tl_if); 1029 return 1; 1030 } 1031 #ifdef TLDEBUG 1032 else { 1033 printf("TL_INTR_TxEOF: ack %d\n", ack); 1034 } 1035 #endif 1036 sc->tl_if.if_timer = 0; 1037 if (sc->tl_if.if_snd.ifq_head != NULL) 1038 tl_ifstart(&sc->tl_if); 1039 break; 1040 case TL_INTR_Stat: 1041 ack++; 1042 #ifdef TLDEBUG 1043 printf("TL_INTR_Stat: ack %d\n", ack); 1044 #endif 1045 tl_read_stats(sc); 1046 break; 1047 case TL_INTR_Adc: 1048 if (int_reg & TL_INTVec_MASK) { 1049 /* adapter check conditions */ 1050 printf("%s: check condition, intvect=0x%x, " 1051 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1052 int_reg & TL_INTVec_MASK, 1053 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1054 tl_reset(sc); 1055 /* shedule reinit of the board */ 1056 timeout(tl_restart, sc, 1); 1057 return(1); 1058 } else { 1059 u_int8_t netstat; 1060 /* Network status */ 1061 netstat = 1062 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1063 printf("%s: network status, NetSts=%x\n", 1064 sc->sc_dev.dv_xname, netstat); 1065 /* Ack interrupts */ 1066 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1067 netstat); 1068 ack++; 1069 } 1070 break; 1071 default: 1072 printf("%s: unhandled interrupt code %x!\n", 1073 sc->sc_dev.dv_xname, int_type); 1074 ack++; 1075 } 1076 1077 if (ack) { 1078 /* Ack the interrupt and enable interrupts */ 1079 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1080 HOST_CMD_IntOn); 1081 return 1; 1082 } 1083 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1084 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1085 return 0; 1086 } 1087 1088 static int 1089 tl_ifioctl(ifp, cmd, data) 1090 struct ifnet *ifp; 1091 ioctl_cmd_t cmd; 1092 caddr_t data; 1093 { 1094 struct tl_softc *sc = ifp->if_softc; 1095 struct ifreq *ifr = (struct ifreq *)data; 1096 int s, error; 1097 1098 s = splnet(); 1099 switch(cmd) { 1100 case SIOCSIFADDR: { 1101 struct ifaddr *ifa = (struct ifaddr *)data; 1102 sc->tl_if.if_flags |= IFF_UP; 1103 if ((error = tl_init(sc)) != NULL) { 1104 sc->tl_if.if_flags &= ~IFF_UP; 1105 break; 1106 } 1107 switch (ifa->ifa_addr->sa_family) { 1108 #ifdef INET 1109 case AF_INET: 1110 arp_ifinit(ifp, ifa); 1111 break; 1112 #endif 1113 #ifdef NS 1114 case AF_NS: { 1115 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1116 1117 if (ns_nullhost(*ina)) 1118 ina->x_host = 1119 (union ns_host*) LLADDR(ifp->if_sadl); 1120 else 1121 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1122 ifp->if_addrlen); 1123 break; 1124 } 1125 #endif 1126 default: 1127 break; 1128 } 1129 break; 1130 } 1131 case SIOCSIFFLAGS: 1132 { 1133 u_int8_t reg; 1134 /* 1135 * If interface is marked up and not running, then start it. 1136 * If it is marked down and running, stop it. 1137 */ 1138 if (ifp->if_flags & IFF_UP) { 1139 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1140 error = tl_init(sc); 1141 /* all flags have been handled by init */ 1142 break; 1143 } 1144 error = 0; 1145 reg = tl_intreg_read_byte(sc, 1146 TL_INT_NET + TL_INT_NetCmd); 1147 if (ifp->if_flags & IFF_PROMISC) 1148 reg |= TL_NETCOMMAND_CAF; 1149 else 1150 reg &= ~TL_NETCOMMAND_CAF; 1151 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1152 reg); 1153 #ifdef TL_PRIV_STATS 1154 if (ifp->if_flags & IFF_LINK0) { 1155 ifp->if_flags &= ~IFF_LINK0; 1156 printf("%s errors statistics\n", 1157 sc->sc_dev.dv_xname); 1158 printf(" %4d RX buffer overrun\n", 1159 sc->ierr_overr); 1160 printf(" %4d RX code error\n", 1161 sc->ierr_code); 1162 printf(" %4d RX crc error\n", 1163 sc->ierr_crc); 1164 printf(" %4d RX out of memory\n", 1165 sc->ierr_nomem); 1166 printf(" %4d TX buffer underrun\n", 1167 sc->oerr_underr); 1168 printf(" %4d TX deffered frames\n", 1169 sc->oerr_deffered); 1170 printf(" %4d TX single collisions\n", 1171 sc->oerr_coll); 1172 printf(" %4d TX multi collisions\n", 1173 sc->oerr_multicoll); 1174 printf(" %4d TX exessive collisions\n", 1175 sc->oerr_exesscoll); 1176 printf(" %4d TX late collisions\n", 1177 sc->oerr_latecoll); 1178 printf(" %4d TX carrier loss\n", 1179 sc->oerr_carrloss); 1180 printf(" %4d TX mbuf copy\n", 1181 sc->oerr_mcopy); 1182 } 1183 #endif 1184 } else { 1185 if (ifp->if_flags & IFF_RUNNING) 1186 tl_shutdown(sc); 1187 error = 0; 1188 } 1189 break; 1190 } 1191 case SIOCADDMULTI: 1192 case SIOCDELMULTI: 1193 /* 1194 * Update multicast listeners 1195 */ 1196 if (cmd == SIOCADDMULTI) 1197 error = ether_addmulti(ifr, &sc->tl_ec); 1198 else 1199 error = ether_delmulti(ifr, &sc->tl_ec); 1200 if (error == ENETRESET) { 1201 tl_addr_filter(sc); 1202 error = 0; 1203 } 1204 break; 1205 case SIOCSIFMEDIA: 1206 case SIOCGIFMEDIA: 1207 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1208 break; 1209 default: 1210 error = EINVAL; 1211 } 1212 splx(s); 1213 return error; 1214 } 1215 1216 static void 1217 tl_ifstart(ifp) 1218 struct ifnet *ifp; 1219 { 1220 tl_softc_t *sc = ifp->if_softc; 1221 struct mbuf *m, *mb_head; 1222 struct Tx_list *Tx; 1223 int segment, size; 1224 1225 txloop: 1226 /* If we don't have more space ... */ 1227 if (sc->Free_Tx == NULL) { 1228 #ifdef TLDEBUG 1229 printf("tl_ifstart: No free TX list\n"); 1230 #endif 1231 return; 1232 } 1233 /* Grab a paquet for output */ 1234 IF_DEQUEUE(&ifp->if_snd, mb_head); 1235 if (mb_head == NULL) { 1236 #ifdef TLDEBUG_TX 1237 printf("tl_ifstart: nothing to send\n"); 1238 #endif 1239 return; 1240 } 1241 Tx = sc->Free_Tx; 1242 sc->Free_Tx = Tx->next; 1243 /* 1244 * Go through each of the mbufs in the chain and initialize 1245 * the transmit list descriptors with the physical address 1246 * and size of the mbuf. 1247 */ 1248 tbdinit: 1249 bzero(Tx, sizeof(struct Tx_list)); 1250 Tx->m = mb_head; 1251 size = 0; 1252 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1253 if (m->m_len != 0) { 1254 if (segment == TL_NSEG) 1255 break; 1256 size += m->m_len; 1257 Tx->hw_list.seg[segment].data_addr = 1258 vtophys(mtod(m, vaddr_t)); 1259 Tx->hw_list.seg[segment].data_count = m->m_len; 1260 segment++; 1261 } 1262 } 1263 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1264 /* 1265 * We ran out of segments, or we will. We have to recopy this 1266 * mbuf chain first. 1267 */ 1268 struct mbuf *mn; 1269 #ifdef TLDEBUG_TX 1270 printf("tl_ifstart: need to copy mbuf\n"); 1271 #endif 1272 #ifdef TL_PRIV_STATS 1273 sc->oerr_mcopy++; 1274 #endif 1275 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1276 if (mn == NULL) { 1277 m_freem(mb_head); 1278 goto bad; 1279 } 1280 if (mb_head->m_pkthdr.len > MHLEN) { 1281 MCLGET(mn, M_DONTWAIT); 1282 if ((mn->m_flags & M_EXT) == 0) { 1283 m_freem(mn); 1284 m_freem(mb_head); 1285 goto bad; 1286 } 1287 } 1288 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1289 mtod(mn, caddr_t)); 1290 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1291 m_freem(mb_head); 1292 mb_head = mn; 1293 goto tbdinit; 1294 } 1295 /* We are at end of mbuf chain. check the size and 1296 * see if it needs to be extended 1297 */ 1298 if (size < ETHER_MIN_TX) { 1299 #ifdef DIAGNOSTIC 1300 if (segment >= TL_NSEG) { 1301 panic("tl_ifstart: to much segmets (%d)\n", segment); 1302 } 1303 #endif 1304 /* 1305 * add the nullbuf in the seg 1306 */ 1307 Tx->hw_list.seg[segment].data_count = 1308 ETHER_MIN_TX - size; 1309 Tx->hw_list.seg[segment].data_addr = 1310 vtophys(nullbuf); 1311 size = ETHER_MIN_TX; 1312 segment++; 1313 } 1314 /* The list is done, finish the list init */ 1315 Tx->hw_list.seg[segment-1].data_count |= 1316 TL_LAST_SEG; 1317 Tx->hw_list.stat = (size << 16) | 0x3000; 1318 #ifdef TLDEBUG_TX 1319 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1320 Tx->hw_list.stat); 1321 #if 0 1322 for(segment = 0; segment < TL_NSEG; segment++) { 1323 printf(" seg %d addr 0x%x len 0x%x\n", 1324 segment, 1325 Tx->hw_list.seg[segment].data_addr, 1326 Tx->hw_list.seg[segment].data_count); 1327 } 1328 #endif 1329 #endif 1330 sc->opkt++; 1331 if (sc->active_Tx == NULL) { 1332 sc->active_Tx = sc->last_Tx = Tx; 1333 #ifdef TLDEBUG_TX 1334 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1335 vtophys(&Tx->hw_list)); 1336 #endif 1337 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1338 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1339 } else { 1340 #ifdef TLDEBUG_TX 1341 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1342 vtophys(&Tx->hw_list)); 1343 #endif 1344 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1345 sc->last_Tx->next = Tx; 1346 sc->last_Tx = Tx; 1347 #ifdef DIAGNOSTIC 1348 if (sc->last_Tx->hw_list.fwd & 0x7) 1349 printf("%s: physical addr 0x%x of list not properly " 1350 "aligned\n", 1351 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1352 #endif 1353 } 1354 #if NBPFILTER > 0 1355 /* Pass packet to bpf if there is a listener */ 1356 if (ifp->if_bpf) 1357 bpf_mtap(ifp->if_bpf, mb_head); 1358 #endif 1359 /* 1360 * Set a 5 second timer just in case we don't hear from the card again. 1361 */ 1362 ifp->if_timer = 5; 1363 goto txloop; 1364 bad: 1365 #ifdef TLDEBUG 1366 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1367 #endif 1368 Tx->next = sc->Free_Tx; 1369 sc->Free_Tx = Tx; 1370 return; 1371 } 1372 1373 static void 1374 tl_ifwatchdog(ifp) 1375 struct ifnet *ifp; 1376 { 1377 tl_softc_t *sc = ifp->if_softc; 1378 1379 if ((ifp->if_flags & IFF_RUNNING) == 0) 1380 return; 1381 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1382 ifp->if_oerrors++; 1383 tl_init(sc); 1384 } 1385 1386 static int 1387 tl_mediachange(ifp) 1388 struct ifnet *ifp; 1389 { 1390 1391 if (ifp->if_flags & IFF_UP) 1392 tl_init(ifp->if_softc); 1393 return (0); 1394 } 1395 1396 static void 1397 tl_mediastatus(ifp, ifmr) 1398 struct ifnet *ifp; 1399 struct ifmediareq *ifmr; 1400 { 1401 tl_softc_t *sc = ifp->if_softc; 1402 1403 mii_pollstat(&sc->tl_mii); 1404 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1405 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1406 } 1407 1408 static int tl_add_RxBuff(Rx, oldm) 1409 struct Rx_list *Rx; 1410 struct mbuf *oldm; 1411 { 1412 struct mbuf *m; 1413 1414 MGETHDR(m, M_DONTWAIT, MT_DATA); 1415 if (m != NULL) { 1416 MCLGET(m, M_DONTWAIT); 1417 if ((m->m_flags & M_EXT) == 0) { 1418 m_freem(m); 1419 if (oldm == NULL) 1420 return 0; 1421 m = oldm; 1422 m->m_data = m->m_ext.ext_buf; 1423 } 1424 } else { 1425 if (oldm == NULL) 1426 return 0; 1427 m = oldm; 1428 m->m_data = m->m_ext.ext_buf; 1429 } 1430 /* 1431 * Move the data pointer up so that the incoming data packet 1432 * will be 32-bit aligned. 1433 */ 1434 m->m_data += 2; 1435 1436 /* (re)init the Rx_list struct */ 1437 1438 Rx->m = m; 1439 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1440 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1441 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1442 return (m != oldm); 1443 } 1444 1445 static void tl_ticks(v) 1446 void *v; 1447 { 1448 tl_softc_t *sc = v; 1449 1450 tl_read_stats(sc); 1451 if (sc->opkt > 0) { 1452 if (sc->oerr_exesscoll > sc->opkt / 100) { 1453 /* exess collisions */ 1454 if (sc->tl_flags & TL_IFACT) /* only print once */ 1455 printf("%s: no carrier\n", 1456 sc->sc_dev.dv_xname); 1457 sc->tl_flags &= ~TL_IFACT; 1458 } else 1459 sc->tl_flags |= TL_IFACT; 1460 sc->oerr_exesscoll = sc->opkt = 0; 1461 sc->tl_lasttx = 0; 1462 } else { 1463 sc->tl_lasttx++; 1464 if (sc->tl_lasttx >= TL_IDLETIME) { 1465 /* 1466 * No TX activity in the last TL_IDLETIME seconds. 1467 * sends a LLC Class1 TEST pkt 1468 */ 1469 struct mbuf *m; 1470 int s; 1471 MGETHDR(m, M_DONTWAIT, MT_DATA); 1472 if (m != NULL) { 1473 #ifdef TLDEBUG 1474 printf("tl_ticks: sending LLC test pkt\n"); 1475 #endif 1476 bcopy(sc->tl_enaddr, 1477 mtod(m, struct ether_header *)->ether_dhost, 1478 6); 1479 bcopy(sc->tl_enaddr, 1480 mtod(m, struct ether_header *)->ether_shost, 1481 6); 1482 mtod(m, struct ether_header *)->ether_type = 1483 htons(3); 1484 mtod(m, unsigned char *)[14] = 0; 1485 mtod(m, unsigned char *)[15] = 0; 1486 mtod(m, unsigned char *)[16] = 0xE3; 1487 /* LLC Class1 TEST (no poll) */ 1488 m->m_len = m->m_pkthdr.len = 1489 sizeof(struct ether_header) + 3; 1490 s = splnet(); 1491 IF_PREPEND(&sc->tl_if.if_snd, m); 1492 tl_ifstart(&sc->tl_if); 1493 splx(s); 1494 } 1495 } 1496 } 1497 1498 /* read statistics every seconds */ 1499 timeout(tl_ticks, v, hz); 1500 } 1501 1502 static void 1503 tl_read_stats(sc) 1504 tl_softc_t *sc; 1505 { 1506 u_int32_t reg; 1507 int ierr_overr; 1508 int ierr_code; 1509 int ierr_crc; 1510 int oerr_underr; 1511 int oerr_deffered; 1512 int oerr_coll; 1513 int oerr_multicoll; 1514 int oerr_exesscoll; 1515 int oerr_latecoll; 1516 int oerr_carrloss; 1517 struct ifnet *ifp = &sc->tl_if; 1518 1519 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1520 ifp->if_opackets += reg & 0x00ffffff; 1521 oerr_underr = reg >> 24; 1522 1523 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1524 ifp->if_ipackets += reg & 0x00ffffff; 1525 ierr_overr = reg >> 24; 1526 1527 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1528 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1529 ierr_code = (reg & TL_FERR_CODE) >> 24; 1530 oerr_deffered = (reg & TL_FERR_DEF); 1531 1532 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1533 oerr_multicoll = (reg & TL_COL_MULTI); 1534 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1535 1536 reg = tl_intreg_read(sc, TL_INT_LERR); 1537 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1538 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1539 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1540 1541 1542 sc->stats_exesscoll += oerr_exesscoll; 1543 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1544 oerr_carrloss; 1545 ifp->if_collisions += oerr_coll + oerr_multicoll; 1546 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1547 1548 if (ierr_overr) 1549 printf("%s: receiver ring buffer overrun\n", 1550 sc->sc_dev.dv_xname); 1551 if (oerr_underr) 1552 printf("%s: transmit buffer underrun\n", 1553 sc->sc_dev.dv_xname); 1554 #ifdef TL_PRIV_STATS 1555 sc->ierr_overr += ierr_overr; 1556 sc->ierr_code += ierr_code; 1557 sc->ierr_crc += ierr_crc; 1558 sc->oerr_underr += oerr_underr; 1559 sc->oerr_deffered += oerr_deffered; 1560 sc->oerr_coll += oerr_coll; 1561 sc->oerr_multicoll += oerr_multicoll; 1562 sc->oerr_exesscoll += oerr_exesscoll; 1563 sc->oerr_latecoll += oerr_latecoll; 1564 sc->oerr_carrloss += oerr_carrloss; 1565 #endif 1566 } 1567 1568 static void tl_addr_filter(sc) 1569 tl_softc_t *sc; 1570 { 1571 struct ether_multistep step; 1572 struct ether_multi *enm; 1573 u_int32_t hash[2] = {0, 0}; 1574 int i; 1575 1576 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1577 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1578 while (enm != NULL) { 1579 #ifdef TLDEBUG 1580 printf("tl_addr_filter: addrs %s %s\n", 1581 ether_sprintf(enm->enm_addrlo), 1582 ether_sprintf(enm->enm_addrhi)); 1583 #endif 1584 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1585 i = tl_multicast_hash(enm->enm_addrlo); 1586 hash[i/32] |= 1 << (i%32); 1587 } else { 1588 hash[0] = hash[1] = 0xffffffff; 1589 sc->tl_if.if_flags |= IFF_ALLMULTI; 1590 break; 1591 } 1592 ETHER_NEXT_MULTI(step, enm); 1593 } 1594 #ifdef TLDEBUG 1595 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1596 #endif 1597 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1598 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1599 } 1600 1601 static int tl_multicast_hash(a) 1602 u_int8_t *a; 1603 { 1604 int hash; 1605 1606 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1607 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1608 1609 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1610 DA(a,36), DA(a,42)); 1611 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1612 DA(a,37), DA(a,43)) << 1; 1613 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1614 DA(a,38), DA(a,44)) << 2; 1615 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1616 DA(a,39), DA(a,45)) << 3; 1617 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1618 DA(a,40), DA(a,46)) << 4; 1619 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1620 DA(a,41), DA(a,47)) << 5; 1621 1622 return hash; 1623 } 1624 1625 #if defined(TLDEBUG_RX) 1626 void 1627 ether_printheader(eh) 1628 struct ether_header *eh; 1629 { 1630 u_char *c = (char*)eh; 1631 int i; 1632 for (i=0; i<sizeof(struct ether_header); i++) 1633 printf("%x ", (u_int)c[i]); 1634 printf("\n"); 1635 } 1636 #endif 1637
Indexes created Tue Sep 23 07:09:52 GMT 2025