if_tl.c revision 1.2
1 /* $NetBSD: if_tl.c,v 1.2 1997/10/21 05:54:31 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include "bpfilter.h" 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <vm/vm.h> 84 #include <vm/vm_param.h> 85 #include <vm/vm_kern.h> 86 87 #if defined(__NetBSD__) 88 #include <net/if_ether.h> 89 #if defined(INET) 90 #include <netinet/if_inarp.h> 91 #endif 92 #include <machine/bus.h> 93 #if defined(__alpha__) 94 #include <machine/intr.h> 95 #endif 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 #include <dev/i2c/i2c_bus.h> 100 #include <dev/i2c/i2c_eeprom.h> 101 #include <dev/mii/mii_adapter.h> 102 #include <dev/mii/mii_adapters_id.h> 103 #include <dev/pci/if_tlregs.h> 104 #endif /* __NetBSD__ */ 105 106 /* number of transmit/receive buffers */ 107 #ifndef TL_NBUF 108 #define TL_NBUF 10 109 #endif 110 111 /* number of seconds the link can be idle */ 112 #ifndef TL_IDLETIME 113 #define TL_IDLETIME 10 114 #endif 115 116 struct tl_softc { 117 struct device sc_dev; /* base device */ 118 bus_space_tag_t tl_bustag; 119 bus_space_handle_t tl_bushandle; /* CSR region handle */ 120 pci_chipset_tag_t tl_pc; 121 void* tl_ih; 122 struct ethercom tl_ec; 123 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 124 struct ifmedia tl_ifmedia; 125 u_int16_t tl_flags; 126 #define TL_IFACT 0x0001 /* chip has interface activity */ 127 u_int8_t tl_lasttx; /* we were without input this many seconds */ 128 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 129 mii_data_t mii; /* mii bus */ 130 struct Rx_list *Rx_list; /* Receive and transmit lists */ 131 struct Tx_list *Tx_list; 132 struct Rx_list *active_Rx, *last_Rx; 133 struct Tx_list *active_Tx, *last_Tx; 134 struct Tx_list *Free_Tx; 135 int opkt; /* used to detect link up/down for AUI/BNC */ 136 int stats_exesscoll; /* idem */ 137 #ifdef TL_PRIV_STATS 138 int ierr_overr; 139 int ierr_code; 140 int ierr_crc; 141 int ierr_nomem; 142 int oerr_underr; 143 int oerr_deffered; 144 int oerr_coll; 145 int oerr_multicoll; 146 int oerr_latecoll; 147 int oerr_exesscoll; 148 int oerr_carrloss; 149 int oerr_mcopy; 150 #endif 151 }; 152 #define tl_if tl_ec.ec_if 153 #define tl_bpf tl_if.if_bpf 154 155 typedef struct tl_softc tl_softc_t; 156 typedef u_long ioctl_cmd_t; 157 158 #define PCI_VENDORID(x) ((x) & 0xFFFF) 159 #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF) 160 #define PCI_CONF_READ(r) pci_conf_read(pa->pa_pc, pa->pa_tag, (r)) 161 #define PCI_CONF_WRITE(r, v) pci_conf_write(pa->pa_pc, pa->pa_tag, (r), (v)) 162 163 #define TL_HR_READ(sc, reg) \ 164 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 165 #define TL_HR_READ_BYTE(sc, reg) \ 166 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 167 #define TL_HR_WRITE(sc, reg, data) \ 168 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 169 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 170 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 171 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 172 173 static int tl_pci_probe __P((struct device *, void *, void *)); 174 static void tl_pci_attach __P((struct device *, struct device *, void *)); 175 static int tl_intr __P((void *)); 176 177 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 178 static int tl_mediachange __P((struct ifnet *)); 179 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 180 static void tl_ifwatchdog __P((struct ifnet *)); 181 static void tl_shutdown __P((void*)); 182 183 static void tl_ifstart __P((struct ifnet *)); 184 static void tl_reset __P((tl_softc_t*)); 185 static int tl_init __P((tl_softc_t*)); 186 static void tl_restart __P((void *)); 187 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 188 static void tl_read_stats __P((tl_softc_t*)); 189 static void tl_ticks __P((void*)); 190 static int tl_multicast_hash __P((u_int8_t*)); 191 static void tl_addr_filter __P((tl_softc_t*)); 192 193 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 194 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 195 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 196 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 197 198 199 #if defined(TLDEBUG_RX) 200 static void ether_printheader __P((struct ether_header*)); 201 #endif 202 203 void tl_mii_set __P((void*, u_int8_t)); 204 void tl_mii_clr __P((void*, u_int8_t)); 205 int tl_mii_read __P((void*, u_int8_t)); 206 207 void tl_i2c_set __P((void*, u_int8_t)); 208 void tl_i2c_clr __P((void*, u_int8_t)); 209 int tl_i2c_read __P((void*, u_int8_t)); 210 211 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 212 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 213 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 214 static __inline void netsio_clr(sc, bits) 215 tl_softc_t* sc; 216 u_int8_t bits; 217 { 218 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 219 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 220 } 221 static __inline void netsio_set(sc, bits) 222 tl_softc_t* sc; 223 u_int8_t bits; 224 { 225 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 226 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 227 } 228 static __inline u_int8_t netsio_read(sc, bits) 229 tl_softc_t* sc; 230 u_int8_t bits; 231 { 232 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 233 } 234 235 struct cfattach tl_ca = { 236 sizeof(tl_softc_t), tl_pci_probe, tl_pci_attach 237 }; 238 239 struct cfdriver tl_cd = { 240 0, "tl", DV_IFNET 241 }; 242 243 static char *nullbuf; 244 245 static int 246 tl_pci_probe(parent, match, aux) 247 struct device *parent; 248 void *match; 249 void *aux; 250 { 251 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 252 253 if (PCI_VENDORID(pa->pa_id) != PCI_VENDOR_COMPAQ) 254 return 0; 255 switch(PCI_CHIPID(pa->pa_id)) { 256 case PCI_PRODUCT_COMPAQ_N100TX: 257 case PCI_PRODUCT_COMPAQ_N10T: 258 case PCI_PRODUCT_COMPAQ_IntNF3P: 259 case PCI_PRODUCT_COMPAQ_IntPL100TX: 260 case PCI_PRODUCT_COMPAQ_DPNet100TX: 261 case PCI_PRODUCT_COMPAQ_DP4000: 262 case PCI_PRODUCT_COMPAQ_NF3P_BNC: 263 case PCI_PRODUCT_COMPAQ_NF3P: 264 return 1; 265 default: 266 return 0; 267 } 268 } 269 270 static void 271 tl_pci_attach(parent, self, aux) 272 struct device * parent; 273 struct device * self; 274 void * aux; 275 { 276 tl_softc_t *sc = (tl_softc_t *)self; 277 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 278 /* int unit = sc->tl_dev.dv_unit; */ 279 struct ifnet * const ifp = &sc->tl_if; 280 u_int32_t cfcs = PCI_CONF_READ(PCI_CFCS); 281 bus_space_tag_t iot, memt; 282 bus_space_handle_t ioh, memh; 283 pci_intr_handle_t intrhandle; 284 const char *model, *intrstr; 285 int i, tmp; 286 287 sc->tl_pc = pa->pa_pc; 288 cfcs &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE); 289 290 /* Map and enable the card */ 291 #if defined(PCI_PREFER_IOSPACE) 292 if (!pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 293 &iot, &ioh, NULL, NULL)) { 294 cfcs |= PCI_COMMAND_IO_ENABLE; 295 } else if (!pci_mapreg_map(pa, PCI_CBMA, 296 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 297 0, &memt, &memh, NULL, NULL) == 0) { 298 cfcs |= PCI_COMMAND_MEM_ENABLE; 299 } else { 300 printf("can't map IO nor MEM space\n"); 301 return; 302 } 303 if (cfcs & PCI_COMMAND_IO_ENABLE) { 304 sc->tl_bustag = iot, sc->tl_bushandle = ioh; 305 } else { 306 sc->tl_bustag = memt, sc->tl_bushandle = memh; 307 } 308 #else 309 if (!pci_mapreg_map(pa, PCI_CBMA, 310 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 311 0, &memt, &memh, NULL, NULL) == 0) { 312 cfcs |= PCI_COMMAND_MEM_ENABLE; 313 } else if (!pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 314 &iot, &ioh, NULL, NULL)) { 315 cfcs |= PCI_COMMAND_IO_ENABLE; 316 } else { 317 printf("can't map MEM nor IO space\n"); 318 return; 319 } 320 if (cfcs & PCI_COMMAND_MEM_ENABLE) { 321 sc->tl_bustag = memt; sc->tl_bushandle = memh; 322 } else { 323 sc->tl_bustag = iot; sc->tl_bushandle = ioh; 324 } 325 #endif 326 327 cfcs |= PCI_COMMAND_MASTER_ENABLE; 328 PCI_CONF_WRITE(PCI_CFCS, cfcs); 329 330 switch(PCI_CHIPID(pa->pa_id)) { 331 case PCI_PRODUCT_COMPAQ_N100TX: 332 model = "Compaq Netelligent 10/100 TX"; 333 sc->mii.adapter_id = COMPAQ_NETLIGENT_10_100; 334 break; 335 case PCI_PRODUCT_COMPAQ_N10T: 336 model = "Compaq Netelligent 10 T"; 337 sc->mii.adapter_id = COMPAQ_NETLIGENT_10; 338 break; 339 case PCI_PRODUCT_COMPAQ_IntNF3P: 340 model = "Compaq Integrated NetFlex 3/P"; 341 sc->mii.adapter_id = COMPAQ_INT_NETFLEX; 342 break; 343 case PCI_PRODUCT_COMPAQ_IntPL100TX: 344 model = "Compaq ProLiant Integrated Netelligent 10/100 TX"; 345 sc->mii.adapter_id = COMPAQ_INT_NETLIGENT_10_100; 346 break; 347 case PCI_PRODUCT_COMPAQ_DPNet100TX: 348 model = "Compaq Dual Port Netelligent 10/100 TX"; 349 sc->mii.adapter_id = COMPAQ_DUAL_NETLIGENT_10_100; 350 break; 351 case PCI_PRODUCT_COMPAQ_DP4000: 352 model = "Compaq Deskpro 4000 5233MMX"; 353 sc->mii.adapter_id = COMPAQ_DSKP4000; 354 break; 355 case PCI_PRODUCT_COMPAQ_NF3P_BNC: 356 model = "Compaq NetFlex 3/P w/ BNC"; 357 sc->mii.adapter_id = COMPAQ_NETFLEX_BNC; 358 break; 359 case PCI_PRODUCT_COMPAQ_NF3P: 360 model = "Compaq NetFlex 3/P"; 361 sc->mii.adapter_id = COMPAQ_NETFLEX; 362 break; 363 default: 364 model = "unknown ThunderLAN board!\n"; 365 } 366 printf(": %s\n%s: ",model, sc->sc_dev.dv_xname); 367 368 /* Map and establish interrupts */ 369 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 370 pa->pa_intrline, &intrhandle)) { 371 printf("couldn't map interrupt\n"); 372 return; 373 } 374 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 375 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 376 tl_intr, sc); 377 if (sc->tl_ih == NULL) { 378 printf("couldn't map interrupt"); 379 if (intrstr != NULL) 380 printf(" at %s", intrstr); 381 printf("\n"); 382 return; 383 } 384 printf("interrupting at %s\n", intrstr); 385 386 387 tl_reset(sc); 388 389 /* fill in the i2c struct */ 390 sc->i2cbus.adapter_softc = sc; 391 sc->i2cbus.set_bit = tl_i2c_set; 392 sc->i2cbus.clr_bit = tl_i2c_clr; 393 sc->i2cbus.read_bit = tl_i2c_read; 394 395 #ifdef TLDEBUG 396 printf("default values of INTreg: 0x%x\n", 397 tl_intreg_read(sc, TL_INT_Defaults)); 398 #endif 399 400 /* read mac addr */ 401 for (i=0; i<ETHER_ADDR_LEN; i++) { 402 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 403 if (tmp < 0) { 404 printf("%s: error reading MAC adress\n", sc->sc_dev.dv_xname); 405 return; 406 } else { 407 sc->tl_enaddr[i] = tmp; 408 } 409 } 410 printf("%s: address %s\n", sc->sc_dev.dv_xname, 411 ether_sprintf(sc->tl_enaddr)); 412 413 sc->mii.adapter_softc = sc; 414 sc->mii.mii_setbit = tl_mii_set; 415 sc->mii.mii_clrbit = tl_mii_clr; 416 sc->mii.mii_readbit = tl_mii_read; 417 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 418 sc->mii.mii_writereg = NULL; 419 if (config_found(self, (void*)&sc->mii, NULL) == NULL) { 420 printf("%s: no mii configured\n", sc->sc_dev.dv_xname); 421 return; 422 } 423 424 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 425 mii_media_add(&sc->tl_ifmedia, &sc->mii); 426 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 427 428 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 429 sc->tl_if.if_softc = sc; 430 sc->tl_pc = pa->pa_pc; 431 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 432 ifp->if_ioctl = tl_ifioctl; 433 ifp->if_start = tl_ifstart; 434 ifp->if_watchdog = tl_ifwatchdog; 435 ifp->if_timer = 0; 436 if_attach(ifp); 437 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 438 #if NBPFILTER > 0 439 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 440 sizeof(struct ether_header)); 441 #endif 442 sc->mii.mii_media_active = IFM_NONE; 443 /* 444 * Add shutdown hook so that DMA is disabled prior to reboot. Not 445 * doing do could allow DMA to corrupt kernel memory during the 446 * reboot before the driver initializes. 447 */ 448 shutdownhook_establish(tl_shutdown, sc); 449 } 450 451 static void 452 tl_reset(sc) 453 tl_softc_t *sc; 454 { 455 int i; 456 457 /* read stats */ 458 if (sc->tl_if.if_flags & IFF_RUNNING) { 459 untimeout(tl_ticks, sc); 460 tl_read_stats(sc); 461 } 462 /* Reset adapter */ 463 TL_HR_WRITE(sc, TL_HOST_CMD, 464 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 465 DELAY(100000); 466 /* Disable interrupts */ 467 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 468 /* setup aregs & hash */ 469 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 470 tl_intreg_write(sc, i, 0); 471 #ifdef TLDEBUG_ADDR 472 printf("Areg & hash registers: \n"); 473 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 474 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 475 #endif 476 /* Setup NetConfig */ 477 tl_intreg_write(sc, TL_INT_NetConfig, 478 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 479 /* Bsize: accept default */ 480 /* TX commit in Acommit: accept default */ 481 /* Load Ld_tmr and Ld_thr */ 482 /* Ld_tmr = 3 */ 483 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 484 /* Ld_thr = 0 */ 485 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 486 /* Unreset MII */ 487 netsio_set(sc, TL_NETSIO_NMRST); 488 DELAY(100000); 489 sc->mii.mii_media_status &= ~IFM_ACTIVE; 490 sc->tl_flags = 0; 491 sc->opkt = 0; 492 sc->stats_exesscoll = 0; 493 } 494 495 static void tl_shutdown(v) 496 void *v; 497 { 498 tl_softc_t *sc = v; 499 struct Tx_list *Tx; 500 int i; 501 502 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 503 return; 504 /* disable interrupts */ 505 TL_HR_WRITE(sc, TL_HOST_CMD, 506 HOST_CMD_IntOff); 507 /* stop TX and RX channels */ 508 TL_HR_WRITE(sc, TL_HOST_CMD, 509 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 510 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 511 DELAY(100000); 512 513 /* stop statistics reading loop, read stats */ 514 untimeout(tl_ticks, sc); 515 tl_read_stats(sc); 516 517 /* deallocate memory allocations */ 518 for (i=0; i< TL_NBUF; i++) { 519 if (sc->Rx_list[i].m) 520 m_freem(sc->Rx_list[i].m); 521 sc->Rx_list[i].m = NULL; 522 } 523 free(sc->Rx_list, M_DEVBUF); 524 sc->Rx_list = NULL; 525 while ((Tx = sc->active_Tx) != NULL) { 526 Tx->hw_list.stat = 0; 527 m_freem(Tx->m); 528 sc->active_Tx = Tx->next; 529 Tx->next = sc->Free_Tx; 530 sc->Free_Tx = Tx; 531 } 532 sc->last_Tx = NULL; 533 free(sc->Tx_list, M_DEVBUF); 534 sc->Tx_list = NULL; 535 if (nullbuf) 536 free(nullbuf, M_DEVBUF); 537 nullbuf = NULL; 538 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 539 sc->mii.mii_media_status &= ~IFM_ACTIVE; 540 sc->tl_flags = 0; 541 } 542 543 static void tl_restart(v) 544 void *v; 545 { 546 tl_init(v); 547 } 548 549 static int tl_init(sc) 550 tl_softc_t *sc; 551 { 552 struct ifnet *ifp = &sc->tl_if; 553 int i, s; 554 555 s = splimp(); 556 /* cancel any pending IO */ 557 tl_shutdown(sc); 558 tl_reset(sc); 559 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 560 splx(s); 561 return 0; 562 } 563 /* Set various register to reasonable value */ 564 /* setup NetCmd in promisc mode if needed */ 565 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 566 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 567 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 568 /* Max receive size : MCLBYTES */ 569 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 570 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 571 (MCLBYTES >> 8) & 0xff); 572 573 /* init MAC addr */ 574 for (i = 0; i < ETHER_ADDR_LEN; i++) 575 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 576 /* add multicast filters */ 577 tl_addr_filter(sc); 578 #ifdef TLDEBUG_ADDR 579 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 580 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 581 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 582 #endif 583 584 /* Pre-allocate receivers mbuf, make the lists */ 585 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 586 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 587 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 588 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 589 sc->tl_if.if_flags &= ~IFF_UP; 590 splx(s); 591 return ENOMEM; 592 } 593 for (i=0; i< TL_NBUF; i++) { 594 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 595 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 596 sc->tl_if.if_flags &= ~IFF_UP; 597 splx(s); 598 return ENOMEM; 599 } 600 if (i > 0) { /* chain the list */ 601 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 602 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 603 #ifdef DIAGNOSTIC 604 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 605 printf("%s: physical addr 0x%x of list not properly aligned\n", 606 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 607 #endif 608 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 609 } 610 } 611 sc->Rx_list[TL_NBUF-1].next = NULL; 612 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 613 sc->Tx_list[TL_NBUF-1].next = NULL; 614 615 sc->active_Rx = &sc->Rx_list[0]; 616 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 617 sc->active_Tx = sc->last_Tx = NULL; 618 sc->Free_Tx = &sc->Tx_list[0]; 619 620 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 621 if (nullbuf == NULL) { 622 printf("%s: can't allocate space for pad buffer\n", 623 sc->sc_dev.dv_xname); 624 sc->tl_if.if_flags &= ~IFF_UP; 625 splx(s); 626 return ENOMEM; 627 } 628 bzero(nullbuf, ETHER_MIN_TX); 629 630 /* set media if needed */ 631 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 632 mii_mediachg(&sc->mii); 633 } 634 635 /* start ticks calls */ 636 timeout(tl_ticks, sc, hz); 637 /* write adress of Rx list and enable interrupts */ 638 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 639 TL_HR_WRITE(sc, TL_HOST_CMD, 640 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 641 sc->tl_if.if_flags |= IFF_RUNNING; 642 sc->tl_if.if_flags &= ~IFF_OACTIVE; 643 return 0; 644 } 645 646 647 static u_int32_t 648 tl_intreg_read(sc, reg) 649 tl_softc_t *sc; 650 u_int32_t reg; 651 { 652 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 653 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 654 } 655 656 static u_int8_t 657 tl_intreg_read_byte(sc, reg) 658 tl_softc_t *sc; 659 u_int32_t reg; 660 { 661 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 662 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 663 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 664 } 665 666 static void 667 tl_intreg_write(sc, reg, val) 668 tl_softc_t *sc; 669 u_int32_t reg; 670 u_int32_t val; 671 { 672 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 673 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 674 } 675 676 static void 677 tl_intreg_write_byte(sc, reg, val) 678 tl_softc_t *sc; 679 u_int32_t reg; 680 u_int8_t val; 681 { 682 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 683 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 684 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 685 } 686 687 void tl_mii_set(v, bit) 688 void *v; 689 u_int8_t bit; 690 { 691 tl_softc_t *sc = v; 692 693 switch (bit) { 694 case MII_DATA: 695 netsio_set(sc, TL_NETSIO_MDATA); 696 break; 697 case MII_CLOCK: 698 netsio_set(sc, TL_NETSIO_MCLK); 699 break; 700 case MII_TXEN: 701 netsio_set(sc, TL_NETSIO_MTXEN); 702 break; 703 default: 704 printf("tl_mii_set: unknown bit %d\n", bit); 705 } 706 } 707 708 void tl_mii_clr(v, bit) 709 void *v; 710 u_int8_t bit; 711 { 712 tl_softc_t *sc = v; 713 714 switch (bit) { 715 case MII_DATA: 716 netsio_clr(sc, TL_NETSIO_MDATA); 717 break; 718 case MII_CLOCK: 719 netsio_clr(sc, TL_NETSIO_MCLK); 720 break; 721 case MII_TXEN: 722 netsio_clr(sc, TL_NETSIO_MTXEN); 723 break; 724 default: 725 printf("tl_mii_clr: unknown bit %d\n", bit); 726 } 727 return; 728 } 729 730 int tl_mii_read(v, bit) 731 void *v; 732 u_int8_t bit; 733 { 734 tl_softc_t *sc = v; 735 736 switch (bit) { 737 case MII_DATA: 738 return netsio_read(sc, TL_NETSIO_MDATA); 739 break; 740 case MII_CLOCK: 741 return netsio_read(sc, TL_NETSIO_MCLK); 742 break; 743 case MII_TXEN: 744 return netsio_read(sc, TL_NETSIO_MTXEN); 745 break; 746 default: 747 printf("tl_mii_read: unknown bit %d\n", bit); 748 return -1; 749 } 750 } 751 752 void tl_i2c_set(v, bit) 753 void *v; 754 u_int8_t bit; 755 { 756 tl_softc_t *sc = v; 757 758 switch (bit) { 759 case I2C_DATA: 760 netsio_set(sc, TL_NETSIO_EDATA); 761 break; 762 case I2C_CLOCK: 763 netsio_set(sc, TL_NETSIO_ECLOCK); 764 break; 765 case I2C_TXEN: 766 netsio_set(sc, TL_NETSIO_ETXEN); 767 break; 768 default: 769 printf("tl_i2c_set: unknown bit %d\n", bit); 770 } 771 return; 772 } 773 774 void tl_i2c_clr(v, bit) 775 void *v; 776 u_int8_t bit; 777 { 778 tl_softc_t *sc = v; 779 780 switch (bit) { 781 case I2C_DATA: 782 netsio_clr(sc, TL_NETSIO_EDATA); 783 break; 784 case I2C_CLOCK: 785 netsio_clr(sc, TL_NETSIO_ECLOCK); 786 break; 787 case I2C_TXEN: 788 netsio_clr(sc, TL_NETSIO_ETXEN); 789 break; 790 default: 791 printf("tl_i2c_clr: unknown bit %d\n", bit); 792 } 793 return; 794 } 795 796 int tl_i2c_read(v, bit) 797 void *v; 798 u_int8_t bit; 799 { 800 tl_softc_t *sc = v; 801 802 switch (bit) { 803 case I2C_DATA: 804 return netsio_read(sc, TL_NETSIO_EDATA); 805 break; 806 case I2C_CLOCK: 807 return netsio_read(sc, TL_NETSIO_ECLOCK); 808 break; 809 case I2C_TXEN: 810 return netsio_read(sc, TL_NETSIO_ETXEN); 811 break; 812 default: 813 printf("tl_i2c_read: unknown bit %d\n", bit); 814 return -1; 815 } 816 } 817 818 static int 819 tl_intr(v) 820 void *v; 821 { 822 tl_softc_t *sc = v; 823 struct ifnet *ifp = &sc->tl_if; 824 struct Rx_list *Rx; 825 struct Tx_list *Tx; 826 struct mbuf *m; 827 u_int32_t int_type, int_reg; 828 int ack = 0; 829 int size; 830 831 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 832 int_type = int_reg & TL_INTR_MASK; 833 if (int_type == 0) 834 return 0; 835 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 836 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 837 int_type, int_reg); 838 #endif 839 /* disable interrupts */ 840 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 841 switch(int_type & TL_INTR_MASK) { 842 case TL_INTR_RxEOF: 843 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 844 /* dequeue and requeue at end of list */ 845 ack++; 846 Rx = sc->active_Rx; 847 sc->active_Rx = Rx->next; 848 m = Rx->m; 849 size = Rx->hw_list.stat >> 16; 850 #ifdef TLDEBUG_RX 851 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 852 #endif 853 if (tl_add_RxBuff(Rx, m ) == 0) { 854 /* No new mbuf, reuse the same. This means that this packet 855 is lost */ 856 m = NULL; 857 #ifdef TL_PRIV_STATS 858 sc->ierr_nomem++; 859 #endif 860 #ifdef TLDEBUG 861 printf("%s: out of mbuf, lost input packet\n", 862 sc->sc_dev.dv_xname); 863 #endif 864 } 865 Rx->next = NULL; 866 Rx->hw_list.fwd = 0; 867 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 868 #ifdef DIAGNOSTIC 869 if (sc->last_Rx->hw_list.fwd & 0x7) 870 printf("%s: physical addr 0x%x of list not properly aligned\n", 871 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 872 #endif 873 sc->last_Rx->next = Rx; 874 sc->last_Rx = Rx; 875 876 /* deliver packet */ 877 if (m) { 878 struct ether_header *eh; 879 if (size < sizeof(struct ether_header)) { 880 m_freem(m); 881 continue; 882 } 883 m->m_pkthdr.rcvif = ifp; 884 m->m_pkthdr.len = m->m_len = 885 size - sizeof(struct ether_header); 886 eh = mtod(m, struct ether_header *); 887 #ifdef TLDEBUG_RX 888 printf("tl_intr: Rx packet:\n"); 889 ether_printheader(eh); 890 #endif 891 #if NBPFILTER > 0 892 if (ifp->if_bpf) { 893 bpf_tap(ifp->if_bpf, 894 mtod(m, caddr_t), 895 size); 896 /* 897 * Only pass this packet up 898 * if it is for us. 899 */ 900 if ((ifp->if_flags & IFF_PROMISC) && 901 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 902 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 903 sizeof(eh->ether_dhost)) != 0) { 904 m_freem(m); 905 continue; 906 } 907 } 908 #endif /* NBPFILTER > 0 */ 909 m->m_data += sizeof(struct ether_header); 910 ether_input(ifp, eh, m); 911 } 912 } 913 #ifdef TLDEBUG_RX 914 printf("TL_INTR_RxEOF: ack %d\n", ack); 915 #else 916 if (ack == 0) { 917 printf("%s: EOF intr without anything to read !\n", 918 sc->sc_dev.dv_xname); 919 tl_reset(sc); 920 /* shedule reinit of the board */ 921 timeout(tl_restart, sc, 1); 922 return(1); 923 } 924 #endif 925 break; 926 case TL_INTR_RxEOC: 927 ack++; 928 #ifdef TLDEBUG_RX 929 printf("TL_INTR_RxEOC: ack %d\n", ack); 930 #endif 931 #ifdef DIAGNOSTIC 932 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 933 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 934 sc->sc_dev.dv_xname); 935 return 0; 936 } else 937 #endif 938 { 939 /* write adress of Rx list and send Rx GO command, ack interrupt 940 and enable interrupts in one command */ 941 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 942 vtophys(&sc->active_Rx->hw_list)); 943 TL_HR_WRITE(sc, TL_HOST_CMD, 944 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 945 HOST_CMD_ACK | HOST_CMD_IntOn); 946 return 1; 947 } 948 case TL_INTR_TxEOF: 949 case TL_INTR_TxEOC: 950 while ((Tx = sc->active_Tx) != NULL) { 951 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 952 break; 953 ack++; 954 #ifdef TLDEBUG_TX 955 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 956 #endif 957 Tx->hw_list.stat = 0; 958 m_freem(Tx->m); 959 Tx->m = NULL; 960 sc->active_Tx = Tx->next; 961 if (sc->active_Tx == NULL) 962 sc->last_Tx = NULL; 963 Tx->next = sc->Free_Tx; 964 sc->Free_Tx = Tx; 965 } 966 /* if this was an EOC, ACK immediatly */ 967 if (int_type == TL_INTR_TxEOC) { 968 #ifdef TLDEBUG_TX 969 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 970 #endif 971 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 972 HOST_CMD_IntOn); 973 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 974 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 975 vtophys(&sc->active_Tx->hw_list)); 976 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 977 } 978 sc->tl_if.if_timer = 0; 979 if (sc->tl_if.if_snd.ifq_head != NULL) 980 tl_ifstart(&sc->tl_if); 981 return 1; 982 } 983 #ifdef TLDEBUG 984 else { 985 printf("TL_INTR_TxEOF: ack %d\n", ack); 986 } 987 #endif 988 sc->tl_if.if_timer = 0; 989 if (sc->tl_if.if_snd.ifq_head != NULL) 990 tl_ifstart(&sc->tl_if); 991 break; 992 case TL_INTR_Stat: 993 ack++; 994 #ifdef TLDEBUG 995 printf("TL_INTR_Stat: ack %d\n", ack); 996 #endif 997 tl_read_stats(sc); 998 break; 999 case TL_INTR_Adc: 1000 if (int_reg & TL_INTVec_MASK) { 1001 /* adapter check conditions */ 1002 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1003 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1004 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1005 tl_reset(sc); 1006 /* shedule reinit of the board */ 1007 timeout(tl_restart, sc, 1); 1008 return(1); 1009 } else { 1010 u_int8_t netstat; 1011 /* Network status */ 1012 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1013 printf("%s: network status, NetSts=%x\n", 1014 sc->sc_dev.dv_xname, netstat); 1015 /* Ack interrupts */ 1016 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1017 ack++; 1018 } 1019 break; 1020 default: 1021 printf("%s: unhandled interrupt code %x!\n", 1022 sc->sc_dev.dv_xname, int_type); 1023 ack++; 1024 } 1025 1026 if (ack) { 1027 /* Ack the interrupt and enable interrupts */ 1028 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1029 HOST_CMD_IntOn); 1030 return 1; 1031 } 1032 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1033 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1034 return 0; 1035 } 1036 1037 static int 1038 tl_ifioctl(ifp, cmd, data) 1039 struct ifnet *ifp; 1040 ioctl_cmd_t cmd; 1041 caddr_t data; 1042 { 1043 struct tl_softc *sc = ifp->if_softc; 1044 struct ifreq *ifr = (struct ifreq *)data; 1045 int s, error; 1046 1047 s = splimp(); 1048 switch(cmd) { 1049 case SIOCSIFADDR: { 1050 struct ifaddr *ifa = (struct ifaddr *)data; 1051 sc->tl_if.if_flags |= IFF_UP; 1052 if ((error = tl_init(sc)) != NULL) { 1053 sc->tl_if.if_flags &= ~IFF_UP; 1054 break; 1055 } 1056 switch (ifa->ifa_addr->sa_family) { 1057 #ifdef INET 1058 case AF_INET: 1059 arp_ifinit(ifp, ifa); 1060 break; 1061 #endif 1062 #ifdef NS 1063 case AF_NS: { 1064 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1065 1066 if (ns_nullhost(*ina)) 1067 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1068 else 1069 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1070 ifp->if_addrlen); 1071 break; 1072 } 1073 #endif 1074 default: 1075 break; 1076 } 1077 break; 1078 } 1079 case SIOCSIFFLAGS: 1080 { 1081 u_int8_t reg; 1082 /* 1083 * If interface is marked up and not running, then start it. 1084 * If it is marked down and running, stop it. 1085 */ 1086 if (ifp->if_flags & IFF_UP) { 1087 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1088 error = tl_init(sc); 1089 /* all flags have been handled by init */ 1090 break; 1091 } 1092 error = 0; 1093 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1094 if (ifp->if_flags & IFF_PROMISC) 1095 reg |= TL_NETCOMMAND_CAF; 1096 else 1097 reg &= ~TL_NETCOMMAND_CAF; 1098 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1099 #ifdef TL_PRIV_STATS 1100 if (ifp->if_flags & IFF_LINK0) { 1101 ifp->if_flags &= ~IFF_LINK0; 1102 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1103 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1104 printf(" %4d RX code error\n", sc->ierr_code); 1105 printf(" %4d RX crc error\n", sc->ierr_crc); 1106 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1107 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1108 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1109 printf(" %4d TX single collisions\n", sc->oerr_coll); 1110 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1111 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1112 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1113 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1114 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1115 } 1116 #endif 1117 } else { 1118 if (ifp->if_flags & IFF_RUNNING) 1119 tl_shutdown(sc); 1120 error = 0; 1121 } 1122 break; 1123 } 1124 case SIOCADDMULTI: 1125 case SIOCDELMULTI: 1126 /* 1127 * Update multicast listeners 1128 */ 1129 if (cmd == SIOCADDMULTI) 1130 error = ether_addmulti(ifr, &sc->tl_ec); 1131 else 1132 error = ether_delmulti(ifr, &sc->tl_ec); 1133 if (error == ENETRESET) { 1134 tl_addr_filter(sc); 1135 error = 0; 1136 } 1137 break; 1138 case SIOCSIFMEDIA: 1139 case SIOCGIFMEDIA: 1140 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1141 break; 1142 default: 1143 error = EINVAL; 1144 } 1145 splx(s); 1146 return error; 1147 } 1148 1149 static void 1150 tl_ifstart(ifp) 1151 struct ifnet *ifp; 1152 { 1153 tl_softc_t *sc = ifp->if_softc; 1154 struct mbuf *m, *mb_head; 1155 struct Tx_list *Tx; 1156 int segment, size; 1157 1158 txloop: 1159 /* If we don't have more space ... */ 1160 if (sc->Free_Tx == NULL) { 1161 #ifdef TLDEBUG 1162 printf("tl_ifstart: No free TX list\n"); 1163 #endif 1164 return; 1165 } 1166 /* Grab a paquet for output */ 1167 IF_DEQUEUE(&ifp->if_snd, mb_head); 1168 if (mb_head == NULL) { 1169 #ifdef TLDEBUG_TX 1170 printf("tl_ifstart: nothing to send\n"); 1171 #endif 1172 return; 1173 } 1174 Tx = sc->Free_Tx; 1175 sc->Free_Tx = Tx->next; 1176 /* 1177 * Go through each of the mbufs in the chain and initialize 1178 * the transmit list descriptors with the physical address 1179 * and size of the mbuf. 1180 */ 1181 tbdinit: 1182 bzero(Tx, sizeof(struct Tx_list)); 1183 Tx->m = mb_head; 1184 size = 0; 1185 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1186 if (m->m_len != 0) { 1187 if (segment == TL_NSEG) 1188 break; 1189 size += m->m_len; 1190 Tx->hw_list.seg[segment].data_addr = 1191 vtophys(mtod(m, vm_offset_t)); 1192 Tx->hw_list.seg[segment].data_count = m->m_len; 1193 segment++; 1194 } 1195 } 1196 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1197 /* 1198 * We ran out of segments, or we will. We have to recopy this mbuf 1199 * chain first. 1200 */ 1201 struct mbuf *mn; 1202 #ifdef TLDEBUG_TX 1203 printf("tl_ifstart: need to copy mbuf\n"); 1204 #endif 1205 #ifdef TL_PRIV_STATS 1206 sc->oerr_mcopy++; 1207 #endif 1208 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1209 if (mn == NULL) { 1210 m_freem(mb_head); 1211 goto bad; 1212 } 1213 if (mb_head->m_pkthdr.len > MHLEN) { 1214 MCLGET(mn, M_DONTWAIT); 1215 if ((mn->m_flags & M_EXT) == 0) { 1216 m_freem(mn); 1217 m_freem(mb_head); 1218 goto bad; 1219 } 1220 } 1221 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1222 mtod(mn, caddr_t)); 1223 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1224 m_freem(mb_head); 1225 mb_head = mn; 1226 goto tbdinit; 1227 } 1228 /* We are at end of mbuf chain. check the size and 1229 * see if it needs to be extended 1230 */ 1231 if (size < ETHER_MIN_TX) { 1232 #ifdef DIAGNOSTIC 1233 if (segment >= TL_NSEG) { 1234 panic("tl_ifstart: to much segmets (%d)\n", segment); 1235 } 1236 #endif 1237 /* 1238 * add the nullbuf in the seg 1239 */ 1240 Tx->hw_list.seg[segment].data_count = 1241 ETHER_MIN_TX - size; 1242 Tx->hw_list.seg[segment].data_addr = 1243 vtophys(nullbuf); 1244 size = ETHER_MIN_TX; 1245 segment++; 1246 } 1247 /* The list is done, finish the list init */ 1248 Tx->hw_list.seg[segment-1].data_count |= 1249 TL_LAST_SEG; 1250 Tx->hw_list.stat = (size << 16) | 0x3000; 1251 #ifdef TLDEBUG_TX 1252 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1253 Tx->hw_list.stat); 1254 #if 0 1255 for(segment = 0; segment < TL_NSEG; segment++) { 1256 printf(" seg %d addr 0x%x len 0x%x\n", 1257 segment, 1258 Tx->hw_list.seg[segment].data_addr, 1259 Tx->hw_list.seg[segment].data_count); 1260 } 1261 #endif 1262 #endif 1263 sc->opkt++; 1264 if (sc->active_Tx == NULL) { 1265 sc->active_Tx = sc->last_Tx = Tx; 1266 #ifdef TLDEBUG_TX 1267 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1268 vtophys(&Tx->hw_list)); 1269 #endif 1270 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1271 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1272 } else { 1273 #ifdef TLDEBUG_TX 1274 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1275 vtophys(&Tx->hw_list)); 1276 #endif 1277 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1278 sc->last_Tx->next = Tx; 1279 sc->last_Tx = Tx; 1280 #ifdef DIAGNOSTIC 1281 if (sc->last_Tx->hw_list.fwd & 0x7) 1282 printf("%s: physical addr 0x%x of list not properly aligned\n", 1283 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1284 #endif 1285 } 1286 #if NBPFILTER > 0 1287 /* Pass packet to bpf if there is a listener */ 1288 if (ifp->if_bpf) 1289 bpf_mtap(ifp->if_bpf, mb_head); 1290 #endif 1291 /* Set a 5 second timer just in case we don't hear from the card again. */ 1292 ifp->if_timer = 5; 1293 1294 goto txloop; 1295 bad: 1296 #ifdef TLDEBUG 1297 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1298 #endif 1299 Tx->next = sc->Free_Tx; 1300 sc->Free_Tx = Tx; 1301 return; 1302 } 1303 1304 static void 1305 tl_ifwatchdog(ifp) 1306 struct ifnet *ifp; 1307 { 1308 tl_softc_t *sc = ifp->if_softc; 1309 1310 if ((ifp->if_flags & IFF_RUNNING) == 0) 1311 return; 1312 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1313 ifp->if_oerrors++; 1314 tl_init(sc); 1315 } 1316 1317 static int 1318 tl_mediachange(ifp) 1319 struct ifnet *ifp; 1320 { 1321 1322 tl_softc_t *sc = ifp->if_softc; 1323 int err; 1324 u_int32_t reg; 1325 int oldmedia; 1326 #ifdef TLDEBUG 1327 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1328 #endif 1329 oldmedia = sc->mii.mii_media_active; 1330 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1331 if ((err = mii_mediachg(&sc->mii)) != 0) 1332 sc->mii.mii_media_active = oldmedia; 1333 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1334 if (sc->mii.mii_media_active & IFM_FDX) 1335 reg |= TL_NETCOMMAND_DUPLEX; 1336 else 1337 reg &= ~TL_NETCOMMAND_DUPLEX; 1338 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1339 return err; 1340 } 1341 1342 static void 1343 tl_mediastatus(ifp, ifmr) 1344 struct ifnet *ifp; 1345 struct ifmediareq *ifmr; 1346 { 1347 tl_softc_t *sc = ifp->if_softc; 1348 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1349 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1350 if (sc->tl_flags & TL_IFACT) 1351 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1352 else 1353 sc->mii.mii_media_status = IFM_AVALID; 1354 else 1355 mii_pollstat(&sc->mii); 1356 1357 ifmr->ifm_active = sc->mii.mii_media_active; 1358 ifmr->ifm_status = sc->mii.mii_media_status; 1359 } 1360 1361 static int tl_add_RxBuff(Rx, oldm) 1362 struct Rx_list *Rx; 1363 struct mbuf *oldm; 1364 { 1365 struct mbuf *m; 1366 1367 MGETHDR(m, M_DONTWAIT, MT_DATA); 1368 if (m != NULL) { 1369 MCLGET(m, M_DONTWAIT); 1370 if ((m->m_flags & M_EXT) == 0) { 1371 m_freem(m); 1372 if (oldm == NULL) 1373 return 0; 1374 m = oldm; 1375 m->m_data = m->m_ext.ext_buf; 1376 } 1377 } else { 1378 if (oldm == NULL) 1379 return 0; 1380 m = oldm; 1381 m->m_data = m->m_ext.ext_buf; 1382 } 1383 /* 1384 * Move the data pointer up so that the incoming data packet 1385 * will be 32-bit aligned. 1386 */ 1387 m->m_data += 2; 1388 1389 /* (re)init the Rx_list struct */ 1390 1391 Rx->m = m; 1392 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1393 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1394 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1395 return (m != oldm); 1396 } 1397 1398 static void tl_ticks(v) 1399 void *v; 1400 { 1401 tl_softc_t *sc = v; 1402 1403 tl_read_stats(sc); 1404 if (sc->opkt > 0) { 1405 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1406 if (sc->tl_flags & TL_IFACT) /* only print once */ 1407 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1408 sc->tl_flags &= ~TL_IFACT; 1409 } else 1410 sc->tl_flags |= TL_IFACT; 1411 sc->oerr_exesscoll = sc->opkt = 0; 1412 sc->tl_lasttx = 0; 1413 } else { 1414 sc->tl_lasttx++; 1415 if (sc->tl_lasttx >= TL_IDLETIME) { 1416 /* 1417 * No TX activity in the last TL_IDLETIME seconds. 1418 * sends a LLC Class1 TEST pkt 1419 */ 1420 struct mbuf *m; 1421 int s; 1422 MGETHDR(m, M_DONTWAIT, MT_DATA); 1423 if (m != NULL) { 1424 #ifdef TLDEBUG 1425 printf("tl_ticks: sending LLC test pkt\n"); 1426 #endif 1427 bcopy(sc->tl_enaddr, 1428 mtod(m, struct ether_header *)->ether_dhost, 6); 1429 bcopy(sc->tl_enaddr, 1430 mtod(m, struct ether_header *)->ether_shost, 6); 1431 mtod(m, struct ether_header *)->ether_type = htons(3); 1432 mtod(m, unsigned char *)[14] = 0; 1433 mtod(m, unsigned char *)[15] = 0; 1434 mtod(m, unsigned char *)[16] = 0xE3; 1435 /* LLC Class1 TEST (no poll) */ 1436 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1437 s = splnet(); 1438 IF_PREPEND(&sc->tl_if.if_snd, m); 1439 tl_ifstart(&sc->tl_if); 1440 splx(s); 1441 } 1442 } 1443 } 1444 1445 /* read statistics every seconds */ 1446 timeout(tl_ticks, v, hz); 1447 } 1448 1449 static void 1450 tl_read_stats(sc) 1451 tl_softc_t *sc; 1452 { 1453 u_int32_t reg; 1454 int ierr_overr; 1455 int ierr_code; 1456 int ierr_crc; 1457 int oerr_underr; 1458 int oerr_deffered; 1459 int oerr_coll; 1460 int oerr_multicoll; 1461 int oerr_exesscoll; 1462 int oerr_latecoll; 1463 int oerr_carrloss; 1464 struct ifnet *ifp = &sc->tl_if; 1465 1466 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1467 ifp->if_opackets += reg & 0x00ffffff; 1468 oerr_underr = reg >> 24; 1469 1470 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1471 ifp->if_ipackets += reg & 0x00ffffff; 1472 ierr_overr = reg >> 24; 1473 1474 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1475 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1476 ierr_code = (reg & TL_FERR_CODE) >> 24; 1477 oerr_deffered = (reg & TL_FERR_DEF); 1478 1479 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1480 oerr_multicoll = (reg & TL_COL_MULTI); 1481 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1482 1483 reg = tl_intreg_read(sc, TL_INT_LERR); 1484 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1485 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1486 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1487 1488 1489 sc->stats_exesscoll += oerr_exesscoll; 1490 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1491 oerr_carrloss; 1492 ifp->if_collisions += oerr_coll + oerr_multicoll; 1493 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1494 1495 if (ierr_overr) 1496 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1497 if (oerr_underr) 1498 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1499 #ifdef TL_PRIV_STATS 1500 sc->ierr_overr += ierr_overr; 1501 sc->ierr_code += ierr_code; 1502 sc->ierr_crc += ierr_crc; 1503 sc->oerr_underr += oerr_underr; 1504 sc->oerr_deffered += oerr_deffered; 1505 sc->oerr_coll += oerr_coll; 1506 sc->oerr_multicoll += oerr_multicoll; 1507 sc->oerr_exesscoll += oerr_exesscoll; 1508 sc->oerr_latecoll += oerr_latecoll; 1509 sc->oerr_carrloss += oerr_carrloss; 1510 #endif 1511 } 1512 1513 static void tl_addr_filter(sc) 1514 tl_softc_t *sc; 1515 { 1516 struct ether_multistep step; 1517 struct ether_multi *enm; 1518 u_int32_t hash[2] = {0, 0}; 1519 int i; 1520 1521 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1522 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1523 while (enm != NULL) { 1524 #ifdef TLDEBUG 1525 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1526 #endif 1527 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1528 i = tl_multicast_hash(enm->enm_addrlo); 1529 hash[i/32] |= 1 << (i%32); 1530 } else { 1531 hash[0] = hash[1] = 0xffffffff; 1532 sc->tl_if.if_flags |= IFF_ALLMULTI; 1533 break; 1534 } 1535 ETHER_NEXT_MULTI(step, enm); 1536 } 1537 #ifdef TLDEBUG 1538 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1539 #endif 1540 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1541 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1542 } 1543 1544 static int tl_multicast_hash(a) 1545 u_int8_t *a; 1546 { 1547 int hash; 1548 1549 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1550 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1551 1552 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1553 DA(a,36), DA(a,42)); 1554 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1555 DA(a,37), DA(a,43)) << 1; 1556 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1557 DA(a,38), DA(a,44)) << 2; 1558 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1559 DA(a,39), DA(a,45)) << 3; 1560 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1561 DA(a,40), DA(a,46)) << 4; 1562 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1563 DA(a,41), DA(a,47)) << 5; 1564 1565 return hash; 1566 } 1567 1568 #if defined(TLDEBUG_RX) 1569 void ether_printheader(eh) 1570 struct ether_header *eh; 1571 { 1572 u_char *c = (char*)eh; 1573 int i; 1574 for (i=0; i<sizeof(struct ether_header); i++) 1575 printf("%x ", (u_int)c[i]); 1576 printf("\n"); 1577 } 1578 #endif 1579
Indexes created Fri Sep 26 20:09:58 GMT 2025