if_tl.c revision 1.22
1 /* $NetBSD: if_tl.c,v 1.22 1999/01/11 22:45:41 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 #if defined(__NetBSD__) && defined(__alpha__) 116 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 117 #undef vtophys 118 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va)) 119 #endif 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 10 124 #endif 125 126 /* number of seconds the link can be idle */ 127 #ifndef TL_IDLETIME 128 #define TL_IDLETIME 10 129 #endif 130 131 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 132 static void tl_pci_attach __P((struct device *, struct device *, void *)); 133 static int tl_intr __P((void *)); 134 135 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 136 static int tl_mediachange __P((struct ifnet *)); 137 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 138 static void tl_ifwatchdog __P((struct ifnet *)); 139 static void tl_shutdown __P((void*)); 140 141 static void tl_ifstart __P((struct ifnet *)); 142 static void tl_reset __P((tl_softc_t*)); 143 static int tl_init __P((tl_softc_t*)); 144 static void tl_restart __P((void *)); 145 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 146 static void tl_read_stats __P((tl_softc_t*)); 147 static void tl_ticks __P((void*)); 148 static int tl_multicast_hash __P((u_int8_t*)); 149 static void tl_addr_filter __P((tl_softc_t*)); 150 151 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 152 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 153 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 154 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 155 156 void tl_mii_sync __P((struct tl_softc *)); 157 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 158 159 160 #if defined(TLDEBUG_RX) 161 static void ether_printheader __P((struct ether_header*)); 162 #endif 163 164 int tl_mii_read __P((struct device *, int, int)); 165 void tl_mii_write __P((struct device *, int, int, int)); 166 167 void tl_statchg __P((struct device *)); 168 169 void tl_i2c_set __P((void*, u_int8_t)); 170 void tl_i2c_clr __P((void*, u_int8_t)); 171 int tl_i2c_read __P((void*, u_int8_t)); 172 173 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 174 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 175 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 176 static __inline void netsio_clr(sc, bits) 177 tl_softc_t* sc; 178 u_int8_t bits; 179 { 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 static __inline void netsio_set(sc, bits) 184 tl_softc_t* sc; 185 u_int8_t bits; 186 { 187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 189 } 190 static __inline u_int8_t netsio_read(sc, bits) 191 tl_softc_t* sc; 192 u_int8_t bits; 193 { 194 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 195 } 196 197 struct cfattach tl_ca = { 198 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 199 }; 200 201 const struct tl_product_desc tl_compaq_products[] = { 202 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 203 "Compaq Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 205 "Compaq Netelligent 10 T" }, 206 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 207 "Compaq Integrated NetFlex 3/P" }, 208 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 209 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 211 "Compaq Dual Port Netelligent 10/100 TX" }, 212 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 213 "Compaq Deskpro 4000 5233MMX" }, 214 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 215 "Compaq NetFlex 3/P w/ BNC" }, 216 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 217 "Compaq NetFlex 3/P" }, 218 { 0, 0, NULL }, 219 }; 220 221 const struct tl_product_desc tl_ti_products[] = { 222 /* 223 * Built-in Ethernet on the TI TravelMate 5000 224 * docking station; better product description? 225 */ 226 { PCI_PRODUCT_TI_TLAN, 0, 227 "Texas Instruments ThunderLAN" }, 228 { 0, 0, NULL }, 229 }; 230 231 struct tl_vendor_desc { 232 u_int32_t tv_vendor; 233 const struct tl_product_desc *tv_products; 234 }; 235 236 const struct tl_vendor_desc tl_vendors[] = { 237 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 238 { PCI_VENDOR_TI, tl_ti_products }, 239 { 0, NULL }, 240 }; 241 242 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 243 244 const struct tl_product_desc * 245 tl_lookup_product(id) 246 u_int32_t id; 247 { 248 const struct tl_product_desc *tp; 249 const struct tl_vendor_desc *tv; 250 251 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 252 if (PCI_VENDOR(id) == tv->tv_vendor) 253 break; 254 255 if ((tp = tv->tv_products) == NULL) 256 return (NULL); 257 258 for (; tp->tp_desc != NULL; tp++) 259 if (PCI_PRODUCT(id) == tp->tp_product) 260 break; 261 262 if (tp->tp_desc == NULL) 263 return (NULL); 264 265 return (tp); 266 } 267 268 static char *nullbuf = NULL; 269 270 static int 271 tl_pci_match(parent, match, aux) 272 struct device *parent; 273 struct cfdata *match; 274 void *aux; 275 { 276 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 277 278 if (tl_lookup_product(pa->pa_id) != NULL) 279 return (1); 280 281 return (0); 282 } 283 284 static void 285 tl_pci_attach(parent, self, aux) 286 struct device * parent; 287 struct device * self; 288 void * aux; 289 { 290 tl_softc_t *sc = (tl_softc_t *)self; 291 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 292 const struct tl_product_desc *tp; 293 struct ifnet * const ifp = &sc->tl_if; 294 bus_space_tag_t iot, memt; 295 bus_space_handle_t ioh, memh; 296 pci_intr_handle_t intrhandle; 297 const char *intrstr; 298 int i, tmp, ioh_valid, memh_valid; 299 pcireg_t csr; 300 301 printf("\n"); 302 303 tp = tl_lookup_product(pa->pa_id); 304 if (tp == NULL) 305 panic("tl_pci_attach: impossible"); 306 sc->tl_product = tp; 307 308 /* Map the card space. */ 309 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 310 &iot, &ioh, NULL, NULL) == 0); 311 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 312 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 313 0, &memt, &memh, NULL, NULL) == 0); 314 315 if (ioh_valid) { 316 sc->tl_bustag = iot; 317 sc->tl_bushandle = ioh; 318 } else if (memh_valid) { 319 sc->tl_bustag = memt; 320 sc->tl_bushandle = memh; 321 } else { 322 printf("%s: unable to map device registers\n", 323 sc->sc_dev.dv_xname); 324 return; 325 } 326 327 /* Enable the device. */ 328 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 329 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 330 csr | PCI_COMMAND_MASTER_ENABLE); 331 332 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 333 334 tl_reset(sc); 335 336 /* fill in the i2c struct */ 337 sc->i2cbus.adapter_softc = sc; 338 sc->i2cbus.set_bit = tl_i2c_set; 339 sc->i2cbus.clr_bit = tl_i2c_clr; 340 sc->i2cbus.read_bit = tl_i2c_read; 341 342 #ifdef TLDEBUG 343 printf("default values of INTreg: 0x%x\n", 344 tl_intreg_read(sc, TL_INT_Defaults)); 345 #endif 346 347 /* read mac addr */ 348 for (i=0; i<ETHER_ADDR_LEN; i++) { 349 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 350 if (tmp < 0) { 351 printf("%s: error reading Ethernet adress\n", 352 sc->sc_dev.dv_xname); 353 return; 354 } else { 355 sc->tl_enaddr[i] = tmp; 356 } 357 } 358 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 359 ether_sprintf(sc->tl_enaddr)); 360 361 /* Map and establish interrupts */ 362 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 363 pa->pa_intrline, &intrhandle)) { 364 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 365 return; 366 } 367 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 368 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 369 tl_intr, sc); 370 if (sc->tl_ih == NULL) { 371 printf("%s: couldn't establish interrupt", 372 sc->sc_dev.dv_xname); 373 if (intrstr != NULL) 374 printf(" at %s", intrstr); 375 printf("\n"); 376 return; 377 } 378 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 379 380 /* 381 * Add shutdown hook so that DMA is disabled prior to reboot. Not 382 * doing do could allow DMA to corrupt kernel memory during the 383 * reboot before the driver initializes. 384 */ 385 (void) shutdownhook_establish(tl_shutdown, sc); 386 387 /* 388 * Initialize our media structures and probe the MII. 389 * 390 * Note that we don't care about the media instance. We 391 * are expecting to have multiple PHYs on the 10/100 cards, 392 * and on those cards we exclude the internal PHY from providing 393 * 10baseT. By ignoring the instance, it allows us to not have 394 * to specify it on the command line when switching media. 395 */ 396 sc->tl_mii.mii_ifp = ifp; 397 sc->tl_mii.mii_readreg = tl_mii_read; 398 sc->tl_mii.mii_writereg = tl_mii_write; 399 sc->tl_mii.mii_statchg = tl_statchg; 400 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 401 tl_mediastatus); 402 mii_phy_probe(self, &sc->tl_mii, 0xffffffff); 403 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 404 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 405 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 406 } else 407 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 408 409 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 410 sc->tl_if.if_softc = sc; 411 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 412 ifp->if_ioctl = tl_ifioctl; 413 ifp->if_start = tl_ifstart; 414 ifp->if_watchdog = tl_ifwatchdog; 415 ifp->if_timer = 0; 416 if_attach(ifp); 417 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 418 #if NBPFILTER > 0 419 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 420 sizeof(struct ether_header)); 421 #endif 422 } 423 424 static void 425 tl_reset(sc) 426 tl_softc_t *sc; 427 { 428 int i; 429 430 /* read stats */ 431 if (sc->tl_if.if_flags & IFF_RUNNING) { 432 untimeout(tl_ticks, sc); 433 tl_read_stats(sc); 434 } 435 /* Reset adapter */ 436 TL_HR_WRITE(sc, TL_HOST_CMD, 437 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 438 DELAY(100000); 439 /* Disable interrupts */ 440 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 441 /* setup aregs & hash */ 442 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 443 tl_intreg_write(sc, i, 0); 444 #ifdef TLDEBUG_ADDR 445 printf("Areg & hash registers: \n"); 446 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 447 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 448 #endif 449 /* Setup NetConfig */ 450 tl_intreg_write(sc, TL_INT_NetConfig, 451 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 452 /* Bsize: accept default */ 453 /* TX commit in Acommit: accept default */ 454 /* Load Ld_tmr and Ld_thr */ 455 /* Ld_tmr = 3 */ 456 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 457 /* Ld_thr = 0 */ 458 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 459 /* Unreset MII */ 460 netsio_set(sc, TL_NETSIO_NMRST); 461 DELAY(100000); 462 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 463 sc->tl_flags = 0; 464 sc->opkt = 0; 465 sc->stats_exesscoll = 0; 466 } 467 468 static void tl_shutdown(v) 469 void *v; 470 { 471 tl_softc_t *sc = v; 472 struct Tx_list *Tx; 473 int i; 474 475 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 476 return; 477 /* disable interrupts */ 478 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 479 /* stop TX and RX channels */ 480 TL_HR_WRITE(sc, TL_HOST_CMD, 481 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 482 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 483 DELAY(100000); 484 485 /* stop statistics reading loop, read stats */ 486 untimeout(tl_ticks, sc); 487 tl_read_stats(sc); 488 489 /* deallocate memory allocations */ 490 for (i=0; i< TL_NBUF; i++) { 491 if (sc->Rx_list[i].m) 492 m_freem(sc->Rx_list[i].m); 493 sc->Rx_list[i].m = NULL; 494 } 495 free(sc->Rx_list, M_DEVBUF); 496 sc->Rx_list = NULL; 497 while ((Tx = sc->active_Tx) != NULL) { 498 Tx->hw_list.stat = 0; 499 m_freem(Tx->m); 500 sc->active_Tx = Tx->next; 501 Tx->next = sc->Free_Tx; 502 sc->Free_Tx = Tx; 503 } 504 sc->last_Tx = NULL; 505 free(sc->Tx_list, M_DEVBUF); 506 sc->Tx_list = NULL; 507 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 508 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 509 sc->tl_flags = 0; 510 } 511 512 static void tl_restart(v) 513 void *v; 514 { 515 tl_init(v); 516 } 517 518 static int tl_init(sc) 519 tl_softc_t *sc; 520 { 521 struct ifnet *ifp = &sc->tl_if; 522 int i, s; 523 524 s = splnet(); 525 /* cancel any pending IO */ 526 tl_shutdown(sc); 527 tl_reset(sc); 528 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 529 splx(s); 530 return 0; 531 } 532 /* Set various register to reasonable value */ 533 /* setup NetCmd in promisc mode if needed */ 534 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 535 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 536 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 537 /* Max receive size : MCLBYTES */ 538 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 539 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 540 (MCLBYTES >> 8) & 0xff); 541 542 /* init MAC addr */ 543 for (i = 0; i < ETHER_ADDR_LEN; i++) 544 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 545 /* add multicast filters */ 546 tl_addr_filter(sc); 547 #ifdef TLDEBUG_ADDR 548 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 549 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 550 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 551 #endif 552 553 /* Pre-allocate receivers mbuf, make the lists */ 554 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 555 M_NOWAIT); 556 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 557 M_NOWAIT); 558 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 559 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 560 sc->tl_if.if_flags &= ~IFF_UP; 561 splx(s); 562 return ENOMEM; 563 } 564 for (i=0; i< TL_NBUF; i++) { 565 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 566 printf("%s: out of mbuf for receive list\n", 567 sc->sc_dev.dv_xname); 568 sc->tl_if.if_flags &= ~IFF_UP; 569 splx(s); 570 return ENOMEM; 571 } 572 if (i > 0) { /* chain the list */ 573 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 574 sc->Rx_list[i-1].hw_list.fwd = 575 vtophys(&sc->Rx_list[i].hw_list); 576 #ifdef DIAGNOSTIC 577 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 578 printf("%s: physical addr 0x%x of list not " 579 "properly aligned\n", 580 sc->sc_dev.dv_xname, 581 sc->Rx_list[i-1].hw_list.fwd); 582 #endif 583 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 584 } 585 } 586 sc->Rx_list[TL_NBUF-1].next = NULL; 587 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 588 sc->Tx_list[TL_NBUF-1].next = NULL; 589 590 sc->active_Rx = &sc->Rx_list[0]; 591 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 592 sc->active_Tx = sc->last_Tx = NULL; 593 sc->Free_Tx = &sc->Tx_list[0]; 594 595 if (nullbuf == NULL) 596 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 597 if (nullbuf == NULL) { 598 printf("%s: can't allocate space for pad buffer\n", 599 sc->sc_dev.dv_xname); 600 sc->tl_if.if_flags &= ~IFF_UP; 601 splx(s); 602 return ENOMEM; 603 } 604 bzero(nullbuf, ETHER_MIN_TX); 605 606 /* set media */ 607 mii_mediachg(&sc->tl_mii); 608 609 /* start ticks calls */ 610 timeout(tl_ticks, sc, hz); 611 /* write adress of Rx list and enable interrupts */ 612 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 613 TL_HR_WRITE(sc, TL_HOST_CMD, 614 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 615 sc->tl_if.if_flags |= IFF_RUNNING; 616 sc->tl_if.if_flags &= ~IFF_OACTIVE; 617 return 0; 618 } 619 620 621 static u_int32_t 622 tl_intreg_read(sc, reg) 623 tl_softc_t *sc; 624 u_int32_t reg; 625 { 626 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 627 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 628 } 629 630 static u_int8_t 631 tl_intreg_read_byte(sc, reg) 632 tl_softc_t *sc; 633 u_int32_t reg; 634 { 635 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 636 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 637 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 638 } 639 640 static void 641 tl_intreg_write(sc, reg, val) 642 tl_softc_t *sc; 643 u_int32_t reg; 644 u_int32_t val; 645 { 646 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 647 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 648 } 649 650 static void 651 tl_intreg_write_byte(sc, reg, val) 652 tl_softc_t *sc; 653 u_int32_t reg; 654 u_int8_t val; 655 { 656 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 657 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 658 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 659 } 660 661 void 662 tl_mii_sync(sc) 663 struct tl_softc *sc; 664 { 665 int i; 666 667 netsio_clr(sc, TL_NETSIO_MTXEN); 668 for (i = 0; i < 32; i++) { 669 netsio_clr(sc, TL_NETSIO_MCLK); 670 netsio_set(sc, TL_NETSIO_MCLK); 671 } 672 } 673 674 void 675 tl_mii_sendbits(sc, data, nbits) 676 struct tl_softc *sc; 677 u_int32_t data; 678 int nbits; 679 { 680 int i; 681 682 netsio_set(sc, TL_NETSIO_MTXEN); 683 for (i = 1 << (nbits - 1); i; i = i >> 1) { 684 netsio_clr(sc, TL_NETSIO_MCLK); 685 netsio_read(sc, TL_NETSIO_MCLK); 686 if (data & i) 687 netsio_set(sc, TL_NETSIO_MDATA); 688 else 689 netsio_clr(sc, TL_NETSIO_MDATA); 690 netsio_set(sc, TL_NETSIO_MCLK); 691 netsio_read(sc, TL_NETSIO_MCLK); 692 } 693 } 694 695 int 696 tl_mii_read(self, phy, reg) 697 struct device *self; 698 int phy, reg; 699 { 700 struct tl_softc *sc = (struct tl_softc *)self; 701 int val = 0, i, err; 702 703 /* 704 * Read the PHY register by manually driving the MII control lines. 705 */ 706 707 tl_mii_sync(sc); 708 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 709 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 710 tl_mii_sendbits(sc, phy, 5); 711 tl_mii_sendbits(sc, reg, 5); 712 713 netsio_clr(sc, TL_NETSIO_MTXEN); 714 netsio_clr(sc, TL_NETSIO_MCLK); 715 netsio_set(sc, TL_NETSIO_MCLK); 716 netsio_clr(sc, TL_NETSIO_MCLK); 717 718 err = netsio_read(sc, TL_NETSIO_MDATA); 719 netsio_set(sc, TL_NETSIO_MCLK); 720 721 /* Even if an error occurs, must still clock out the cycle. */ 722 for (i = 0; i < 16; i++) { 723 val <<= 1; 724 netsio_clr(sc, TL_NETSIO_MCLK); 725 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 726 val |= 1; 727 netsio_set(sc, TL_NETSIO_MCLK); 728 } 729 netsio_clr(sc, TL_NETSIO_MCLK); 730 netsio_set(sc, TL_NETSIO_MCLK); 731 732 return (err ? 0 : val); 733 } 734 735 void 736 tl_mii_write(self, phy, reg, val) 737 struct device *self; 738 int phy, reg, val; 739 { 740 struct tl_softc *sc = (struct tl_softc *)self; 741 742 /* 743 * Write the PHY register by manually driving the MII control lines. 744 */ 745 746 tl_mii_sync(sc); 747 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 748 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 749 tl_mii_sendbits(sc, phy, 5); 750 tl_mii_sendbits(sc, reg, 5); 751 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 752 tl_mii_sendbits(sc, val, 16); 753 754 netsio_clr(sc, TL_NETSIO_MCLK); 755 netsio_set(sc, TL_NETSIO_MCLK); 756 } 757 758 void 759 tl_statchg(self) 760 struct device *self; 761 { 762 tl_softc_t *sc = (struct tl_softc *)self; 763 u_int32_t reg; 764 765 #ifdef TLDEBUG 766 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 767 #endif 768 769 /* 770 * We must keep the ThunderLAN and the PHY in sync as 771 * to the status of full-duplex! 772 */ 773 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 774 if (sc->tl_mii.mii_media_active & IFM_FDX) 775 reg |= TL_NETCOMMAND_DUPLEX; 776 else 777 reg &= ~TL_NETCOMMAND_DUPLEX; 778 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 779 780 /* XXX Update ifp->if_baudrate */ 781 } 782 783 void tl_i2c_set(v, bit) 784 void *v; 785 u_int8_t bit; 786 { 787 tl_softc_t *sc = v; 788 789 switch (bit) { 790 case I2C_DATA: 791 netsio_set(sc, TL_NETSIO_EDATA); 792 break; 793 case I2C_CLOCK: 794 netsio_set(sc, TL_NETSIO_ECLOCK); 795 break; 796 case I2C_TXEN: 797 netsio_set(sc, TL_NETSIO_ETXEN); 798 break; 799 default: 800 printf("tl_i2c_set: unknown bit %d\n", bit); 801 } 802 return; 803 } 804 805 void tl_i2c_clr(v, bit) 806 void *v; 807 u_int8_t bit; 808 { 809 tl_softc_t *sc = v; 810 811 switch (bit) { 812 case I2C_DATA: 813 netsio_clr(sc, TL_NETSIO_EDATA); 814 break; 815 case I2C_CLOCK: 816 netsio_clr(sc, TL_NETSIO_ECLOCK); 817 break; 818 case I2C_TXEN: 819 netsio_clr(sc, TL_NETSIO_ETXEN); 820 break; 821 default: 822 printf("tl_i2c_clr: unknown bit %d\n", bit); 823 } 824 return; 825 } 826 827 int tl_i2c_read(v, bit) 828 void *v; 829 u_int8_t bit; 830 { 831 tl_softc_t *sc = v; 832 833 switch (bit) { 834 case I2C_DATA: 835 return netsio_read(sc, TL_NETSIO_EDATA); 836 break; 837 case I2C_CLOCK: 838 return netsio_read(sc, TL_NETSIO_ECLOCK); 839 break; 840 case I2C_TXEN: 841 return netsio_read(sc, TL_NETSIO_ETXEN); 842 break; 843 default: 844 printf("tl_i2c_read: unknown bit %d\n", bit); 845 return -1; 846 } 847 } 848 849 static int 850 tl_intr(v) 851 void *v; 852 { 853 tl_softc_t *sc = v; 854 struct ifnet *ifp = &sc->tl_if; 855 struct Rx_list *Rx; 856 struct Tx_list *Tx; 857 struct mbuf *m; 858 u_int32_t int_type, int_reg; 859 int ack = 0; 860 int size; 861 862 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 863 int_type = int_reg & TL_INTR_MASK; 864 if (int_type == 0) 865 return 0; 866 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 867 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 868 int_type, int_reg); 869 #endif 870 /* disable interrupts */ 871 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 872 switch(int_type & TL_INTR_MASK) { 873 case TL_INTR_RxEOF: 874 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 875 /* dequeue and requeue at end of list */ 876 ack++; 877 Rx = sc->active_Rx; 878 sc->active_Rx = Rx->next; 879 m = Rx->m; 880 size = Rx->hw_list.stat >> 16; 881 #ifdef TLDEBUG_RX 882 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 883 Rx, size); 884 #endif 885 if (tl_add_RxBuff(Rx, m ) == 0) { 886 /* 887 * No new mbuf, reuse the same. This means 888 * that this packet 889 * is lost 890 */ 891 m = NULL; 892 #ifdef TL_PRIV_STATS 893 sc->ierr_nomem++; 894 #endif 895 #ifdef TLDEBUG 896 printf("%s: out of mbuf, lost input packet\n", 897 sc->sc_dev.dv_xname); 898 #endif 899 } 900 Rx->next = NULL; 901 Rx->hw_list.fwd = 0; 902 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 903 #ifdef DIAGNOSTIC 904 if (sc->last_Rx->hw_list.fwd & 0x7) 905 printf("%s: physical addr 0x%x of list not " 906 "properly aligned\n", 907 sc->sc_dev.dv_xname, 908 sc->last_Rx->hw_list.fwd); 909 #endif 910 sc->last_Rx->next = Rx; 911 sc->last_Rx = Rx; 912 913 /* deliver packet */ 914 if (m) { 915 struct ether_header *eh; 916 if (size < sizeof(struct ether_header)) { 917 m_freem(m); 918 continue; 919 } 920 m->m_pkthdr.rcvif = ifp; 921 m->m_pkthdr.len = m->m_len = 922 size - sizeof(struct ether_header); 923 eh = mtod(m, struct ether_header *); 924 #ifdef TLDEBUG_RX 925 printf("tl_intr: Rx packet:\n"); 926 ether_printheader(eh); 927 #endif 928 #if NBPFILTER > 0 929 if (ifp->if_bpf) { 930 bpf_tap(ifp->if_bpf, 931 mtod(m, caddr_t), size); 932 /* 933 * Only pass this packet up 934 * if it is for us. 935 */ 936 if ((ifp->if_flags & IFF_PROMISC) && 937 /* !mcast and !bcast */ 938 (eh->ether_dhost[0] & 1) == 0 && 939 bcmp(eh->ether_dhost, 940 LLADDR(ifp->if_sadl), 941 sizeof(eh->ether_dhost)) != 0) { 942 m_freem(m); 943 continue; 944 } 945 } 946 #endif /* NBPFILTER > 0 */ 947 m->m_data += sizeof(struct ether_header); 948 ether_input(ifp, eh, m); 949 } 950 } 951 #ifdef TLDEBUG_RX 952 printf("TL_INTR_RxEOF: ack %d\n", ack); 953 #else 954 if (ack == 0) { 955 printf("%s: EOF intr without anything to read !\n", 956 sc->sc_dev.dv_xname); 957 tl_reset(sc); 958 /* shedule reinit of the board */ 959 timeout(tl_restart, sc, 1); 960 return(1); 961 } 962 #endif 963 break; 964 case TL_INTR_RxEOC: 965 ack++; 966 #ifdef TLDEBUG_RX 967 printf("TL_INTR_RxEOC: ack %d\n", ack); 968 #endif 969 #ifdef DIAGNOSTIC 970 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 971 printf("%s: Rx EOC interrupt and active Rx list not " 972 "cleared\n", sc->sc_dev.dv_xname); 973 return 0; 974 } else 975 #endif 976 { 977 /* 978 * write adress of Rx list and send Rx GO command, ack 979 * interrupt and enable interrupts in one command 980 */ 981 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 982 vtophys(&sc->active_Rx->hw_list)); 983 TL_HR_WRITE(sc, TL_HOST_CMD, 984 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 985 HOST_CMD_ACK | HOST_CMD_IntOn); 986 return 1; 987 } 988 case TL_INTR_TxEOF: 989 case TL_INTR_TxEOC: 990 while ((Tx = sc->active_Tx) != NULL) { 991 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 992 break; 993 ack++; 994 #ifdef TLDEBUG_TX 995 printf("TL_INTR_TxEOC: list 0x%xp done\n", 996 vtophys(&Tx->hw_list)); 997 #endif 998 Tx->hw_list.stat = 0; 999 m_freem(Tx->m); 1000 Tx->m = NULL; 1001 sc->active_Tx = Tx->next; 1002 if (sc->active_Tx == NULL) 1003 sc->last_Tx = NULL; 1004 Tx->next = sc->Free_Tx; 1005 sc->Free_Tx = Tx; 1006 } 1007 /* if this was an EOC, ACK immediatly */ 1008 if (int_type == TL_INTR_TxEOC) { 1009 #ifdef TLDEBUG_TX 1010 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1011 ack); 1012 #endif 1013 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1014 HOST_CMD_ACK | HOST_CMD_IntOn); 1015 if ( sc->active_Tx != NULL) { 1016 /* needs a Tx go command */ 1017 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1018 vtophys(&sc->active_Tx->hw_list)); 1019 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1020 } 1021 sc->tl_if.if_timer = 0; 1022 if (sc->tl_if.if_snd.ifq_head != NULL) 1023 tl_ifstart(&sc->tl_if); 1024 return 1; 1025 } 1026 #ifdef TLDEBUG 1027 else { 1028 printf("TL_INTR_TxEOF: ack %d\n", ack); 1029 } 1030 #endif 1031 sc->tl_if.if_timer = 0; 1032 if (sc->tl_if.if_snd.ifq_head != NULL) 1033 tl_ifstart(&sc->tl_if); 1034 break; 1035 case TL_INTR_Stat: 1036 ack++; 1037 #ifdef TLDEBUG 1038 printf("TL_INTR_Stat: ack %d\n", ack); 1039 #endif 1040 tl_read_stats(sc); 1041 break; 1042 case TL_INTR_Adc: 1043 if (int_reg & TL_INTVec_MASK) { 1044 /* adapter check conditions */ 1045 printf("%s: check condition, intvect=0x%x, " 1046 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1047 int_reg & TL_INTVec_MASK, 1048 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1049 tl_reset(sc); 1050 /* shedule reinit of the board */ 1051 timeout(tl_restart, sc, 1); 1052 return(1); 1053 } else { 1054 u_int8_t netstat; 1055 /* Network status */ 1056 netstat = 1057 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1058 printf("%s: network status, NetSts=%x\n", 1059 sc->sc_dev.dv_xname, netstat); 1060 /* Ack interrupts */ 1061 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1062 netstat); 1063 ack++; 1064 } 1065 break; 1066 default: 1067 printf("%s: unhandled interrupt code %x!\n", 1068 sc->sc_dev.dv_xname, int_type); 1069 ack++; 1070 } 1071 1072 if (ack) { 1073 /* Ack the interrupt and enable interrupts */ 1074 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1075 HOST_CMD_IntOn); 1076 return 1; 1077 } 1078 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1079 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1080 return 0; 1081 } 1082 1083 static int 1084 tl_ifioctl(ifp, cmd, data) 1085 struct ifnet *ifp; 1086 ioctl_cmd_t cmd; 1087 caddr_t data; 1088 { 1089 struct tl_softc *sc = ifp->if_softc; 1090 struct ifreq *ifr = (struct ifreq *)data; 1091 int s, error; 1092 1093 s = splnet(); 1094 switch(cmd) { 1095 case SIOCSIFADDR: { 1096 struct ifaddr *ifa = (struct ifaddr *)data; 1097 sc->tl_if.if_flags |= IFF_UP; 1098 if ((error = tl_init(sc)) != NULL) { 1099 sc->tl_if.if_flags &= ~IFF_UP; 1100 break; 1101 } 1102 switch (ifa->ifa_addr->sa_family) { 1103 #ifdef INET 1104 case AF_INET: 1105 arp_ifinit(ifp, ifa); 1106 break; 1107 #endif 1108 #ifdef NS 1109 case AF_NS: { 1110 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1111 1112 if (ns_nullhost(*ina)) 1113 ina->x_host = 1114 *(union ns_host*) LLADDR(ifp->if_sadl); 1115 else 1116 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1117 ifp->if_addrlen); 1118 break; 1119 } 1120 #endif 1121 default: 1122 break; 1123 } 1124 break; 1125 } 1126 case SIOCSIFFLAGS: 1127 { 1128 u_int8_t reg; 1129 /* 1130 * If interface is marked up and not running, then start it. 1131 * If it is marked down and running, stop it. 1132 */ 1133 if (ifp->if_flags & IFF_UP) { 1134 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1135 error = tl_init(sc); 1136 /* all flags have been handled by init */ 1137 break; 1138 } 1139 error = 0; 1140 reg = tl_intreg_read_byte(sc, 1141 TL_INT_NET + TL_INT_NetCmd); 1142 if (ifp->if_flags & IFF_PROMISC) 1143 reg |= TL_NETCOMMAND_CAF; 1144 else 1145 reg &= ~TL_NETCOMMAND_CAF; 1146 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1147 reg); 1148 #ifdef TL_PRIV_STATS 1149 if (ifp->if_flags & IFF_LINK0) { 1150 ifp->if_flags &= ~IFF_LINK0; 1151 printf("%s errors statistics\n", 1152 sc->sc_dev.dv_xname); 1153 printf(" %4d RX buffer overrun\n", 1154 sc->ierr_overr); 1155 printf(" %4d RX code error\n", 1156 sc->ierr_code); 1157 printf(" %4d RX crc error\n", 1158 sc->ierr_crc); 1159 printf(" %4d RX out of memory\n", 1160 sc->ierr_nomem); 1161 printf(" %4d TX buffer underrun\n", 1162 sc->oerr_underr); 1163 printf(" %4d TX deffered frames\n", 1164 sc->oerr_deffered); 1165 printf(" %4d TX single collisions\n", 1166 sc->oerr_coll); 1167 printf(" %4d TX multi collisions\n", 1168 sc->oerr_multicoll); 1169 printf(" %4d TX exessive collisions\n", 1170 sc->oerr_exesscoll); 1171 printf(" %4d TX late collisions\n", 1172 sc->oerr_latecoll); 1173 printf(" %4d TX carrier loss\n", 1174 sc->oerr_carrloss); 1175 printf(" %4d TX mbuf copy\n", 1176 sc->oerr_mcopy); 1177 } 1178 #endif 1179 } else { 1180 if (ifp->if_flags & IFF_RUNNING) 1181 tl_shutdown(sc); 1182 error = 0; 1183 } 1184 break; 1185 } 1186 case SIOCADDMULTI: 1187 case SIOCDELMULTI: 1188 /* 1189 * Update multicast listeners 1190 */ 1191 if (cmd == SIOCADDMULTI) 1192 error = ether_addmulti(ifr, &sc->tl_ec); 1193 else 1194 error = ether_delmulti(ifr, &sc->tl_ec); 1195 if (error == ENETRESET) { 1196 tl_addr_filter(sc); 1197 error = 0; 1198 } 1199 break; 1200 case SIOCSIFMEDIA: 1201 case SIOCGIFMEDIA: 1202 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1203 break; 1204 default: 1205 error = EINVAL; 1206 } 1207 splx(s); 1208 return error; 1209 } 1210 1211 static void 1212 tl_ifstart(ifp) 1213 struct ifnet *ifp; 1214 { 1215 tl_softc_t *sc = ifp->if_softc; 1216 struct mbuf *m, *mb_head; 1217 struct Tx_list *Tx; 1218 int segment, size; 1219 1220 txloop: 1221 /* If we don't have more space ... */ 1222 if (sc->Free_Tx == NULL) { 1223 #ifdef TLDEBUG 1224 printf("tl_ifstart: No free TX list\n"); 1225 #endif 1226 return; 1227 } 1228 /* Grab a paquet for output */ 1229 IF_DEQUEUE(&ifp->if_snd, mb_head); 1230 if (mb_head == NULL) { 1231 #ifdef TLDEBUG_TX 1232 printf("tl_ifstart: nothing to send\n"); 1233 #endif 1234 return; 1235 } 1236 Tx = sc->Free_Tx; 1237 sc->Free_Tx = Tx->next; 1238 /* 1239 * Go through each of the mbufs in the chain and initialize 1240 * the transmit list descriptors with the physical address 1241 * and size of the mbuf. 1242 */ 1243 tbdinit: 1244 bzero(Tx, sizeof(struct Tx_list)); 1245 Tx->m = mb_head; 1246 size = 0; 1247 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1248 if (m->m_len != 0) { 1249 if (segment == TL_NSEG) 1250 break; 1251 size += m->m_len; 1252 Tx->hw_list.seg[segment].data_addr = 1253 vtophys(mtod(m, vaddr_t)); 1254 Tx->hw_list.seg[segment].data_count = m->m_len; 1255 segment++; 1256 } 1257 } 1258 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1259 /* 1260 * We ran out of segments, or we will. We have to recopy this 1261 * mbuf chain first. 1262 */ 1263 struct mbuf *mn; 1264 #ifdef TLDEBUG_TX 1265 printf("tl_ifstart: need to copy mbuf\n"); 1266 #endif 1267 #ifdef TL_PRIV_STATS 1268 sc->oerr_mcopy++; 1269 #endif 1270 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1271 if (mn == NULL) { 1272 m_freem(mb_head); 1273 goto bad; 1274 } 1275 if (mb_head->m_pkthdr.len > MHLEN) { 1276 MCLGET(mn, M_DONTWAIT); 1277 if ((mn->m_flags & M_EXT) == 0) { 1278 m_freem(mn); 1279 m_freem(mb_head); 1280 goto bad; 1281 } 1282 } 1283 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1284 mtod(mn, caddr_t)); 1285 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1286 m_freem(mb_head); 1287 mb_head = mn; 1288 goto tbdinit; 1289 } 1290 /* We are at end of mbuf chain. check the size and 1291 * see if it needs to be extended 1292 */ 1293 if (size < ETHER_MIN_TX) { 1294 #ifdef DIAGNOSTIC 1295 if (segment >= TL_NSEG) { 1296 panic("tl_ifstart: to much segmets (%d)\n", segment); 1297 } 1298 #endif 1299 /* 1300 * add the nullbuf in the seg 1301 */ 1302 Tx->hw_list.seg[segment].data_count = 1303 ETHER_MIN_TX - size; 1304 Tx->hw_list.seg[segment].data_addr = 1305 vtophys(nullbuf); 1306 size = ETHER_MIN_TX; 1307 segment++; 1308 } 1309 /* The list is done, finish the list init */ 1310 Tx->hw_list.seg[segment-1].data_count |= 1311 TL_LAST_SEG; 1312 Tx->hw_list.stat = (size << 16) | 0x3000; 1313 #ifdef TLDEBUG_TX 1314 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1315 Tx->hw_list.stat); 1316 #if 0 1317 for(segment = 0; segment < TL_NSEG; segment++) { 1318 printf(" seg %d addr 0x%x len 0x%x\n", 1319 segment, 1320 Tx->hw_list.seg[segment].data_addr, 1321 Tx->hw_list.seg[segment].data_count); 1322 } 1323 #endif 1324 #endif 1325 sc->opkt++; 1326 if (sc->active_Tx == NULL) { 1327 sc->active_Tx = sc->last_Tx = Tx; 1328 #ifdef TLDEBUG_TX 1329 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1330 vtophys(&Tx->hw_list)); 1331 #endif 1332 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1333 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1334 } else { 1335 #ifdef TLDEBUG_TX 1336 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1337 vtophys(&Tx->hw_list)); 1338 #endif 1339 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1340 sc->last_Tx->next = Tx; 1341 sc->last_Tx = Tx; 1342 #ifdef DIAGNOSTIC 1343 if (sc->last_Tx->hw_list.fwd & 0x7) 1344 printf("%s: physical addr 0x%x of list not properly " 1345 "aligned\n", 1346 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1347 #endif 1348 } 1349 #if NBPFILTER > 0 1350 /* Pass packet to bpf if there is a listener */ 1351 if (ifp->if_bpf) 1352 bpf_mtap(ifp->if_bpf, mb_head); 1353 #endif 1354 /* 1355 * Set a 5 second timer just in case we don't hear from the card again. 1356 */ 1357 ifp->if_timer = 5; 1358 goto txloop; 1359 bad: 1360 #ifdef TLDEBUG 1361 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1362 #endif 1363 Tx->next = sc->Free_Tx; 1364 sc->Free_Tx = Tx; 1365 return; 1366 } 1367 1368 static void 1369 tl_ifwatchdog(ifp) 1370 struct ifnet *ifp; 1371 { 1372 tl_softc_t *sc = ifp->if_softc; 1373 1374 if ((ifp->if_flags & IFF_RUNNING) == 0) 1375 return; 1376 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1377 ifp->if_oerrors++; 1378 tl_init(sc); 1379 } 1380 1381 static int 1382 tl_mediachange(ifp) 1383 struct ifnet *ifp; 1384 { 1385 1386 if (ifp->if_flags & IFF_UP) 1387 tl_init(ifp->if_softc); 1388 return (0); 1389 } 1390 1391 static void 1392 tl_mediastatus(ifp, ifmr) 1393 struct ifnet *ifp; 1394 struct ifmediareq *ifmr; 1395 { 1396 tl_softc_t *sc = ifp->if_softc; 1397 1398 mii_pollstat(&sc->tl_mii); 1399 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1400 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1401 } 1402 1403 static int tl_add_RxBuff(Rx, oldm) 1404 struct Rx_list *Rx; 1405 struct mbuf *oldm; 1406 { 1407 struct mbuf *m; 1408 1409 MGETHDR(m, M_DONTWAIT, MT_DATA); 1410 if (m != NULL) { 1411 MCLGET(m, M_DONTWAIT); 1412 if ((m->m_flags & M_EXT) == 0) { 1413 m_freem(m); 1414 if (oldm == NULL) 1415 return 0; 1416 m = oldm; 1417 m->m_data = m->m_ext.ext_buf; 1418 } 1419 } else { 1420 if (oldm == NULL) 1421 return 0; 1422 m = oldm; 1423 m->m_data = m->m_ext.ext_buf; 1424 } 1425 /* 1426 * Move the data pointer up so that the incoming data packet 1427 * will be 32-bit aligned. 1428 */ 1429 m->m_data += 2; 1430 1431 /* (re)init the Rx_list struct */ 1432 1433 Rx->m = m; 1434 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1435 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1436 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1437 return (m != oldm); 1438 } 1439 1440 static void tl_ticks(v) 1441 void *v; 1442 { 1443 tl_softc_t *sc = v; 1444 1445 tl_read_stats(sc); 1446 1447 /* Tick the MII. */ 1448 mii_tick(&sc->tl_mii); 1449 1450 if (sc->opkt > 0) { 1451 if (sc->oerr_exesscoll > sc->opkt / 100) { 1452 /* exess collisions */ 1453 if (sc->tl_flags & TL_IFACT) /* only print once */ 1454 printf("%s: no carrier\n", 1455 sc->sc_dev.dv_xname); 1456 sc->tl_flags &= ~TL_IFACT; 1457 } else 1458 sc->tl_flags |= TL_IFACT; 1459 sc->oerr_exesscoll = sc->opkt = 0; 1460 sc->tl_lasttx = 0; 1461 } else { 1462 sc->tl_lasttx++; 1463 if (sc->tl_lasttx >= TL_IDLETIME) { 1464 /* 1465 * No TX activity in the last TL_IDLETIME seconds. 1466 * sends a LLC Class1 TEST pkt 1467 */ 1468 struct mbuf *m; 1469 int s; 1470 MGETHDR(m, M_DONTWAIT, MT_DATA); 1471 if (m != NULL) { 1472 #ifdef TLDEBUG 1473 printf("tl_ticks: sending LLC test pkt\n"); 1474 #endif 1475 bcopy(sc->tl_enaddr, 1476 mtod(m, struct ether_header *)->ether_dhost, 1477 6); 1478 bcopy(sc->tl_enaddr, 1479 mtod(m, struct ether_header *)->ether_shost, 1480 6); 1481 mtod(m, struct ether_header *)->ether_type = 1482 htons(3); 1483 mtod(m, unsigned char *)[14] = 0; 1484 mtod(m, unsigned char *)[15] = 0; 1485 mtod(m, unsigned char *)[16] = 0xE3; 1486 /* LLC Class1 TEST (no poll) */ 1487 m->m_len = m->m_pkthdr.len = 1488 sizeof(struct ether_header) + 3; 1489 s = splnet(); 1490 IF_PREPEND(&sc->tl_if.if_snd, m); 1491 tl_ifstart(&sc->tl_if); 1492 splx(s); 1493 } 1494 } 1495 } 1496 1497 /* read statistics every seconds */ 1498 timeout(tl_ticks, v, hz); 1499 } 1500 1501 static void 1502 tl_read_stats(sc) 1503 tl_softc_t *sc; 1504 { 1505 u_int32_t reg; 1506 int ierr_overr; 1507 int ierr_code; 1508 int ierr_crc; 1509 int oerr_underr; 1510 int oerr_deffered; 1511 int oerr_coll; 1512 int oerr_multicoll; 1513 int oerr_exesscoll; 1514 int oerr_latecoll; 1515 int oerr_carrloss; 1516 struct ifnet *ifp = &sc->tl_if; 1517 1518 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1519 ifp->if_opackets += reg & 0x00ffffff; 1520 oerr_underr = reg >> 24; 1521 1522 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1523 ifp->if_ipackets += reg & 0x00ffffff; 1524 ierr_overr = reg >> 24; 1525 1526 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1527 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1528 ierr_code = (reg & TL_FERR_CODE) >> 24; 1529 oerr_deffered = (reg & TL_FERR_DEF); 1530 1531 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1532 oerr_multicoll = (reg & TL_COL_MULTI); 1533 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1534 1535 reg = tl_intreg_read(sc, TL_INT_LERR); 1536 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1537 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1538 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1539 1540 1541 sc->stats_exesscoll += oerr_exesscoll; 1542 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1543 oerr_carrloss; 1544 ifp->if_collisions += oerr_coll + oerr_multicoll; 1545 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1546 1547 if (ierr_overr) 1548 printf("%s: receiver ring buffer overrun\n", 1549 sc->sc_dev.dv_xname); 1550 if (oerr_underr) 1551 printf("%s: transmit buffer underrun\n", 1552 sc->sc_dev.dv_xname); 1553 #ifdef TL_PRIV_STATS 1554 sc->ierr_overr += ierr_overr; 1555 sc->ierr_code += ierr_code; 1556 sc->ierr_crc += ierr_crc; 1557 sc->oerr_underr += oerr_underr; 1558 sc->oerr_deffered += oerr_deffered; 1559 sc->oerr_coll += oerr_coll; 1560 sc->oerr_multicoll += oerr_multicoll; 1561 sc->oerr_exesscoll += oerr_exesscoll; 1562 sc->oerr_latecoll += oerr_latecoll; 1563 sc->oerr_carrloss += oerr_carrloss; 1564 #endif 1565 } 1566 1567 static void tl_addr_filter(sc) 1568 tl_softc_t *sc; 1569 { 1570 struct ether_multistep step; 1571 struct ether_multi *enm; 1572 u_int32_t hash[2] = {0, 0}; 1573 int i; 1574 1575 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1576 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1577 while (enm != NULL) { 1578 #ifdef TLDEBUG 1579 printf("tl_addr_filter: addrs %s %s\n", 1580 ether_sprintf(enm->enm_addrlo), 1581 ether_sprintf(enm->enm_addrhi)); 1582 #endif 1583 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1584 i = tl_multicast_hash(enm->enm_addrlo); 1585 hash[i/32] |= 1 << (i%32); 1586 } else { 1587 hash[0] = hash[1] = 0xffffffff; 1588 sc->tl_if.if_flags |= IFF_ALLMULTI; 1589 break; 1590 } 1591 ETHER_NEXT_MULTI(step, enm); 1592 } 1593 #ifdef TLDEBUG 1594 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1595 #endif 1596 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1597 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1598 } 1599 1600 static int tl_multicast_hash(a) 1601 u_int8_t *a; 1602 { 1603 int hash; 1604 1605 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1606 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1607 1608 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1609 DA(a,36), DA(a,42)); 1610 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1611 DA(a,37), DA(a,43)) << 1; 1612 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1613 DA(a,38), DA(a,44)) << 2; 1614 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1615 DA(a,39), DA(a,45)) << 3; 1616 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1617 DA(a,40), DA(a,46)) << 4; 1618 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1619 DA(a,41), DA(a,47)) << 5; 1620 1621 return hash; 1622 } 1623 1624 #if defined(TLDEBUG_RX) 1625 void 1626 ether_printheader(eh) 1627 struct ether_header *eh; 1628 { 1629 u_char *c = (char*)eh; 1630 int i; 1631 for (i=0; i<sizeof(struct ether_header); i++) 1632 printf("%x ", (u_int)c[i]); 1633 printf("\n"); 1634 } 1635 #endif 1636
Indexes created Fri Sep 26 20:09:58 GMT 2025