if_tl.c revision 1.23
1 /* $NetBSD: if_tl.c,v 1.23 1999/03/25 16:15:00 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 #if defined(__NetBSD__) && defined(__alpha__) 116 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 117 #undef vtophys 118 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va)) 119 #endif 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 10 124 #endif 125 126 /* number of seconds the link can be idle */ 127 #ifndef TL_IDLETIME 128 #define TL_IDLETIME 10 129 #endif 130 131 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 132 static void tl_pci_attach __P((struct device *, struct device *, void *)); 133 static int tl_intr __P((void *)); 134 135 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 136 static int tl_mediachange __P((struct ifnet *)); 137 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 138 static void tl_ifwatchdog __P((struct ifnet *)); 139 static void tl_shutdown __P((void*)); 140 141 static void tl_ifstart __P((struct ifnet *)); 142 static void tl_reset __P((tl_softc_t*)); 143 static int tl_init __P((tl_softc_t*)); 144 static void tl_restart __P((void *)); 145 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 146 static void tl_read_stats __P((tl_softc_t*)); 147 static void tl_ticks __P((void*)); 148 static int tl_multicast_hash __P((u_int8_t*)); 149 static void tl_addr_filter __P((tl_softc_t*)); 150 151 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 152 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 153 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 154 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 155 156 void tl_mii_sync __P((struct tl_softc *)); 157 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 158 159 160 #if defined(TLDEBUG_RX) 161 static void ether_printheader __P((struct ether_header*)); 162 #endif 163 164 int tl_mii_read __P((struct device *, int, int)); 165 void tl_mii_write __P((struct device *, int, int, int)); 166 167 void tl_statchg __P((struct device *)); 168 169 void tl_i2c_set __P((void*, u_int8_t)); 170 void tl_i2c_clr __P((void*, u_int8_t)); 171 int tl_i2c_read __P((void*, u_int8_t)); 172 173 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 174 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 175 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 176 static __inline void netsio_clr(sc, bits) 177 tl_softc_t* sc; 178 u_int8_t bits; 179 { 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 static __inline void netsio_set(sc, bits) 184 tl_softc_t* sc; 185 u_int8_t bits; 186 { 187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 189 } 190 static __inline u_int8_t netsio_read(sc, bits) 191 tl_softc_t* sc; 192 u_int8_t bits; 193 { 194 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 195 } 196 197 struct cfattach tl_ca = { 198 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 199 }; 200 201 const struct tl_product_desc tl_compaq_products[] = { 202 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 203 "Compaq Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 205 "Compaq Netelligent 10 T" }, 206 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 207 "Compaq Integrated NetFlex 3/P" }, 208 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 209 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 211 "Compaq Dual Port Netelligent 10/100 TX" }, 212 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 213 "Compaq Deskpro 4000 5233MMX" }, 214 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 215 "Compaq NetFlex 3/P w/ BNC" }, 216 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 217 "Compaq NetFlex 3/P" }, 218 { 0, 0, NULL }, 219 }; 220 221 const struct tl_product_desc tl_ti_products[] = { 222 /* 223 * Built-in Ethernet on the TI TravelMate 5000 224 * docking station; better product description? 225 */ 226 { PCI_PRODUCT_TI_TLAN, 0, 227 "Texas Instruments ThunderLAN" }, 228 { 0, 0, NULL }, 229 }; 230 231 struct tl_vendor_desc { 232 u_int32_t tv_vendor; 233 const struct tl_product_desc *tv_products; 234 }; 235 236 const struct tl_vendor_desc tl_vendors[] = { 237 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 238 { PCI_VENDOR_TI, tl_ti_products }, 239 { 0, NULL }, 240 }; 241 242 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 243 244 const struct tl_product_desc * 245 tl_lookup_product(id) 246 u_int32_t id; 247 { 248 const struct tl_product_desc *tp; 249 const struct tl_vendor_desc *tv; 250 251 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 252 if (PCI_VENDOR(id) == tv->tv_vendor) 253 break; 254 255 if ((tp = tv->tv_products) == NULL) 256 return (NULL); 257 258 for (; tp->tp_desc != NULL; tp++) 259 if (PCI_PRODUCT(id) == tp->tp_product) 260 break; 261 262 if (tp->tp_desc == NULL) 263 return (NULL); 264 265 return (tp); 266 } 267 268 static char *nullbuf = NULL; 269 270 static int 271 tl_pci_match(parent, match, aux) 272 struct device *parent; 273 struct cfdata *match; 274 void *aux; 275 { 276 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 277 278 if (tl_lookup_product(pa->pa_id) != NULL) 279 return (1); 280 281 return (0); 282 } 283 284 static void 285 tl_pci_attach(parent, self, aux) 286 struct device * parent; 287 struct device * self; 288 void * aux; 289 { 290 tl_softc_t *sc = (tl_softc_t *)self; 291 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 292 const struct tl_product_desc *tp; 293 struct ifnet * const ifp = &sc->tl_if; 294 bus_space_tag_t iot, memt; 295 bus_space_handle_t ioh, memh; 296 pci_intr_handle_t intrhandle; 297 const char *intrstr; 298 int i, tmp, ioh_valid, memh_valid; 299 int reg_io, reg_mem; 300 pcireg_t reg10, reg14; 301 pcireg_t csr; 302 303 printf("\n"); 304 305 tp = tl_lookup_product(pa->pa_id); 306 if (tp == NULL) 307 panic("tl_pci_attach: impossible"); 308 sc->tl_product = tp; 309 310 /* 311 * Map the card space. Fisrt we have to find the I/O and MEM 312 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 313 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 314 * The ThunderLAN manual is not consistent about this either (there 315 * are both cases in code examples). 316 */ 317 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 318 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 319 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 320 reg_io = 0x10; 321 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 322 reg_io = 0x14; 323 else 324 reg_io = 0; 325 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 326 reg_mem = 0x10; 327 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 328 reg_mem = 0x14; 329 else 330 reg_mem = 0; 331 332 if (reg_io != 0) 333 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 334 0, &iot, &ioh, NULL, NULL) == 0); 335 else 336 ioh_valid = 0; 337 if (reg_mem != 0) 338 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 339 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 340 0, &memt, &memh, NULL, NULL) == 0); 341 else 342 memh_valid = 0; 343 344 if (ioh_valid) { 345 sc->tl_bustag = iot; 346 sc->tl_bushandle = ioh; 347 } else if (memh_valid) { 348 sc->tl_bustag = memt; 349 sc->tl_bushandle = memh; 350 } else { 351 printf("%s: unable to map device registers\n", 352 sc->sc_dev.dv_xname); 353 return; 354 } 355 356 /* Enable the device. */ 357 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 358 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 359 csr | PCI_COMMAND_MASTER_ENABLE); 360 361 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 362 363 tl_reset(sc); 364 365 /* fill in the i2c struct */ 366 sc->i2cbus.adapter_softc = sc; 367 sc->i2cbus.set_bit = tl_i2c_set; 368 sc->i2cbus.clr_bit = tl_i2c_clr; 369 sc->i2cbus.read_bit = tl_i2c_read; 370 371 #ifdef TLDEBUG 372 printf("default values of INTreg: 0x%x\n", 373 tl_intreg_read(sc, TL_INT_Defaults)); 374 #endif 375 376 /* read mac addr */ 377 for (i=0; i<ETHER_ADDR_LEN; i++) { 378 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 379 if (tmp < 0) { 380 printf("%s: error reading Ethernet adress\n", 381 sc->sc_dev.dv_xname); 382 return; 383 } else { 384 sc->tl_enaddr[i] = tmp; 385 } 386 } 387 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 388 ether_sprintf(sc->tl_enaddr)); 389 390 /* Map and establish interrupts */ 391 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 392 pa->pa_intrline, &intrhandle)) { 393 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 394 return; 395 } 396 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 397 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 398 tl_intr, sc); 399 if (sc->tl_ih == NULL) { 400 printf("%s: couldn't establish interrupt", 401 sc->sc_dev.dv_xname); 402 if (intrstr != NULL) 403 printf(" at %s", intrstr); 404 printf("\n"); 405 return; 406 } 407 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 408 409 /* 410 * Add shutdown hook so that DMA is disabled prior to reboot. Not 411 * doing do could allow DMA to corrupt kernel memory during the 412 * reboot before the driver initializes. 413 */ 414 (void) shutdownhook_establish(tl_shutdown, sc); 415 416 /* 417 * Initialize our media structures and probe the MII. 418 * 419 * Note that we don't care about the media instance. We 420 * are expecting to have multiple PHYs on the 10/100 cards, 421 * and on those cards we exclude the internal PHY from providing 422 * 10baseT. By ignoring the instance, it allows us to not have 423 * to specify it on the command line when switching media. 424 */ 425 sc->tl_mii.mii_ifp = ifp; 426 sc->tl_mii.mii_readreg = tl_mii_read; 427 sc->tl_mii.mii_writereg = tl_mii_write; 428 sc->tl_mii.mii_statchg = tl_statchg; 429 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 430 tl_mediastatus); 431 mii_phy_probe(self, &sc->tl_mii, 0xffffffff); 432 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 433 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 434 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 435 } else 436 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 437 438 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 439 sc->tl_if.if_softc = sc; 440 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 441 ifp->if_ioctl = tl_ifioctl; 442 ifp->if_start = tl_ifstart; 443 ifp->if_watchdog = tl_ifwatchdog; 444 ifp->if_timer = 0; 445 if_attach(ifp); 446 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 447 #if NBPFILTER > 0 448 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 449 sizeof(struct ether_header)); 450 #endif 451 } 452 453 static void 454 tl_reset(sc) 455 tl_softc_t *sc; 456 { 457 int i; 458 459 /* read stats */ 460 if (sc->tl_if.if_flags & IFF_RUNNING) { 461 untimeout(tl_ticks, sc); 462 tl_read_stats(sc); 463 } 464 /* Reset adapter */ 465 TL_HR_WRITE(sc, TL_HOST_CMD, 466 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 467 DELAY(100000); 468 /* Disable interrupts */ 469 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 470 /* setup aregs & hash */ 471 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 472 tl_intreg_write(sc, i, 0); 473 #ifdef TLDEBUG_ADDR 474 printf("Areg & hash registers: \n"); 475 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 476 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 477 #endif 478 /* Setup NetConfig */ 479 tl_intreg_write(sc, TL_INT_NetConfig, 480 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 481 /* Bsize: accept default */ 482 /* TX commit in Acommit: accept default */ 483 /* Load Ld_tmr and Ld_thr */ 484 /* Ld_tmr = 3 */ 485 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 486 /* Ld_thr = 0 */ 487 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 488 /* Unreset MII */ 489 netsio_set(sc, TL_NETSIO_NMRST); 490 DELAY(100000); 491 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 492 sc->tl_flags = 0; 493 sc->opkt = 0; 494 sc->stats_exesscoll = 0; 495 } 496 497 static void tl_shutdown(v) 498 void *v; 499 { 500 tl_softc_t *sc = v; 501 struct Tx_list *Tx; 502 int i; 503 504 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 505 return; 506 /* disable interrupts */ 507 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 508 /* stop TX and RX channels */ 509 TL_HR_WRITE(sc, TL_HOST_CMD, 510 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 511 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 512 DELAY(100000); 513 514 /* stop statistics reading loop, read stats */ 515 untimeout(tl_ticks, sc); 516 tl_read_stats(sc); 517 518 /* deallocate memory allocations */ 519 for (i=0; i< TL_NBUF; i++) { 520 if (sc->Rx_list[i].m) 521 m_freem(sc->Rx_list[i].m); 522 sc->Rx_list[i].m = NULL; 523 } 524 free(sc->Rx_list, M_DEVBUF); 525 sc->Rx_list = NULL; 526 while ((Tx = sc->active_Tx) != NULL) { 527 Tx->hw_list.stat = 0; 528 m_freem(Tx->m); 529 sc->active_Tx = Tx->next; 530 Tx->next = sc->Free_Tx; 531 sc->Free_Tx = Tx; 532 } 533 sc->last_Tx = NULL; 534 free(sc->Tx_list, M_DEVBUF); 535 sc->Tx_list = NULL; 536 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 537 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 538 sc->tl_flags = 0; 539 } 540 541 static void tl_restart(v) 542 void *v; 543 { 544 tl_init(v); 545 } 546 547 static int tl_init(sc) 548 tl_softc_t *sc; 549 { 550 struct ifnet *ifp = &sc->tl_if; 551 int i, s; 552 553 s = splnet(); 554 /* cancel any pending IO */ 555 tl_shutdown(sc); 556 tl_reset(sc); 557 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 558 splx(s); 559 return 0; 560 } 561 /* Set various register to reasonable value */ 562 /* setup NetCmd in promisc mode if needed */ 563 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 564 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 565 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 566 /* Max receive size : MCLBYTES */ 567 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 568 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 569 (MCLBYTES >> 8) & 0xff); 570 571 /* init MAC addr */ 572 for (i = 0; i < ETHER_ADDR_LEN; i++) 573 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 574 /* add multicast filters */ 575 tl_addr_filter(sc); 576 #ifdef TLDEBUG_ADDR 577 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 578 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 579 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 580 #endif 581 582 /* Pre-allocate receivers mbuf, make the lists */ 583 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 584 M_NOWAIT); 585 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 586 M_NOWAIT); 587 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 588 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 589 sc->tl_if.if_flags &= ~IFF_UP; 590 splx(s); 591 return ENOMEM; 592 } 593 for (i=0; i< TL_NBUF; i++) { 594 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 595 printf("%s: out of mbuf for receive list\n", 596 sc->sc_dev.dv_xname); 597 sc->tl_if.if_flags &= ~IFF_UP; 598 splx(s); 599 return ENOMEM; 600 } 601 if (i > 0) { /* chain the list */ 602 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 603 sc->Rx_list[i-1].hw_list.fwd = 604 vtophys(&sc->Rx_list[i].hw_list); 605 #ifdef DIAGNOSTIC 606 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 607 printf("%s: physical addr 0x%x of list not " 608 "properly aligned\n", 609 sc->sc_dev.dv_xname, 610 sc->Rx_list[i-1].hw_list.fwd); 611 #endif 612 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 613 } 614 } 615 sc->Rx_list[TL_NBUF-1].next = NULL; 616 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 617 sc->Tx_list[TL_NBUF-1].next = NULL; 618 619 sc->active_Rx = &sc->Rx_list[0]; 620 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 621 sc->active_Tx = sc->last_Tx = NULL; 622 sc->Free_Tx = &sc->Tx_list[0]; 623 624 if (nullbuf == NULL) 625 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 626 if (nullbuf == NULL) { 627 printf("%s: can't allocate space for pad buffer\n", 628 sc->sc_dev.dv_xname); 629 sc->tl_if.if_flags &= ~IFF_UP; 630 splx(s); 631 return ENOMEM; 632 } 633 bzero(nullbuf, ETHER_MIN_TX); 634 635 /* set media */ 636 mii_mediachg(&sc->tl_mii); 637 638 /* start ticks calls */ 639 timeout(tl_ticks, sc, hz); 640 /* write adress of Rx list and enable interrupts */ 641 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 642 TL_HR_WRITE(sc, TL_HOST_CMD, 643 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 644 sc->tl_if.if_flags |= IFF_RUNNING; 645 sc->tl_if.if_flags &= ~IFF_OACTIVE; 646 return 0; 647 } 648 649 650 static u_int32_t 651 tl_intreg_read(sc, reg) 652 tl_softc_t *sc; 653 u_int32_t reg; 654 { 655 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 656 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 657 } 658 659 static u_int8_t 660 tl_intreg_read_byte(sc, reg) 661 tl_softc_t *sc; 662 u_int32_t reg; 663 { 664 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 665 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 666 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 667 } 668 669 static void 670 tl_intreg_write(sc, reg, val) 671 tl_softc_t *sc; 672 u_int32_t reg; 673 u_int32_t val; 674 { 675 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 676 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 677 } 678 679 static void 680 tl_intreg_write_byte(sc, reg, val) 681 tl_softc_t *sc; 682 u_int32_t reg; 683 u_int8_t val; 684 { 685 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 686 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 687 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 688 } 689 690 void 691 tl_mii_sync(sc) 692 struct tl_softc *sc; 693 { 694 int i; 695 696 netsio_clr(sc, TL_NETSIO_MTXEN); 697 for (i = 0; i < 32; i++) { 698 netsio_clr(sc, TL_NETSIO_MCLK); 699 netsio_set(sc, TL_NETSIO_MCLK); 700 } 701 } 702 703 void 704 tl_mii_sendbits(sc, data, nbits) 705 struct tl_softc *sc; 706 u_int32_t data; 707 int nbits; 708 { 709 int i; 710 711 netsio_set(sc, TL_NETSIO_MTXEN); 712 for (i = 1 << (nbits - 1); i; i = i >> 1) { 713 netsio_clr(sc, TL_NETSIO_MCLK); 714 netsio_read(sc, TL_NETSIO_MCLK); 715 if (data & i) 716 netsio_set(sc, TL_NETSIO_MDATA); 717 else 718 netsio_clr(sc, TL_NETSIO_MDATA); 719 netsio_set(sc, TL_NETSIO_MCLK); 720 netsio_read(sc, TL_NETSIO_MCLK); 721 } 722 } 723 724 int 725 tl_mii_read(self, phy, reg) 726 struct device *self; 727 int phy, reg; 728 { 729 struct tl_softc *sc = (struct tl_softc *)self; 730 int val = 0, i, err; 731 732 /* 733 * Read the PHY register by manually driving the MII control lines. 734 */ 735 736 tl_mii_sync(sc); 737 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 738 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 739 tl_mii_sendbits(sc, phy, 5); 740 tl_mii_sendbits(sc, reg, 5); 741 742 netsio_clr(sc, TL_NETSIO_MTXEN); 743 netsio_clr(sc, TL_NETSIO_MCLK); 744 netsio_set(sc, TL_NETSIO_MCLK); 745 netsio_clr(sc, TL_NETSIO_MCLK); 746 747 err = netsio_read(sc, TL_NETSIO_MDATA); 748 netsio_set(sc, TL_NETSIO_MCLK); 749 750 /* Even if an error occurs, must still clock out the cycle. */ 751 for (i = 0; i < 16; i++) { 752 val <<= 1; 753 netsio_clr(sc, TL_NETSIO_MCLK); 754 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 755 val |= 1; 756 netsio_set(sc, TL_NETSIO_MCLK); 757 } 758 netsio_clr(sc, TL_NETSIO_MCLK); 759 netsio_set(sc, TL_NETSIO_MCLK); 760 761 return (err ? 0 : val); 762 } 763 764 void 765 tl_mii_write(self, phy, reg, val) 766 struct device *self; 767 int phy, reg, val; 768 { 769 struct tl_softc *sc = (struct tl_softc *)self; 770 771 /* 772 * Write the PHY register by manually driving the MII control lines. 773 */ 774 775 tl_mii_sync(sc); 776 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 777 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 778 tl_mii_sendbits(sc, phy, 5); 779 tl_mii_sendbits(sc, reg, 5); 780 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 781 tl_mii_sendbits(sc, val, 16); 782 783 netsio_clr(sc, TL_NETSIO_MCLK); 784 netsio_set(sc, TL_NETSIO_MCLK); 785 } 786 787 void 788 tl_statchg(self) 789 struct device *self; 790 { 791 tl_softc_t *sc = (struct tl_softc *)self; 792 u_int32_t reg; 793 794 #ifdef TLDEBUG 795 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 796 #endif 797 798 /* 799 * We must keep the ThunderLAN and the PHY in sync as 800 * to the status of full-duplex! 801 */ 802 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 803 if (sc->tl_mii.mii_media_active & IFM_FDX) 804 reg |= TL_NETCOMMAND_DUPLEX; 805 else 806 reg &= ~TL_NETCOMMAND_DUPLEX; 807 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 808 809 /* XXX Update ifp->if_baudrate */ 810 } 811 812 void tl_i2c_set(v, bit) 813 void *v; 814 u_int8_t bit; 815 { 816 tl_softc_t *sc = v; 817 818 switch (bit) { 819 case I2C_DATA: 820 netsio_set(sc, TL_NETSIO_EDATA); 821 break; 822 case I2C_CLOCK: 823 netsio_set(sc, TL_NETSIO_ECLOCK); 824 break; 825 case I2C_TXEN: 826 netsio_set(sc, TL_NETSIO_ETXEN); 827 break; 828 default: 829 printf("tl_i2c_set: unknown bit %d\n", bit); 830 } 831 return; 832 } 833 834 void tl_i2c_clr(v, bit) 835 void *v; 836 u_int8_t bit; 837 { 838 tl_softc_t *sc = v; 839 840 switch (bit) { 841 case I2C_DATA: 842 netsio_clr(sc, TL_NETSIO_EDATA); 843 break; 844 case I2C_CLOCK: 845 netsio_clr(sc, TL_NETSIO_ECLOCK); 846 break; 847 case I2C_TXEN: 848 netsio_clr(sc, TL_NETSIO_ETXEN); 849 break; 850 default: 851 printf("tl_i2c_clr: unknown bit %d\n", bit); 852 } 853 return; 854 } 855 856 int tl_i2c_read(v, bit) 857 void *v; 858 u_int8_t bit; 859 { 860 tl_softc_t *sc = v; 861 862 switch (bit) { 863 case I2C_DATA: 864 return netsio_read(sc, TL_NETSIO_EDATA); 865 break; 866 case I2C_CLOCK: 867 return netsio_read(sc, TL_NETSIO_ECLOCK); 868 break; 869 case I2C_TXEN: 870 return netsio_read(sc, TL_NETSIO_ETXEN); 871 break; 872 default: 873 printf("tl_i2c_read: unknown bit %d\n", bit); 874 return -1; 875 } 876 } 877 878 static int 879 tl_intr(v) 880 void *v; 881 { 882 tl_softc_t *sc = v; 883 struct ifnet *ifp = &sc->tl_if; 884 struct Rx_list *Rx; 885 struct Tx_list *Tx; 886 struct mbuf *m; 887 u_int32_t int_type, int_reg; 888 int ack = 0; 889 int size; 890 891 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 892 int_type = int_reg & TL_INTR_MASK; 893 if (int_type == 0) 894 return 0; 895 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 896 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 897 int_type, int_reg); 898 #endif 899 /* disable interrupts */ 900 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 901 switch(int_type & TL_INTR_MASK) { 902 case TL_INTR_RxEOF: 903 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 904 /* dequeue and requeue at end of list */ 905 ack++; 906 Rx = sc->active_Rx; 907 sc->active_Rx = Rx->next; 908 m = Rx->m; 909 size = Rx->hw_list.stat >> 16; 910 #ifdef TLDEBUG_RX 911 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 912 Rx, size); 913 #endif 914 if (tl_add_RxBuff(Rx, m ) == 0) { 915 /* 916 * No new mbuf, reuse the same. This means 917 * that this packet 918 * is lost 919 */ 920 m = NULL; 921 #ifdef TL_PRIV_STATS 922 sc->ierr_nomem++; 923 #endif 924 #ifdef TLDEBUG 925 printf("%s: out of mbuf, lost input packet\n", 926 sc->sc_dev.dv_xname); 927 #endif 928 } 929 Rx->next = NULL; 930 Rx->hw_list.fwd = 0; 931 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 932 #ifdef DIAGNOSTIC 933 if (sc->last_Rx->hw_list.fwd & 0x7) 934 printf("%s: physical addr 0x%x of list not " 935 "properly aligned\n", 936 sc->sc_dev.dv_xname, 937 sc->last_Rx->hw_list.fwd); 938 #endif 939 sc->last_Rx->next = Rx; 940 sc->last_Rx = Rx; 941 942 /* deliver packet */ 943 if (m) { 944 struct ether_header *eh; 945 if (size < sizeof(struct ether_header)) { 946 m_freem(m); 947 continue; 948 } 949 m->m_pkthdr.rcvif = ifp; 950 m->m_pkthdr.len = m->m_len = 951 size - sizeof(struct ether_header); 952 eh = mtod(m, struct ether_header *); 953 #ifdef TLDEBUG_RX 954 printf("tl_intr: Rx packet:\n"); 955 ether_printheader(eh); 956 #endif 957 #if NBPFILTER > 0 958 if (ifp->if_bpf) { 959 bpf_tap(ifp->if_bpf, 960 mtod(m, caddr_t), size); 961 /* 962 * Only pass this packet up 963 * if it is for us. 964 */ 965 if ((ifp->if_flags & IFF_PROMISC) && 966 /* !mcast and !bcast */ 967 (eh->ether_dhost[0] & 1) == 0 && 968 bcmp(eh->ether_dhost, 969 LLADDR(ifp->if_sadl), 970 sizeof(eh->ether_dhost)) != 0) { 971 m_freem(m); 972 continue; 973 } 974 } 975 #endif /* NBPFILTER > 0 */ 976 m->m_data += sizeof(struct ether_header); 977 ether_input(ifp, eh, m); 978 } 979 } 980 #ifdef TLDEBUG_RX 981 printf("TL_INTR_RxEOF: ack %d\n", ack); 982 #else 983 if (ack == 0) { 984 printf("%s: EOF intr without anything to read !\n", 985 sc->sc_dev.dv_xname); 986 tl_reset(sc); 987 /* shedule reinit of the board */ 988 timeout(tl_restart, sc, 1); 989 return(1); 990 } 991 #endif 992 break; 993 case TL_INTR_RxEOC: 994 ack++; 995 #ifdef TLDEBUG_RX 996 printf("TL_INTR_RxEOC: ack %d\n", ack); 997 #endif 998 #ifdef DIAGNOSTIC 999 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 1000 printf("%s: Rx EOC interrupt and active Rx list not " 1001 "cleared\n", sc->sc_dev.dv_xname); 1002 return 0; 1003 } else 1004 #endif 1005 { 1006 /* 1007 * write adress of Rx list and send Rx GO command, ack 1008 * interrupt and enable interrupts in one command 1009 */ 1010 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1011 vtophys(&sc->active_Rx->hw_list)); 1012 TL_HR_WRITE(sc, TL_HOST_CMD, 1013 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1014 HOST_CMD_ACK | HOST_CMD_IntOn); 1015 return 1; 1016 } 1017 case TL_INTR_TxEOF: 1018 case TL_INTR_TxEOC: 1019 while ((Tx = sc->active_Tx) != NULL) { 1020 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 1021 break; 1022 ack++; 1023 #ifdef TLDEBUG_TX 1024 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1025 vtophys(&Tx->hw_list)); 1026 #endif 1027 Tx->hw_list.stat = 0; 1028 m_freem(Tx->m); 1029 Tx->m = NULL; 1030 sc->active_Tx = Tx->next; 1031 if (sc->active_Tx == NULL) 1032 sc->last_Tx = NULL; 1033 Tx->next = sc->Free_Tx; 1034 sc->Free_Tx = Tx; 1035 } 1036 /* if this was an EOC, ACK immediatly */ 1037 if (int_type == TL_INTR_TxEOC) { 1038 #ifdef TLDEBUG_TX 1039 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1040 ack); 1041 #endif 1042 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1043 HOST_CMD_ACK | HOST_CMD_IntOn); 1044 if ( sc->active_Tx != NULL) { 1045 /* needs a Tx go command */ 1046 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1047 vtophys(&sc->active_Tx->hw_list)); 1048 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1049 } 1050 sc->tl_if.if_timer = 0; 1051 if (sc->tl_if.if_snd.ifq_head != NULL) 1052 tl_ifstart(&sc->tl_if); 1053 return 1; 1054 } 1055 #ifdef TLDEBUG 1056 else { 1057 printf("TL_INTR_TxEOF: ack %d\n", ack); 1058 } 1059 #endif 1060 sc->tl_if.if_timer = 0; 1061 if (sc->tl_if.if_snd.ifq_head != NULL) 1062 tl_ifstart(&sc->tl_if); 1063 break; 1064 case TL_INTR_Stat: 1065 ack++; 1066 #ifdef TLDEBUG 1067 printf("TL_INTR_Stat: ack %d\n", ack); 1068 #endif 1069 tl_read_stats(sc); 1070 break; 1071 case TL_INTR_Adc: 1072 if (int_reg & TL_INTVec_MASK) { 1073 /* adapter check conditions */ 1074 printf("%s: check condition, intvect=0x%x, " 1075 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1076 int_reg & TL_INTVec_MASK, 1077 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1078 tl_reset(sc); 1079 /* shedule reinit of the board */ 1080 timeout(tl_restart, sc, 1); 1081 return(1); 1082 } else { 1083 u_int8_t netstat; 1084 /* Network status */ 1085 netstat = 1086 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1087 printf("%s: network status, NetSts=%x\n", 1088 sc->sc_dev.dv_xname, netstat); 1089 /* Ack interrupts */ 1090 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1091 netstat); 1092 ack++; 1093 } 1094 break; 1095 default: 1096 printf("%s: unhandled interrupt code %x!\n", 1097 sc->sc_dev.dv_xname, int_type); 1098 ack++; 1099 } 1100 1101 if (ack) { 1102 /* Ack the interrupt and enable interrupts */ 1103 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1104 HOST_CMD_IntOn); 1105 return 1; 1106 } 1107 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1108 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1109 return 0; 1110 } 1111 1112 static int 1113 tl_ifioctl(ifp, cmd, data) 1114 struct ifnet *ifp; 1115 ioctl_cmd_t cmd; 1116 caddr_t data; 1117 { 1118 struct tl_softc *sc = ifp->if_softc; 1119 struct ifreq *ifr = (struct ifreq *)data; 1120 int s, error; 1121 1122 s = splnet(); 1123 switch(cmd) { 1124 case SIOCSIFADDR: { 1125 struct ifaddr *ifa = (struct ifaddr *)data; 1126 sc->tl_if.if_flags |= IFF_UP; 1127 if ((error = tl_init(sc)) != NULL) { 1128 sc->tl_if.if_flags &= ~IFF_UP; 1129 break; 1130 } 1131 switch (ifa->ifa_addr->sa_family) { 1132 #ifdef INET 1133 case AF_INET: 1134 arp_ifinit(ifp, ifa); 1135 break; 1136 #endif 1137 #ifdef NS 1138 case AF_NS: { 1139 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1140 1141 if (ns_nullhost(*ina)) 1142 ina->x_host = 1143 *(union ns_host*) LLADDR(ifp->if_sadl); 1144 else 1145 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1146 ifp->if_addrlen); 1147 break; 1148 } 1149 #endif 1150 default: 1151 break; 1152 } 1153 break; 1154 } 1155 case SIOCSIFFLAGS: 1156 { 1157 u_int8_t reg; 1158 /* 1159 * If interface is marked up and not running, then start it. 1160 * If it is marked down and running, stop it. 1161 */ 1162 if (ifp->if_flags & IFF_UP) { 1163 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1164 error = tl_init(sc); 1165 /* all flags have been handled by init */ 1166 break; 1167 } 1168 error = 0; 1169 reg = tl_intreg_read_byte(sc, 1170 TL_INT_NET + TL_INT_NetCmd); 1171 if (ifp->if_flags & IFF_PROMISC) 1172 reg |= TL_NETCOMMAND_CAF; 1173 else 1174 reg &= ~TL_NETCOMMAND_CAF; 1175 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1176 reg); 1177 #ifdef TL_PRIV_STATS 1178 if (ifp->if_flags & IFF_LINK0) { 1179 ifp->if_flags &= ~IFF_LINK0; 1180 printf("%s errors statistics\n", 1181 sc->sc_dev.dv_xname); 1182 printf(" %4d RX buffer overrun\n", 1183 sc->ierr_overr); 1184 printf(" %4d RX code error\n", 1185 sc->ierr_code); 1186 printf(" %4d RX crc error\n", 1187 sc->ierr_crc); 1188 printf(" %4d RX out of memory\n", 1189 sc->ierr_nomem); 1190 printf(" %4d TX buffer underrun\n", 1191 sc->oerr_underr); 1192 printf(" %4d TX deffered frames\n", 1193 sc->oerr_deffered); 1194 printf(" %4d TX single collisions\n", 1195 sc->oerr_coll); 1196 printf(" %4d TX multi collisions\n", 1197 sc->oerr_multicoll); 1198 printf(" %4d TX exessive collisions\n", 1199 sc->oerr_exesscoll); 1200 printf(" %4d TX late collisions\n", 1201 sc->oerr_latecoll); 1202 printf(" %4d TX carrier loss\n", 1203 sc->oerr_carrloss); 1204 printf(" %4d TX mbuf copy\n", 1205 sc->oerr_mcopy); 1206 } 1207 #endif 1208 } else { 1209 if (ifp->if_flags & IFF_RUNNING) 1210 tl_shutdown(sc); 1211 error = 0; 1212 } 1213 break; 1214 } 1215 case SIOCADDMULTI: 1216 case SIOCDELMULTI: 1217 /* 1218 * Update multicast listeners 1219 */ 1220 if (cmd == SIOCADDMULTI) 1221 error = ether_addmulti(ifr, &sc->tl_ec); 1222 else 1223 error = ether_delmulti(ifr, &sc->tl_ec); 1224 if (error == ENETRESET) { 1225 tl_addr_filter(sc); 1226 error = 0; 1227 } 1228 break; 1229 case SIOCSIFMEDIA: 1230 case SIOCGIFMEDIA: 1231 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1232 break; 1233 default: 1234 error = EINVAL; 1235 } 1236 splx(s); 1237 return error; 1238 } 1239 1240 static void 1241 tl_ifstart(ifp) 1242 struct ifnet *ifp; 1243 { 1244 tl_softc_t *sc = ifp->if_softc; 1245 struct mbuf *m, *mb_head; 1246 struct Tx_list *Tx; 1247 int segment, size; 1248 1249 txloop: 1250 /* If we don't have more space ... */ 1251 if (sc->Free_Tx == NULL) { 1252 #ifdef TLDEBUG 1253 printf("tl_ifstart: No free TX list\n"); 1254 #endif 1255 return; 1256 } 1257 /* Grab a paquet for output */ 1258 IF_DEQUEUE(&ifp->if_snd, mb_head); 1259 if (mb_head == NULL) { 1260 #ifdef TLDEBUG_TX 1261 printf("tl_ifstart: nothing to send\n"); 1262 #endif 1263 return; 1264 } 1265 Tx = sc->Free_Tx; 1266 sc->Free_Tx = Tx->next; 1267 /* 1268 * Go through each of the mbufs in the chain and initialize 1269 * the transmit list descriptors with the physical address 1270 * and size of the mbuf. 1271 */ 1272 tbdinit: 1273 bzero(Tx, sizeof(struct Tx_list)); 1274 Tx->m = mb_head; 1275 size = 0; 1276 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1277 if (m->m_len != 0) { 1278 if (segment == TL_NSEG) 1279 break; 1280 size += m->m_len; 1281 Tx->hw_list.seg[segment].data_addr = 1282 vtophys(mtod(m, vaddr_t)); 1283 Tx->hw_list.seg[segment].data_count = m->m_len; 1284 segment++; 1285 } 1286 } 1287 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1288 /* 1289 * We ran out of segments, or we will. We have to recopy this 1290 * mbuf chain first. 1291 */ 1292 struct mbuf *mn; 1293 #ifdef TLDEBUG_TX 1294 printf("tl_ifstart: need to copy mbuf\n"); 1295 #endif 1296 #ifdef TL_PRIV_STATS 1297 sc->oerr_mcopy++; 1298 #endif 1299 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1300 if (mn == NULL) { 1301 m_freem(mb_head); 1302 goto bad; 1303 } 1304 if (mb_head->m_pkthdr.len > MHLEN) { 1305 MCLGET(mn, M_DONTWAIT); 1306 if ((mn->m_flags & M_EXT) == 0) { 1307 m_freem(mn); 1308 m_freem(mb_head); 1309 goto bad; 1310 } 1311 } 1312 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1313 mtod(mn, caddr_t)); 1314 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1315 m_freem(mb_head); 1316 mb_head = mn; 1317 goto tbdinit; 1318 } 1319 /* We are at end of mbuf chain. check the size and 1320 * see if it needs to be extended 1321 */ 1322 if (size < ETHER_MIN_TX) { 1323 #ifdef DIAGNOSTIC 1324 if (segment >= TL_NSEG) { 1325 panic("tl_ifstart: to much segmets (%d)\n", segment); 1326 } 1327 #endif 1328 /* 1329 * add the nullbuf in the seg 1330 */ 1331 Tx->hw_list.seg[segment].data_count = 1332 ETHER_MIN_TX - size; 1333 Tx->hw_list.seg[segment].data_addr = 1334 vtophys(nullbuf); 1335 size = ETHER_MIN_TX; 1336 segment++; 1337 } 1338 /* The list is done, finish the list init */ 1339 Tx->hw_list.seg[segment-1].data_count |= 1340 TL_LAST_SEG; 1341 Tx->hw_list.stat = (size << 16) | 0x3000; 1342 #ifdef TLDEBUG_TX 1343 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1344 Tx->hw_list.stat); 1345 #if 0 1346 for(segment = 0; segment < TL_NSEG; segment++) { 1347 printf(" seg %d addr 0x%x len 0x%x\n", 1348 segment, 1349 Tx->hw_list.seg[segment].data_addr, 1350 Tx->hw_list.seg[segment].data_count); 1351 } 1352 #endif 1353 #endif 1354 sc->opkt++; 1355 if (sc->active_Tx == NULL) { 1356 sc->active_Tx = sc->last_Tx = Tx; 1357 #ifdef TLDEBUG_TX 1358 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1359 vtophys(&Tx->hw_list)); 1360 #endif 1361 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1362 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1363 } else { 1364 #ifdef TLDEBUG_TX 1365 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1366 vtophys(&Tx->hw_list)); 1367 #endif 1368 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1369 sc->last_Tx->next = Tx; 1370 sc->last_Tx = Tx; 1371 #ifdef DIAGNOSTIC 1372 if (sc->last_Tx->hw_list.fwd & 0x7) 1373 printf("%s: physical addr 0x%x of list not properly " 1374 "aligned\n", 1375 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1376 #endif 1377 } 1378 #if NBPFILTER > 0 1379 /* Pass packet to bpf if there is a listener */ 1380 if (ifp->if_bpf) 1381 bpf_mtap(ifp->if_bpf, mb_head); 1382 #endif 1383 /* 1384 * Set a 5 second timer just in case we don't hear from the card again. 1385 */ 1386 ifp->if_timer = 5; 1387 goto txloop; 1388 bad: 1389 #ifdef TLDEBUG 1390 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1391 #endif 1392 Tx->next = sc->Free_Tx; 1393 sc->Free_Tx = Tx; 1394 return; 1395 } 1396 1397 static void 1398 tl_ifwatchdog(ifp) 1399 struct ifnet *ifp; 1400 { 1401 tl_softc_t *sc = ifp->if_softc; 1402 1403 if ((ifp->if_flags & IFF_RUNNING) == 0) 1404 return; 1405 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1406 ifp->if_oerrors++; 1407 tl_init(sc); 1408 } 1409 1410 static int 1411 tl_mediachange(ifp) 1412 struct ifnet *ifp; 1413 { 1414 1415 if (ifp->if_flags & IFF_UP) 1416 tl_init(ifp->if_softc); 1417 return (0); 1418 } 1419 1420 static void 1421 tl_mediastatus(ifp, ifmr) 1422 struct ifnet *ifp; 1423 struct ifmediareq *ifmr; 1424 { 1425 tl_softc_t *sc = ifp->if_softc; 1426 1427 mii_pollstat(&sc->tl_mii); 1428 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1429 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1430 } 1431 1432 static int tl_add_RxBuff(Rx, oldm) 1433 struct Rx_list *Rx; 1434 struct mbuf *oldm; 1435 { 1436 struct mbuf *m; 1437 1438 MGETHDR(m, M_DONTWAIT, MT_DATA); 1439 if (m != NULL) { 1440 MCLGET(m, M_DONTWAIT); 1441 if ((m->m_flags & M_EXT) == 0) { 1442 m_freem(m); 1443 if (oldm == NULL) 1444 return 0; 1445 m = oldm; 1446 m->m_data = m->m_ext.ext_buf; 1447 } 1448 } else { 1449 if (oldm == NULL) 1450 return 0; 1451 m = oldm; 1452 m->m_data = m->m_ext.ext_buf; 1453 } 1454 /* 1455 * Move the data pointer up so that the incoming data packet 1456 * will be 32-bit aligned. 1457 */ 1458 m->m_data += 2; 1459 1460 /* (re)init the Rx_list struct */ 1461 1462 Rx->m = m; 1463 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1464 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1465 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1466 return (m != oldm); 1467 } 1468 1469 static void tl_ticks(v) 1470 void *v; 1471 { 1472 tl_softc_t *sc = v; 1473 1474 tl_read_stats(sc); 1475 1476 /* Tick the MII. */ 1477 mii_tick(&sc->tl_mii); 1478 1479 if (sc->opkt > 0) { 1480 if (sc->oerr_exesscoll > sc->opkt / 100) { 1481 /* exess collisions */ 1482 if (sc->tl_flags & TL_IFACT) /* only print once */ 1483 printf("%s: no carrier\n", 1484 sc->sc_dev.dv_xname); 1485 sc->tl_flags &= ~TL_IFACT; 1486 } else 1487 sc->tl_flags |= TL_IFACT; 1488 sc->oerr_exesscoll = sc->opkt = 0; 1489 sc->tl_lasttx = 0; 1490 } else { 1491 sc->tl_lasttx++; 1492 if (sc->tl_lasttx >= TL_IDLETIME) { 1493 /* 1494 * No TX activity in the last TL_IDLETIME seconds. 1495 * sends a LLC Class1 TEST pkt 1496 */ 1497 struct mbuf *m; 1498 int s; 1499 MGETHDR(m, M_DONTWAIT, MT_DATA); 1500 if (m != NULL) { 1501 #ifdef TLDEBUG 1502 printf("tl_ticks: sending LLC test pkt\n"); 1503 #endif 1504 bcopy(sc->tl_enaddr, 1505 mtod(m, struct ether_header *)->ether_dhost, 1506 6); 1507 bcopy(sc->tl_enaddr, 1508 mtod(m, struct ether_header *)->ether_shost, 1509 6); 1510 mtod(m, struct ether_header *)->ether_type = 1511 htons(3); 1512 mtod(m, unsigned char *)[14] = 0; 1513 mtod(m, unsigned char *)[15] = 0; 1514 mtod(m, unsigned char *)[16] = 0xE3; 1515 /* LLC Class1 TEST (no poll) */ 1516 m->m_len = m->m_pkthdr.len = 1517 sizeof(struct ether_header) + 3; 1518 s = splnet(); 1519 IF_PREPEND(&sc->tl_if.if_snd, m); 1520 tl_ifstart(&sc->tl_if); 1521 splx(s); 1522 } 1523 } 1524 } 1525 1526 /* read statistics every seconds */ 1527 timeout(tl_ticks, v, hz); 1528 } 1529 1530 static void 1531 tl_read_stats(sc) 1532 tl_softc_t *sc; 1533 { 1534 u_int32_t reg; 1535 int ierr_overr; 1536 int ierr_code; 1537 int ierr_crc; 1538 int oerr_underr; 1539 int oerr_deffered; 1540 int oerr_coll; 1541 int oerr_multicoll; 1542 int oerr_exesscoll; 1543 int oerr_latecoll; 1544 int oerr_carrloss; 1545 struct ifnet *ifp = &sc->tl_if; 1546 1547 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1548 ifp->if_opackets += reg & 0x00ffffff; 1549 oerr_underr = reg >> 24; 1550 1551 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1552 ifp->if_ipackets += reg & 0x00ffffff; 1553 ierr_overr = reg >> 24; 1554 1555 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1556 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1557 ierr_code = (reg & TL_FERR_CODE) >> 24; 1558 oerr_deffered = (reg & TL_FERR_DEF); 1559 1560 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1561 oerr_multicoll = (reg & TL_COL_MULTI); 1562 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1563 1564 reg = tl_intreg_read(sc, TL_INT_LERR); 1565 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1566 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1567 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1568 1569 1570 sc->stats_exesscoll += oerr_exesscoll; 1571 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1572 oerr_carrloss; 1573 ifp->if_collisions += oerr_coll + oerr_multicoll; 1574 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1575 1576 if (ierr_overr) 1577 printf("%s: receiver ring buffer overrun\n", 1578 sc->sc_dev.dv_xname); 1579 if (oerr_underr) 1580 printf("%s: transmit buffer underrun\n", 1581 sc->sc_dev.dv_xname); 1582 #ifdef TL_PRIV_STATS 1583 sc->ierr_overr += ierr_overr; 1584 sc->ierr_code += ierr_code; 1585 sc->ierr_crc += ierr_crc; 1586 sc->oerr_underr += oerr_underr; 1587 sc->oerr_deffered += oerr_deffered; 1588 sc->oerr_coll += oerr_coll; 1589 sc->oerr_multicoll += oerr_multicoll; 1590 sc->oerr_exesscoll += oerr_exesscoll; 1591 sc->oerr_latecoll += oerr_latecoll; 1592 sc->oerr_carrloss += oerr_carrloss; 1593 #endif 1594 } 1595 1596 static void tl_addr_filter(sc) 1597 tl_softc_t *sc; 1598 { 1599 struct ether_multistep step; 1600 struct ether_multi *enm; 1601 u_int32_t hash[2] = {0, 0}; 1602 int i; 1603 1604 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1605 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1606 while (enm != NULL) { 1607 #ifdef TLDEBUG 1608 printf("tl_addr_filter: addrs %s %s\n", 1609 ether_sprintf(enm->enm_addrlo), 1610 ether_sprintf(enm->enm_addrhi)); 1611 #endif 1612 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1613 i = tl_multicast_hash(enm->enm_addrlo); 1614 hash[i/32] |= 1 << (i%32); 1615 } else { 1616 hash[0] = hash[1] = 0xffffffff; 1617 sc->tl_if.if_flags |= IFF_ALLMULTI; 1618 break; 1619 } 1620 ETHER_NEXT_MULTI(step, enm); 1621 } 1622 #ifdef TLDEBUG 1623 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1624 #endif 1625 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1626 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1627 } 1628 1629 static int tl_multicast_hash(a) 1630 u_int8_t *a; 1631 { 1632 int hash; 1633 1634 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1635 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1636 1637 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1638 DA(a,36), DA(a,42)); 1639 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1640 DA(a,37), DA(a,43)) << 1; 1641 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1642 DA(a,38), DA(a,44)) << 2; 1643 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1644 DA(a,39), DA(a,45)) << 3; 1645 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1646 DA(a,40), DA(a,46)) << 4; 1647 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1648 DA(a,41), DA(a,47)) << 5; 1649 1650 return hash; 1651 } 1652 1653 #if defined(TLDEBUG_RX) 1654 void 1655 ether_printheader(eh) 1656 struct ether_header *eh; 1657 { 1658 u_char *c = (char*)eh; 1659 int i; 1660 for (i=0; i<sizeof(struct ether_header); i++) 1661 printf("%x ", (u_int)c[i]); 1662 printf("\n"); 1663 } 1664 #endif 1665
Indexes created Wed Sep 24 02:09:48 GMT 2025