if_tl.c revision 1.25
1 /* $NetBSD: if_tl.c,v 1.25 1999/11/04 00:24:33 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 #if defined(__NetBSD__) && defined(__alpha__) 116 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 117 #undef vtophys 118 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va)) 119 #endif 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 10 124 #endif 125 126 /* number of seconds the link can be idle */ 127 #ifndef TL_IDLETIME 128 #define TL_IDLETIME 10 129 #endif 130 131 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 132 static void tl_pci_attach __P((struct device *, struct device *, void *)); 133 static int tl_intr __P((void *)); 134 135 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 136 static int tl_mediachange __P((struct ifnet *)); 137 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 138 static void tl_ifwatchdog __P((struct ifnet *)); 139 static void tl_shutdown __P((void*)); 140 141 static void tl_ifstart __P((struct ifnet *)); 142 static void tl_reset __P((tl_softc_t*)); 143 static int tl_init __P((tl_softc_t*)); 144 static void tl_restart __P((void *)); 145 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 146 static void tl_read_stats __P((tl_softc_t*)); 147 static void tl_ticks __P((void*)); 148 static int tl_multicast_hash __P((u_int8_t*)); 149 static void tl_addr_filter __P((tl_softc_t*)); 150 151 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 152 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 153 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 154 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 155 156 void tl_mii_sync __P((struct tl_softc *)); 157 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 158 159 160 #if defined(TLDEBUG_RX) 161 static void ether_printheader __P((struct ether_header*)); 162 #endif 163 164 int tl_mii_read __P((struct device *, int, int)); 165 void tl_mii_write __P((struct device *, int, int, int)); 166 167 void tl_statchg __P((struct device *)); 168 169 void tl_i2c_set __P((void*, u_int8_t)); 170 void tl_i2c_clr __P((void*, u_int8_t)); 171 int tl_i2c_read __P((void*, u_int8_t)); 172 173 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 174 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 175 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 176 static __inline void netsio_clr(sc, bits) 177 tl_softc_t* sc; 178 u_int8_t bits; 179 { 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 static __inline void netsio_set(sc, bits) 184 tl_softc_t* sc; 185 u_int8_t bits; 186 { 187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 189 } 190 static __inline u_int8_t netsio_read(sc, bits) 191 tl_softc_t* sc; 192 u_int8_t bits; 193 { 194 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 195 } 196 197 struct cfattach tl_ca = { 198 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 199 }; 200 201 const struct tl_product_desc tl_compaq_products[] = { 202 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 203 "Compaq Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 205 "Compaq Netelligent 10 T" }, 206 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 207 "Compaq Integrated NetFlex 3/P" }, 208 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 209 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 211 "Compaq Dual Port Netelligent 10/100 TX" }, 212 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 213 "Compaq Deskpro 4000 5233MMX" }, 214 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 215 "Compaq NetFlex 3/P w/ BNC" }, 216 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 217 "Compaq NetFlex 3/P" }, 218 { 0, 0, NULL }, 219 }; 220 221 const struct tl_product_desc tl_ti_products[] = { 222 /* 223 * Built-in Ethernet on the TI TravelMate 5000 224 * docking station; better product description? 225 */ 226 { PCI_PRODUCT_TI_TLAN, 0, 227 "Texas Instruments ThunderLAN" }, 228 { 0, 0, NULL }, 229 }; 230 231 struct tl_vendor_desc { 232 u_int32_t tv_vendor; 233 const struct tl_product_desc *tv_products; 234 }; 235 236 const struct tl_vendor_desc tl_vendors[] = { 237 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 238 { PCI_VENDOR_TI, tl_ti_products }, 239 { 0, NULL }, 240 }; 241 242 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 243 244 const struct tl_product_desc * 245 tl_lookup_product(id) 246 u_int32_t id; 247 { 248 const struct tl_product_desc *tp; 249 const struct tl_vendor_desc *tv; 250 251 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 252 if (PCI_VENDOR(id) == tv->tv_vendor) 253 break; 254 255 if ((tp = tv->tv_products) == NULL) 256 return (NULL); 257 258 for (; tp->tp_desc != NULL; tp++) 259 if (PCI_PRODUCT(id) == tp->tp_product) 260 break; 261 262 if (tp->tp_desc == NULL) 263 return (NULL); 264 265 return (tp); 266 } 267 268 static char *nullbuf = NULL; 269 270 static int 271 tl_pci_match(parent, match, aux) 272 struct device *parent; 273 struct cfdata *match; 274 void *aux; 275 { 276 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 277 278 if (tl_lookup_product(pa->pa_id) != NULL) 279 return (1); 280 281 return (0); 282 } 283 284 static void 285 tl_pci_attach(parent, self, aux) 286 struct device * parent; 287 struct device * self; 288 void * aux; 289 { 290 tl_softc_t *sc = (tl_softc_t *)self; 291 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 292 const struct tl_product_desc *tp; 293 struct ifnet * const ifp = &sc->tl_if; 294 bus_space_tag_t iot, memt; 295 bus_space_handle_t ioh, memh; 296 pci_intr_handle_t intrhandle; 297 const char *intrstr; 298 int i, tmp, ioh_valid, memh_valid; 299 int reg_io, reg_mem; 300 pcireg_t reg10, reg14; 301 pcireg_t csr; 302 303 printf("\n"); 304 305 tp = tl_lookup_product(pa->pa_id); 306 if (tp == NULL) 307 panic("tl_pci_attach: impossible"); 308 sc->tl_product = tp; 309 310 /* 311 * Map the card space. Fisrt we have to find the I/O and MEM 312 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 313 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 314 * The ThunderLAN manual is not consistent about this either (there 315 * are both cases in code examples). 316 */ 317 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 318 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 319 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 320 reg_io = 0x10; 321 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 322 reg_io = 0x14; 323 else 324 reg_io = 0; 325 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 326 reg_mem = 0x10; 327 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 328 reg_mem = 0x14; 329 else 330 reg_mem = 0; 331 332 if (reg_io != 0) 333 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 334 0, &iot, &ioh, NULL, NULL) == 0); 335 else 336 ioh_valid = 0; 337 if (reg_mem != 0) 338 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 339 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 340 0, &memt, &memh, NULL, NULL) == 0); 341 else 342 memh_valid = 0; 343 344 if (ioh_valid) { 345 sc->tl_bustag = iot; 346 sc->tl_bushandle = ioh; 347 } else if (memh_valid) { 348 sc->tl_bustag = memt; 349 sc->tl_bushandle = memh; 350 } else { 351 printf("%s: unable to map device registers\n", 352 sc->sc_dev.dv_xname); 353 return; 354 } 355 356 /* Enable the device. */ 357 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 358 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 359 csr | PCI_COMMAND_MASTER_ENABLE); 360 361 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 362 363 tl_reset(sc); 364 365 /* fill in the i2c struct */ 366 sc->i2cbus.adapter_softc = sc; 367 sc->i2cbus.set_bit = tl_i2c_set; 368 sc->i2cbus.clr_bit = tl_i2c_clr; 369 sc->i2cbus.read_bit = tl_i2c_read; 370 371 #ifdef TLDEBUG 372 printf("default values of INTreg: 0x%x\n", 373 tl_intreg_read(sc, TL_INT_Defaults)); 374 #endif 375 376 /* read mac addr */ 377 for (i=0; i<ETHER_ADDR_LEN; i++) { 378 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 379 if (tmp < 0) { 380 printf("%s: error reading Ethernet adress\n", 381 sc->sc_dev.dv_xname); 382 return; 383 } else { 384 sc->tl_enaddr[i] = tmp; 385 } 386 } 387 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 388 ether_sprintf(sc->tl_enaddr)); 389 390 /* Map and establish interrupts */ 391 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 392 pa->pa_intrline, &intrhandle)) { 393 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 394 return; 395 } 396 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 397 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 398 tl_intr, sc); 399 if (sc->tl_ih == NULL) { 400 printf("%s: couldn't establish interrupt", 401 sc->sc_dev.dv_xname); 402 if (intrstr != NULL) 403 printf(" at %s", intrstr); 404 printf("\n"); 405 return; 406 } 407 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 408 409 /* 410 * Add shutdown hook so that DMA is disabled prior to reboot. Not 411 * doing do could allow DMA to corrupt kernel memory during the 412 * reboot before the driver initializes. 413 */ 414 (void) shutdownhook_establish(tl_shutdown, sc); 415 416 /* 417 * Initialize our media structures and probe the MII. 418 * 419 * Note that we don't care about the media instance. We 420 * are expecting to have multiple PHYs on the 10/100 cards, 421 * and on those cards we exclude the internal PHY from providing 422 * 10baseT. By ignoring the instance, it allows us to not have 423 * to specify it on the command line when switching media. 424 */ 425 sc->tl_mii.mii_ifp = ifp; 426 sc->tl_mii.mii_readreg = tl_mii_read; 427 sc->tl_mii.mii_writereg = tl_mii_write; 428 sc->tl_mii.mii_statchg = tl_statchg; 429 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 430 tl_mediastatus); 431 mii_phy_probe(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 432 MII_OFFSET_ANY); 433 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 434 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 435 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 436 } else 437 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 438 439 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 440 sc->tl_if.if_softc = sc; 441 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 442 ifp->if_ioctl = tl_ifioctl; 443 ifp->if_start = tl_ifstart; 444 ifp->if_watchdog = tl_ifwatchdog; 445 ifp->if_timer = 0; 446 if_attach(ifp); 447 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 448 #if NBPFILTER > 0 449 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 450 sizeof(struct ether_header)); 451 #endif 452 } 453 454 static void 455 tl_reset(sc) 456 tl_softc_t *sc; 457 { 458 int i; 459 460 /* read stats */ 461 if (sc->tl_if.if_flags & IFF_RUNNING) { 462 untimeout(tl_ticks, sc); 463 tl_read_stats(sc); 464 } 465 /* Reset adapter */ 466 TL_HR_WRITE(sc, TL_HOST_CMD, 467 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 468 DELAY(100000); 469 /* Disable interrupts */ 470 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 471 /* setup aregs & hash */ 472 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 473 tl_intreg_write(sc, i, 0); 474 #ifdef TLDEBUG_ADDR 475 printf("Areg & hash registers: \n"); 476 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 477 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 478 #endif 479 /* Setup NetConfig */ 480 tl_intreg_write(sc, TL_INT_NetConfig, 481 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 482 /* Bsize: accept default */ 483 /* TX commit in Acommit: accept default */ 484 /* Load Ld_tmr and Ld_thr */ 485 /* Ld_tmr = 3 */ 486 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 487 /* Ld_thr = 0 */ 488 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 489 /* Unreset MII */ 490 netsio_set(sc, TL_NETSIO_NMRST); 491 DELAY(100000); 492 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 493 sc->tl_flags = 0; 494 sc->opkt = 0; 495 sc->stats_exesscoll = 0; 496 } 497 498 static void tl_shutdown(v) 499 void *v; 500 { 501 tl_softc_t *sc = v; 502 struct Tx_list *Tx; 503 int i; 504 505 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 506 return; 507 /* disable interrupts */ 508 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 509 /* stop TX and RX channels */ 510 TL_HR_WRITE(sc, TL_HOST_CMD, 511 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 512 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 513 DELAY(100000); 514 515 /* stop statistics reading loop, read stats */ 516 untimeout(tl_ticks, sc); 517 tl_read_stats(sc); 518 519 /* deallocate memory allocations */ 520 for (i=0; i< TL_NBUF; i++) { 521 if (sc->Rx_list[i].m) 522 m_freem(sc->Rx_list[i].m); 523 sc->Rx_list[i].m = NULL; 524 } 525 free(sc->Rx_list, M_DEVBUF); 526 sc->Rx_list = NULL; 527 while ((Tx = sc->active_Tx) != NULL) { 528 Tx->hw_list.stat = 0; 529 m_freem(Tx->m); 530 sc->active_Tx = Tx->next; 531 Tx->next = sc->Free_Tx; 532 sc->Free_Tx = Tx; 533 } 534 sc->last_Tx = NULL; 535 free(sc->Tx_list, M_DEVBUF); 536 sc->Tx_list = NULL; 537 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 538 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 539 sc->tl_flags = 0; 540 } 541 542 static void tl_restart(v) 543 void *v; 544 { 545 tl_init(v); 546 } 547 548 static int tl_init(sc) 549 tl_softc_t *sc; 550 { 551 struct ifnet *ifp = &sc->tl_if; 552 int i, s; 553 554 s = splnet(); 555 /* cancel any pending IO */ 556 tl_shutdown(sc); 557 tl_reset(sc); 558 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 559 splx(s); 560 return 0; 561 } 562 /* Set various register to reasonable value */ 563 /* setup NetCmd in promisc mode if needed */ 564 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 565 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 566 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 567 /* Max receive size : MCLBYTES */ 568 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 569 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 570 (MCLBYTES >> 8) & 0xff); 571 572 /* init MAC addr */ 573 for (i = 0; i < ETHER_ADDR_LEN; i++) 574 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 575 /* add multicast filters */ 576 tl_addr_filter(sc); 577 #ifdef TLDEBUG_ADDR 578 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 579 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 580 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 581 #endif 582 583 /* Pre-allocate receivers mbuf, make the lists */ 584 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 585 M_NOWAIT); 586 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 587 M_NOWAIT); 588 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 589 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 590 sc->tl_if.if_flags &= ~IFF_UP; 591 splx(s); 592 return ENOMEM; 593 } 594 for (i=0; i< TL_NBUF; i++) { 595 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 596 printf("%s: out of mbuf for receive list\n", 597 sc->sc_dev.dv_xname); 598 sc->tl_if.if_flags &= ~IFF_UP; 599 splx(s); 600 return ENOMEM; 601 } 602 if (i > 0) { /* chain the list */ 603 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 604 sc->Rx_list[i-1].hw_list.fwd = 605 vtophys(&sc->Rx_list[i].hw_list); 606 #ifdef DIAGNOSTIC 607 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 608 printf("%s: physical addr 0x%x of list not " 609 "properly aligned\n", 610 sc->sc_dev.dv_xname, 611 sc->Rx_list[i-1].hw_list.fwd); 612 #endif 613 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 614 } 615 } 616 sc->Rx_list[TL_NBUF-1].next = NULL; 617 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 618 sc->Tx_list[TL_NBUF-1].next = NULL; 619 620 sc->active_Rx = &sc->Rx_list[0]; 621 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 622 sc->active_Tx = sc->last_Tx = NULL; 623 sc->Free_Tx = &sc->Tx_list[0]; 624 625 if (nullbuf == NULL) 626 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 627 if (nullbuf == NULL) { 628 printf("%s: can't allocate space for pad buffer\n", 629 sc->sc_dev.dv_xname); 630 sc->tl_if.if_flags &= ~IFF_UP; 631 splx(s); 632 return ENOMEM; 633 } 634 bzero(nullbuf, ETHER_MIN_TX); 635 636 /* set media */ 637 mii_mediachg(&sc->tl_mii); 638 639 /* start ticks calls */ 640 timeout(tl_ticks, sc, hz); 641 /* write adress of Rx list and enable interrupts */ 642 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 643 TL_HR_WRITE(sc, TL_HOST_CMD, 644 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 645 sc->tl_if.if_flags |= IFF_RUNNING; 646 sc->tl_if.if_flags &= ~IFF_OACTIVE; 647 return 0; 648 } 649 650 651 static u_int32_t 652 tl_intreg_read(sc, reg) 653 tl_softc_t *sc; 654 u_int32_t reg; 655 { 656 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 657 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 658 } 659 660 static u_int8_t 661 tl_intreg_read_byte(sc, reg) 662 tl_softc_t *sc; 663 u_int32_t reg; 664 { 665 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 666 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 667 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 668 } 669 670 static void 671 tl_intreg_write(sc, reg, val) 672 tl_softc_t *sc; 673 u_int32_t reg; 674 u_int32_t val; 675 { 676 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 677 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 678 } 679 680 static void 681 tl_intreg_write_byte(sc, reg, val) 682 tl_softc_t *sc; 683 u_int32_t reg; 684 u_int8_t val; 685 { 686 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 687 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 688 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 689 } 690 691 void 692 tl_mii_sync(sc) 693 struct tl_softc *sc; 694 { 695 int i; 696 697 netsio_clr(sc, TL_NETSIO_MTXEN); 698 for (i = 0; i < 32; i++) { 699 netsio_clr(sc, TL_NETSIO_MCLK); 700 netsio_set(sc, TL_NETSIO_MCLK); 701 } 702 } 703 704 void 705 tl_mii_sendbits(sc, data, nbits) 706 struct tl_softc *sc; 707 u_int32_t data; 708 int nbits; 709 { 710 int i; 711 712 netsio_set(sc, TL_NETSIO_MTXEN); 713 for (i = 1 << (nbits - 1); i; i = i >> 1) { 714 netsio_clr(sc, TL_NETSIO_MCLK); 715 netsio_read(sc, TL_NETSIO_MCLK); 716 if (data & i) 717 netsio_set(sc, TL_NETSIO_MDATA); 718 else 719 netsio_clr(sc, TL_NETSIO_MDATA); 720 netsio_set(sc, TL_NETSIO_MCLK); 721 netsio_read(sc, TL_NETSIO_MCLK); 722 } 723 } 724 725 int 726 tl_mii_read(self, phy, reg) 727 struct device *self; 728 int phy, reg; 729 { 730 struct tl_softc *sc = (struct tl_softc *)self; 731 int val = 0, i, err; 732 733 /* 734 * Read the PHY register by manually driving the MII control lines. 735 */ 736 737 tl_mii_sync(sc); 738 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 739 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 740 tl_mii_sendbits(sc, phy, 5); 741 tl_mii_sendbits(sc, reg, 5); 742 743 netsio_clr(sc, TL_NETSIO_MTXEN); 744 netsio_clr(sc, TL_NETSIO_MCLK); 745 netsio_set(sc, TL_NETSIO_MCLK); 746 netsio_clr(sc, TL_NETSIO_MCLK); 747 748 err = netsio_read(sc, TL_NETSIO_MDATA); 749 netsio_set(sc, TL_NETSIO_MCLK); 750 751 /* Even if an error occurs, must still clock out the cycle. */ 752 for (i = 0; i < 16; i++) { 753 val <<= 1; 754 netsio_clr(sc, TL_NETSIO_MCLK); 755 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 756 val |= 1; 757 netsio_set(sc, TL_NETSIO_MCLK); 758 } 759 netsio_clr(sc, TL_NETSIO_MCLK); 760 netsio_set(sc, TL_NETSIO_MCLK); 761 762 return (err ? 0 : val); 763 } 764 765 void 766 tl_mii_write(self, phy, reg, val) 767 struct device *self; 768 int phy, reg, val; 769 { 770 struct tl_softc *sc = (struct tl_softc *)self; 771 772 /* 773 * Write the PHY register by manually driving the MII control lines. 774 */ 775 776 tl_mii_sync(sc); 777 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 778 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 779 tl_mii_sendbits(sc, phy, 5); 780 tl_mii_sendbits(sc, reg, 5); 781 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 782 tl_mii_sendbits(sc, val, 16); 783 784 netsio_clr(sc, TL_NETSIO_MCLK); 785 netsio_set(sc, TL_NETSIO_MCLK); 786 } 787 788 void 789 tl_statchg(self) 790 struct device *self; 791 { 792 tl_softc_t *sc = (struct tl_softc *)self; 793 u_int32_t reg; 794 795 #ifdef TLDEBUG 796 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 797 #endif 798 799 /* 800 * We must keep the ThunderLAN and the PHY in sync as 801 * to the status of full-duplex! 802 */ 803 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 804 if (sc->tl_mii.mii_media_active & IFM_FDX) 805 reg |= TL_NETCOMMAND_DUPLEX; 806 else 807 reg &= ~TL_NETCOMMAND_DUPLEX; 808 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 809 810 /* XXX Update ifp->if_baudrate */ 811 } 812 813 void tl_i2c_set(v, bit) 814 void *v; 815 u_int8_t bit; 816 { 817 tl_softc_t *sc = v; 818 819 switch (bit) { 820 case I2C_DATA: 821 netsio_set(sc, TL_NETSIO_EDATA); 822 break; 823 case I2C_CLOCK: 824 netsio_set(sc, TL_NETSIO_ECLOCK); 825 break; 826 case I2C_TXEN: 827 netsio_set(sc, TL_NETSIO_ETXEN); 828 break; 829 default: 830 printf("tl_i2c_set: unknown bit %d\n", bit); 831 } 832 return; 833 } 834 835 void tl_i2c_clr(v, bit) 836 void *v; 837 u_int8_t bit; 838 { 839 tl_softc_t *sc = v; 840 841 switch (bit) { 842 case I2C_DATA: 843 netsio_clr(sc, TL_NETSIO_EDATA); 844 break; 845 case I2C_CLOCK: 846 netsio_clr(sc, TL_NETSIO_ECLOCK); 847 break; 848 case I2C_TXEN: 849 netsio_clr(sc, TL_NETSIO_ETXEN); 850 break; 851 default: 852 printf("tl_i2c_clr: unknown bit %d\n", bit); 853 } 854 return; 855 } 856 857 int tl_i2c_read(v, bit) 858 void *v; 859 u_int8_t bit; 860 { 861 tl_softc_t *sc = v; 862 863 switch (bit) { 864 case I2C_DATA: 865 return netsio_read(sc, TL_NETSIO_EDATA); 866 break; 867 case I2C_CLOCK: 868 return netsio_read(sc, TL_NETSIO_ECLOCK); 869 break; 870 case I2C_TXEN: 871 return netsio_read(sc, TL_NETSIO_ETXEN); 872 break; 873 default: 874 printf("tl_i2c_read: unknown bit %d\n", bit); 875 return -1; 876 } 877 } 878 879 static int 880 tl_intr(v) 881 void *v; 882 { 883 tl_softc_t *sc = v; 884 struct ifnet *ifp = &sc->tl_if; 885 struct Rx_list *Rx; 886 struct Tx_list *Tx; 887 struct mbuf *m; 888 u_int32_t int_type, int_reg; 889 int ack = 0; 890 int size; 891 892 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 893 int_type = int_reg & TL_INTR_MASK; 894 if (int_type == 0) 895 return 0; 896 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 897 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 898 int_type, int_reg); 899 #endif 900 /* disable interrupts */ 901 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 902 switch(int_type & TL_INTR_MASK) { 903 case TL_INTR_RxEOF: 904 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 905 /* dequeue and requeue at end of list */ 906 ack++; 907 Rx = sc->active_Rx; 908 sc->active_Rx = Rx->next; 909 m = Rx->m; 910 size = Rx->hw_list.stat >> 16; 911 #ifdef TLDEBUG_RX 912 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 913 Rx, size); 914 #endif 915 if (tl_add_RxBuff(Rx, m ) == 0) { 916 /* 917 * No new mbuf, reuse the same. This means 918 * that this packet 919 * is lost 920 */ 921 m = NULL; 922 #ifdef TL_PRIV_STATS 923 sc->ierr_nomem++; 924 #endif 925 #ifdef TLDEBUG 926 printf("%s: out of mbuf, lost input packet\n", 927 sc->sc_dev.dv_xname); 928 #endif 929 } 930 Rx->next = NULL; 931 Rx->hw_list.fwd = 0; 932 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 933 #ifdef DIAGNOSTIC 934 if (sc->last_Rx->hw_list.fwd & 0x7) 935 printf("%s: physical addr 0x%x of list not " 936 "properly aligned\n", 937 sc->sc_dev.dv_xname, 938 sc->last_Rx->hw_list.fwd); 939 #endif 940 sc->last_Rx->next = Rx; 941 sc->last_Rx = Rx; 942 943 /* deliver packet */ 944 if (m) { 945 struct ether_header *eh; 946 if (size < sizeof(struct ether_header)) { 947 m_freem(m); 948 continue; 949 } 950 m->m_pkthdr.rcvif = ifp; 951 m->m_pkthdr.len = m->m_len = size; 952 eh = mtod(m, struct ether_header *); 953 #ifdef TLDEBUG_RX 954 printf("tl_intr: Rx packet:\n"); 955 ether_printheader(eh); 956 #endif 957 #if NBPFILTER > 0 958 if (ifp->if_bpf) { 959 bpf_tap(ifp->if_bpf, 960 mtod(m, caddr_t), size); 961 /* 962 * Only pass this packet up 963 * if it is for us. 964 */ 965 if ((ifp->if_flags & IFF_PROMISC) && 966 /* !mcast and !bcast */ 967 (eh->ether_dhost[0] & 1) == 0 && 968 bcmp(eh->ether_dhost, 969 LLADDR(ifp->if_sadl), 970 sizeof(eh->ether_dhost)) != 0) { 971 m_freem(m); 972 continue; 973 } 974 } 975 #endif /* NBPFILTER > 0 */ 976 (*ifp->if_input)(ifp, m); 977 } 978 } 979 #ifdef TLDEBUG_RX 980 printf("TL_INTR_RxEOF: ack %d\n", ack); 981 #else 982 if (ack == 0) { 983 printf("%s: EOF intr without anything to read !\n", 984 sc->sc_dev.dv_xname); 985 tl_reset(sc); 986 /* shedule reinit of the board */ 987 timeout(tl_restart, sc, 1); 988 return(1); 989 } 990 #endif 991 break; 992 case TL_INTR_RxEOC: 993 ack++; 994 #ifdef TLDEBUG_RX 995 printf("TL_INTR_RxEOC: ack %d\n", ack); 996 #endif 997 #ifdef DIAGNOSTIC 998 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 999 printf("%s: Rx EOC interrupt and active Rx list not " 1000 "cleared\n", sc->sc_dev.dv_xname); 1001 return 0; 1002 } else 1003 #endif 1004 { 1005 /* 1006 * write adress of Rx list and send Rx GO command, ack 1007 * interrupt and enable interrupts in one command 1008 */ 1009 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1010 vtophys(&sc->active_Rx->hw_list)); 1011 TL_HR_WRITE(sc, TL_HOST_CMD, 1012 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1013 HOST_CMD_ACK | HOST_CMD_IntOn); 1014 return 1; 1015 } 1016 case TL_INTR_TxEOF: 1017 case TL_INTR_TxEOC: 1018 while ((Tx = sc->active_Tx) != NULL) { 1019 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 1020 break; 1021 ack++; 1022 #ifdef TLDEBUG_TX 1023 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1024 vtophys(&Tx->hw_list)); 1025 #endif 1026 Tx->hw_list.stat = 0; 1027 m_freem(Tx->m); 1028 Tx->m = NULL; 1029 sc->active_Tx = Tx->next; 1030 if (sc->active_Tx == NULL) 1031 sc->last_Tx = NULL; 1032 Tx->next = sc->Free_Tx; 1033 sc->Free_Tx = Tx; 1034 } 1035 /* if this was an EOC, ACK immediatly */ 1036 if (int_type == TL_INTR_TxEOC) { 1037 #ifdef TLDEBUG_TX 1038 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1039 ack); 1040 #endif 1041 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1042 HOST_CMD_ACK | HOST_CMD_IntOn); 1043 if ( sc->active_Tx != NULL) { 1044 /* needs a Tx go command */ 1045 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1046 vtophys(&sc->active_Tx->hw_list)); 1047 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1048 } 1049 sc->tl_if.if_timer = 0; 1050 if (sc->tl_if.if_snd.ifq_head != NULL) 1051 tl_ifstart(&sc->tl_if); 1052 return 1; 1053 } 1054 #ifdef TLDEBUG 1055 else { 1056 printf("TL_INTR_TxEOF: ack %d\n", ack); 1057 } 1058 #endif 1059 sc->tl_if.if_timer = 0; 1060 if (sc->tl_if.if_snd.ifq_head != NULL) 1061 tl_ifstart(&sc->tl_if); 1062 break; 1063 case TL_INTR_Stat: 1064 ack++; 1065 #ifdef TLDEBUG 1066 printf("TL_INTR_Stat: ack %d\n", ack); 1067 #endif 1068 tl_read_stats(sc); 1069 break; 1070 case TL_INTR_Adc: 1071 if (int_reg & TL_INTVec_MASK) { 1072 /* adapter check conditions */ 1073 printf("%s: check condition, intvect=0x%x, " 1074 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1075 int_reg & TL_INTVec_MASK, 1076 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1077 tl_reset(sc); 1078 /* shedule reinit of the board */ 1079 timeout(tl_restart, sc, 1); 1080 return(1); 1081 } else { 1082 u_int8_t netstat; 1083 /* Network status */ 1084 netstat = 1085 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1086 printf("%s: network status, NetSts=%x\n", 1087 sc->sc_dev.dv_xname, netstat); 1088 /* Ack interrupts */ 1089 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1090 netstat); 1091 ack++; 1092 } 1093 break; 1094 default: 1095 printf("%s: unhandled interrupt code %x!\n", 1096 sc->sc_dev.dv_xname, int_type); 1097 ack++; 1098 } 1099 1100 if (ack) { 1101 /* Ack the interrupt and enable interrupts */ 1102 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1103 HOST_CMD_IntOn); 1104 return 1; 1105 } 1106 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1107 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1108 return 0; 1109 } 1110 1111 static int 1112 tl_ifioctl(ifp, cmd, data) 1113 struct ifnet *ifp; 1114 ioctl_cmd_t cmd; 1115 caddr_t data; 1116 { 1117 struct tl_softc *sc = ifp->if_softc; 1118 struct ifreq *ifr = (struct ifreq *)data; 1119 int s, error; 1120 1121 s = splnet(); 1122 switch(cmd) { 1123 case SIOCSIFADDR: { 1124 struct ifaddr *ifa = (struct ifaddr *)data; 1125 sc->tl_if.if_flags |= IFF_UP; 1126 if ((error = tl_init(sc)) != NULL) { 1127 sc->tl_if.if_flags &= ~IFF_UP; 1128 break; 1129 } 1130 switch (ifa->ifa_addr->sa_family) { 1131 #ifdef INET 1132 case AF_INET: 1133 arp_ifinit(ifp, ifa); 1134 break; 1135 #endif 1136 #ifdef NS 1137 case AF_NS: { 1138 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1139 1140 if (ns_nullhost(*ina)) 1141 ina->x_host = 1142 *(union ns_host*) LLADDR(ifp->if_sadl); 1143 else 1144 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1145 ifp->if_addrlen); 1146 break; 1147 } 1148 #endif 1149 default: 1150 break; 1151 } 1152 break; 1153 } 1154 case SIOCSIFFLAGS: 1155 { 1156 u_int8_t reg; 1157 /* 1158 * If interface is marked up and not running, then start it. 1159 * If it is marked down and running, stop it. 1160 */ 1161 if (ifp->if_flags & IFF_UP) { 1162 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1163 error = tl_init(sc); 1164 /* all flags have been handled by init */ 1165 break; 1166 } 1167 error = 0; 1168 reg = tl_intreg_read_byte(sc, 1169 TL_INT_NET + TL_INT_NetCmd); 1170 if (ifp->if_flags & IFF_PROMISC) 1171 reg |= TL_NETCOMMAND_CAF; 1172 else 1173 reg &= ~TL_NETCOMMAND_CAF; 1174 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1175 reg); 1176 #ifdef TL_PRIV_STATS 1177 if (ifp->if_flags & IFF_LINK0) { 1178 ifp->if_flags &= ~IFF_LINK0; 1179 printf("%s errors statistics\n", 1180 sc->sc_dev.dv_xname); 1181 printf(" %4d RX buffer overrun\n", 1182 sc->ierr_overr); 1183 printf(" %4d RX code error\n", 1184 sc->ierr_code); 1185 printf(" %4d RX crc error\n", 1186 sc->ierr_crc); 1187 printf(" %4d RX out of memory\n", 1188 sc->ierr_nomem); 1189 printf(" %4d TX buffer underrun\n", 1190 sc->oerr_underr); 1191 printf(" %4d TX deffered frames\n", 1192 sc->oerr_deffered); 1193 printf(" %4d TX single collisions\n", 1194 sc->oerr_coll); 1195 printf(" %4d TX multi collisions\n", 1196 sc->oerr_multicoll); 1197 printf(" %4d TX exessive collisions\n", 1198 sc->oerr_exesscoll); 1199 printf(" %4d TX late collisions\n", 1200 sc->oerr_latecoll); 1201 printf(" %4d TX carrier loss\n", 1202 sc->oerr_carrloss); 1203 printf(" %4d TX mbuf copy\n", 1204 sc->oerr_mcopy); 1205 } 1206 #endif 1207 } else { 1208 if (ifp->if_flags & IFF_RUNNING) 1209 tl_shutdown(sc); 1210 error = 0; 1211 } 1212 break; 1213 } 1214 case SIOCADDMULTI: 1215 case SIOCDELMULTI: 1216 /* 1217 * Update multicast listeners 1218 */ 1219 if (cmd == SIOCADDMULTI) 1220 error = ether_addmulti(ifr, &sc->tl_ec); 1221 else 1222 error = ether_delmulti(ifr, &sc->tl_ec); 1223 if (error == ENETRESET) { 1224 tl_addr_filter(sc); 1225 error = 0; 1226 } 1227 break; 1228 case SIOCSIFMEDIA: 1229 case SIOCGIFMEDIA: 1230 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1231 break; 1232 default: 1233 error = EINVAL; 1234 } 1235 splx(s); 1236 return error; 1237 } 1238 1239 static void 1240 tl_ifstart(ifp) 1241 struct ifnet *ifp; 1242 { 1243 tl_softc_t *sc = ifp->if_softc; 1244 struct mbuf *m, *mb_head; 1245 struct Tx_list *Tx; 1246 int segment, size; 1247 1248 txloop: 1249 /* If we don't have more space ... */ 1250 if (sc->Free_Tx == NULL) { 1251 #ifdef TLDEBUG 1252 printf("tl_ifstart: No free TX list\n"); 1253 #endif 1254 return; 1255 } 1256 /* Grab a paquet for output */ 1257 IF_DEQUEUE(&ifp->if_snd, mb_head); 1258 if (mb_head == NULL) { 1259 #ifdef TLDEBUG_TX 1260 printf("tl_ifstart: nothing to send\n"); 1261 #endif 1262 return; 1263 } 1264 Tx = sc->Free_Tx; 1265 sc->Free_Tx = Tx->next; 1266 /* 1267 * Go through each of the mbufs in the chain and initialize 1268 * the transmit list descriptors with the physical address 1269 * and size of the mbuf. 1270 */ 1271 tbdinit: 1272 bzero(Tx, sizeof(struct Tx_list)); 1273 Tx->m = mb_head; 1274 size = 0; 1275 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1276 if (m->m_len != 0) { 1277 if (segment == TL_NSEG) 1278 break; 1279 size += m->m_len; 1280 Tx->hw_list.seg[segment].data_addr = 1281 vtophys(mtod(m, vaddr_t)); 1282 Tx->hw_list.seg[segment].data_count = m->m_len; 1283 segment++; 1284 } 1285 } 1286 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1287 /* 1288 * We ran out of segments, or we will. We have to recopy this 1289 * mbuf chain first. 1290 */ 1291 struct mbuf *mn; 1292 #ifdef TLDEBUG_TX 1293 printf("tl_ifstart: need to copy mbuf\n"); 1294 #endif 1295 #ifdef TL_PRIV_STATS 1296 sc->oerr_mcopy++; 1297 #endif 1298 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1299 if (mn == NULL) { 1300 m_freem(mb_head); 1301 goto bad; 1302 } 1303 if (mb_head->m_pkthdr.len > MHLEN) { 1304 MCLGET(mn, M_DONTWAIT); 1305 if ((mn->m_flags & M_EXT) == 0) { 1306 m_freem(mn); 1307 m_freem(mb_head); 1308 goto bad; 1309 } 1310 } 1311 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1312 mtod(mn, caddr_t)); 1313 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1314 m_freem(mb_head); 1315 mb_head = mn; 1316 goto tbdinit; 1317 } 1318 /* We are at end of mbuf chain. check the size and 1319 * see if it needs to be extended 1320 */ 1321 if (size < ETHER_MIN_TX) { 1322 #ifdef DIAGNOSTIC 1323 if (segment >= TL_NSEG) { 1324 panic("tl_ifstart: to much segmets (%d)\n", segment); 1325 } 1326 #endif 1327 /* 1328 * add the nullbuf in the seg 1329 */ 1330 Tx->hw_list.seg[segment].data_count = 1331 ETHER_MIN_TX - size; 1332 Tx->hw_list.seg[segment].data_addr = 1333 vtophys(nullbuf); 1334 size = ETHER_MIN_TX; 1335 segment++; 1336 } 1337 /* The list is done, finish the list init */ 1338 Tx->hw_list.seg[segment-1].data_count |= 1339 TL_LAST_SEG; 1340 Tx->hw_list.stat = (size << 16) | 0x3000; 1341 #ifdef TLDEBUG_TX 1342 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1343 Tx->hw_list.stat); 1344 #if 0 1345 for(segment = 0; segment < TL_NSEG; segment++) { 1346 printf(" seg %d addr 0x%x len 0x%x\n", 1347 segment, 1348 Tx->hw_list.seg[segment].data_addr, 1349 Tx->hw_list.seg[segment].data_count); 1350 } 1351 #endif 1352 #endif 1353 sc->opkt++; 1354 if (sc->active_Tx == NULL) { 1355 sc->active_Tx = sc->last_Tx = Tx; 1356 #ifdef TLDEBUG_TX 1357 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1358 vtophys(&Tx->hw_list)); 1359 #endif 1360 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1361 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1362 } else { 1363 #ifdef TLDEBUG_TX 1364 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1365 vtophys(&Tx->hw_list)); 1366 #endif 1367 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1368 sc->last_Tx->next = Tx; 1369 sc->last_Tx = Tx; 1370 #ifdef DIAGNOSTIC 1371 if (sc->last_Tx->hw_list.fwd & 0x7) 1372 printf("%s: physical addr 0x%x of list not properly " 1373 "aligned\n", 1374 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1375 #endif 1376 } 1377 #if NBPFILTER > 0 1378 /* Pass packet to bpf if there is a listener */ 1379 if (ifp->if_bpf) 1380 bpf_mtap(ifp->if_bpf, mb_head); 1381 #endif 1382 /* 1383 * Set a 5 second timer just in case we don't hear from the card again. 1384 */ 1385 ifp->if_timer = 5; 1386 goto txloop; 1387 bad: 1388 #ifdef TLDEBUG 1389 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1390 #endif 1391 Tx->next = sc->Free_Tx; 1392 sc->Free_Tx = Tx; 1393 return; 1394 } 1395 1396 static void 1397 tl_ifwatchdog(ifp) 1398 struct ifnet *ifp; 1399 { 1400 tl_softc_t *sc = ifp->if_softc; 1401 1402 if ((ifp->if_flags & IFF_RUNNING) == 0) 1403 return; 1404 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1405 ifp->if_oerrors++; 1406 tl_init(sc); 1407 } 1408 1409 static int 1410 tl_mediachange(ifp) 1411 struct ifnet *ifp; 1412 { 1413 1414 if (ifp->if_flags & IFF_UP) 1415 tl_init(ifp->if_softc); 1416 return (0); 1417 } 1418 1419 static void 1420 tl_mediastatus(ifp, ifmr) 1421 struct ifnet *ifp; 1422 struct ifmediareq *ifmr; 1423 { 1424 tl_softc_t *sc = ifp->if_softc; 1425 1426 mii_pollstat(&sc->tl_mii); 1427 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1428 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1429 } 1430 1431 static int tl_add_RxBuff(Rx, oldm) 1432 struct Rx_list *Rx; 1433 struct mbuf *oldm; 1434 { 1435 struct mbuf *m; 1436 1437 MGETHDR(m, M_DONTWAIT, MT_DATA); 1438 if (m != NULL) { 1439 MCLGET(m, M_DONTWAIT); 1440 if ((m->m_flags & M_EXT) == 0) { 1441 m_freem(m); 1442 if (oldm == NULL) 1443 return 0; 1444 m = oldm; 1445 m->m_data = m->m_ext.ext_buf; 1446 } 1447 } else { 1448 if (oldm == NULL) 1449 return 0; 1450 m = oldm; 1451 m->m_data = m->m_ext.ext_buf; 1452 } 1453 /* 1454 * Move the data pointer up so that the incoming data packet 1455 * will be 32-bit aligned. 1456 */ 1457 m->m_data += 2; 1458 1459 /* (re)init the Rx_list struct */ 1460 1461 Rx->m = m; 1462 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1463 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1464 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1465 return (m != oldm); 1466 } 1467 1468 static void tl_ticks(v) 1469 void *v; 1470 { 1471 tl_softc_t *sc = v; 1472 1473 tl_read_stats(sc); 1474 1475 /* Tick the MII. */ 1476 mii_tick(&sc->tl_mii); 1477 1478 if (sc->opkt > 0) { 1479 if (sc->oerr_exesscoll > sc->opkt / 100) { 1480 /* exess collisions */ 1481 if (sc->tl_flags & TL_IFACT) /* only print once */ 1482 printf("%s: no carrier\n", 1483 sc->sc_dev.dv_xname); 1484 sc->tl_flags &= ~TL_IFACT; 1485 } else 1486 sc->tl_flags |= TL_IFACT; 1487 sc->oerr_exesscoll = sc->opkt = 0; 1488 sc->tl_lasttx = 0; 1489 } else { 1490 sc->tl_lasttx++; 1491 if (sc->tl_lasttx >= TL_IDLETIME) { 1492 /* 1493 * No TX activity in the last TL_IDLETIME seconds. 1494 * sends a LLC Class1 TEST pkt 1495 */ 1496 struct mbuf *m; 1497 int s; 1498 MGETHDR(m, M_DONTWAIT, MT_DATA); 1499 if (m != NULL) { 1500 #ifdef TLDEBUG 1501 printf("tl_ticks: sending LLC test pkt\n"); 1502 #endif 1503 bcopy(sc->tl_enaddr, 1504 mtod(m, struct ether_header *)->ether_dhost, 1505 6); 1506 bcopy(sc->tl_enaddr, 1507 mtod(m, struct ether_header *)->ether_shost, 1508 6); 1509 mtod(m, struct ether_header *)->ether_type = 1510 htons(3); 1511 mtod(m, unsigned char *)[14] = 0; 1512 mtod(m, unsigned char *)[15] = 0; 1513 mtod(m, unsigned char *)[16] = 0xE3; 1514 /* LLC Class1 TEST (no poll) */ 1515 m->m_len = m->m_pkthdr.len = 1516 sizeof(struct ether_header) + 3; 1517 s = splnet(); 1518 IF_PREPEND(&sc->tl_if.if_snd, m); 1519 tl_ifstart(&sc->tl_if); 1520 splx(s); 1521 } 1522 } 1523 } 1524 1525 /* read statistics every seconds */ 1526 timeout(tl_ticks, v, hz); 1527 } 1528 1529 static void 1530 tl_read_stats(sc) 1531 tl_softc_t *sc; 1532 { 1533 u_int32_t reg; 1534 int ierr_overr; 1535 int ierr_code; 1536 int ierr_crc; 1537 int oerr_underr; 1538 int oerr_deffered; 1539 int oerr_coll; 1540 int oerr_multicoll; 1541 int oerr_exesscoll; 1542 int oerr_latecoll; 1543 int oerr_carrloss; 1544 struct ifnet *ifp = &sc->tl_if; 1545 1546 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1547 ifp->if_opackets += reg & 0x00ffffff; 1548 oerr_underr = reg >> 24; 1549 1550 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1551 ifp->if_ipackets += reg & 0x00ffffff; 1552 ierr_overr = reg >> 24; 1553 1554 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1555 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1556 ierr_code = (reg & TL_FERR_CODE) >> 24; 1557 oerr_deffered = (reg & TL_FERR_DEF); 1558 1559 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1560 oerr_multicoll = (reg & TL_COL_MULTI); 1561 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1562 1563 reg = tl_intreg_read(sc, TL_INT_LERR); 1564 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1565 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1566 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1567 1568 1569 sc->stats_exesscoll += oerr_exesscoll; 1570 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1571 oerr_carrloss; 1572 ifp->if_collisions += oerr_coll + oerr_multicoll; 1573 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1574 1575 if (ierr_overr) 1576 printf("%s: receiver ring buffer overrun\n", 1577 sc->sc_dev.dv_xname); 1578 if (oerr_underr) 1579 printf("%s: transmit buffer underrun\n", 1580 sc->sc_dev.dv_xname); 1581 #ifdef TL_PRIV_STATS 1582 sc->ierr_overr += ierr_overr; 1583 sc->ierr_code += ierr_code; 1584 sc->ierr_crc += ierr_crc; 1585 sc->oerr_underr += oerr_underr; 1586 sc->oerr_deffered += oerr_deffered; 1587 sc->oerr_coll += oerr_coll; 1588 sc->oerr_multicoll += oerr_multicoll; 1589 sc->oerr_exesscoll += oerr_exesscoll; 1590 sc->oerr_latecoll += oerr_latecoll; 1591 sc->oerr_carrloss += oerr_carrloss; 1592 #endif 1593 } 1594 1595 static void tl_addr_filter(sc) 1596 tl_softc_t *sc; 1597 { 1598 struct ether_multistep step; 1599 struct ether_multi *enm; 1600 u_int32_t hash[2] = {0, 0}; 1601 int i; 1602 1603 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1604 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1605 while (enm != NULL) { 1606 #ifdef TLDEBUG 1607 printf("tl_addr_filter: addrs %s %s\n", 1608 ether_sprintf(enm->enm_addrlo), 1609 ether_sprintf(enm->enm_addrhi)); 1610 #endif 1611 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1612 i = tl_multicast_hash(enm->enm_addrlo); 1613 hash[i/32] |= 1 << (i%32); 1614 } else { 1615 hash[0] = hash[1] = 0xffffffff; 1616 sc->tl_if.if_flags |= IFF_ALLMULTI; 1617 break; 1618 } 1619 ETHER_NEXT_MULTI(step, enm); 1620 } 1621 #ifdef TLDEBUG 1622 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1623 #endif 1624 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1625 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1626 } 1627 1628 static int tl_multicast_hash(a) 1629 u_int8_t *a; 1630 { 1631 int hash; 1632 1633 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1634 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1635 1636 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1637 DA(a,36), DA(a,42)); 1638 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1639 DA(a,37), DA(a,43)) << 1; 1640 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1641 DA(a,38), DA(a,44)) << 2; 1642 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1643 DA(a,39), DA(a,45)) << 3; 1644 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1645 DA(a,40), DA(a,46)) << 4; 1646 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1647 DA(a,41), DA(a,47)) << 5; 1648 1649 return hash; 1650 } 1651 1652 #if defined(TLDEBUG_RX) 1653 void 1654 ether_printheader(eh) 1655 struct ether_header *eh; 1656 { 1657 u_char *c = (char*)eh; 1658 int i; 1659 for (i=0; i<sizeof(struct ether_header); i++) 1660 printf("%x ", (u_int)c[i]); 1661 printf("\n"); 1662 } 1663 #endif 1664
Indexes created Fri Sep 26 08:10:20 GMT 2025