if_tl.c revision 1.4
1 /* $NetBSD: if_tl.c,v 1.4 1997/11/17 01:58:29 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include "bpfilter.h" 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <vm/vm.h> 84 #include <vm/vm_param.h> 85 #include <vm/vm_kern.h> 86 87 #if defined(__NetBSD__) 88 #include <net/if_ether.h> 89 #if defined(INET) 90 #include <netinet/if_inarp.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 #include <dev/i2c/i2c_bus.h> 100 #include <dev/i2c/i2c_eeprom.h> 101 #include <dev/mii/mii_adapter.h> 102 #include <dev/mii/mii_adapters_id.h> 103 #include <dev/pci/if_tlregs.h> 104 #endif /* __NetBSD__ */ 105 106 /* number of transmit/receive buffers */ 107 #ifndef TL_NBUF 108 #define TL_NBUF 10 109 #endif 110 111 /* number of seconds the link can be idle */ 112 #ifndef TL_IDLETIME 113 #define TL_IDLETIME 10 114 #endif 115 116 struct tl_softc { 117 struct device sc_dev; /* base device */ 118 bus_space_tag_t tl_bustag; 119 bus_space_handle_t tl_bushandle; /* CSR region handle */ 120 void* tl_ih; 121 struct ethercom tl_ec; 122 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 123 struct ifmedia tl_ifmedia; 124 u_int16_t tl_flags; 125 #define TL_IFACT 0x0001 /* chip has interface activity */ 126 u_int8_t tl_lasttx; /* we were without input this many seconds */ 127 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 128 mii_data_t mii; /* mii bus */ 129 struct Rx_list *Rx_list; /* Receive and transmit lists */ 130 struct Tx_list *Tx_list; 131 struct Rx_list *active_Rx, *last_Rx; 132 struct Tx_list *active_Tx, *last_Tx; 133 struct Tx_list *Free_Tx; 134 int opkt; /* used to detect link up/down for AUI/BNC */ 135 int stats_exesscoll; /* idem */ 136 #ifdef TL_PRIV_STATS 137 int ierr_overr; 138 int ierr_code; 139 int ierr_crc; 140 int ierr_nomem; 141 int oerr_underr; 142 int oerr_deffered; 143 int oerr_coll; 144 int oerr_multicoll; 145 int oerr_latecoll; 146 int oerr_exesscoll; 147 int oerr_carrloss; 148 int oerr_mcopy; 149 #endif 150 }; 151 #define tl_if tl_ec.ec_if 152 #define tl_bpf tl_if.if_bpf 153 154 typedef struct tl_softc tl_softc_t; 155 typedef u_long ioctl_cmd_t; 156 157 #define TL_HR_READ(sc, reg) \ 158 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 159 #define TL_HR_READ_BYTE(sc, reg) \ 160 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 161 #define TL_HR_WRITE(sc, reg, data) \ 162 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 163 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 164 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 165 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 166 167 static int tl_pci_match __P((struct device *, void *, void *)); 168 static void tl_pci_attach __P((struct device *, struct device *, void *)); 169 static int tl_intr __P((void *)); 170 171 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 172 static int tl_mediachange __P((struct ifnet *)); 173 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 174 static void tl_ifwatchdog __P((struct ifnet *)); 175 static void tl_shutdown __P((void*)); 176 177 static void tl_ifstart __P((struct ifnet *)); 178 static void tl_reset __P((tl_softc_t*)); 179 static int tl_init __P((tl_softc_t*)); 180 static void tl_restart __P((void *)); 181 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 182 static void tl_read_stats __P((tl_softc_t*)); 183 static void tl_ticks __P((void*)); 184 static int tl_multicast_hash __P((u_int8_t*)); 185 static void tl_addr_filter __P((tl_softc_t*)); 186 187 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 188 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 189 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 190 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 191 192 193 #if defined(TLDEBUG_RX) 194 static void ether_printheader __P((struct ether_header*)); 195 #endif 196 197 void tl_mii_set __P((void*, u_int8_t)); 198 void tl_mii_clr __P((void*, u_int8_t)); 199 int tl_mii_read __P((void*, u_int8_t)); 200 201 void tl_i2c_set __P((void*, u_int8_t)); 202 void tl_i2c_clr __P((void*, u_int8_t)); 203 int tl_i2c_read __P((void*, u_int8_t)); 204 205 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 206 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 207 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 208 static __inline void netsio_clr(sc, bits) 209 tl_softc_t* sc; 210 u_int8_t bits; 211 { 212 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 213 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 214 } 215 static __inline void netsio_set(sc, bits) 216 tl_softc_t* sc; 217 u_int8_t bits; 218 { 219 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 220 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 221 } 222 static __inline u_int8_t netsio_read(sc, bits) 223 tl_softc_t* sc; 224 u_int8_t bits; 225 { 226 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 227 } 228 229 struct cfattach tl_ca = { 230 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 231 }; 232 233 struct cfdriver tl_cd = { 234 0, "tl", DV_IFNET 235 }; 236 237 struct tl_product_desc { 238 u_int32_t tp_product; 239 u_int32_t tp_adapter; 240 const char *tp_desc; 241 }; 242 243 const struct tl_product_desc tl_compaq_products[] = { 244 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 245 "Compaq Netelligent 10/100 TX" }, 246 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 247 "Compaq Netelligent 10 T" }, 248 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 249 "Compaq Integrated NetFlex 3/P" }, 250 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 251 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 252 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 253 "Compaq Dual Port Netelligent 10/100 TX" }, 254 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 255 "Compaq Deskpro 4000 5233MMX" }, 256 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 257 "Compaq NetFlex 3/P w/ BNC" }, 258 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 259 "Compaq NetFlex 3/P" }, 260 { 0, 0, NULL }, 261 }; 262 263 const struct tl_product_desc tl_ti_products[] = { 264 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 265 "Texas Instruments ThunderLAN" }, 266 { 0, 0, NULL }, 267 }; 268 269 struct tl_vendor_desc { 270 u_int32_t tv_vendor; 271 const struct tl_product_desc *tv_products; 272 }; 273 274 const struct tl_vendor_desc tl_vendors[] = { 275 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 276 { PCI_VENDOR_TI, tl_ti_products }, 277 { 0, NULL }, 278 }; 279 280 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 281 282 const struct tl_product_desc * 283 tl_lookup_product(id) 284 u_int32_t id; 285 { 286 const struct tl_product_desc *tp; 287 const struct tl_vendor_desc *tv; 288 289 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 290 if (PCI_VENDOR(id) == tv->tv_vendor) 291 break; 292 293 if ((tp = tv->tv_products) == NULL) 294 return (NULL); 295 296 for (; tp->tp_desc != NULL; tp++) 297 if (PCI_PRODUCT(id) == tp->tp_product) 298 break; 299 300 if (tp->tp_desc == NULL) 301 return (NULL); 302 303 return (tp); 304 } 305 306 static char *nullbuf; 307 308 static int 309 tl_pci_match(parent, match, aux) 310 struct device *parent; 311 void *match; 312 void *aux; 313 { 314 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 315 316 if (tl_lookup_product(pa->pa_id) != NULL) 317 return (1); 318 319 return (0); 320 } 321 322 static void 323 tl_pci_attach(parent, self, aux) 324 struct device * parent; 325 struct device * self; 326 void * aux; 327 { 328 tl_softc_t *sc = (tl_softc_t *)self; 329 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 330 const struct tl_product_desc *tp; 331 struct ifnet * const ifp = &sc->tl_if; 332 bus_space_tag_t iot, memt; 333 bus_space_handle_t ioh, memh; 334 pci_intr_handle_t intrhandle; 335 const char *intrstr; 336 int i, tmp, ioh_valid, memh_valid; 337 pcireg_t csr; 338 339 printf("\n"); 340 341 /* Map the card space. */ 342 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 343 &iot, &ioh, NULL, NULL) == 0); 344 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 345 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 346 0, &memt, &memh, NULL, NULL) == 0); 347 348 if (memh_valid) { 349 sc->tl_bustag = memt; 350 sc->tl_bushandle = memh; 351 } else if (ioh_valid) { 352 sc->tl_bustag = iot; 353 sc->tl_bushandle = ioh; 354 } else { 355 printf("%s: unable to map device registers\n", 356 sc->sc_dev.dv_xname); 357 return; 358 } 359 360 /* Enable the device. */ 361 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 362 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 363 csr | PCI_COMMAND_MASTER_ENABLE); 364 365 tp = tl_lookup_product(pa->pa_id); 366 if (tp == NULL) 367 panic("tl_pci_attach: impossible"); 368 369 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 370 sc->mii.adapter_id = tp->tp_adapter; 371 372 tl_reset(sc); 373 374 /* fill in the i2c struct */ 375 sc->i2cbus.adapter_softc = sc; 376 sc->i2cbus.set_bit = tl_i2c_set; 377 sc->i2cbus.clr_bit = tl_i2c_clr; 378 sc->i2cbus.read_bit = tl_i2c_read; 379 380 #ifdef TLDEBUG 381 printf("default values of INTreg: 0x%x\n", 382 tl_intreg_read(sc, TL_INT_Defaults)); 383 #endif 384 385 /* read mac addr */ 386 for (i=0; i<ETHER_ADDR_LEN; i++) { 387 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 388 if (tmp < 0) { 389 printf("%s: error reading Ethernet adress\n", 390 sc->sc_dev.dv_xname); 391 return; 392 } else { 393 sc->tl_enaddr[i] = tmp; 394 } 395 } 396 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 397 ether_sprintf(sc->tl_enaddr)); 398 399 /* Map and establish interrupts */ 400 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 401 pa->pa_intrline, &intrhandle)) { 402 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 403 return; 404 } 405 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 406 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 407 tl_intr, sc); 408 if (sc->tl_ih == NULL) { 409 printf("%s: couldn't establish interrupt", 410 sc->sc_dev.dv_xname); 411 if (intrstr != NULL) 412 printf(" at %s", intrstr); 413 printf("\n"); 414 return; 415 } 416 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 417 418 /* 419 * Add shutdown hook so that DMA is disabled prior to reboot. Not 420 * doing do could allow DMA to corrupt kernel memory during the 421 * reboot before the driver initializes. 422 */ 423 (void) shutdownhook_establish(tl_shutdown, sc); 424 425 sc->mii.adapter_softc = sc; 426 sc->mii.mii_setbit = tl_mii_set; 427 sc->mii.mii_clrbit = tl_mii_clr; 428 sc->mii.mii_readbit = tl_mii_read; 429 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 430 sc->mii.mii_writereg = NULL; 431 if (config_found(self, (void*)&sc->mii, NULL) == NULL) { 432 printf("%s: no mii configured\n", sc->sc_dev.dv_xname); 433 return; 434 } 435 436 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 437 mii_media_add(&sc->tl_ifmedia, &sc->mii); 438 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 439 440 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 441 sc->tl_if.if_softc = sc; 442 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 443 ifp->if_ioctl = tl_ifioctl; 444 ifp->if_start = tl_ifstart; 445 ifp->if_watchdog = tl_ifwatchdog; 446 ifp->if_timer = 0; 447 if_attach(ifp); 448 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 449 #if NBPFILTER > 0 450 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 451 sizeof(struct ether_header)); 452 #endif 453 sc->mii.mii_media_active = IFM_NONE; 454 } 455 456 static void 457 tl_reset(sc) 458 tl_softc_t *sc; 459 { 460 int i; 461 462 /* read stats */ 463 if (sc->tl_if.if_flags & IFF_RUNNING) { 464 untimeout(tl_ticks, sc); 465 tl_read_stats(sc); 466 } 467 /* Reset adapter */ 468 TL_HR_WRITE(sc, TL_HOST_CMD, 469 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 470 DELAY(100000); 471 /* Disable interrupts */ 472 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 473 /* setup aregs & hash */ 474 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 475 tl_intreg_write(sc, i, 0); 476 #ifdef TLDEBUG_ADDR 477 printf("Areg & hash registers: \n"); 478 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 479 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 480 #endif 481 /* Setup NetConfig */ 482 tl_intreg_write(sc, TL_INT_NetConfig, 483 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 484 /* Bsize: accept default */ 485 /* TX commit in Acommit: accept default */ 486 /* Load Ld_tmr and Ld_thr */ 487 /* Ld_tmr = 3 */ 488 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 489 /* Ld_thr = 0 */ 490 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 491 /* Unreset MII */ 492 netsio_set(sc, TL_NETSIO_NMRST); 493 DELAY(100000); 494 sc->mii.mii_media_status &= ~IFM_ACTIVE; 495 sc->tl_flags = 0; 496 sc->opkt = 0; 497 sc->stats_exesscoll = 0; 498 } 499 500 static void tl_shutdown(v) 501 void *v; 502 { 503 tl_softc_t *sc = v; 504 struct Tx_list *Tx; 505 int i; 506 507 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 508 return; 509 /* disable interrupts */ 510 TL_HR_WRITE(sc, TL_HOST_CMD, 511 HOST_CMD_IntOff); 512 /* stop TX and RX channels */ 513 TL_HR_WRITE(sc, TL_HOST_CMD, 514 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 515 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 516 DELAY(100000); 517 518 /* stop statistics reading loop, read stats */ 519 untimeout(tl_ticks, sc); 520 tl_read_stats(sc); 521 522 /* deallocate memory allocations */ 523 for (i=0; i< TL_NBUF; i++) { 524 if (sc->Rx_list[i].m) 525 m_freem(sc->Rx_list[i].m); 526 sc->Rx_list[i].m = NULL; 527 } 528 free(sc->Rx_list, M_DEVBUF); 529 sc->Rx_list = NULL; 530 while ((Tx = sc->active_Tx) != NULL) { 531 Tx->hw_list.stat = 0; 532 m_freem(Tx->m); 533 sc->active_Tx = Tx->next; 534 Tx->next = sc->Free_Tx; 535 sc->Free_Tx = Tx; 536 } 537 sc->last_Tx = NULL; 538 free(sc->Tx_list, M_DEVBUF); 539 sc->Tx_list = NULL; 540 if (nullbuf) 541 free(nullbuf, M_DEVBUF); 542 nullbuf = NULL; 543 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 544 sc->mii.mii_media_status &= ~IFM_ACTIVE; 545 sc->tl_flags = 0; 546 } 547 548 static void tl_restart(v) 549 void *v; 550 { 551 tl_init(v); 552 } 553 554 static int tl_init(sc) 555 tl_softc_t *sc; 556 { 557 struct ifnet *ifp = &sc->tl_if; 558 int i, s; 559 560 s = splimp(); 561 /* cancel any pending IO */ 562 tl_shutdown(sc); 563 tl_reset(sc); 564 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 565 splx(s); 566 return 0; 567 } 568 /* Set various register to reasonable value */ 569 /* setup NetCmd in promisc mode if needed */ 570 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 571 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 572 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 573 /* Max receive size : MCLBYTES */ 574 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 575 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 576 (MCLBYTES >> 8) & 0xff); 577 578 /* init MAC addr */ 579 for (i = 0; i < ETHER_ADDR_LEN; i++) 580 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 581 /* add multicast filters */ 582 tl_addr_filter(sc); 583 #ifdef TLDEBUG_ADDR 584 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 585 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 586 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 587 #endif 588 589 /* Pre-allocate receivers mbuf, make the lists */ 590 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 591 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 592 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 593 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 594 sc->tl_if.if_flags &= ~IFF_UP; 595 splx(s); 596 return ENOMEM; 597 } 598 for (i=0; i< TL_NBUF; i++) { 599 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 600 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 601 sc->tl_if.if_flags &= ~IFF_UP; 602 splx(s); 603 return ENOMEM; 604 } 605 if (i > 0) { /* chain the list */ 606 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 607 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 608 #ifdef DIAGNOSTIC 609 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 610 printf("%s: physical addr 0x%x of list not properly aligned\n", 611 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 612 #endif 613 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 614 } 615 } 616 sc->Rx_list[TL_NBUF-1].next = NULL; 617 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 618 sc->Tx_list[TL_NBUF-1].next = NULL; 619 620 sc->active_Rx = &sc->Rx_list[0]; 621 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 622 sc->active_Tx = sc->last_Tx = NULL; 623 sc->Free_Tx = &sc->Tx_list[0]; 624 625 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 626 if (nullbuf == NULL) { 627 printf("%s: can't allocate space for pad buffer\n", 628 sc->sc_dev.dv_xname); 629 sc->tl_if.if_flags &= ~IFF_UP; 630 splx(s); 631 return ENOMEM; 632 } 633 bzero(nullbuf, ETHER_MIN_TX); 634 635 /* set media if needed */ 636 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 637 mii_mediachg(&sc->mii); 638 } 639 640 /* start ticks calls */ 641 timeout(tl_ticks, sc, hz); 642 /* write adress of Rx list and enable interrupts */ 643 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 644 TL_HR_WRITE(sc, TL_HOST_CMD, 645 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 646 sc->tl_if.if_flags |= IFF_RUNNING; 647 sc->tl_if.if_flags &= ~IFF_OACTIVE; 648 return 0; 649 } 650 651 652 static u_int32_t 653 tl_intreg_read(sc, reg) 654 tl_softc_t *sc; 655 u_int32_t reg; 656 { 657 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 658 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 659 } 660 661 static u_int8_t 662 tl_intreg_read_byte(sc, reg) 663 tl_softc_t *sc; 664 u_int32_t reg; 665 { 666 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 667 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 668 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 669 } 670 671 static void 672 tl_intreg_write(sc, reg, val) 673 tl_softc_t *sc; 674 u_int32_t reg; 675 u_int32_t val; 676 { 677 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 678 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 679 } 680 681 static void 682 tl_intreg_write_byte(sc, reg, val) 683 tl_softc_t *sc; 684 u_int32_t reg; 685 u_int8_t val; 686 { 687 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 688 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 689 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 690 } 691 692 void tl_mii_set(v, bit) 693 void *v; 694 u_int8_t bit; 695 { 696 tl_softc_t *sc = v; 697 698 switch (bit) { 699 case MII_DATA: 700 netsio_set(sc, TL_NETSIO_MDATA); 701 break; 702 case MII_CLOCK: 703 netsio_set(sc, TL_NETSIO_MCLK); 704 break; 705 case MII_TXEN: 706 netsio_set(sc, TL_NETSIO_MTXEN); 707 break; 708 default: 709 printf("tl_mii_set: unknown bit %d\n", bit); 710 } 711 } 712 713 void tl_mii_clr(v, bit) 714 void *v; 715 u_int8_t bit; 716 { 717 tl_softc_t *sc = v; 718 719 switch (bit) { 720 case MII_DATA: 721 netsio_clr(sc, TL_NETSIO_MDATA); 722 break; 723 case MII_CLOCK: 724 netsio_clr(sc, TL_NETSIO_MCLK); 725 break; 726 case MII_TXEN: 727 netsio_clr(sc, TL_NETSIO_MTXEN); 728 break; 729 default: 730 printf("tl_mii_clr: unknown bit %d\n", bit); 731 } 732 return; 733 } 734 735 int tl_mii_read(v, bit) 736 void *v; 737 u_int8_t bit; 738 { 739 tl_softc_t *sc = v; 740 741 switch (bit) { 742 case MII_DATA: 743 return netsio_read(sc, TL_NETSIO_MDATA); 744 break; 745 case MII_CLOCK: 746 return netsio_read(sc, TL_NETSIO_MCLK); 747 break; 748 case MII_TXEN: 749 return netsio_read(sc, TL_NETSIO_MTXEN); 750 break; 751 default: 752 printf("tl_mii_read: unknown bit %d\n", bit); 753 return -1; 754 } 755 } 756 757 void tl_i2c_set(v, bit) 758 void *v; 759 u_int8_t bit; 760 { 761 tl_softc_t *sc = v; 762 763 switch (bit) { 764 case I2C_DATA: 765 netsio_set(sc, TL_NETSIO_EDATA); 766 break; 767 case I2C_CLOCK: 768 netsio_set(sc, TL_NETSIO_ECLOCK); 769 break; 770 case I2C_TXEN: 771 netsio_set(sc, TL_NETSIO_ETXEN); 772 break; 773 default: 774 printf("tl_i2c_set: unknown bit %d\n", bit); 775 } 776 return; 777 } 778 779 void tl_i2c_clr(v, bit) 780 void *v; 781 u_int8_t bit; 782 { 783 tl_softc_t *sc = v; 784 785 switch (bit) { 786 case I2C_DATA: 787 netsio_clr(sc, TL_NETSIO_EDATA); 788 break; 789 case I2C_CLOCK: 790 netsio_clr(sc, TL_NETSIO_ECLOCK); 791 break; 792 case I2C_TXEN: 793 netsio_clr(sc, TL_NETSIO_ETXEN); 794 break; 795 default: 796 printf("tl_i2c_clr: unknown bit %d\n", bit); 797 } 798 return; 799 } 800 801 int tl_i2c_read(v, bit) 802 void *v; 803 u_int8_t bit; 804 { 805 tl_softc_t *sc = v; 806 807 switch (bit) { 808 case I2C_DATA: 809 return netsio_read(sc, TL_NETSIO_EDATA); 810 break; 811 case I2C_CLOCK: 812 return netsio_read(sc, TL_NETSIO_ECLOCK); 813 break; 814 case I2C_TXEN: 815 return netsio_read(sc, TL_NETSIO_ETXEN); 816 break; 817 default: 818 printf("tl_i2c_read: unknown bit %d\n", bit); 819 return -1; 820 } 821 } 822 823 static int 824 tl_intr(v) 825 void *v; 826 { 827 tl_softc_t *sc = v; 828 struct ifnet *ifp = &sc->tl_if; 829 struct Rx_list *Rx; 830 struct Tx_list *Tx; 831 struct mbuf *m; 832 u_int32_t int_type, int_reg; 833 int ack = 0; 834 int size; 835 836 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 837 int_type = int_reg & TL_INTR_MASK; 838 if (int_type == 0) 839 return 0; 840 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 841 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 842 int_type, int_reg); 843 #endif 844 /* disable interrupts */ 845 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 846 switch(int_type & TL_INTR_MASK) { 847 case TL_INTR_RxEOF: 848 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 849 /* dequeue and requeue at end of list */ 850 ack++; 851 Rx = sc->active_Rx; 852 sc->active_Rx = Rx->next; 853 m = Rx->m; 854 size = Rx->hw_list.stat >> 16; 855 #ifdef TLDEBUG_RX 856 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 857 #endif 858 if (tl_add_RxBuff(Rx, m ) == 0) { 859 /* No new mbuf, reuse the same. This means that this packet 860 is lost */ 861 m = NULL; 862 #ifdef TL_PRIV_STATS 863 sc->ierr_nomem++; 864 #endif 865 #ifdef TLDEBUG 866 printf("%s: out of mbuf, lost input packet\n", 867 sc->sc_dev.dv_xname); 868 #endif 869 } 870 Rx->next = NULL; 871 Rx->hw_list.fwd = 0; 872 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 873 #ifdef DIAGNOSTIC 874 if (sc->last_Rx->hw_list.fwd & 0x7) 875 printf("%s: physical addr 0x%x of list not properly aligned\n", 876 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 877 #endif 878 sc->last_Rx->next = Rx; 879 sc->last_Rx = Rx; 880 881 /* deliver packet */ 882 if (m) { 883 struct ether_header *eh; 884 if (size < sizeof(struct ether_header)) { 885 m_freem(m); 886 continue; 887 } 888 m->m_pkthdr.rcvif = ifp; 889 m->m_pkthdr.len = m->m_len = 890 size - sizeof(struct ether_header); 891 eh = mtod(m, struct ether_header *); 892 #ifdef TLDEBUG_RX 893 printf("tl_intr: Rx packet:\n"); 894 ether_printheader(eh); 895 #endif 896 #if NBPFILTER > 0 897 if (ifp->if_bpf) { 898 bpf_tap(ifp->if_bpf, 899 mtod(m, caddr_t), 900 size); 901 /* 902 * Only pass this packet up 903 * if it is for us. 904 */ 905 if ((ifp->if_flags & IFF_PROMISC) && 906 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 907 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 908 sizeof(eh->ether_dhost)) != 0) { 909 m_freem(m); 910 continue; 911 } 912 } 913 #endif /* NBPFILTER > 0 */ 914 m->m_data += sizeof(struct ether_header); 915 ether_input(ifp, eh, m); 916 } 917 } 918 #ifdef TLDEBUG_RX 919 printf("TL_INTR_RxEOF: ack %d\n", ack); 920 #else 921 if (ack == 0) { 922 printf("%s: EOF intr without anything to read !\n", 923 sc->sc_dev.dv_xname); 924 tl_reset(sc); 925 /* shedule reinit of the board */ 926 timeout(tl_restart, sc, 1); 927 return(1); 928 } 929 #endif 930 break; 931 case TL_INTR_RxEOC: 932 ack++; 933 #ifdef TLDEBUG_RX 934 printf("TL_INTR_RxEOC: ack %d\n", ack); 935 #endif 936 #ifdef DIAGNOSTIC 937 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 938 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 939 sc->sc_dev.dv_xname); 940 return 0; 941 } else 942 #endif 943 { 944 /* write adress of Rx list and send Rx GO command, ack interrupt 945 and enable interrupts in one command */ 946 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 947 vtophys(&sc->active_Rx->hw_list)); 948 TL_HR_WRITE(sc, TL_HOST_CMD, 949 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 950 HOST_CMD_ACK | HOST_CMD_IntOn); 951 return 1; 952 } 953 case TL_INTR_TxEOF: 954 case TL_INTR_TxEOC: 955 while ((Tx = sc->active_Tx) != NULL) { 956 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 957 break; 958 ack++; 959 #ifdef TLDEBUG_TX 960 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 961 #endif 962 Tx->hw_list.stat = 0; 963 m_freem(Tx->m); 964 Tx->m = NULL; 965 sc->active_Tx = Tx->next; 966 if (sc->active_Tx == NULL) 967 sc->last_Tx = NULL; 968 Tx->next = sc->Free_Tx; 969 sc->Free_Tx = Tx; 970 } 971 /* if this was an EOC, ACK immediatly */ 972 if (int_type == TL_INTR_TxEOC) { 973 #ifdef TLDEBUG_TX 974 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 975 #endif 976 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 977 HOST_CMD_IntOn); 978 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 979 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 980 vtophys(&sc->active_Tx->hw_list)); 981 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 982 } 983 sc->tl_if.if_timer = 0; 984 if (sc->tl_if.if_snd.ifq_head != NULL) 985 tl_ifstart(&sc->tl_if); 986 return 1; 987 } 988 #ifdef TLDEBUG 989 else { 990 printf("TL_INTR_TxEOF: ack %d\n", ack); 991 } 992 #endif 993 sc->tl_if.if_timer = 0; 994 if (sc->tl_if.if_snd.ifq_head != NULL) 995 tl_ifstart(&sc->tl_if); 996 break; 997 case TL_INTR_Stat: 998 ack++; 999 #ifdef TLDEBUG 1000 printf("TL_INTR_Stat: ack %d\n", ack); 1001 #endif 1002 tl_read_stats(sc); 1003 break; 1004 case TL_INTR_Adc: 1005 if (int_reg & TL_INTVec_MASK) { 1006 /* adapter check conditions */ 1007 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1008 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1009 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1010 tl_reset(sc); 1011 /* shedule reinit of the board */ 1012 timeout(tl_restart, sc, 1); 1013 return(1); 1014 } else { 1015 u_int8_t netstat; 1016 /* Network status */ 1017 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1018 printf("%s: network status, NetSts=%x\n", 1019 sc->sc_dev.dv_xname, netstat); 1020 /* Ack interrupts */ 1021 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1022 ack++; 1023 } 1024 break; 1025 default: 1026 printf("%s: unhandled interrupt code %x!\n", 1027 sc->sc_dev.dv_xname, int_type); 1028 ack++; 1029 } 1030 1031 if (ack) { 1032 /* Ack the interrupt and enable interrupts */ 1033 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1034 HOST_CMD_IntOn); 1035 return 1; 1036 } 1037 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1038 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1039 return 0; 1040 } 1041 1042 static int 1043 tl_ifioctl(ifp, cmd, data) 1044 struct ifnet *ifp; 1045 ioctl_cmd_t cmd; 1046 caddr_t data; 1047 { 1048 struct tl_softc *sc = ifp->if_softc; 1049 struct ifreq *ifr = (struct ifreq *)data; 1050 int s, error; 1051 1052 s = splimp(); 1053 switch(cmd) { 1054 case SIOCSIFADDR: { 1055 struct ifaddr *ifa = (struct ifaddr *)data; 1056 sc->tl_if.if_flags |= IFF_UP; 1057 if ((error = tl_init(sc)) != NULL) { 1058 sc->tl_if.if_flags &= ~IFF_UP; 1059 break; 1060 } 1061 switch (ifa->ifa_addr->sa_family) { 1062 #ifdef INET 1063 case AF_INET: 1064 arp_ifinit(ifp, ifa); 1065 break; 1066 #endif 1067 #ifdef NS 1068 case AF_NS: { 1069 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1070 1071 if (ns_nullhost(*ina)) 1072 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1073 else 1074 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1075 ifp->if_addrlen); 1076 break; 1077 } 1078 #endif 1079 default: 1080 break; 1081 } 1082 break; 1083 } 1084 case SIOCSIFFLAGS: 1085 { 1086 u_int8_t reg; 1087 /* 1088 * If interface is marked up and not running, then start it. 1089 * If it is marked down and running, stop it. 1090 */ 1091 if (ifp->if_flags & IFF_UP) { 1092 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1093 error = tl_init(sc); 1094 /* all flags have been handled by init */ 1095 break; 1096 } 1097 error = 0; 1098 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1099 if (ifp->if_flags & IFF_PROMISC) 1100 reg |= TL_NETCOMMAND_CAF; 1101 else 1102 reg &= ~TL_NETCOMMAND_CAF; 1103 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1104 #ifdef TL_PRIV_STATS 1105 if (ifp->if_flags & IFF_LINK0) { 1106 ifp->if_flags &= ~IFF_LINK0; 1107 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1108 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1109 printf(" %4d RX code error\n", sc->ierr_code); 1110 printf(" %4d RX crc error\n", sc->ierr_crc); 1111 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1112 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1113 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1114 printf(" %4d TX single collisions\n", sc->oerr_coll); 1115 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1116 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1117 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1118 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1119 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1120 } 1121 #endif 1122 } else { 1123 if (ifp->if_flags & IFF_RUNNING) 1124 tl_shutdown(sc); 1125 error = 0; 1126 } 1127 break; 1128 } 1129 case SIOCADDMULTI: 1130 case SIOCDELMULTI: 1131 /* 1132 * Update multicast listeners 1133 */ 1134 if (cmd == SIOCADDMULTI) 1135 error = ether_addmulti(ifr, &sc->tl_ec); 1136 else 1137 error = ether_delmulti(ifr, &sc->tl_ec); 1138 if (error == ENETRESET) { 1139 tl_addr_filter(sc); 1140 error = 0; 1141 } 1142 break; 1143 case SIOCSIFMEDIA: 1144 case SIOCGIFMEDIA: 1145 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1146 break; 1147 default: 1148 error = EINVAL; 1149 } 1150 splx(s); 1151 return error; 1152 } 1153 1154 static void 1155 tl_ifstart(ifp) 1156 struct ifnet *ifp; 1157 { 1158 tl_softc_t *sc = ifp->if_softc; 1159 struct mbuf *m, *mb_head; 1160 struct Tx_list *Tx; 1161 int segment, size; 1162 1163 txloop: 1164 /* If we don't have more space ... */ 1165 if (sc->Free_Tx == NULL) { 1166 #ifdef TLDEBUG 1167 printf("tl_ifstart: No free TX list\n"); 1168 #endif 1169 return; 1170 } 1171 /* Grab a paquet for output */ 1172 IF_DEQUEUE(&ifp->if_snd, mb_head); 1173 if (mb_head == NULL) { 1174 #ifdef TLDEBUG_TX 1175 printf("tl_ifstart: nothing to send\n"); 1176 #endif 1177 return; 1178 } 1179 Tx = sc->Free_Tx; 1180 sc->Free_Tx = Tx->next; 1181 /* 1182 * Go through each of the mbufs in the chain and initialize 1183 * the transmit list descriptors with the physical address 1184 * and size of the mbuf. 1185 */ 1186 tbdinit: 1187 bzero(Tx, sizeof(struct Tx_list)); 1188 Tx->m = mb_head; 1189 size = 0; 1190 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1191 if (m->m_len != 0) { 1192 if (segment == TL_NSEG) 1193 break; 1194 size += m->m_len; 1195 Tx->hw_list.seg[segment].data_addr = 1196 vtophys(mtod(m, vm_offset_t)); 1197 Tx->hw_list.seg[segment].data_count = m->m_len; 1198 segment++; 1199 } 1200 } 1201 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1202 /* 1203 * We ran out of segments, or we will. We have to recopy this mbuf 1204 * chain first. 1205 */ 1206 struct mbuf *mn; 1207 #ifdef TLDEBUG_TX 1208 printf("tl_ifstart: need to copy mbuf\n"); 1209 #endif 1210 #ifdef TL_PRIV_STATS 1211 sc->oerr_mcopy++; 1212 #endif 1213 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1214 if (mn == NULL) { 1215 m_freem(mb_head); 1216 goto bad; 1217 } 1218 if (mb_head->m_pkthdr.len > MHLEN) { 1219 MCLGET(mn, M_DONTWAIT); 1220 if ((mn->m_flags & M_EXT) == 0) { 1221 m_freem(mn); 1222 m_freem(mb_head); 1223 goto bad; 1224 } 1225 } 1226 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1227 mtod(mn, caddr_t)); 1228 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1229 m_freem(mb_head); 1230 mb_head = mn; 1231 goto tbdinit; 1232 } 1233 /* We are at end of mbuf chain. check the size and 1234 * see if it needs to be extended 1235 */ 1236 if (size < ETHER_MIN_TX) { 1237 #ifdef DIAGNOSTIC 1238 if (segment >= TL_NSEG) { 1239 panic("tl_ifstart: to much segmets (%d)\n", segment); 1240 } 1241 #endif 1242 /* 1243 * add the nullbuf in the seg 1244 */ 1245 Tx->hw_list.seg[segment].data_count = 1246 ETHER_MIN_TX - size; 1247 Tx->hw_list.seg[segment].data_addr = 1248 vtophys(nullbuf); 1249 size = ETHER_MIN_TX; 1250 segment++; 1251 } 1252 /* The list is done, finish the list init */ 1253 Tx->hw_list.seg[segment-1].data_count |= 1254 TL_LAST_SEG; 1255 Tx->hw_list.stat = (size << 16) | 0x3000; 1256 #ifdef TLDEBUG_TX 1257 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1258 Tx->hw_list.stat); 1259 #if 0 1260 for(segment = 0; segment < TL_NSEG; segment++) { 1261 printf(" seg %d addr 0x%x len 0x%x\n", 1262 segment, 1263 Tx->hw_list.seg[segment].data_addr, 1264 Tx->hw_list.seg[segment].data_count); 1265 } 1266 #endif 1267 #endif 1268 sc->opkt++; 1269 if (sc->active_Tx == NULL) { 1270 sc->active_Tx = sc->last_Tx = Tx; 1271 #ifdef TLDEBUG_TX 1272 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1273 vtophys(&Tx->hw_list)); 1274 #endif 1275 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1276 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1277 } else { 1278 #ifdef TLDEBUG_TX 1279 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1280 vtophys(&Tx->hw_list)); 1281 #endif 1282 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1283 sc->last_Tx->next = Tx; 1284 sc->last_Tx = Tx; 1285 #ifdef DIAGNOSTIC 1286 if (sc->last_Tx->hw_list.fwd & 0x7) 1287 printf("%s: physical addr 0x%x of list not properly aligned\n", 1288 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1289 #endif 1290 } 1291 #if NBPFILTER > 0 1292 /* Pass packet to bpf if there is a listener */ 1293 if (ifp->if_bpf) 1294 bpf_mtap(ifp->if_bpf, mb_head); 1295 #endif 1296 /* Set a 5 second timer just in case we don't hear from the card again. */ 1297 ifp->if_timer = 5; 1298 1299 goto txloop; 1300 bad: 1301 #ifdef TLDEBUG 1302 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1303 #endif 1304 Tx->next = sc->Free_Tx; 1305 sc->Free_Tx = Tx; 1306 return; 1307 } 1308 1309 static void 1310 tl_ifwatchdog(ifp) 1311 struct ifnet *ifp; 1312 { 1313 tl_softc_t *sc = ifp->if_softc; 1314 1315 if ((ifp->if_flags & IFF_RUNNING) == 0) 1316 return; 1317 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1318 ifp->if_oerrors++; 1319 tl_init(sc); 1320 } 1321 1322 static int 1323 tl_mediachange(ifp) 1324 struct ifnet *ifp; 1325 { 1326 1327 tl_softc_t *sc = ifp->if_softc; 1328 int err; 1329 u_int32_t reg; 1330 int oldmedia; 1331 #ifdef TLDEBUG 1332 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1333 #endif 1334 oldmedia = sc->mii.mii_media_active; 1335 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1336 if ((err = mii_mediachg(&sc->mii)) != 0) 1337 sc->mii.mii_media_active = oldmedia; 1338 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1339 if (sc->mii.mii_media_active & IFM_FDX) 1340 reg |= TL_NETCOMMAND_DUPLEX; 1341 else 1342 reg &= ~TL_NETCOMMAND_DUPLEX; 1343 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1344 return err; 1345 } 1346 1347 static void 1348 tl_mediastatus(ifp, ifmr) 1349 struct ifnet *ifp; 1350 struct ifmediareq *ifmr; 1351 { 1352 tl_softc_t *sc = ifp->if_softc; 1353 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1354 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1355 if (sc->tl_flags & TL_IFACT) 1356 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1357 else 1358 sc->mii.mii_media_status = IFM_AVALID; 1359 else 1360 mii_pollstat(&sc->mii); 1361 1362 ifmr->ifm_active = sc->mii.mii_media_active; 1363 ifmr->ifm_status = sc->mii.mii_media_status; 1364 } 1365 1366 static int tl_add_RxBuff(Rx, oldm) 1367 struct Rx_list *Rx; 1368 struct mbuf *oldm; 1369 { 1370 struct mbuf *m; 1371 1372 MGETHDR(m, M_DONTWAIT, MT_DATA); 1373 if (m != NULL) { 1374 MCLGET(m, M_DONTWAIT); 1375 if ((m->m_flags & M_EXT) == 0) { 1376 m_freem(m); 1377 if (oldm == NULL) 1378 return 0; 1379 m = oldm; 1380 m->m_data = m->m_ext.ext_buf; 1381 } 1382 } else { 1383 if (oldm == NULL) 1384 return 0; 1385 m = oldm; 1386 m->m_data = m->m_ext.ext_buf; 1387 } 1388 /* 1389 * Move the data pointer up so that the incoming data packet 1390 * will be 32-bit aligned. 1391 */ 1392 m->m_data += 2; 1393 1394 /* (re)init the Rx_list struct */ 1395 1396 Rx->m = m; 1397 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1398 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1399 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1400 return (m != oldm); 1401 } 1402 1403 static void tl_ticks(v) 1404 void *v; 1405 { 1406 tl_softc_t *sc = v; 1407 1408 tl_read_stats(sc); 1409 if (sc->opkt > 0) { 1410 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1411 if (sc->tl_flags & TL_IFACT) /* only print once */ 1412 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1413 sc->tl_flags &= ~TL_IFACT; 1414 } else 1415 sc->tl_flags |= TL_IFACT; 1416 sc->oerr_exesscoll = sc->opkt = 0; 1417 sc->tl_lasttx = 0; 1418 } else { 1419 sc->tl_lasttx++; 1420 if (sc->tl_lasttx >= TL_IDLETIME) { 1421 /* 1422 * No TX activity in the last TL_IDLETIME seconds. 1423 * sends a LLC Class1 TEST pkt 1424 */ 1425 struct mbuf *m; 1426 int s; 1427 MGETHDR(m, M_DONTWAIT, MT_DATA); 1428 if (m != NULL) { 1429 #ifdef TLDEBUG 1430 printf("tl_ticks: sending LLC test pkt\n"); 1431 #endif 1432 bcopy(sc->tl_enaddr, 1433 mtod(m, struct ether_header *)->ether_dhost, 6); 1434 bcopy(sc->tl_enaddr, 1435 mtod(m, struct ether_header *)->ether_shost, 6); 1436 mtod(m, struct ether_header *)->ether_type = htons(3); 1437 mtod(m, unsigned char *)[14] = 0; 1438 mtod(m, unsigned char *)[15] = 0; 1439 mtod(m, unsigned char *)[16] = 0xE3; 1440 /* LLC Class1 TEST (no poll) */ 1441 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1442 s = splnet(); 1443 IF_PREPEND(&sc->tl_if.if_snd, m); 1444 tl_ifstart(&sc->tl_if); 1445 splx(s); 1446 } 1447 } 1448 } 1449 1450 /* read statistics every seconds */ 1451 timeout(tl_ticks, v, hz); 1452 } 1453 1454 static void 1455 tl_read_stats(sc) 1456 tl_softc_t *sc; 1457 { 1458 u_int32_t reg; 1459 int ierr_overr; 1460 int ierr_code; 1461 int ierr_crc; 1462 int oerr_underr; 1463 int oerr_deffered; 1464 int oerr_coll; 1465 int oerr_multicoll; 1466 int oerr_exesscoll; 1467 int oerr_latecoll; 1468 int oerr_carrloss; 1469 struct ifnet *ifp = &sc->tl_if; 1470 1471 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1472 ifp->if_opackets += reg & 0x00ffffff; 1473 oerr_underr = reg >> 24; 1474 1475 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1476 ifp->if_ipackets += reg & 0x00ffffff; 1477 ierr_overr = reg >> 24; 1478 1479 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1480 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1481 ierr_code = (reg & TL_FERR_CODE) >> 24; 1482 oerr_deffered = (reg & TL_FERR_DEF); 1483 1484 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1485 oerr_multicoll = (reg & TL_COL_MULTI); 1486 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1487 1488 reg = tl_intreg_read(sc, TL_INT_LERR); 1489 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1490 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1491 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1492 1493 1494 sc->stats_exesscoll += oerr_exesscoll; 1495 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1496 oerr_carrloss; 1497 ifp->if_collisions += oerr_coll + oerr_multicoll; 1498 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1499 1500 if (ierr_overr) 1501 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1502 if (oerr_underr) 1503 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1504 #ifdef TL_PRIV_STATS 1505 sc->ierr_overr += ierr_overr; 1506 sc->ierr_code += ierr_code; 1507 sc->ierr_crc += ierr_crc; 1508 sc->oerr_underr += oerr_underr; 1509 sc->oerr_deffered += oerr_deffered; 1510 sc->oerr_coll += oerr_coll; 1511 sc->oerr_multicoll += oerr_multicoll; 1512 sc->oerr_exesscoll += oerr_exesscoll; 1513 sc->oerr_latecoll += oerr_latecoll; 1514 sc->oerr_carrloss += oerr_carrloss; 1515 #endif 1516 } 1517 1518 static void tl_addr_filter(sc) 1519 tl_softc_t *sc; 1520 { 1521 struct ether_multistep step; 1522 struct ether_multi *enm; 1523 u_int32_t hash[2] = {0, 0}; 1524 int i; 1525 1526 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1527 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1528 while (enm != NULL) { 1529 #ifdef TLDEBUG 1530 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1531 #endif 1532 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1533 i = tl_multicast_hash(enm->enm_addrlo); 1534 hash[i/32] |= 1 << (i%32); 1535 } else { 1536 hash[0] = hash[1] = 0xffffffff; 1537 sc->tl_if.if_flags |= IFF_ALLMULTI; 1538 break; 1539 } 1540 ETHER_NEXT_MULTI(step, enm); 1541 } 1542 #ifdef TLDEBUG 1543 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1544 #endif 1545 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1546 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1547 } 1548 1549 static int tl_multicast_hash(a) 1550 u_int8_t *a; 1551 { 1552 int hash; 1553 1554 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1555 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1556 1557 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1558 DA(a,36), DA(a,42)); 1559 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1560 DA(a,37), DA(a,43)) << 1; 1561 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1562 DA(a,38), DA(a,44)) << 2; 1563 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1564 DA(a,39), DA(a,45)) << 3; 1565 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1566 DA(a,40), DA(a,46)) << 4; 1567 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1568 DA(a,41), DA(a,47)) << 5; 1569 1570 return hash; 1571 } 1572 1573 #if defined(TLDEBUG_RX) 1574 void ether_printheader(eh) 1575 struct ether_header *eh; 1576 { 1577 u_char *c = (char*)eh; 1578 int i; 1579 for (i=0; i<sizeof(struct ether_header); i++) 1580 printf("%x ", (u_int)c[i]); 1581 printf("\n"); 1582 } 1583 #endif 1584
Indexes created Tue Sep 23 07:09:52 GMT 2025