if_tl.c revision 1.43
1 /* $NetBSD: if_tl.c,v 1.43 2001/08/03 16:53:08 bouyer Exp $ */ 2 3 /* XXX ALTQ XXX */ 4 5 /* 6 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Texas Instruments ThunderLAN ethernet controller 36 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 37 * available from www.ti.com 38 */ 39 40 #undef TLDEBUG 41 #define TL_PRIV_STATS 42 #undef TLDEBUG_RX 43 #undef TLDEBUG_TX 44 #undef TLDEBUG_ADDR 45 46 #include "opt_inet.h" 47 #include "opt_ns.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #endif 82 83 #ifdef NS 84 #include <netns/ns.h> 85 #include <netns/ns_if.h> 86 #endif 87 88 #if defined(__NetBSD__) 89 #include <net/if_ether.h> 90 #include <uvm/uvm_extern.h> 91 #if defined(INET) 92 #include <netinet/if_inarp.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/i2c/i2c_bus.h> 103 #include <dev/i2c/i2c_eeprom.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 108 #include <dev/mii/tlphyvar.h> 109 110 #include <dev/pci/if_tlregs.h> 111 #include <dev/pci/if_tlvar.h> 112 #endif /* __NetBSD__ */ 113 114 /* number of transmit/receive buffers */ 115 #ifndef TL_NBUF 116 #define TL_NBUF 10 117 #endif 118 119 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 120 static void tl_pci_attach __P((struct device *, struct device *, void *)); 121 static int tl_intr __P((void *)); 122 123 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 124 static int tl_mediachange __P((struct ifnet *)); 125 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 126 static void tl_ifwatchdog __P((struct ifnet *)); 127 static void tl_shutdown __P((void*)); 128 129 static void tl_ifstart __P((struct ifnet *)); 130 static void tl_reset __P((tl_softc_t*)); 131 static int tl_init __P((tl_softc_t*)); 132 static void tl_restart __P((void *)); 133 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 134 static void tl_read_stats __P((tl_softc_t*)); 135 static void tl_ticks __P((void*)); 136 static int tl_multicast_hash __P((u_int8_t*)); 137 static void tl_addr_filter __P((tl_softc_t*)); 138 139 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 140 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 141 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 143 144 void tl_mii_sync __P((struct tl_softc *)); 145 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 146 147 148 #if defined(TLDEBUG_RX) 149 static void ether_printheader __P((struct ether_header*)); 150 #endif 151 152 int tl_mii_read __P((struct device *, int, int)); 153 void tl_mii_write __P((struct device *, int, int, int)); 154 155 void tl_statchg __P((struct device *)); 156 157 void tl_i2c_set __P((void*, u_int8_t)); 158 void tl_i2c_clr __P((void*, u_int8_t)); 159 int tl_i2c_read __P((void*, u_int8_t)); 160 161 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 162 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 163 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_clr(sc, bits) 165 tl_softc_t* sc; 166 u_int8_t bits; 167 { 168 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 169 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 170 } 171 static __inline void netsio_set(sc, bits) 172 tl_softc_t* sc; 173 u_int8_t bits; 174 { 175 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 176 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 177 } 178 static __inline u_int8_t netsio_read(sc, bits) 179 tl_softc_t* sc; 180 u_int8_t bits; 181 { 182 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 183 } 184 185 struct cfattach tl_ca = { 186 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 187 }; 188 189 const struct tl_product_desc tl_compaq_products[] = { 190 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 191 "Compaq Netelligent 10/100 TX" }, 192 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 193 "Compaq Netelligent 10 T" }, 194 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 195 "Compaq Integrated NetFlex 3/P" }, 196 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 197 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 198 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 199 "Compaq Dual Port Netelligent 10/100 TX" }, 200 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 201 "Compaq Deskpro 4000 5233MMX" }, 202 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 203 "Compaq NetFlex 3/P w/ BNC" }, 204 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 205 "Compaq NetFlex 3/P" }, 206 { 0, 0, NULL }, 207 }; 208 209 const struct tl_product_desc tl_ti_products[] = { 210 /* 211 * Built-in Ethernet on the TI TravelMate 5000 212 * docking station; better product description? 213 */ 214 { PCI_PRODUCT_TI_TLAN, 0, 215 "Texas Instruments ThunderLAN" }, 216 { 0, 0, NULL }, 217 }; 218 219 struct tl_vendor_desc { 220 u_int32_t tv_vendor; 221 const struct tl_product_desc *tv_products; 222 }; 223 224 const struct tl_vendor_desc tl_vendors[] = { 225 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 226 { PCI_VENDOR_TI, tl_ti_products }, 227 { 0, NULL }, 228 }; 229 230 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 231 232 const struct tl_product_desc * 233 tl_lookup_product(id) 234 u_int32_t id; 235 { 236 const struct tl_product_desc *tp; 237 const struct tl_vendor_desc *tv; 238 239 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 240 if (PCI_VENDOR(id) == tv->tv_vendor) 241 break; 242 243 if ((tp = tv->tv_products) == NULL) 244 return (NULL); 245 246 for (; tp->tp_desc != NULL; tp++) 247 if (PCI_PRODUCT(id) == tp->tp_product) 248 break; 249 250 if (tp->tp_desc == NULL) 251 return (NULL); 252 253 return (tp); 254 } 255 256 static char *nullbuf = NULL; 257 static bus_dmamap_t nullbuf_dmamap = NULL; 258 259 static int 260 tl_pci_match(parent, match, aux) 261 struct device *parent; 262 struct cfdata *match; 263 void *aux; 264 { 265 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 266 267 if (tl_lookup_product(pa->pa_id) != NULL) 268 return (1); 269 270 return (0); 271 } 272 273 static void 274 tl_pci_attach(parent, self, aux) 275 struct device * parent; 276 struct device * self; 277 void * aux; 278 { 279 tl_softc_t *sc = (tl_softc_t *)self; 280 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 281 const struct tl_product_desc *tp; 282 struct ifnet * const ifp = &sc->tl_if; 283 bus_space_tag_t iot, memt; 284 bus_space_handle_t ioh, memh; 285 pci_intr_handle_t intrhandle; 286 const char *intrstr; 287 int i, tmp, ioh_valid, memh_valid; 288 int reg_io, reg_mem; 289 pcireg_t reg10, reg14; 290 pcireg_t csr; 291 292 printf("\n"); 293 294 callout_init(&sc->tl_tick_ch); 295 callout_init(&sc->tl_restart_ch); 296 297 tp = tl_lookup_product(pa->pa_id); 298 if (tp == NULL) 299 panic("tl_pci_attach: impossible"); 300 sc->tl_product = tp; 301 302 /* 303 * Map the card space. Fisrt we have to find the I/O and MEM 304 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 305 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 306 * The ThunderLAN manual is not consistent about this either (there 307 * are both cases in code examples). 308 */ 309 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 310 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 311 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 312 reg_io = 0x10; 313 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 314 reg_io = 0x14; 315 else 316 reg_io = 0; 317 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 318 reg_mem = 0x10; 319 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 320 reg_mem = 0x14; 321 else 322 reg_mem = 0; 323 324 if (reg_io != 0) 325 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 326 0, &iot, &ioh, NULL, NULL) == 0); 327 else 328 ioh_valid = 0; 329 if (reg_mem != 0) 330 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 331 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 332 0, &memt, &memh, NULL, NULL) == 0); 333 else 334 memh_valid = 0; 335 336 if (ioh_valid) { 337 sc->tl_bustag = iot; 338 sc->tl_bushandle = ioh; 339 } else if (memh_valid) { 340 sc->tl_bustag = memt; 341 sc->tl_bushandle = memh; 342 } else { 343 printf("%s: unable to map device registers\n", 344 sc->sc_dev.dv_xname); 345 return; 346 } 347 sc->tl_dmatag = pa->pa_dmat; 348 349 /* Enable the device. */ 350 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 351 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 352 csr | PCI_COMMAND_MASTER_ENABLE); 353 354 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 355 356 tl_reset(sc); 357 358 /* fill in the i2c struct */ 359 sc->i2cbus.adapter_softc = sc; 360 sc->i2cbus.set_bit = tl_i2c_set; 361 sc->i2cbus.clr_bit = tl_i2c_clr; 362 sc->i2cbus.read_bit = tl_i2c_read; 363 364 #ifdef TLDEBUG 365 printf("default values of INTreg: 0x%x\n", 366 tl_intreg_read(sc, TL_INT_Defaults)); 367 #endif 368 369 /* read mac addr */ 370 for (i=0; i<ETHER_ADDR_LEN; i++) { 371 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 372 if (tmp < 0) { 373 printf("%s: error reading Ethernet adress\n", 374 sc->sc_dev.dv_xname); 375 return; 376 } else { 377 sc->tl_enaddr[i] = tmp; 378 } 379 } 380 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 381 ether_sprintf(sc->tl_enaddr)); 382 383 /* Map and establish interrupts */ 384 if (pci_intr_map(pa, &intrhandle)) { 385 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 386 return; 387 } 388 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 389 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 390 tl_intr, sc); 391 if (sc->tl_ih == NULL) { 392 printf("%s: couldn't establish interrupt", 393 sc->sc_dev.dv_xname); 394 if (intrstr != NULL) 395 printf(" at %s", intrstr); 396 printf("\n"); 397 return; 398 } 399 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 400 401 /* init these pointers, so that tl_shutdown won't try to read them */ 402 sc->Rx_list = NULL; 403 sc->Tx_list = NULL; 404 405 /* 406 * Add shutdown hook so that DMA is disabled prior to reboot. Not 407 * doing do could allow DMA to corrupt kernel memory during the 408 * reboot before the driver initializes. 409 */ 410 (void) shutdownhook_establish(tl_shutdown, sc); 411 412 /* 413 * Initialize our media structures and probe the MII. 414 * 415 * Note that we don't care about the media instance. We 416 * are expecting to have multiple PHYs on the 10/100 cards, 417 * and on those cards we exclude the internal PHY from providing 418 * 10baseT. By ignoring the instance, it allows us to not have 419 * to specify it on the command line when switching media. 420 */ 421 sc->tl_mii.mii_ifp = ifp; 422 sc->tl_mii.mii_readreg = tl_mii_read; 423 sc->tl_mii.mii_writereg = tl_mii_write; 424 sc->tl_mii.mii_statchg = tl_statchg; 425 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 426 tl_mediastatus); 427 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 428 MII_OFFSET_ANY, 0); 429 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 430 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 431 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 432 } else 433 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 434 435 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 436 sc->tl_if.if_softc = sc; 437 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 438 ifp->if_ioctl = tl_ifioctl; 439 ifp->if_start = tl_ifstart; 440 ifp->if_watchdog = tl_ifwatchdog; 441 ifp->if_timer = 0; 442 if_attach(ifp); 443 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 444 } 445 446 static void 447 tl_reset(sc) 448 tl_softc_t *sc; 449 { 450 int i; 451 452 /* read stats */ 453 if (sc->tl_if.if_flags & IFF_RUNNING) { 454 callout_stop(&sc->tl_tick_ch); 455 tl_read_stats(sc); 456 } 457 /* Reset adapter */ 458 TL_HR_WRITE(sc, TL_HOST_CMD, 459 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 460 DELAY(100000); 461 /* Disable interrupts */ 462 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 463 /* setup aregs & hash */ 464 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 465 tl_intreg_write(sc, i, 0); 466 #ifdef TLDEBUG_ADDR 467 printf("Areg & hash registers: \n"); 468 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 469 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 470 #endif 471 /* Setup NetConfig */ 472 tl_intreg_write(sc, TL_INT_NetConfig, 473 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 474 /* Bsize: accept default */ 475 /* TX commit in Acommit: accept default */ 476 /* Load Ld_tmr and Ld_thr */ 477 /* Ld_tmr = 3 */ 478 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 479 /* Ld_thr = 0 */ 480 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 481 /* Unreset MII */ 482 netsio_set(sc, TL_NETSIO_NMRST); 483 DELAY(100000); 484 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 485 } 486 487 static void tl_shutdown(v) 488 void *v; 489 { 490 tl_softc_t *sc = v; 491 struct Tx_list *Tx; 492 int i; 493 494 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 495 return; 496 /* disable interrupts */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 498 /* stop TX and RX channels */ 499 TL_HR_WRITE(sc, TL_HOST_CMD, 500 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 501 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 502 DELAY(100000); 503 504 /* stop statistics reading loop, read stats */ 505 callout_stop(&sc->tl_tick_ch); 506 tl_read_stats(sc); 507 508 /* Down the MII. */ 509 mii_down(&sc->tl_mii); 510 511 /* deallocate memory allocations */ 512 if (sc->Rx_list) { 513 for (i=0; i< TL_NBUF; i++) { 514 if (sc->Rx_list[i].m) { 515 bus_dmamap_unload(sc->tl_dmatag, 516 sc->Rx_list[i].m_dmamap); 517 m_freem(sc->Rx_list[i].m); 518 } 519 sc->Rx_list[i].m = NULL; 520 } 521 free(sc->Rx_list, M_DEVBUF); 522 sc->Rx_list = NULL; 523 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 524 bus_dmamem_free(sc->tl_dmatag, sc->Rx_dmamap->dm_segs, 525 sc->Rx_dmamap->dm_nsegs); 526 sc->hw_Rx_list = NULL; 527 while ((Tx = sc->active_Tx) != NULL) { 528 Tx->hw_list->stat = 0; 529 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 530 m_freem(Tx->m); 531 sc->active_Tx = Tx->next; 532 Tx->next = sc->Free_Tx; 533 sc->Free_Tx = Tx; 534 } 535 sc->last_Tx = NULL; 536 free(sc->Tx_list, M_DEVBUF); 537 sc->Tx_list = NULL; 538 bus_dmamem_free(sc->tl_dmatag, sc->Tx_dmamap->dm_segs, 539 sc->Tx_dmamap->dm_nsegs); 540 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 541 sc->hw_Tx_list = NULL; 542 } 543 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 544 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 545 } 546 547 static void tl_restart(v) 548 void *v; 549 { 550 tl_init(v); 551 } 552 553 static int tl_init(sc) 554 tl_softc_t *sc; 555 { 556 struct ifnet *ifp = &sc->tl_if; 557 int i, s, error; 558 bus_dma_segment_t segs; 559 int nsegs; 560 char *errstring; 561 562 s = splnet(); 563 /* cancel any pending IO */ 564 tl_shutdown(sc); 565 tl_reset(sc); 566 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 567 splx(s); 568 return 0; 569 } 570 /* Set various register to reasonable value */ 571 /* setup NetCmd in promisc mode if needed */ 572 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 573 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 574 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 575 /* Max receive size : MCLBYTES */ 576 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 577 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 578 (MCLBYTES >> 8) & 0xff); 579 580 /* init MAC addr */ 581 for (i = 0; i < ETHER_ADDR_LEN; i++) 582 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 583 /* add multicast filters */ 584 tl_addr_filter(sc); 585 #ifdef TLDEBUG_ADDR 586 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 587 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 588 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 589 #endif 590 591 /* Pre-allocate receivers mbuf, make the lists */ 592 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 593 M_NOWAIT); 594 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 595 M_NOWAIT); 596 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 597 errstring = "out of memory for lists"; 598 error = ENOMEM; 599 goto bad; 600 } 601 memset(sc->Rx_list, 0, sizeof(struct Rx_list) * TL_NBUF); 602 memset(sc->Tx_list, 0, sizeof(struct Tx_list) * TL_NBUF); 603 error = bus_dmamap_create(sc->tl_dmatag, 604 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 605 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 606 &sc->Rx_dmamap); 607 if (error == 0) 608 error = bus_dmamap_create(sc->tl_dmatag, 609 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 610 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 611 &sc->Tx_dmamap); 612 if (error) { 613 errstring = "can't allocate DMA maps for lists"; 614 goto bad; 615 } 616 error = bus_dmamem_alloc(sc->tl_dmatag, 617 sizeof(struct tl_Rx_list) * TL_NBUF, 0, PAGE_SIZE, 618 &segs, 1, &nsegs, BUS_DMA_NOWAIT); 619 if (error == 0) 620 error = bus_dmamem_map(sc->tl_dmatag, &segs, nsegs, 621 sizeof(struct tl_Rx_list) * TL_NBUF, 622 (caddr_t*)&sc->hw_Rx_list, 623 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 624 if (error == 0) 625 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 626 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 627 BUS_DMA_WAITOK); 628 if (error == 0) 629 error = bus_dmamem_alloc(sc->tl_dmatag, 630 sizeof(struct tl_Tx_list) * TL_NBUF, 0, PAGE_SIZE, 631 &segs, 1, &nsegs, BUS_DMA_NOWAIT); 632 if (error == 0) 633 error = bus_dmamem_map(sc->tl_dmatag, &segs, nsegs, 634 sizeof(struct tl_Tx_list) * TL_NBUF, 635 (caddr_t*)&sc->hw_Tx_list, 636 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 637 if (error == 0) 638 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 639 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 640 BUS_DMA_WAITOK); 641 if (error) { 642 errstring = "can't allocate DMA memory for lists"; 643 goto bad; 644 } 645 memset(sc->hw_Rx_list, 0, sizeof(struct tl_Rx_list) * TL_NBUF); 646 memset(sc->hw_Tx_list, 0, sizeof(struct tl_Tx_list) * TL_NBUF); 647 for (i=0; i< TL_NBUF; i++) { 648 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 649 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 650 &sc->Rx_list[i].m_dmamap); 651 if (error == 0) { 652 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 653 TL_NSEG, MCLBYTES, 0, 654 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 655 &sc->Tx_list[i].m_dmamap); 656 } 657 if (error) { 658 errstring = "can't allocate DMA maps for mbufs"; 659 goto bad; 660 } 661 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 662 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 663 + sizeof(struct tl_Rx_list) * i; 664 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 665 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 666 + sizeof(struct tl_Tx_list) * i; 667 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 668 errstring = "out of mbuf for receive list"; 669 error = ENOMEM; 670 goto bad; 671 } 672 if (i > 0) { /* chain the list */ 673 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 674 sc->hw_Rx_list[i-1].fwd = 675 htole32(sc->Rx_list[i].hw_listaddr); 676 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 677 } 678 } 679 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 680 sc->Rx_list[TL_NBUF-1].next = NULL; 681 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 682 sc->Tx_list[TL_NBUF-1].next = NULL; 683 684 sc->active_Rx = &sc->Rx_list[0]; 685 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 686 sc->active_Tx = sc->last_Tx = NULL; 687 sc->Free_Tx = &sc->Tx_list[0]; 688 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 689 sizeof(struct tl_Rx_list) * TL_NBUF, 690 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 691 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 692 sizeof(struct tl_Tx_list) * TL_NBUF, 693 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 694 695 if (nullbuf == NULL) { 696 error = bus_dmamap_create(sc->tl_dmatag, 697 ETHER_MIN_TX, 1, 698 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 699 &nullbuf_dmamap); 700 if (error == 0) 701 error = bus_dmamem_alloc(sc->tl_dmatag, ETHER_MIN_TX, 0, 702 PAGE_SIZE, &segs, 1, &nsegs, BUS_DMA_WAITOK); 703 if (error == 0) 704 error = bus_dmamem_map(sc->tl_dmatag, &segs, nsegs, 705 ETHER_MIN_TX, (caddr_t*)&nullbuf, BUS_DMA_WAITOK); 706 if (error == 0) 707 error = bus_dmamap_load(sc->tl_dmatag, nullbuf_dmamap, 708 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 709 } 710 if (error) { 711 errstring = "can't allocate space for pad buffer"; 712 goto bad; 713 } 714 memset(nullbuf, 0, ETHER_MIN_TX); 715 bus_dmamap_sync(sc->tl_dmatag, nullbuf_dmamap, 0, ETHER_MIN_TX, 716 BUS_DMASYNC_PREWRITE); 717 718 /* set media */ 719 mii_mediachg(&sc->tl_mii); 720 721 /* start ticks calls */ 722 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 723 /* write adress of Rx list and enable interrupts */ 724 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 725 TL_HR_WRITE(sc, TL_HOST_CMD, 726 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 727 sc->tl_if.if_flags |= IFF_RUNNING; 728 sc->tl_if.if_flags &= ~IFF_OACTIVE; 729 return 0; 730 bad: 731 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 732 sc->tl_if.if_flags &= ~IFF_UP; 733 splx(s); 734 return error; 735 } 736 737 738 static u_int32_t 739 tl_intreg_read(sc, reg) 740 tl_softc_t *sc; 741 u_int32_t reg; 742 { 743 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 744 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 745 } 746 747 static u_int8_t 748 tl_intreg_read_byte(sc, reg) 749 tl_softc_t *sc; 750 u_int32_t reg; 751 { 752 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 753 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 754 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 755 } 756 757 static void 758 tl_intreg_write(sc, reg, val) 759 tl_softc_t *sc; 760 u_int32_t reg; 761 u_int32_t val; 762 { 763 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 764 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 765 } 766 767 static void 768 tl_intreg_write_byte(sc, reg, val) 769 tl_softc_t *sc; 770 u_int32_t reg; 771 u_int8_t val; 772 { 773 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 774 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 775 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 776 } 777 778 void 779 tl_mii_sync(sc) 780 struct tl_softc *sc; 781 { 782 int i; 783 784 netsio_clr(sc, TL_NETSIO_MTXEN); 785 for (i = 0; i < 32; i++) { 786 netsio_clr(sc, TL_NETSIO_MCLK); 787 netsio_set(sc, TL_NETSIO_MCLK); 788 } 789 } 790 791 void 792 tl_mii_sendbits(sc, data, nbits) 793 struct tl_softc *sc; 794 u_int32_t data; 795 int nbits; 796 { 797 int i; 798 799 netsio_set(sc, TL_NETSIO_MTXEN); 800 for (i = 1 << (nbits - 1); i; i = i >> 1) { 801 netsio_clr(sc, TL_NETSIO_MCLK); 802 netsio_read(sc, TL_NETSIO_MCLK); 803 if (data & i) 804 netsio_set(sc, TL_NETSIO_MDATA); 805 else 806 netsio_clr(sc, TL_NETSIO_MDATA); 807 netsio_set(sc, TL_NETSIO_MCLK); 808 netsio_read(sc, TL_NETSIO_MCLK); 809 } 810 } 811 812 int 813 tl_mii_read(self, phy, reg) 814 struct device *self; 815 int phy, reg; 816 { 817 struct tl_softc *sc = (struct tl_softc *)self; 818 int val = 0, i, err; 819 820 /* 821 * Read the PHY register by manually driving the MII control lines. 822 */ 823 824 tl_mii_sync(sc); 825 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 826 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 827 tl_mii_sendbits(sc, phy, 5); 828 tl_mii_sendbits(sc, reg, 5); 829 830 netsio_clr(sc, TL_NETSIO_MTXEN); 831 netsio_clr(sc, TL_NETSIO_MCLK); 832 netsio_set(sc, TL_NETSIO_MCLK); 833 netsio_clr(sc, TL_NETSIO_MCLK); 834 835 err = netsio_read(sc, TL_NETSIO_MDATA); 836 netsio_set(sc, TL_NETSIO_MCLK); 837 838 /* Even if an error occurs, must still clock out the cycle. */ 839 for (i = 0; i < 16; i++) { 840 val <<= 1; 841 netsio_clr(sc, TL_NETSIO_MCLK); 842 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 843 val |= 1; 844 netsio_set(sc, TL_NETSIO_MCLK); 845 } 846 netsio_clr(sc, TL_NETSIO_MCLK); 847 netsio_set(sc, TL_NETSIO_MCLK); 848 849 return (err ? 0 : val); 850 } 851 852 void 853 tl_mii_write(self, phy, reg, val) 854 struct device *self; 855 int phy, reg, val; 856 { 857 struct tl_softc *sc = (struct tl_softc *)self; 858 859 /* 860 * Write the PHY register by manually driving the MII control lines. 861 */ 862 863 tl_mii_sync(sc); 864 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 865 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 866 tl_mii_sendbits(sc, phy, 5); 867 tl_mii_sendbits(sc, reg, 5); 868 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 869 tl_mii_sendbits(sc, val, 16); 870 871 netsio_clr(sc, TL_NETSIO_MCLK); 872 netsio_set(sc, TL_NETSIO_MCLK); 873 } 874 875 void 876 tl_statchg(self) 877 struct device *self; 878 { 879 tl_softc_t *sc = (struct tl_softc *)self; 880 u_int32_t reg; 881 882 #ifdef TLDEBUG 883 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 884 #endif 885 886 /* 887 * We must keep the ThunderLAN and the PHY in sync as 888 * to the status of full-duplex! 889 */ 890 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 891 if (sc->tl_mii.mii_media_active & IFM_FDX) 892 reg |= TL_NETCOMMAND_DUPLEX; 893 else 894 reg &= ~TL_NETCOMMAND_DUPLEX; 895 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 896 } 897 898 void tl_i2c_set(v, bit) 899 void *v; 900 u_int8_t bit; 901 { 902 tl_softc_t *sc = v; 903 904 switch (bit) { 905 case I2C_DATA: 906 netsio_set(sc, TL_NETSIO_EDATA); 907 break; 908 case I2C_CLOCK: 909 netsio_set(sc, TL_NETSIO_ECLOCK); 910 break; 911 case I2C_TXEN: 912 netsio_set(sc, TL_NETSIO_ETXEN); 913 break; 914 default: 915 printf("tl_i2c_set: unknown bit %d\n", bit); 916 } 917 return; 918 } 919 920 void tl_i2c_clr(v, bit) 921 void *v; 922 u_int8_t bit; 923 { 924 tl_softc_t *sc = v; 925 926 switch (bit) { 927 case I2C_DATA: 928 netsio_clr(sc, TL_NETSIO_EDATA); 929 break; 930 case I2C_CLOCK: 931 netsio_clr(sc, TL_NETSIO_ECLOCK); 932 break; 933 case I2C_TXEN: 934 netsio_clr(sc, TL_NETSIO_ETXEN); 935 break; 936 default: 937 printf("tl_i2c_clr: unknown bit %d\n", bit); 938 } 939 return; 940 } 941 942 int tl_i2c_read(v, bit) 943 void *v; 944 u_int8_t bit; 945 { 946 tl_softc_t *sc = v; 947 948 switch (bit) { 949 case I2C_DATA: 950 return netsio_read(sc, TL_NETSIO_EDATA); 951 break; 952 case I2C_CLOCK: 953 return netsio_read(sc, TL_NETSIO_ECLOCK); 954 break; 955 case I2C_TXEN: 956 return netsio_read(sc, TL_NETSIO_ETXEN); 957 break; 958 default: 959 printf("tl_i2c_read: unknown bit %d\n", bit); 960 return -1; 961 } 962 } 963 964 static int 965 tl_intr(v) 966 void *v; 967 { 968 tl_softc_t *sc = v; 969 struct ifnet *ifp = &sc->tl_if; 970 struct Rx_list *Rx; 971 struct Tx_list *Tx; 972 struct mbuf *m; 973 u_int32_t int_type, int_reg; 974 int ack = 0; 975 int size; 976 977 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 978 int_type = int_reg & TL_INTR_MASK; 979 if (int_type == 0) 980 return 0; 981 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 982 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 983 int_type, int_reg); 984 #endif 985 /* disable interrupts */ 986 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 987 switch(int_type & TL_INTR_MASK) { 988 case TL_INTR_RxEOF: 989 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 990 sizeof(struct tl_Rx_list) * TL_NBUF, 991 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 992 while(le32toh(sc->active_Rx->hw_list->stat) & 993 TL_RX_CSTAT_CPLT) { 994 /* dequeue and requeue at end of list */ 995 ack++; 996 Rx = sc->active_Rx; 997 sc->active_Rx = Rx->next; 998 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 999 MCLBYTES, BUS_DMASYNC_POSTREAD); 1000 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1001 m = Rx->m; 1002 size = le32toh(Rx->hw_list->stat) >> 16; 1003 #ifdef TLDEBUG_RX 1004 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1005 Rx, size); 1006 #endif 1007 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1008 /* 1009 * No new mbuf, reuse the same. This means 1010 * that this packet 1011 * is lost 1012 */ 1013 m = NULL; 1014 #ifdef TL_PRIV_STATS 1015 sc->ierr_nomem++; 1016 #endif 1017 #ifdef TLDEBUG 1018 printf("%s: out of mbuf, lost input packet\n", 1019 sc->sc_dev.dv_xname); 1020 #endif 1021 } 1022 Rx->next = NULL; 1023 Rx->hw_list->fwd = 0; 1024 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1025 sc->last_Rx->next = Rx; 1026 sc->last_Rx = Rx; 1027 1028 /* deliver packet */ 1029 if (m) { 1030 if (size < sizeof(struct ether_header)) { 1031 m_freem(m); 1032 continue; 1033 } 1034 m->m_pkthdr.rcvif = ifp; 1035 m->m_pkthdr.len = m->m_len = size; 1036 #ifdef TLDEBUG_RX 1037 { struct ether_header *eh = 1038 mtod(m, struct ether_header *); 1039 printf("tl_intr: Rx packet:\n"); 1040 ether_printheader(eh); } 1041 #endif 1042 #if NBPFILTER > 0 1043 if (ifp->if_bpf) 1044 bpf_mtap(ifp->if_bpf, m); 1045 #endif /* NBPFILTER > 0 */ 1046 (*ifp->if_input)(ifp, m); 1047 } 1048 } 1049 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1050 sizeof(struct tl_Rx_list) * TL_NBUF, 1051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1052 #ifdef TLDEBUG_RX 1053 printf("TL_INTR_RxEOF: ack %d\n", ack); 1054 #else 1055 if (ack == 0) { 1056 printf("%s: EOF intr without anything to read !\n", 1057 sc->sc_dev.dv_xname); 1058 tl_reset(sc); 1059 /* shedule reinit of the board */ 1060 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1061 return(1); 1062 } 1063 #endif 1064 break; 1065 case TL_INTR_RxEOC: 1066 ack++; 1067 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1068 sizeof(struct tl_Rx_list) * TL_NBUF, 1069 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1070 #ifdef TLDEBUG_RX 1071 printf("TL_INTR_RxEOC: ack %d\n", ack); 1072 #endif 1073 #ifdef DIAGNOSTIC 1074 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1075 printf("%s: Rx EOC interrupt and active Tx list not " 1076 "cleared\n", sc->sc_dev.dv_xname); 1077 return 0; 1078 } else 1079 #endif 1080 { 1081 /* 1082 * write adress of Rx list and send Rx GO command, ack 1083 * interrupt and enable interrupts in one command 1084 */ 1085 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1086 TL_HR_WRITE(sc, TL_HOST_CMD, 1087 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1088 HOST_CMD_ACK | HOST_CMD_IntOn); 1089 return 1; 1090 } 1091 case TL_INTR_TxEOF: 1092 case TL_INTR_TxEOC: 1093 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1094 sizeof(struct tl_Tx_list) * TL_NBUF, 1095 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1096 while ((Tx = sc->active_Tx) != NULL) { 1097 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1098 break; 1099 ack++; 1100 #ifdef TLDEBUG_TX 1101 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1102 Tx->hw_listaddr); 1103 #endif 1104 Tx->hw_list->stat = 0; 1105 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1106 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1107 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1108 m_freem(Tx->m); 1109 Tx->m = NULL; 1110 sc->active_Tx = Tx->next; 1111 if (sc->active_Tx == NULL) 1112 sc->last_Tx = NULL; 1113 Tx->next = sc->Free_Tx; 1114 sc->Free_Tx = Tx; 1115 } 1116 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1117 sizeof(struct tl_Tx_list) * TL_NBUF, 1118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1119 /* if this was an EOC, ACK immediatly */ 1120 if (int_type == TL_INTR_TxEOC) { 1121 #ifdef TLDEBUG_TX 1122 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1123 ack); 1124 #endif 1125 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1126 HOST_CMD_ACK | HOST_CMD_IntOn); 1127 if ( sc->active_Tx != NULL) { 1128 /* needs a Tx go command */ 1129 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1130 sc->active_Tx->hw_listaddr); 1131 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1132 } 1133 sc->tl_if.if_timer = 0; 1134 if (sc->tl_if.if_snd.ifq_head != NULL) 1135 tl_ifstart(&sc->tl_if); 1136 return 1; 1137 } 1138 #ifdef TLDEBUG 1139 else { 1140 printf("TL_INTR_TxEOF: ack %d\n", ack); 1141 } 1142 #endif 1143 sc->tl_if.if_timer = 0; 1144 if (sc->tl_if.if_snd.ifq_head != NULL) 1145 tl_ifstart(&sc->tl_if); 1146 break; 1147 case TL_INTR_Stat: 1148 ack++; 1149 #ifdef TLDEBUG 1150 printf("TL_INTR_Stat: ack %d\n", ack); 1151 #endif 1152 tl_read_stats(sc); 1153 break; 1154 case TL_INTR_Adc: 1155 if (int_reg & TL_INTVec_MASK) { 1156 /* adapter check conditions */ 1157 printf("%s: check condition, intvect=0x%x, " 1158 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1159 int_reg & TL_INTVec_MASK, 1160 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1161 tl_reset(sc); 1162 /* shedule reinit of the board */ 1163 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1164 return(1); 1165 } else { 1166 u_int8_t netstat; 1167 /* Network status */ 1168 netstat = 1169 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1170 printf("%s: network status, NetSts=%x\n", 1171 sc->sc_dev.dv_xname, netstat); 1172 /* Ack interrupts */ 1173 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1174 netstat); 1175 ack++; 1176 } 1177 break; 1178 default: 1179 printf("%s: unhandled interrupt code %x!\n", 1180 sc->sc_dev.dv_xname, int_type); 1181 ack++; 1182 } 1183 1184 if (ack) { 1185 /* Ack the interrupt and enable interrupts */ 1186 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1187 HOST_CMD_IntOn); 1188 return 1; 1189 } 1190 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1191 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1192 return 0; 1193 } 1194 1195 static int 1196 tl_ifioctl(ifp, cmd, data) 1197 struct ifnet *ifp; 1198 ioctl_cmd_t cmd; 1199 caddr_t data; 1200 { 1201 struct tl_softc *sc = ifp->if_softc; 1202 struct ifreq *ifr = (struct ifreq *)data; 1203 int s, error; 1204 1205 s = splnet(); 1206 switch(cmd) { 1207 case SIOCSIFADDR: { 1208 struct ifaddr *ifa = (struct ifaddr *)data; 1209 sc->tl_if.if_flags |= IFF_UP; 1210 if ((error = tl_init(sc)) != NULL) { 1211 sc->tl_if.if_flags &= ~IFF_UP; 1212 break; 1213 } 1214 switch (ifa->ifa_addr->sa_family) { 1215 #ifdef INET 1216 case AF_INET: 1217 arp_ifinit(ifp, ifa); 1218 break; 1219 #endif 1220 #ifdef NS 1221 case AF_NS: { 1222 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1223 1224 if (ns_nullhost(*ina)) 1225 ina->x_host = 1226 *(union ns_host*) LLADDR(ifp->if_sadl); 1227 else 1228 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1229 ifp->if_addrlen); 1230 break; 1231 } 1232 #endif 1233 default: 1234 break; 1235 } 1236 break; 1237 } 1238 case SIOCSIFFLAGS: 1239 { 1240 u_int8_t reg; 1241 /* 1242 * If interface is marked up and not running, then start it. 1243 * If it is marked down and running, stop it. 1244 */ 1245 if (ifp->if_flags & IFF_UP) { 1246 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1247 error = tl_init(sc); 1248 /* all flags have been handled by init */ 1249 break; 1250 } 1251 error = 0; 1252 reg = tl_intreg_read_byte(sc, 1253 TL_INT_NET + TL_INT_NetCmd); 1254 if (ifp->if_flags & IFF_PROMISC) 1255 reg |= TL_NETCOMMAND_CAF; 1256 else 1257 reg &= ~TL_NETCOMMAND_CAF; 1258 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1259 reg); 1260 #ifdef TL_PRIV_STATS 1261 if (ifp->if_flags & IFF_LINK0) { 1262 ifp->if_flags &= ~IFF_LINK0; 1263 printf("%s errors statistics\n", 1264 sc->sc_dev.dv_xname); 1265 printf(" %4d RX buffer overrun\n", 1266 sc->ierr_overr); 1267 printf(" %4d RX code error\n", 1268 sc->ierr_code); 1269 printf(" %4d RX crc error\n", 1270 sc->ierr_crc); 1271 printf(" %4d RX out of memory\n", 1272 sc->ierr_nomem); 1273 printf(" %4d TX buffer underrun\n", 1274 sc->oerr_underr); 1275 printf(" %4d TX deffered frames\n", 1276 sc->oerr_deffered); 1277 printf(" %4d TX single collisions\n", 1278 sc->oerr_coll); 1279 printf(" %4d TX multi collisions\n", 1280 sc->oerr_multicoll); 1281 printf(" %4d TX exessive collisions\n", 1282 sc->oerr_exesscoll); 1283 printf(" %4d TX late collisions\n", 1284 sc->oerr_latecoll); 1285 printf(" %4d TX carrier loss\n", 1286 sc->oerr_carrloss); 1287 printf(" %4d TX mbuf copy\n", 1288 sc->oerr_mcopy); 1289 } 1290 #endif 1291 } else { 1292 if (ifp->if_flags & IFF_RUNNING) 1293 tl_shutdown(sc); 1294 error = 0; 1295 } 1296 break; 1297 } 1298 case SIOCADDMULTI: 1299 case SIOCDELMULTI: 1300 /* 1301 * Update multicast listeners 1302 */ 1303 if (cmd == SIOCADDMULTI) 1304 error = ether_addmulti(ifr, &sc->tl_ec); 1305 else 1306 error = ether_delmulti(ifr, &sc->tl_ec); 1307 if (error == ENETRESET) { 1308 tl_addr_filter(sc); 1309 error = 0; 1310 } 1311 break; 1312 case SIOCSIFMEDIA: 1313 case SIOCGIFMEDIA: 1314 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1315 break; 1316 default: 1317 error = EINVAL; 1318 } 1319 splx(s); 1320 return error; 1321 } 1322 1323 static void 1324 tl_ifstart(ifp) 1325 struct ifnet *ifp; 1326 { 1327 tl_softc_t *sc = ifp->if_softc; 1328 struct mbuf *mb_head; 1329 struct Tx_list *Tx; 1330 int segment, size; 1331 int again = 0, error; 1332 1333 txloop: 1334 /* If we don't have more space ... */ 1335 if (sc->Free_Tx == NULL) { 1336 #ifdef TLDEBUG 1337 printf("tl_ifstart: No free TX list\n"); 1338 #endif 1339 return; 1340 } 1341 /* Grab a paquet for output */ 1342 IF_DEQUEUE(&ifp->if_snd, mb_head); 1343 if (mb_head == NULL) { 1344 #ifdef TLDEBUG_TX 1345 printf("tl_ifstart: nothing to send\n"); 1346 #endif 1347 return; 1348 } 1349 Tx = sc->Free_Tx; 1350 sc->Free_Tx = Tx->next; 1351 Tx->next = NULL; 1352 /* 1353 * Go through each of the mbufs in the chain and initialize 1354 * the transmit list descriptors with the physical address 1355 * and size of the mbuf. 1356 */ 1357 tbdinit: 1358 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1359 Tx->m = mb_head; 1360 size = mb_head->m_pkthdr.len; 1361 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1362 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1363 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1364 struct mbuf *mn; 1365 /* 1366 * We ran out of segments, or we will. We have to recopy this 1367 * mbuf chain first. 1368 */ 1369 if (error == 0) 1370 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1371 if (again) { 1372 /* already copyed, can't do much more */ 1373 m_freem(mb_head); 1374 goto bad; 1375 } 1376 again = 1; 1377 #ifdef TLDEBUG_TX 1378 printf("tl_ifstart: need to copy mbuf\n"); 1379 #endif 1380 #ifdef TL_PRIV_STATS 1381 sc->oerr_mcopy++; 1382 #endif 1383 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1384 if (mn == NULL) { 1385 m_freem(mb_head); 1386 goto bad; 1387 } 1388 if (mb_head->m_pkthdr.len > MHLEN) { 1389 MCLGET(mn, M_DONTWAIT); 1390 if ((mn->m_flags & M_EXT) == 0) { 1391 m_freem(mn); 1392 m_freem(mb_head); 1393 goto bad; 1394 } 1395 } 1396 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1397 mtod(mn, caddr_t)); 1398 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1399 m_freem(mb_head); 1400 mb_head = mn; 1401 goto tbdinit; 1402 } 1403 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1404 Tx->hw_list->seg[segment].data_addr = 1405 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1406 Tx->hw_list->seg[segment].data_count = 1407 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1408 } 1409 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1410 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1411 /* We are at end of mbuf chain. check the size and 1412 * see if it needs to be extended 1413 */ 1414 if (size < ETHER_MIN_TX) { 1415 #ifdef DIAGNOSTIC 1416 if (segment >= TL_NSEG) { 1417 panic("tl_ifstart: to much segmets (%d)\n", segment); 1418 } 1419 #endif 1420 /* 1421 * add the nullbuf in the seg 1422 */ 1423 Tx->hw_list->seg[segment].data_count = 1424 htole32(ETHER_MIN_TX - size); 1425 size = ETHER_MIN_TX; 1426 Tx->hw_list->seg[segment].data_addr = 1427 htole32(nullbuf_dmamap->dm_segs[0].ds_addr); 1428 segment++; 1429 } 1430 /* The list is done, finish the list init */ 1431 Tx->hw_list->seg[segment-1].data_count |= 1432 htole32(TL_LAST_SEG); 1433 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1434 #ifdef TLDEBUG_TX 1435 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1436 le32toh(Tx->hw_list->stat)); 1437 #if 0 1438 for(segment = 0; segment < TL_NSEG; segment++) { 1439 printf(" seg %d addr 0x%x len 0x%x\n", 1440 segment, 1441 le32toh(Tx->hw_list->seg[segment].data_addr), 1442 le32toh(Tx->hw_list->seg[segment].data_count)); 1443 } 1444 #endif 1445 #endif 1446 if (sc->active_Tx == NULL) { 1447 sc->active_Tx = sc->last_Tx = Tx; 1448 #ifdef TLDEBUG_TX 1449 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1450 Tx->hw_listaddr)); 1451 #endif 1452 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1453 sizeof(struct tl_Tx_list) * TL_NBUF, 1454 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1455 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1456 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1457 } else { 1458 #ifdef TLDEBUG_TX 1459 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1460 Tx->hw_listaddr)); 1461 #endif 1462 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1463 sc->last_Tx->next = Tx; 1464 sc->last_Tx = Tx; 1465 #ifdef DIAGNOSTIC 1466 if (sc->last_Tx->hw_list->fwd & 0x7) 1467 printf("%s: physical addr 0x%x of list not properly " 1468 "aligned\n", 1469 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1470 #endif 1471 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1472 sizeof(struct tl_Tx_list) * TL_NBUF, 1473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1474 } 1475 #if NBPFILTER > 0 1476 /* Pass packet to bpf if there is a listener */ 1477 if (ifp->if_bpf) 1478 bpf_mtap(ifp->if_bpf, mb_head); 1479 #endif 1480 /* 1481 * Set a 5 second timer just in case we don't hear from the card again. 1482 */ 1483 ifp->if_timer = 5; 1484 goto txloop; 1485 bad: 1486 #ifdef TLDEBUG 1487 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1488 #endif 1489 Tx->next = sc->Free_Tx; 1490 sc->Free_Tx = Tx; 1491 return; 1492 } 1493 1494 static void 1495 tl_ifwatchdog(ifp) 1496 struct ifnet *ifp; 1497 { 1498 tl_softc_t *sc = ifp->if_softc; 1499 1500 if ((ifp->if_flags & IFF_RUNNING) == 0) 1501 return; 1502 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1503 ifp->if_oerrors++; 1504 tl_init(sc); 1505 } 1506 1507 static int 1508 tl_mediachange(ifp) 1509 struct ifnet *ifp; 1510 { 1511 1512 if (ifp->if_flags & IFF_UP) 1513 tl_init(ifp->if_softc); 1514 return (0); 1515 } 1516 1517 static void 1518 tl_mediastatus(ifp, ifmr) 1519 struct ifnet *ifp; 1520 struct ifmediareq *ifmr; 1521 { 1522 tl_softc_t *sc = ifp->if_softc; 1523 1524 mii_pollstat(&sc->tl_mii); 1525 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1526 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1527 } 1528 1529 static int tl_add_RxBuff(sc, Rx, oldm) 1530 tl_softc_t *sc; 1531 struct Rx_list *Rx; 1532 struct mbuf *oldm; 1533 { 1534 struct mbuf *m; 1535 int error; 1536 1537 MGETHDR(m, M_DONTWAIT, MT_DATA); 1538 if (m != NULL) { 1539 MCLGET(m, M_DONTWAIT); 1540 if ((m->m_flags & M_EXT) == 0) { 1541 m_freem(m); 1542 if (oldm == NULL) 1543 return 0; 1544 m = oldm; 1545 m->m_data = m->m_ext.ext_buf; 1546 } 1547 } else { 1548 if (oldm == NULL) 1549 return 0; 1550 m = oldm; 1551 m->m_data = m->m_ext.ext_buf; 1552 } 1553 1554 /* (re)init the Rx_list struct */ 1555 1556 Rx->m = m; 1557 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1558 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1559 printf("%s: bus_dmamap_load() failed (error %d) for " 1560 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1561 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1562 m_freem(m); 1563 Rx->m = NULL; 1564 return 0; 1565 } 1566 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1567 MCLBYTES, BUS_DMASYNC_PREREAD); 1568 /* 1569 * Move the data pointer up so that the incoming data packet 1570 * will be 32-bit aligned. 1571 */ 1572 m->m_data += 2; 1573 1574 Rx->hw_list->stat = 1575 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1576 Rx->hw_list->seg.data_count = 1577 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1578 Rx->hw_list->seg.data_addr = 1579 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1580 return (m != oldm); 1581 } 1582 1583 static void tl_ticks(v) 1584 void *v; 1585 { 1586 tl_softc_t *sc = v; 1587 1588 tl_read_stats(sc); 1589 1590 /* Tick the MII. */ 1591 mii_tick(&sc->tl_mii); 1592 1593 /* read statistics every seconds */ 1594 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1595 } 1596 1597 static void 1598 tl_read_stats(sc) 1599 tl_softc_t *sc; 1600 { 1601 u_int32_t reg; 1602 int ierr_overr; 1603 int ierr_code; 1604 int ierr_crc; 1605 int oerr_underr; 1606 int oerr_deffered; 1607 int oerr_coll; 1608 int oerr_multicoll; 1609 int oerr_exesscoll; 1610 int oerr_latecoll; 1611 int oerr_carrloss; 1612 struct ifnet *ifp = &sc->tl_if; 1613 1614 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1615 ifp->if_opackets += reg & 0x00ffffff; 1616 oerr_underr = reg >> 24; 1617 1618 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1619 ifp->if_ipackets += reg & 0x00ffffff; 1620 ierr_overr = reg >> 24; 1621 1622 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1623 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1624 ierr_code = (reg & TL_FERR_CODE) >> 24; 1625 oerr_deffered = (reg & TL_FERR_DEF); 1626 1627 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1628 oerr_multicoll = (reg & TL_COL_MULTI); 1629 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1630 1631 reg = tl_intreg_read(sc, TL_INT_LERR); 1632 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1633 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1634 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1635 1636 1637 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1638 oerr_carrloss; 1639 ifp->if_collisions += oerr_coll + oerr_multicoll; 1640 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1641 1642 if (ierr_overr) 1643 printf("%s: receiver ring buffer overrun\n", 1644 sc->sc_dev.dv_xname); 1645 if (oerr_underr) 1646 printf("%s: transmit buffer underrun\n", 1647 sc->sc_dev.dv_xname); 1648 #ifdef TL_PRIV_STATS 1649 sc->ierr_overr += ierr_overr; 1650 sc->ierr_code += ierr_code; 1651 sc->ierr_crc += ierr_crc; 1652 sc->oerr_underr += oerr_underr; 1653 sc->oerr_deffered += oerr_deffered; 1654 sc->oerr_coll += oerr_coll; 1655 sc->oerr_multicoll += oerr_multicoll; 1656 sc->oerr_exesscoll += oerr_exesscoll; 1657 sc->oerr_latecoll += oerr_latecoll; 1658 sc->oerr_carrloss += oerr_carrloss; 1659 #endif 1660 } 1661 1662 static void tl_addr_filter(sc) 1663 tl_softc_t *sc; 1664 { 1665 struct ether_multistep step; 1666 struct ether_multi *enm; 1667 u_int32_t hash[2] = {0, 0}; 1668 int i; 1669 1670 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1671 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1672 while (enm != NULL) { 1673 #ifdef TLDEBUG 1674 printf("tl_addr_filter: addrs %s %s\n", 1675 ether_sprintf(enm->enm_addrlo), 1676 ether_sprintf(enm->enm_addrhi)); 1677 #endif 1678 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1679 i = tl_multicast_hash(enm->enm_addrlo); 1680 hash[i/32] |= 1 << (i%32); 1681 } else { 1682 hash[0] = hash[1] = 0xffffffff; 1683 sc->tl_if.if_flags |= IFF_ALLMULTI; 1684 break; 1685 } 1686 ETHER_NEXT_MULTI(step, enm); 1687 } 1688 #ifdef TLDEBUG 1689 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1690 #endif 1691 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1692 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1693 } 1694 1695 static int tl_multicast_hash(a) 1696 u_int8_t *a; 1697 { 1698 int hash; 1699 1700 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1701 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1702 1703 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1704 DA(a,36), DA(a,42)); 1705 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1706 DA(a,37), DA(a,43)) << 1; 1707 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1708 DA(a,38), DA(a,44)) << 2; 1709 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1710 DA(a,39), DA(a,45)) << 3; 1711 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1712 DA(a,40), DA(a,46)) << 4; 1713 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1714 DA(a,41), DA(a,47)) << 5; 1715 1716 return hash; 1717 } 1718 1719 #if defined(TLDEBUG_RX) 1720 void 1721 ether_printheader(eh) 1722 struct ether_header *eh; 1723 { 1724 u_char *c = (char*)eh; 1725 int i; 1726 for (i=0; i<sizeof(struct ether_header); i++) 1727 printf("%x ", (u_int)c[i]); 1728 printf("\n"); 1729 } 1730 #endif 1731
Indexes created Tue Sep 23 21:09:50 GMT 2025