if_tl.c revision 1.47
1 /* $NetBSD: if_tl.c,v 1.47 2001/11/13 07:48:45 lukem Exp $ */ 2 3 /* XXX ALTQ XXX */ 4 5 /* 6 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Texas Instruments ThunderLAN ethernet controller 36 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 37 * available from www.ti.com 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.47 2001/11/13 07:48:45 lukem Exp $"); 42 43 #undef TLDEBUG 44 #define TL_PRIV_STATS 45 #undef TLDEBUG_RX 46 #undef TLDEBUG_TX 47 #undef TLDEBUG_ADDR 48 49 #include "opt_inet.h" 50 #include "opt_ns.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/mbuf.h> 55 #include <sys/protosw.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 62 #include <sys/device.h> 63 64 #include <net/if.h> 65 #if defined(SIOCSIFMEDIA) 66 #include <net/if_media.h> 67 #endif 68 #include <net/if_types.h> 69 #include <net/if_dl.h> 70 #include <net/route.h> 71 #include <net/netisr.h> 72 73 #include "bpfilter.h" 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #endif 85 86 #ifdef NS 87 #include <netns/ns.h> 88 #include <netns/ns_if.h> 89 #endif 90 91 #if defined(__NetBSD__) 92 #include <net/if_ether.h> 93 #include <uvm/uvm_extern.h> 94 #if defined(INET) 95 #include <netinet/if_inarp.h> 96 #endif 97 98 #include <machine/bus.h> 99 #include <machine/intr.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/i2c/i2c_bus.h> 106 #include <dev/i2c/i2c_eeprom.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/mii/tlphyvar.h> 112 113 #include <dev/pci/if_tlregs.h> 114 #include <dev/pci/if_tlvar.h> 115 #endif /* __NetBSD__ */ 116 117 /* number of transmit/receive buffers */ 118 #ifndef TL_NBUF 119 #define TL_NBUF 10 120 #endif 121 122 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 123 static void tl_pci_attach __P((struct device *, struct device *, void *)); 124 static int tl_intr __P((void *)); 125 126 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 127 static int tl_mediachange __P((struct ifnet *)); 128 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 129 static void tl_ifwatchdog __P((struct ifnet *)); 130 static void tl_shutdown __P((void*)); 131 132 static void tl_ifstart __P((struct ifnet *)); 133 static void tl_reset __P((tl_softc_t*)); 134 static int tl_init __P((struct ifnet *)); 135 static void tl_stop __P((struct ifnet *, int)); 136 static void tl_restart __P((void *)); 137 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 138 static void tl_read_stats __P((tl_softc_t*)); 139 static void tl_ticks __P((void*)); 140 static int tl_multicast_hash __P((u_int8_t*)); 141 static void tl_addr_filter __P((tl_softc_t*)); 142 143 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 145 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 146 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 147 148 void tl_mii_sync __P((struct tl_softc *)); 149 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 150 151 152 #if defined(TLDEBUG_RX) 153 static void ether_printheader __P((struct ether_header*)); 154 #endif 155 156 int tl_mii_read __P((struct device *, int, int)); 157 void tl_mii_write __P((struct device *, int, int, int)); 158 159 void tl_statchg __P((struct device *)); 160 161 void tl_i2c_set __P((void*, u_int8_t)); 162 void tl_i2c_clr __P((void*, u_int8_t)); 163 int tl_i2c_read __P((void*, u_int8_t)); 164 165 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 167 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 168 static __inline void netsio_clr(sc, bits) 169 tl_softc_t* sc; 170 u_int8_t bits; 171 { 172 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 173 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 174 } 175 static __inline void netsio_set(sc, bits) 176 tl_softc_t* sc; 177 u_int8_t bits; 178 { 179 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 180 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 181 } 182 static __inline u_int8_t netsio_read(sc, bits) 183 tl_softc_t* sc; 184 u_int8_t bits; 185 { 186 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 187 } 188 189 struct cfattach tl_ca = { 190 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 191 }; 192 193 const struct tl_product_desc tl_compaq_products[] = { 194 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 195 "Compaq Netelligent 10/100 TX" }, 196 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 197 "Compaq Netelligent 10 T" }, 198 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 199 "Compaq Integrated NetFlex 3/P" }, 200 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 201 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 202 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 203 "Compaq Dual Port Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 205 "Compaq Deskpro 4000 5233MMX" }, 206 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 207 "Compaq NetFlex 3/P w/ BNC" }, 208 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 209 "Compaq NetFlex 3/P" }, 210 { 0, 0, NULL }, 211 }; 212 213 const struct tl_product_desc tl_ti_products[] = { 214 /* 215 * Built-in Ethernet on the TI TravelMate 5000 216 * docking station; better product description? 217 */ 218 { PCI_PRODUCT_TI_TLAN, 0, 219 "Texas Instruments ThunderLAN" }, 220 { 0, 0, NULL }, 221 }; 222 223 struct tl_vendor_desc { 224 u_int32_t tv_vendor; 225 const struct tl_product_desc *tv_products; 226 }; 227 228 const struct tl_vendor_desc tl_vendors[] = { 229 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 230 { PCI_VENDOR_TI, tl_ti_products }, 231 { 0, NULL }, 232 }; 233 234 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 235 236 const struct tl_product_desc * 237 tl_lookup_product(id) 238 u_int32_t id; 239 { 240 const struct tl_product_desc *tp; 241 const struct tl_vendor_desc *tv; 242 243 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 244 if (PCI_VENDOR(id) == tv->tv_vendor) 245 break; 246 247 if ((tp = tv->tv_products) == NULL) 248 return (NULL); 249 250 for (; tp->tp_desc != NULL; tp++) 251 if (PCI_PRODUCT(id) == tp->tp_product) 252 break; 253 254 if (tp->tp_desc == NULL) 255 return (NULL); 256 257 return (tp); 258 } 259 260 static int 261 tl_pci_match(parent, match, aux) 262 struct device *parent; 263 struct cfdata *match; 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 267 268 if (tl_lookup_product(pa->pa_id) != NULL) 269 return (1); 270 271 return (0); 272 } 273 274 static void 275 tl_pci_attach(parent, self, aux) 276 struct device * parent; 277 struct device * self; 278 void * aux; 279 { 280 tl_softc_t *sc = (tl_softc_t *)self; 281 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 282 const struct tl_product_desc *tp; 283 struct ifnet * const ifp = &sc->tl_if; 284 bus_space_tag_t iot, memt; 285 bus_space_handle_t ioh, memh; 286 pci_intr_handle_t intrhandle; 287 const char *intrstr; 288 int i, tmp, ioh_valid, memh_valid; 289 int reg_io, reg_mem; 290 pcireg_t reg10, reg14; 291 pcireg_t csr; 292 293 printf("\n"); 294 295 callout_init(&sc->tl_tick_ch); 296 callout_init(&sc->tl_restart_ch); 297 298 tp = tl_lookup_product(pa->pa_id); 299 if (tp == NULL) 300 panic("tl_pci_attach: impossible"); 301 sc->tl_product = tp; 302 303 /* 304 * Map the card space. Fisrt we have to find the I/O and MEM 305 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 306 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 307 * The ThunderLAN manual is not consistent about this either (there 308 * are both cases in code examples). 309 */ 310 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 311 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 312 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 313 reg_io = 0x10; 314 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 315 reg_io = 0x14; 316 else 317 reg_io = 0; 318 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 319 reg_mem = 0x10; 320 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 321 reg_mem = 0x14; 322 else 323 reg_mem = 0; 324 325 if (reg_io != 0) 326 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 327 0, &iot, &ioh, NULL, NULL) == 0); 328 else 329 ioh_valid = 0; 330 if (reg_mem != 0) 331 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 332 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 333 0, &memt, &memh, NULL, NULL) == 0); 334 else 335 memh_valid = 0; 336 337 if (ioh_valid) { 338 sc->tl_bustag = iot; 339 sc->tl_bushandle = ioh; 340 } else if (memh_valid) { 341 sc->tl_bustag = memt; 342 sc->tl_bushandle = memh; 343 } else { 344 printf("%s: unable to map device registers\n", 345 sc->sc_dev.dv_xname); 346 return; 347 } 348 sc->tl_dmatag = pa->pa_dmat; 349 350 /* Enable the device. */ 351 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 352 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 353 csr | PCI_COMMAND_MASTER_ENABLE); 354 355 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 356 357 tl_reset(sc); 358 359 /* fill in the i2c struct */ 360 sc->i2cbus.adapter_softc = sc; 361 sc->i2cbus.set_bit = tl_i2c_set; 362 sc->i2cbus.clr_bit = tl_i2c_clr; 363 sc->i2cbus.read_bit = tl_i2c_read; 364 365 #ifdef TLDEBUG 366 printf("default values of INTreg: 0x%x\n", 367 tl_intreg_read(sc, TL_INT_Defaults)); 368 #endif 369 370 /* read mac addr */ 371 for (i=0; i<ETHER_ADDR_LEN; i++) { 372 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 373 if (tmp < 0) { 374 printf("%s: error reading Ethernet adress\n", 375 sc->sc_dev.dv_xname); 376 return; 377 } else { 378 sc->tl_enaddr[i] = tmp; 379 } 380 } 381 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 382 ether_sprintf(sc->tl_enaddr)); 383 384 /* Map and establish interrupts */ 385 if (pci_intr_map(pa, &intrhandle)) { 386 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 387 return; 388 } 389 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 390 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 391 tl_intr, sc); 392 if (sc->tl_ih == NULL) { 393 printf("%s: couldn't establish interrupt", 394 sc->sc_dev.dv_xname); 395 if (intrstr != NULL) 396 printf(" at %s", intrstr); 397 printf("\n"); 398 return; 399 } 400 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 401 402 /* init these pointers, so that tl_shutdown won't try to read them */ 403 sc->Rx_list = NULL; 404 sc->Tx_list = NULL; 405 406 /* allocate DMA-safe memory for control structs */ 407 if (bus_dmamem_alloc(sc->tl_dmatag, 408 PAGE_SIZE, 0, PAGE_SIZE, 409 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 410 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 411 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 412 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 413 printf("%s: can't allocate DMA memory for lists\n", 414 sc->sc_dev.dv_xname); 415 return; 416 } 417 /* 418 * Add shutdown hook so that DMA is disabled prior to reboot. Not 419 * doing do could allow DMA to corrupt kernel memory during the 420 * reboot before the driver initializes. 421 */ 422 (void) shutdownhook_establish(tl_shutdown, ifp); 423 424 /* 425 * Initialize our media structures and probe the MII. 426 * 427 * Note that we don't care about the media instance. We 428 * are expecting to have multiple PHYs on the 10/100 cards, 429 * and on those cards we exclude the internal PHY from providing 430 * 10baseT. By ignoring the instance, it allows us to not have 431 * to specify it on the command line when switching media. 432 */ 433 sc->tl_mii.mii_ifp = ifp; 434 sc->tl_mii.mii_readreg = tl_mii_read; 435 sc->tl_mii.mii_writereg = tl_mii_write; 436 sc->tl_mii.mii_statchg = tl_statchg; 437 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 438 tl_mediastatus); 439 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 440 MII_OFFSET_ANY, 0); 441 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 442 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 444 } else 445 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 446 447 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 448 sc->tl_if.if_softc = sc; 449 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 450 ifp->if_ioctl = tl_ifioctl; 451 ifp->if_start = tl_ifstart; 452 ifp->if_watchdog = tl_ifwatchdog; 453 ifp->if_init = tl_init; 454 ifp->if_stop = tl_stop; 455 ifp->if_timer = 0; 456 if_attach(ifp); 457 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 458 } 459 460 static void 461 tl_reset(sc) 462 tl_softc_t *sc; 463 { 464 int i; 465 466 /* read stats */ 467 if (sc->tl_if.if_flags & IFF_RUNNING) { 468 callout_stop(&sc->tl_tick_ch); 469 tl_read_stats(sc); 470 } 471 /* Reset adapter */ 472 TL_HR_WRITE(sc, TL_HOST_CMD, 473 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 474 DELAY(100000); 475 /* Disable interrupts */ 476 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 477 /* setup aregs & hash */ 478 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 479 tl_intreg_write(sc, i, 0); 480 #ifdef TLDEBUG_ADDR 481 printf("Areg & hash registers: \n"); 482 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 483 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 484 #endif 485 /* Setup NetConfig */ 486 tl_intreg_write(sc, TL_INT_NetConfig, 487 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 488 /* Bsize: accept default */ 489 /* TX commit in Acommit: accept default */ 490 /* Load Ld_tmr and Ld_thr */ 491 /* Ld_tmr = 3 */ 492 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 493 /* Ld_thr = 0 */ 494 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 495 /* Unreset MII */ 496 netsio_set(sc, TL_NETSIO_NMRST); 497 DELAY(100000); 498 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 499 } 500 501 static void tl_shutdown(v) 502 void *v; 503 { 504 tl_stop(v, 1); 505 } 506 507 static void tl_stop(ifp, disable) 508 struct ifnet *ifp; 509 int disable; 510 { 511 tl_softc_t *sc = ifp->if_softc; 512 struct Tx_list *Tx; 513 int i; 514 515 if ((ifp->if_flags & IFF_RUNNING) == 0) 516 return; 517 /* disable interrupts */ 518 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 519 /* stop TX and RX channels */ 520 TL_HR_WRITE(sc, TL_HOST_CMD, 521 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 522 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 523 DELAY(100000); 524 525 /* stop statistics reading loop, read stats */ 526 callout_stop(&sc->tl_tick_ch); 527 tl_read_stats(sc); 528 529 /* Down the MII. */ 530 mii_down(&sc->tl_mii); 531 532 /* deallocate memory allocations */ 533 if (sc->Rx_list) { 534 for (i=0; i< TL_NBUF; i++) { 535 if (sc->Rx_list[i].m) { 536 bus_dmamap_unload(sc->tl_dmatag, 537 sc->Rx_list[i].m_dmamap); 538 m_freem(sc->Rx_list[i].m); 539 } 540 bus_dmamap_destroy(sc->tl_dmatag, 541 sc->Rx_list[i].m_dmamap); 542 sc->Rx_list[i].m = NULL; 543 } 544 free(sc->Rx_list, M_DEVBUF); 545 sc->Rx_list = NULL; 546 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 547 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 548 sc->hw_Rx_list = NULL; 549 while ((Tx = sc->active_Tx) != NULL) { 550 Tx->hw_list->stat = 0; 551 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 552 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 553 m_freem(Tx->m); 554 sc->active_Tx = Tx->next; 555 Tx->next = sc->Free_Tx; 556 sc->Free_Tx = Tx; 557 } 558 sc->last_Tx = NULL; 559 free(sc->Tx_list, M_DEVBUF); 560 sc->Tx_list = NULL; 561 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 562 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 563 sc->hw_Tx_list = NULL; 564 } 565 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 566 ifp->if_timer = 0; 567 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 568 } 569 570 static void tl_restart(v) 571 void *v; 572 { 573 tl_init(v); 574 } 575 576 static int tl_init(ifp) 577 struct ifnet *ifp; 578 { 579 tl_softc_t *sc = ifp->if_softc; 580 int i, s, error; 581 char *errstring; 582 char *nullbuf; 583 584 s = splnet(); 585 /* cancel any pending IO */ 586 tl_stop(ifp, 1); 587 tl_reset(sc); 588 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 589 splx(s); 590 return 0; 591 } 592 /* Set various register to reasonable value */ 593 /* setup NetCmd in promisc mode if needed */ 594 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 595 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 596 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 597 /* Max receive size : MCLBYTES */ 598 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 599 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 600 (MCLBYTES >> 8) & 0xff); 601 602 /* init MAC addr */ 603 for (i = 0; i < ETHER_ADDR_LEN; i++) 604 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 605 /* add multicast filters */ 606 tl_addr_filter(sc); 607 #ifdef TLDEBUG_ADDR 608 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 609 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 610 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 611 #endif 612 613 /* Pre-allocate receivers mbuf, make the lists */ 614 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 615 M_NOWAIT); 616 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 617 M_NOWAIT); 618 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 619 errstring = "out of memory for lists"; 620 error = ENOMEM; 621 goto bad; 622 } 623 memset(sc->Rx_list, 0, sizeof(struct Rx_list) * TL_NBUF); 624 memset(sc->Tx_list, 0, sizeof(struct Tx_list) * TL_NBUF); 625 error = bus_dmamap_create(sc->tl_dmatag, 626 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 627 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 628 &sc->Rx_dmamap); 629 if (error == 0) 630 error = bus_dmamap_create(sc->tl_dmatag, 631 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 632 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 633 &sc->Tx_dmamap); 634 if (error == 0) 635 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 636 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 637 &sc->null_dmamap); 638 if (error) { 639 errstring = "can't allocate DMA maps for lists"; 640 goto bad; 641 } 642 memset(sc->ctrl, 0, PAGE_SIZE); 643 sc->hw_Rx_list = (void *)sc->ctrl; 644 sc->hw_Tx_list = 645 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 646 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 647 sizeof(struct tl_Tx_list) * TL_NBUF; 648 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 649 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 650 BUS_DMA_WAITOK); 651 if (error == 0) 652 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 653 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 654 BUS_DMA_WAITOK); 655 if (error == 0) 656 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 657 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 658 if (error) { 659 errstring = "can't DMA map DMA memory for lists"; 660 goto bad; 661 } 662 for (i=0; i< TL_NBUF; i++) { 663 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 664 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 665 &sc->Rx_list[i].m_dmamap); 666 if (error == 0) { 667 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 668 TL_NSEG, MCLBYTES, 0, 669 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 670 &sc->Tx_list[i].m_dmamap); 671 } 672 if (error) { 673 errstring = "can't allocate DMA maps for mbufs"; 674 goto bad; 675 } 676 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 677 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 678 + sizeof(struct tl_Rx_list) * i; 679 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 680 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 681 + sizeof(struct tl_Tx_list) * i; 682 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 683 errstring = "out of mbuf for receive list"; 684 error = ENOMEM; 685 goto bad; 686 } 687 if (i > 0) { /* chain the list */ 688 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 689 sc->hw_Rx_list[i-1].fwd = 690 htole32(sc->Rx_list[i].hw_listaddr); 691 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 692 } 693 } 694 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 695 sc->Rx_list[TL_NBUF-1].next = NULL; 696 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 697 sc->Tx_list[TL_NBUF-1].next = NULL; 698 699 sc->active_Rx = &sc->Rx_list[0]; 700 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 701 sc->active_Tx = sc->last_Tx = NULL; 702 sc->Free_Tx = &sc->Tx_list[0]; 703 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 704 sizeof(struct tl_Rx_list) * TL_NBUF, 705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 706 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 707 sizeof(struct tl_Tx_list) * TL_NBUF, 708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 709 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 710 BUS_DMASYNC_PREWRITE); 711 712 /* set media */ 713 mii_mediachg(&sc->tl_mii); 714 715 /* start ticks calls */ 716 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 717 /* write adress of Rx list and enable interrupts */ 718 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 719 TL_HR_WRITE(sc, TL_HOST_CMD, 720 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 721 sc->tl_if.if_flags |= IFF_RUNNING; 722 sc->tl_if.if_flags &= ~IFF_OACTIVE; 723 return 0; 724 bad: 725 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 726 splx(s); 727 return error; 728 } 729 730 731 static u_int32_t 732 tl_intreg_read(sc, reg) 733 tl_softc_t *sc; 734 u_int32_t reg; 735 { 736 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 737 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 738 } 739 740 static u_int8_t 741 tl_intreg_read_byte(sc, reg) 742 tl_softc_t *sc; 743 u_int32_t reg; 744 { 745 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 746 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 747 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 748 } 749 750 static void 751 tl_intreg_write(sc, reg, val) 752 tl_softc_t *sc; 753 u_int32_t reg; 754 u_int32_t val; 755 { 756 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 757 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 758 } 759 760 static void 761 tl_intreg_write_byte(sc, reg, val) 762 tl_softc_t *sc; 763 u_int32_t reg; 764 u_int8_t val; 765 { 766 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 767 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 768 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 769 } 770 771 void 772 tl_mii_sync(sc) 773 struct tl_softc *sc; 774 { 775 int i; 776 777 netsio_clr(sc, TL_NETSIO_MTXEN); 778 for (i = 0; i < 32; i++) { 779 netsio_clr(sc, TL_NETSIO_MCLK); 780 netsio_set(sc, TL_NETSIO_MCLK); 781 } 782 } 783 784 void 785 tl_mii_sendbits(sc, data, nbits) 786 struct tl_softc *sc; 787 u_int32_t data; 788 int nbits; 789 { 790 int i; 791 792 netsio_set(sc, TL_NETSIO_MTXEN); 793 for (i = 1 << (nbits - 1); i; i = i >> 1) { 794 netsio_clr(sc, TL_NETSIO_MCLK); 795 netsio_read(sc, TL_NETSIO_MCLK); 796 if (data & i) 797 netsio_set(sc, TL_NETSIO_MDATA); 798 else 799 netsio_clr(sc, TL_NETSIO_MDATA); 800 netsio_set(sc, TL_NETSIO_MCLK); 801 netsio_read(sc, TL_NETSIO_MCLK); 802 } 803 } 804 805 int 806 tl_mii_read(self, phy, reg) 807 struct device *self; 808 int phy, reg; 809 { 810 struct tl_softc *sc = (struct tl_softc *)self; 811 int val = 0, i, err; 812 813 /* 814 * Read the PHY register by manually driving the MII control lines. 815 */ 816 817 tl_mii_sync(sc); 818 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 819 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 820 tl_mii_sendbits(sc, phy, 5); 821 tl_mii_sendbits(sc, reg, 5); 822 823 netsio_clr(sc, TL_NETSIO_MTXEN); 824 netsio_clr(sc, TL_NETSIO_MCLK); 825 netsio_set(sc, TL_NETSIO_MCLK); 826 netsio_clr(sc, TL_NETSIO_MCLK); 827 828 err = netsio_read(sc, TL_NETSIO_MDATA); 829 netsio_set(sc, TL_NETSIO_MCLK); 830 831 /* Even if an error occurs, must still clock out the cycle. */ 832 for (i = 0; i < 16; i++) { 833 val <<= 1; 834 netsio_clr(sc, TL_NETSIO_MCLK); 835 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 836 val |= 1; 837 netsio_set(sc, TL_NETSIO_MCLK); 838 } 839 netsio_clr(sc, TL_NETSIO_MCLK); 840 netsio_set(sc, TL_NETSIO_MCLK); 841 842 return (err ? 0 : val); 843 } 844 845 void 846 tl_mii_write(self, phy, reg, val) 847 struct device *self; 848 int phy, reg, val; 849 { 850 struct tl_softc *sc = (struct tl_softc *)self; 851 852 /* 853 * Write the PHY register by manually driving the MII control lines. 854 */ 855 856 tl_mii_sync(sc); 857 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 858 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 859 tl_mii_sendbits(sc, phy, 5); 860 tl_mii_sendbits(sc, reg, 5); 861 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 862 tl_mii_sendbits(sc, val, 16); 863 864 netsio_clr(sc, TL_NETSIO_MCLK); 865 netsio_set(sc, TL_NETSIO_MCLK); 866 } 867 868 void 869 tl_statchg(self) 870 struct device *self; 871 { 872 tl_softc_t *sc = (struct tl_softc *)self; 873 u_int32_t reg; 874 875 #ifdef TLDEBUG 876 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 877 #endif 878 879 /* 880 * We must keep the ThunderLAN and the PHY in sync as 881 * to the status of full-duplex! 882 */ 883 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 884 if (sc->tl_mii.mii_media_active & IFM_FDX) 885 reg |= TL_NETCOMMAND_DUPLEX; 886 else 887 reg &= ~TL_NETCOMMAND_DUPLEX; 888 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 889 } 890 891 void tl_i2c_set(v, bit) 892 void *v; 893 u_int8_t bit; 894 { 895 tl_softc_t *sc = v; 896 897 switch (bit) { 898 case I2C_DATA: 899 netsio_set(sc, TL_NETSIO_EDATA); 900 break; 901 case I2C_CLOCK: 902 netsio_set(sc, TL_NETSIO_ECLOCK); 903 break; 904 case I2C_TXEN: 905 netsio_set(sc, TL_NETSIO_ETXEN); 906 break; 907 default: 908 printf("tl_i2c_set: unknown bit %d\n", bit); 909 } 910 return; 911 } 912 913 void tl_i2c_clr(v, bit) 914 void *v; 915 u_int8_t bit; 916 { 917 tl_softc_t *sc = v; 918 919 switch (bit) { 920 case I2C_DATA: 921 netsio_clr(sc, TL_NETSIO_EDATA); 922 break; 923 case I2C_CLOCK: 924 netsio_clr(sc, TL_NETSIO_ECLOCK); 925 break; 926 case I2C_TXEN: 927 netsio_clr(sc, TL_NETSIO_ETXEN); 928 break; 929 default: 930 printf("tl_i2c_clr: unknown bit %d\n", bit); 931 } 932 return; 933 } 934 935 int tl_i2c_read(v, bit) 936 void *v; 937 u_int8_t bit; 938 { 939 tl_softc_t *sc = v; 940 941 switch (bit) { 942 case I2C_DATA: 943 return netsio_read(sc, TL_NETSIO_EDATA); 944 break; 945 case I2C_CLOCK: 946 return netsio_read(sc, TL_NETSIO_ECLOCK); 947 break; 948 case I2C_TXEN: 949 return netsio_read(sc, TL_NETSIO_ETXEN); 950 break; 951 default: 952 printf("tl_i2c_read: unknown bit %d\n", bit); 953 return -1; 954 } 955 } 956 957 static int 958 tl_intr(v) 959 void *v; 960 { 961 tl_softc_t *sc = v; 962 struct ifnet *ifp = &sc->tl_if; 963 struct Rx_list *Rx; 964 struct Tx_list *Tx; 965 struct mbuf *m; 966 u_int32_t int_type, int_reg; 967 int ack = 0; 968 int size; 969 970 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 971 int_type = int_reg & TL_INTR_MASK; 972 if (int_type == 0) 973 return 0; 974 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 975 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 976 int_type, int_reg); 977 #endif 978 /* disable interrupts */ 979 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 980 switch(int_type & TL_INTR_MASK) { 981 case TL_INTR_RxEOF: 982 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 983 sizeof(struct tl_Rx_list) * TL_NBUF, 984 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 985 while(le32toh(sc->active_Rx->hw_list->stat) & 986 TL_RX_CSTAT_CPLT) { 987 /* dequeue and requeue at end of list */ 988 ack++; 989 Rx = sc->active_Rx; 990 sc->active_Rx = Rx->next; 991 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 992 MCLBYTES, BUS_DMASYNC_POSTREAD); 993 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 994 m = Rx->m; 995 size = le32toh(Rx->hw_list->stat) >> 16; 996 #ifdef TLDEBUG_RX 997 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 998 Rx, size); 999 #endif 1000 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1001 /* 1002 * No new mbuf, reuse the same. This means 1003 * that this packet 1004 * is lost 1005 */ 1006 m = NULL; 1007 #ifdef TL_PRIV_STATS 1008 sc->ierr_nomem++; 1009 #endif 1010 #ifdef TLDEBUG 1011 printf("%s: out of mbuf, lost input packet\n", 1012 sc->sc_dev.dv_xname); 1013 #endif 1014 } 1015 Rx->next = NULL; 1016 Rx->hw_list->fwd = 0; 1017 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1018 sc->last_Rx->next = Rx; 1019 sc->last_Rx = Rx; 1020 1021 /* deliver packet */ 1022 if (m) { 1023 if (size < sizeof(struct ether_header)) { 1024 m_freem(m); 1025 continue; 1026 } 1027 m->m_pkthdr.rcvif = ifp; 1028 m->m_pkthdr.len = m->m_len = size; 1029 #ifdef TLDEBUG_RX 1030 { struct ether_header *eh = 1031 mtod(m, struct ether_header *); 1032 printf("tl_intr: Rx packet:\n"); 1033 ether_printheader(eh); } 1034 #endif 1035 #if NBPFILTER > 0 1036 if (ifp->if_bpf) 1037 bpf_mtap(ifp->if_bpf, m); 1038 #endif /* NBPFILTER > 0 */ 1039 (*ifp->if_input)(ifp, m); 1040 } 1041 } 1042 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1043 sizeof(struct tl_Rx_list) * TL_NBUF, 1044 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1045 #ifdef TLDEBUG_RX 1046 printf("TL_INTR_RxEOF: ack %d\n", ack); 1047 #else 1048 if (ack == 0) { 1049 printf("%s: EOF intr without anything to read !\n", 1050 sc->sc_dev.dv_xname); 1051 tl_reset(sc); 1052 /* shedule reinit of the board */ 1053 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1054 return(1); 1055 } 1056 #endif 1057 break; 1058 case TL_INTR_RxEOC: 1059 ack++; 1060 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1061 sizeof(struct tl_Rx_list) * TL_NBUF, 1062 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1063 #ifdef TLDEBUG_RX 1064 printf("TL_INTR_RxEOC: ack %d\n", ack); 1065 #endif 1066 #ifdef DIAGNOSTIC 1067 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1068 printf("%s: Rx EOC interrupt and active Tx list not " 1069 "cleared\n", sc->sc_dev.dv_xname); 1070 return 0; 1071 } else 1072 #endif 1073 { 1074 /* 1075 * write adress of Rx list and send Rx GO command, ack 1076 * interrupt and enable interrupts in one command 1077 */ 1078 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1079 TL_HR_WRITE(sc, TL_HOST_CMD, 1080 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1081 HOST_CMD_ACK | HOST_CMD_IntOn); 1082 return 1; 1083 } 1084 case TL_INTR_TxEOF: 1085 case TL_INTR_TxEOC: 1086 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1087 sizeof(struct tl_Tx_list) * TL_NBUF, 1088 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1089 while ((Tx = sc->active_Tx) != NULL) { 1090 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1091 break; 1092 ack++; 1093 #ifdef TLDEBUG_TX 1094 printf("TL_INTR_TxEOC: list 0x%x done\n", 1095 (int)Tx->hw_listaddr); 1096 #endif 1097 Tx->hw_list->stat = 0; 1098 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1099 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1100 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1101 m_freem(Tx->m); 1102 Tx->m = NULL; 1103 sc->active_Tx = Tx->next; 1104 if (sc->active_Tx == NULL) 1105 sc->last_Tx = NULL; 1106 Tx->next = sc->Free_Tx; 1107 sc->Free_Tx = Tx; 1108 } 1109 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1110 sizeof(struct tl_Tx_list) * TL_NBUF, 1111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1112 /* if this was an EOC, ACK immediatly */ 1113 if (ack) 1114 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1115 if (int_type == TL_INTR_TxEOC) { 1116 #ifdef TLDEBUG_TX 1117 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1118 ack); 1119 #endif 1120 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1121 HOST_CMD_ACK | HOST_CMD_IntOn); 1122 if ( sc->active_Tx != NULL) { 1123 /* needs a Tx go command */ 1124 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1125 sc->active_Tx->hw_listaddr); 1126 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1127 } 1128 sc->tl_if.if_timer = 0; 1129 if (sc->tl_if.if_snd.ifq_head != NULL) 1130 tl_ifstart(&sc->tl_if); 1131 return 1; 1132 } 1133 #ifdef TLDEBUG 1134 else { 1135 printf("TL_INTR_TxEOF: ack %d\n", ack); 1136 } 1137 #endif 1138 sc->tl_if.if_timer = 0; 1139 if (sc->tl_if.if_snd.ifq_head != NULL) 1140 tl_ifstart(&sc->tl_if); 1141 break; 1142 case TL_INTR_Stat: 1143 ack++; 1144 #ifdef TLDEBUG 1145 printf("TL_INTR_Stat: ack %d\n", ack); 1146 #endif 1147 tl_read_stats(sc); 1148 break; 1149 case TL_INTR_Adc: 1150 if (int_reg & TL_INTVec_MASK) { 1151 /* adapter check conditions */ 1152 printf("%s: check condition, intvect=0x%x, " 1153 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1154 int_reg & TL_INTVec_MASK, 1155 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1156 tl_reset(sc); 1157 /* shedule reinit of the board */ 1158 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1159 return(1); 1160 } else { 1161 u_int8_t netstat; 1162 /* Network status */ 1163 netstat = 1164 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1165 printf("%s: network status, NetSts=%x\n", 1166 sc->sc_dev.dv_xname, netstat); 1167 /* Ack interrupts */ 1168 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1169 netstat); 1170 ack++; 1171 } 1172 break; 1173 default: 1174 printf("%s: unhandled interrupt code %x!\n", 1175 sc->sc_dev.dv_xname, int_type); 1176 ack++; 1177 } 1178 1179 if (ack) { 1180 /* Ack the interrupt and enable interrupts */ 1181 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1182 HOST_CMD_IntOn); 1183 return 1; 1184 } 1185 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1186 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1187 return 0; 1188 } 1189 1190 static int 1191 tl_ifioctl(ifp, cmd, data) 1192 struct ifnet *ifp; 1193 ioctl_cmd_t cmd; 1194 caddr_t data; 1195 { 1196 struct tl_softc *sc = ifp->if_softc; 1197 struct ifreq *ifr = (struct ifreq *)data; 1198 int s, error; 1199 1200 s = splnet(); 1201 switch(cmd) { 1202 case SIOCSIFMEDIA: 1203 case SIOCGIFMEDIA: 1204 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1205 break; 1206 default: 1207 error = ether_ioctl(ifp, cmd, data); 1208 if (error == ENETRESET) { 1209 tl_addr_filter(sc); 1210 error = 0; 1211 } 1212 } 1213 splx(s); 1214 return error; 1215 } 1216 1217 static void 1218 tl_ifstart(ifp) 1219 struct ifnet *ifp; 1220 { 1221 tl_softc_t *sc = ifp->if_softc; 1222 struct mbuf *mb_head; 1223 struct Tx_list *Tx; 1224 int segment, size; 1225 int again, error; 1226 1227 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1228 return; 1229 txloop: 1230 /* If we don't have more space ... */ 1231 if (sc->Free_Tx == NULL) { 1232 #ifdef TLDEBUG 1233 printf("tl_ifstart: No free TX list\n"); 1234 #endif 1235 sc->tl_if.if_flags |= IFF_OACTIVE; 1236 return; 1237 } 1238 /* Grab a paquet for output */ 1239 IF_DEQUEUE(&ifp->if_snd, mb_head); 1240 if (mb_head == NULL) { 1241 #ifdef TLDEBUG_TX 1242 printf("tl_ifstart: nothing to send\n"); 1243 #endif 1244 return; 1245 } 1246 Tx = sc->Free_Tx; 1247 sc->Free_Tx = Tx->next; 1248 Tx->next = NULL; 1249 again = 0; 1250 /* 1251 * Go through each of the mbufs in the chain and initialize 1252 * the transmit list descriptors with the physical address 1253 * and size of the mbuf. 1254 */ 1255 tbdinit: 1256 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1257 Tx->m = mb_head; 1258 size = mb_head->m_pkthdr.len; 1259 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1260 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1261 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1262 struct mbuf *mn; 1263 /* 1264 * We ran out of segments, or we will. We have to recopy this 1265 * mbuf chain first. 1266 */ 1267 if (error == 0) 1268 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1269 if (again) { 1270 /* already copyed, can't do much more */ 1271 m_freem(mb_head); 1272 goto bad; 1273 } 1274 again = 1; 1275 #ifdef TLDEBUG_TX 1276 printf("tl_ifstart: need to copy mbuf\n"); 1277 #endif 1278 #ifdef TL_PRIV_STATS 1279 sc->oerr_mcopy++; 1280 #endif 1281 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1282 if (mn == NULL) { 1283 m_freem(mb_head); 1284 goto bad; 1285 } 1286 if (mb_head->m_pkthdr.len > MHLEN) { 1287 MCLGET(mn, M_DONTWAIT); 1288 if ((mn->m_flags & M_EXT) == 0) { 1289 m_freem(mn); 1290 m_freem(mb_head); 1291 goto bad; 1292 } 1293 } 1294 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1295 mtod(mn, caddr_t)); 1296 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1297 m_freem(mb_head); 1298 mb_head = mn; 1299 goto tbdinit; 1300 } 1301 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1302 Tx->hw_list->seg[segment].data_addr = 1303 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1304 Tx->hw_list->seg[segment].data_count = 1305 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1306 } 1307 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1309 /* We are at end of mbuf chain. check the size and 1310 * see if it needs to be extended 1311 */ 1312 if (size < ETHER_MIN_TX) { 1313 #ifdef DIAGNOSTIC 1314 if (segment >= TL_NSEG) { 1315 panic("tl_ifstart: to much segmets (%d)\n", segment); 1316 } 1317 #endif 1318 /* 1319 * add the nullbuf in the seg 1320 */ 1321 Tx->hw_list->seg[segment].data_count = 1322 htole32(ETHER_MIN_TX - size); 1323 Tx->hw_list->seg[segment].data_addr = 1324 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1325 size = ETHER_MIN_TX; 1326 segment++; 1327 } 1328 /* The list is done, finish the list init */ 1329 Tx->hw_list->seg[segment-1].data_count |= 1330 htole32(TL_LAST_SEG); 1331 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1332 #ifdef TLDEBUG_TX 1333 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1334 le32toh(Tx->hw_list->stat)); 1335 #if 0 1336 for(segment = 0; segment < TL_NSEG; segment++) { 1337 printf(" seg %d addr 0x%x len 0x%x\n", 1338 segment, 1339 le32toh(Tx->hw_list->seg[segment].data_addr), 1340 le32toh(Tx->hw_list->seg[segment].data_count)); 1341 } 1342 #endif 1343 #endif 1344 if (sc->active_Tx == NULL) { 1345 sc->active_Tx = sc->last_Tx = Tx; 1346 #ifdef TLDEBUG_TX 1347 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1348 (int)Tx->hw_listaddr); 1349 #endif 1350 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1351 sizeof(struct tl_Tx_list) * TL_NBUF, 1352 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1353 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1354 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1355 } else { 1356 #ifdef TLDEBUG_TX 1357 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1358 (int)Tx->hw_listaddr); 1359 #endif 1360 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1361 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1362 sizeof(struct tl_Tx_list) * TL_NBUF, 1363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1364 sc->last_Tx->next = Tx; 1365 sc->last_Tx = Tx; 1366 #ifdef DIAGNOSTIC 1367 if (sc->last_Tx->hw_list->fwd & 0x7) 1368 printf("%s: physical addr 0x%x of list not properly " 1369 "aligned\n", 1370 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1371 #endif 1372 } 1373 #if NBPFILTER > 0 1374 /* Pass packet to bpf if there is a listener */ 1375 if (ifp->if_bpf) 1376 bpf_mtap(ifp->if_bpf, mb_head); 1377 #endif 1378 /* 1379 * Set a 5 second timer just in case we don't hear from the card again. 1380 */ 1381 ifp->if_timer = 5; 1382 goto txloop; 1383 bad: 1384 #ifdef TLDEBUG 1385 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1386 #endif 1387 Tx->next = sc->Free_Tx; 1388 sc->Free_Tx = Tx; 1389 return; 1390 } 1391 1392 static void 1393 tl_ifwatchdog(ifp) 1394 struct ifnet *ifp; 1395 { 1396 tl_softc_t *sc = ifp->if_softc; 1397 1398 if ((ifp->if_flags & IFF_RUNNING) == 0) 1399 return; 1400 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1401 ifp->if_oerrors++; 1402 tl_init(ifp); 1403 } 1404 1405 static int 1406 tl_mediachange(ifp) 1407 struct ifnet *ifp; 1408 { 1409 1410 if (ifp->if_flags & IFF_UP) 1411 tl_init(ifp->if_softc); 1412 return (0); 1413 } 1414 1415 static void 1416 tl_mediastatus(ifp, ifmr) 1417 struct ifnet *ifp; 1418 struct ifmediareq *ifmr; 1419 { 1420 tl_softc_t *sc = ifp->if_softc; 1421 1422 mii_pollstat(&sc->tl_mii); 1423 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1424 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1425 } 1426 1427 static int tl_add_RxBuff(sc, Rx, oldm) 1428 tl_softc_t *sc; 1429 struct Rx_list *Rx; 1430 struct mbuf *oldm; 1431 { 1432 struct mbuf *m; 1433 int error; 1434 1435 MGETHDR(m, M_DONTWAIT, MT_DATA); 1436 if (m != NULL) { 1437 MCLGET(m, M_DONTWAIT); 1438 if ((m->m_flags & M_EXT) == 0) { 1439 m_freem(m); 1440 if (oldm == NULL) 1441 return 0; 1442 m = oldm; 1443 m->m_data = m->m_ext.ext_buf; 1444 } 1445 } else { 1446 if (oldm == NULL) 1447 return 0; 1448 m = oldm; 1449 m->m_data = m->m_ext.ext_buf; 1450 } 1451 1452 /* (re)init the Rx_list struct */ 1453 1454 Rx->m = m; 1455 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1456 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1457 printf("%s: bus_dmamap_load() failed (error %d) for " 1458 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1459 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1460 m_freem(m); 1461 Rx->m = NULL; 1462 return 0; 1463 } 1464 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1465 MCLBYTES, BUS_DMASYNC_PREREAD); 1466 /* 1467 * Move the data pointer up so that the incoming data packet 1468 * will be 32-bit aligned. 1469 */ 1470 m->m_data += 2; 1471 1472 Rx->hw_list->stat = 1473 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1474 Rx->hw_list->seg.data_count = 1475 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1476 Rx->hw_list->seg.data_addr = 1477 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1478 return (m != oldm); 1479 } 1480 1481 static void tl_ticks(v) 1482 void *v; 1483 { 1484 tl_softc_t *sc = v; 1485 1486 tl_read_stats(sc); 1487 1488 /* Tick the MII. */ 1489 mii_tick(&sc->tl_mii); 1490 1491 /* read statistics every seconds */ 1492 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1493 } 1494 1495 static void 1496 tl_read_stats(sc) 1497 tl_softc_t *sc; 1498 { 1499 u_int32_t reg; 1500 int ierr_overr; 1501 int ierr_code; 1502 int ierr_crc; 1503 int oerr_underr; 1504 int oerr_deffered; 1505 int oerr_coll; 1506 int oerr_multicoll; 1507 int oerr_exesscoll; 1508 int oerr_latecoll; 1509 int oerr_carrloss; 1510 struct ifnet *ifp = &sc->tl_if; 1511 1512 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1513 ifp->if_opackets += reg & 0x00ffffff; 1514 oerr_underr = reg >> 24; 1515 1516 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1517 ifp->if_ipackets += reg & 0x00ffffff; 1518 ierr_overr = reg >> 24; 1519 1520 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1521 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1522 ierr_code = (reg & TL_FERR_CODE) >> 24; 1523 oerr_deffered = (reg & TL_FERR_DEF); 1524 1525 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1526 oerr_multicoll = (reg & TL_COL_MULTI); 1527 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1528 1529 reg = tl_intreg_read(sc, TL_INT_LERR); 1530 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1531 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1532 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1533 1534 1535 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1536 oerr_carrloss; 1537 ifp->if_collisions += oerr_coll + oerr_multicoll; 1538 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1539 1540 if (ierr_overr) 1541 printf("%s: receiver ring buffer overrun\n", 1542 sc->sc_dev.dv_xname); 1543 if (oerr_underr) 1544 printf("%s: transmit buffer underrun\n", 1545 sc->sc_dev.dv_xname); 1546 #ifdef TL_PRIV_STATS 1547 sc->ierr_overr += ierr_overr; 1548 sc->ierr_code += ierr_code; 1549 sc->ierr_crc += ierr_crc; 1550 sc->oerr_underr += oerr_underr; 1551 sc->oerr_deffered += oerr_deffered; 1552 sc->oerr_coll += oerr_coll; 1553 sc->oerr_multicoll += oerr_multicoll; 1554 sc->oerr_exesscoll += oerr_exesscoll; 1555 sc->oerr_latecoll += oerr_latecoll; 1556 sc->oerr_carrloss += oerr_carrloss; 1557 #endif 1558 } 1559 1560 static void tl_addr_filter(sc) 1561 tl_softc_t *sc; 1562 { 1563 struct ether_multistep step; 1564 struct ether_multi *enm; 1565 u_int32_t hash[2] = {0, 0}; 1566 int i; 1567 1568 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1569 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1570 while (enm != NULL) { 1571 #ifdef TLDEBUG 1572 printf("tl_addr_filter: addrs %s %s\n", 1573 ether_sprintf(enm->enm_addrlo), 1574 ether_sprintf(enm->enm_addrhi)); 1575 #endif 1576 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1577 i = tl_multicast_hash(enm->enm_addrlo); 1578 hash[i/32] |= 1 << (i%32); 1579 } else { 1580 hash[0] = hash[1] = 0xffffffff; 1581 sc->tl_if.if_flags |= IFF_ALLMULTI; 1582 break; 1583 } 1584 ETHER_NEXT_MULTI(step, enm); 1585 } 1586 #ifdef TLDEBUG 1587 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1588 #endif 1589 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1590 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1591 } 1592 1593 static int tl_multicast_hash(a) 1594 u_int8_t *a; 1595 { 1596 int hash; 1597 1598 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1599 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1600 1601 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1602 DA(a,36), DA(a,42)); 1603 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1604 DA(a,37), DA(a,43)) << 1; 1605 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1606 DA(a,38), DA(a,44)) << 2; 1607 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1608 DA(a,39), DA(a,45)) << 3; 1609 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1610 DA(a,40), DA(a,46)) << 4; 1611 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1612 DA(a,41), DA(a,47)) << 5; 1613 1614 return hash; 1615 } 1616 1617 #if defined(TLDEBUG_RX) 1618 void 1619 ether_printheader(eh) 1620 struct ether_header *eh; 1621 { 1622 u_char *c = (char*)eh; 1623 int i; 1624 for (i=0; i<sizeof(struct ether_header); i++) 1625 printf("%x ", (u_int)c[i]); 1626 printf("\n"); 1627 } 1628 #endif 1629
Indexes created Thu Sep 25 16:09:42 GMT 2025