if_tl.c revision 1.49
1 /* $NetBSD: if_tl.c,v 1.49 2002/02/28 00:52:21 christos Exp $ */ 2 3 /* XXX ALTQ XXX */ 4 5 /* 6 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Texas Instruments ThunderLAN ethernet controller 36 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 37 * available from www.ti.com 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.49 2002/02/28 00:52:21 christos Exp $"); 42 43 #undef TLDEBUG 44 #define TL_PRIV_STATS 45 #undef TLDEBUG_RX 46 #undef TLDEBUG_TX 47 #undef TLDEBUG_ADDR 48 49 #include "opt_inet.h" 50 #include "opt_ns.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/mbuf.h> 55 #include <sys/protosw.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/malloc.h> 60 #include <sys/kernel.h> 61 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 62 #include <sys/device.h> 63 64 #include <net/if.h> 65 #if defined(SIOCSIFMEDIA) 66 #include <net/if_media.h> 67 #endif 68 #include <net/if_types.h> 69 #include <net/if_dl.h> 70 #include <net/route.h> 71 #include <net/netisr.h> 72 73 #include "bpfilter.h" 74 #if NBPFILTER > 0 75 #include <net/bpf.h> 76 #include <net/bpfdesc.h> 77 #endif 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #endif 85 86 #ifdef NS 87 #include <netns/ns.h> 88 #include <netns/ns_if.h> 89 #endif 90 91 #if defined(__NetBSD__) 92 #include <net/if_ether.h> 93 #include <uvm/uvm_extern.h> 94 #if defined(INET) 95 #include <netinet/if_inarp.h> 96 #endif 97 98 #include <machine/bus.h> 99 #include <machine/intr.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/i2c/i2c_bus.h> 106 #include <dev/i2c/i2c_eeprom.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/mii/tlphyvar.h> 112 113 #include <dev/pci/if_tlregs.h> 114 #include <dev/pci/if_tlvar.h> 115 #endif /* __NetBSD__ */ 116 117 /* number of transmit/receive buffers */ 118 #ifndef TL_NBUF 119 #define TL_NBUF 10 120 #endif 121 122 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 123 static void tl_pci_attach __P((struct device *, struct device *, void *)); 124 static int tl_intr __P((void *)); 125 126 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 127 static int tl_mediachange __P((struct ifnet *)); 128 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 129 static void tl_ifwatchdog __P((struct ifnet *)); 130 static void tl_shutdown __P((void*)); 131 132 static void tl_ifstart __P((struct ifnet *)); 133 static void tl_reset __P((tl_softc_t*)); 134 static int tl_init __P((struct ifnet *)); 135 static void tl_stop __P((struct ifnet *, int)); 136 static void tl_restart __P((void *)); 137 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 138 static void tl_read_stats __P((tl_softc_t*)); 139 static void tl_ticks __P((void*)); 140 static int tl_multicast_hash __P((u_int8_t*)); 141 static void tl_addr_filter __P((tl_softc_t*)); 142 143 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 145 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 146 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 147 148 void tl_mii_sync __P((struct tl_softc *)); 149 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 150 151 152 #if defined(TLDEBUG_RX) 153 static void ether_printheader __P((struct ether_header*)); 154 #endif 155 156 int tl_mii_read __P((struct device *, int, int)); 157 void tl_mii_write __P((struct device *, int, int, int)); 158 159 void tl_statchg __P((struct device *)); 160 161 void tl_i2c_set __P((void*, u_int8_t)); 162 void tl_i2c_clr __P((void*, u_int8_t)); 163 int tl_i2c_read __P((void*, u_int8_t)); 164 165 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 167 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 168 static __inline void netsio_clr(sc, bits) 169 tl_softc_t* sc; 170 u_int8_t bits; 171 { 172 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 173 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 174 } 175 static __inline void netsio_set(sc, bits) 176 tl_softc_t* sc; 177 u_int8_t bits; 178 { 179 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 180 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 181 } 182 static __inline u_int8_t netsio_read(sc, bits) 183 tl_softc_t* sc; 184 u_int8_t bits; 185 { 186 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 187 } 188 189 struct cfattach tl_ca = { 190 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 191 }; 192 193 const struct tl_product_desc tl_compaq_products[] = { 194 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 195 "Compaq Netelligent 10/100 TX" }, 196 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 197 "Compaq Netelligent 10 T" }, 198 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 199 "Compaq Integrated NetFlex 3/P" }, 200 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 201 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 202 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 203 "Compaq Dual Port Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 205 "Compaq Deskpro 4000 5233MMX" }, 206 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 207 "Compaq NetFlex 3/P w/ BNC" }, 208 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 209 "Compaq NetFlex 3/P" }, 210 { 0, 0, NULL }, 211 }; 212 213 const struct tl_product_desc tl_ti_products[] = { 214 /* 215 * Built-in Ethernet on the TI TravelMate 5000 216 * docking station; better product description? 217 */ 218 { PCI_PRODUCT_TI_TLAN, 0, 219 "Texas Instruments ThunderLAN" }, 220 { 0, 0, NULL }, 221 }; 222 223 struct tl_vendor_desc { 224 u_int32_t tv_vendor; 225 const struct tl_product_desc *tv_products; 226 }; 227 228 const struct tl_vendor_desc tl_vendors[] = { 229 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 230 { PCI_VENDOR_TI, tl_ti_products }, 231 { 0, NULL }, 232 }; 233 234 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 235 236 const struct tl_product_desc * 237 tl_lookup_product(id) 238 u_int32_t id; 239 { 240 const struct tl_product_desc *tp; 241 const struct tl_vendor_desc *tv; 242 243 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 244 if (PCI_VENDOR(id) == tv->tv_vendor) 245 break; 246 247 if ((tp = tv->tv_products) == NULL) 248 return (NULL); 249 250 for (; tp->tp_desc != NULL; tp++) 251 if (PCI_PRODUCT(id) == tp->tp_product) 252 break; 253 254 if (tp->tp_desc == NULL) 255 return (NULL); 256 257 return (tp); 258 } 259 260 static int 261 tl_pci_match(parent, match, aux) 262 struct device *parent; 263 struct cfdata *match; 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 267 268 if (tl_lookup_product(pa->pa_id) != NULL) 269 return (1); 270 271 return (0); 272 } 273 274 static void 275 tl_pci_attach(parent, self, aux) 276 struct device * parent; 277 struct device * self; 278 void * aux; 279 { 280 tl_softc_t *sc = (tl_softc_t *)self; 281 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 282 const struct tl_product_desc *tp; 283 struct ifnet * const ifp = &sc->tl_if; 284 bus_space_tag_t iot, memt; 285 bus_space_handle_t ioh, memh; 286 pci_intr_handle_t intrhandle; 287 const char *intrstr; 288 int i, tmp, ioh_valid, memh_valid; 289 int reg_io, reg_mem; 290 pcireg_t reg10, reg14; 291 pcireg_t csr; 292 293 printf("\n"); 294 295 callout_init(&sc->tl_tick_ch); 296 callout_init(&sc->tl_restart_ch); 297 298 tp = tl_lookup_product(pa->pa_id); 299 if (tp == NULL) 300 panic("tl_pci_attach: impossible"); 301 sc->tl_product = tp; 302 303 /* 304 * Map the card space. Fisrt we have to find the I/O and MEM 305 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 306 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 307 * The ThunderLAN manual is not consistent about this either (there 308 * are both cases in code examples). 309 */ 310 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 311 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 312 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 313 reg_io = 0x10; 314 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 315 reg_io = 0x14; 316 else 317 reg_io = 0; 318 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 319 reg_mem = 0x10; 320 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 321 reg_mem = 0x14; 322 else 323 reg_mem = 0; 324 325 if (reg_io != 0) 326 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 327 0, &iot, &ioh, NULL, NULL) == 0); 328 else 329 ioh_valid = 0; 330 if (reg_mem != 0) 331 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 332 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 333 0, &memt, &memh, NULL, NULL) == 0); 334 else 335 memh_valid = 0; 336 337 if (ioh_valid) { 338 sc->tl_bustag = iot; 339 sc->tl_bushandle = ioh; 340 } else if (memh_valid) { 341 sc->tl_bustag = memt; 342 sc->tl_bushandle = memh; 343 } else { 344 printf("%s: unable to map device registers\n", 345 sc->sc_dev.dv_xname); 346 return; 347 } 348 sc->tl_dmatag = pa->pa_dmat; 349 350 /* Enable the device. */ 351 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 352 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 353 csr | PCI_COMMAND_MASTER_ENABLE); 354 355 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 356 357 tl_reset(sc); 358 359 /* fill in the i2c struct */ 360 sc->i2cbus.adapter_softc = sc; 361 sc->i2cbus.set_bit = tl_i2c_set; 362 sc->i2cbus.clr_bit = tl_i2c_clr; 363 sc->i2cbus.read_bit = tl_i2c_read; 364 365 #ifdef TLDEBUG 366 printf("default values of INTreg: 0x%x\n", 367 tl_intreg_read(sc, TL_INT_Defaults)); 368 #endif 369 370 /* read mac addr */ 371 for (i=0; i<ETHER_ADDR_LEN; i++) { 372 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 373 if (tmp < 0) { 374 printf("%s: error reading Ethernet adress\n", 375 sc->sc_dev.dv_xname); 376 return; 377 } else { 378 sc->tl_enaddr[i] = tmp; 379 } 380 } 381 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 382 ether_sprintf(sc->tl_enaddr)); 383 384 /* Map and establish interrupts */ 385 if (pci_intr_map(pa, &intrhandle)) { 386 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 387 return; 388 } 389 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 390 sc->tl_if.if_softc = sc; 391 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 392 tl_intr, sc); 393 if (sc->tl_ih == NULL) { 394 printf("%s: couldn't establish interrupt", 395 sc->sc_dev.dv_xname); 396 if (intrstr != NULL) 397 printf(" at %s", intrstr); 398 printf("\n"); 399 return; 400 } 401 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 402 403 /* init these pointers, so that tl_shutdown won't try to read them */ 404 sc->Rx_list = NULL; 405 sc->Tx_list = NULL; 406 407 /* allocate DMA-safe memory for control structs */ 408 if (bus_dmamem_alloc(sc->tl_dmatag, 409 PAGE_SIZE, 0, PAGE_SIZE, 410 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 411 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 412 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 413 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 414 printf("%s: can't allocate DMA memory for lists\n", 415 sc->sc_dev.dv_xname); 416 return; 417 } 418 /* 419 * Add shutdown hook so that DMA is disabled prior to reboot. Not 420 * doing do could allow DMA to corrupt kernel memory during the 421 * reboot before the driver initializes. 422 */ 423 (void) shutdownhook_establish(tl_shutdown, ifp); 424 425 /* 426 * Initialize our media structures and probe the MII. 427 * 428 * Note that we don't care about the media instance. We 429 * are expecting to have multiple PHYs on the 10/100 cards, 430 * and on those cards we exclude the internal PHY from providing 431 * 10baseT. By ignoring the instance, it allows us to not have 432 * to specify it on the command line when switching media. 433 */ 434 sc->tl_mii.mii_ifp = ifp; 435 sc->tl_mii.mii_readreg = tl_mii_read; 436 sc->tl_mii.mii_writereg = tl_mii_write; 437 sc->tl_mii.mii_statchg = tl_statchg; 438 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 439 tl_mediastatus); 440 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 441 MII_OFFSET_ANY, 0); 442 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 443 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 444 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 445 } else 446 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 447 448 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 449 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 450 ifp->if_ioctl = tl_ifioctl; 451 ifp->if_start = tl_ifstart; 452 ifp->if_watchdog = tl_ifwatchdog; 453 ifp->if_init = tl_init; 454 ifp->if_stop = tl_stop; 455 ifp->if_timer = 0; 456 if_attach(ifp); 457 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 458 } 459 460 static void 461 tl_reset(sc) 462 tl_softc_t *sc; 463 { 464 int i; 465 466 /* read stats */ 467 if (sc->tl_if.if_flags & IFF_RUNNING) { 468 callout_stop(&sc->tl_tick_ch); 469 tl_read_stats(sc); 470 } 471 /* Reset adapter */ 472 TL_HR_WRITE(sc, TL_HOST_CMD, 473 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 474 DELAY(100000); 475 /* Disable interrupts */ 476 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 477 /* setup aregs & hash */ 478 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 479 tl_intreg_write(sc, i, 0); 480 #ifdef TLDEBUG_ADDR 481 printf("Areg & hash registers: \n"); 482 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 483 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 484 #endif 485 /* Setup NetConfig */ 486 tl_intreg_write(sc, TL_INT_NetConfig, 487 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 488 /* Bsize: accept default */ 489 /* TX commit in Acommit: accept default */ 490 /* Load Ld_tmr and Ld_thr */ 491 /* Ld_tmr = 3 */ 492 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 493 /* Ld_thr = 0 */ 494 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 495 /* Unreset MII */ 496 netsio_set(sc, TL_NETSIO_NMRST); 497 DELAY(100000); 498 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 499 } 500 501 static void tl_shutdown(v) 502 void *v; 503 { 504 tl_stop(v, 1); 505 } 506 507 static void tl_stop(ifp, disable) 508 struct ifnet *ifp; 509 int disable; 510 { 511 tl_softc_t *sc = ifp->if_softc; 512 struct Tx_list *Tx; 513 int i; 514 515 if ((ifp->if_flags & IFF_RUNNING) == 0) 516 return; 517 /* disable interrupts */ 518 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 519 /* stop TX and RX channels */ 520 TL_HR_WRITE(sc, TL_HOST_CMD, 521 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 522 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 523 DELAY(100000); 524 525 /* stop statistics reading loop, read stats */ 526 callout_stop(&sc->tl_tick_ch); 527 tl_read_stats(sc); 528 529 /* Down the MII. */ 530 mii_down(&sc->tl_mii); 531 532 /* deallocate memory allocations */ 533 if (sc->Rx_list) { 534 for (i=0; i< TL_NBUF; i++) { 535 if (sc->Rx_list[i].m) { 536 bus_dmamap_unload(sc->tl_dmatag, 537 sc->Rx_list[i].m_dmamap); 538 m_freem(sc->Rx_list[i].m); 539 } 540 bus_dmamap_destroy(sc->tl_dmatag, 541 sc->Rx_list[i].m_dmamap); 542 sc->Rx_list[i].m = NULL; 543 } 544 free(sc->Rx_list, M_DEVBUF); 545 sc->Rx_list = NULL; 546 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 547 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 548 sc->hw_Rx_list = NULL; 549 while ((Tx = sc->active_Tx) != NULL) { 550 Tx->hw_list->stat = 0; 551 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 552 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 553 m_freem(Tx->m); 554 sc->active_Tx = Tx->next; 555 Tx->next = sc->Free_Tx; 556 sc->Free_Tx = Tx; 557 } 558 sc->last_Tx = NULL; 559 free(sc->Tx_list, M_DEVBUF); 560 sc->Tx_list = NULL; 561 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 562 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 563 sc->hw_Tx_list = NULL; 564 } 565 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 566 ifp->if_timer = 0; 567 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 568 } 569 570 static void tl_restart(v) 571 void *v; 572 { 573 tl_init(v); 574 } 575 576 static int tl_init(ifp) 577 struct ifnet *ifp; 578 { 579 tl_softc_t *sc = ifp->if_softc; 580 int i, s, error; 581 char *errstring; 582 char *nullbuf; 583 584 s = splnet(); 585 /* cancel any pending IO */ 586 tl_stop(ifp, 1); 587 tl_reset(sc); 588 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 589 splx(s); 590 return 0; 591 } 592 /* Set various register to reasonable value */ 593 /* setup NetCmd in promisc mode if needed */ 594 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 595 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 596 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 597 /* Max receive size : MCLBYTES */ 598 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 599 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 600 (MCLBYTES >> 8) & 0xff); 601 602 /* init MAC addr */ 603 for (i = 0; i < ETHER_ADDR_LEN; i++) 604 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 605 /* add multicast filters */ 606 tl_addr_filter(sc); 607 #ifdef TLDEBUG_ADDR 608 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 609 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 610 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 611 #endif 612 613 /* Pre-allocate receivers mbuf, make the lists */ 614 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 615 M_NOWAIT|M_ZERO); 616 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 617 M_NOWAIT|M_ZERO); 618 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 619 errstring = "out of memory for lists"; 620 error = ENOMEM; 621 goto bad; 622 } 623 error = bus_dmamap_create(sc->tl_dmatag, 624 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 625 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 626 &sc->Rx_dmamap); 627 if (error == 0) 628 error = bus_dmamap_create(sc->tl_dmatag, 629 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 630 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 631 &sc->Tx_dmamap); 632 if (error == 0) 633 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 634 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 635 &sc->null_dmamap); 636 if (error) { 637 errstring = "can't allocate DMA maps for lists"; 638 goto bad; 639 } 640 memset(sc->ctrl, 0, PAGE_SIZE); 641 sc->hw_Rx_list = (void *)sc->ctrl; 642 sc->hw_Tx_list = 643 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 644 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 645 sizeof(struct tl_Tx_list) * TL_NBUF; 646 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 647 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 648 BUS_DMA_WAITOK); 649 if (error == 0) 650 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 651 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 652 BUS_DMA_WAITOK); 653 if (error == 0) 654 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 655 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 656 if (error) { 657 errstring = "can't DMA map DMA memory for lists"; 658 goto bad; 659 } 660 for (i=0; i< TL_NBUF; i++) { 661 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 662 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 663 &sc->Rx_list[i].m_dmamap); 664 if (error == 0) { 665 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 666 TL_NSEG, MCLBYTES, 0, 667 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 668 &sc->Tx_list[i].m_dmamap); 669 } 670 if (error) { 671 errstring = "can't allocate DMA maps for mbufs"; 672 goto bad; 673 } 674 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 675 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 676 + sizeof(struct tl_Rx_list) * i; 677 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 678 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 679 + sizeof(struct tl_Tx_list) * i; 680 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 681 errstring = "out of mbuf for receive list"; 682 error = ENOMEM; 683 goto bad; 684 } 685 if (i > 0) { /* chain the list */ 686 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 687 sc->hw_Rx_list[i-1].fwd = 688 htole32(sc->Rx_list[i].hw_listaddr); 689 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 690 } 691 } 692 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 693 sc->Rx_list[TL_NBUF-1].next = NULL; 694 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 695 sc->Tx_list[TL_NBUF-1].next = NULL; 696 697 sc->active_Rx = &sc->Rx_list[0]; 698 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 699 sc->active_Tx = sc->last_Tx = NULL; 700 sc->Free_Tx = &sc->Tx_list[0]; 701 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 702 sizeof(struct tl_Rx_list) * TL_NBUF, 703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 704 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 705 sizeof(struct tl_Tx_list) * TL_NBUF, 706 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 707 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 708 BUS_DMASYNC_PREWRITE); 709 710 /* set media */ 711 mii_mediachg(&sc->tl_mii); 712 713 /* start ticks calls */ 714 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 715 /* write adress of Rx list and enable interrupts */ 716 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 717 TL_HR_WRITE(sc, TL_HOST_CMD, 718 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 719 sc->tl_if.if_flags |= IFF_RUNNING; 720 sc->tl_if.if_flags &= ~IFF_OACTIVE; 721 return 0; 722 bad: 723 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 724 splx(s); 725 return error; 726 } 727 728 729 static u_int32_t 730 tl_intreg_read(sc, reg) 731 tl_softc_t *sc; 732 u_int32_t reg; 733 { 734 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 735 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 736 } 737 738 static u_int8_t 739 tl_intreg_read_byte(sc, reg) 740 tl_softc_t *sc; 741 u_int32_t reg; 742 { 743 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 744 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 745 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 746 } 747 748 static void 749 tl_intreg_write(sc, reg, val) 750 tl_softc_t *sc; 751 u_int32_t reg; 752 u_int32_t val; 753 { 754 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 755 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 756 } 757 758 static void 759 tl_intreg_write_byte(sc, reg, val) 760 tl_softc_t *sc; 761 u_int32_t reg; 762 u_int8_t val; 763 { 764 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 765 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 766 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 767 } 768 769 void 770 tl_mii_sync(sc) 771 struct tl_softc *sc; 772 { 773 int i; 774 775 netsio_clr(sc, TL_NETSIO_MTXEN); 776 for (i = 0; i < 32; i++) { 777 netsio_clr(sc, TL_NETSIO_MCLK); 778 netsio_set(sc, TL_NETSIO_MCLK); 779 } 780 } 781 782 void 783 tl_mii_sendbits(sc, data, nbits) 784 struct tl_softc *sc; 785 u_int32_t data; 786 int nbits; 787 { 788 int i; 789 790 netsio_set(sc, TL_NETSIO_MTXEN); 791 for (i = 1 << (nbits - 1); i; i = i >> 1) { 792 netsio_clr(sc, TL_NETSIO_MCLK); 793 netsio_read(sc, TL_NETSIO_MCLK); 794 if (data & i) 795 netsio_set(sc, TL_NETSIO_MDATA); 796 else 797 netsio_clr(sc, TL_NETSIO_MDATA); 798 netsio_set(sc, TL_NETSIO_MCLK); 799 netsio_read(sc, TL_NETSIO_MCLK); 800 } 801 } 802 803 int 804 tl_mii_read(self, phy, reg) 805 struct device *self; 806 int phy, reg; 807 { 808 struct tl_softc *sc = (struct tl_softc *)self; 809 int val = 0, i, err; 810 811 /* 812 * Read the PHY register by manually driving the MII control lines. 813 */ 814 815 tl_mii_sync(sc); 816 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 817 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 818 tl_mii_sendbits(sc, phy, 5); 819 tl_mii_sendbits(sc, reg, 5); 820 821 netsio_clr(sc, TL_NETSIO_MTXEN); 822 netsio_clr(sc, TL_NETSIO_MCLK); 823 netsio_set(sc, TL_NETSIO_MCLK); 824 netsio_clr(sc, TL_NETSIO_MCLK); 825 826 err = netsio_read(sc, TL_NETSIO_MDATA); 827 netsio_set(sc, TL_NETSIO_MCLK); 828 829 /* Even if an error occurs, must still clock out the cycle. */ 830 for (i = 0; i < 16; i++) { 831 val <<= 1; 832 netsio_clr(sc, TL_NETSIO_MCLK); 833 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 834 val |= 1; 835 netsio_set(sc, TL_NETSIO_MCLK); 836 } 837 netsio_clr(sc, TL_NETSIO_MCLK); 838 netsio_set(sc, TL_NETSIO_MCLK); 839 840 return (err ? 0 : val); 841 } 842 843 void 844 tl_mii_write(self, phy, reg, val) 845 struct device *self; 846 int phy, reg, val; 847 { 848 struct tl_softc *sc = (struct tl_softc *)self; 849 850 /* 851 * Write the PHY register by manually driving the MII control lines. 852 */ 853 854 tl_mii_sync(sc); 855 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 856 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 857 tl_mii_sendbits(sc, phy, 5); 858 tl_mii_sendbits(sc, reg, 5); 859 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 860 tl_mii_sendbits(sc, val, 16); 861 862 netsio_clr(sc, TL_NETSIO_MCLK); 863 netsio_set(sc, TL_NETSIO_MCLK); 864 } 865 866 void 867 tl_statchg(self) 868 struct device *self; 869 { 870 tl_softc_t *sc = (struct tl_softc *)self; 871 u_int32_t reg; 872 873 #ifdef TLDEBUG 874 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 875 #endif 876 877 /* 878 * We must keep the ThunderLAN and the PHY in sync as 879 * to the status of full-duplex! 880 */ 881 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 882 if (sc->tl_mii.mii_media_active & IFM_FDX) 883 reg |= TL_NETCOMMAND_DUPLEX; 884 else 885 reg &= ~TL_NETCOMMAND_DUPLEX; 886 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 887 } 888 889 void tl_i2c_set(v, bit) 890 void *v; 891 u_int8_t bit; 892 { 893 tl_softc_t *sc = v; 894 895 switch (bit) { 896 case I2C_DATA: 897 netsio_set(sc, TL_NETSIO_EDATA); 898 break; 899 case I2C_CLOCK: 900 netsio_set(sc, TL_NETSIO_ECLOCK); 901 break; 902 case I2C_TXEN: 903 netsio_set(sc, TL_NETSIO_ETXEN); 904 break; 905 default: 906 printf("tl_i2c_set: unknown bit %d\n", bit); 907 } 908 return; 909 } 910 911 void tl_i2c_clr(v, bit) 912 void *v; 913 u_int8_t bit; 914 { 915 tl_softc_t *sc = v; 916 917 switch (bit) { 918 case I2C_DATA: 919 netsio_clr(sc, TL_NETSIO_EDATA); 920 break; 921 case I2C_CLOCK: 922 netsio_clr(sc, TL_NETSIO_ECLOCK); 923 break; 924 case I2C_TXEN: 925 netsio_clr(sc, TL_NETSIO_ETXEN); 926 break; 927 default: 928 printf("tl_i2c_clr: unknown bit %d\n", bit); 929 } 930 return; 931 } 932 933 int tl_i2c_read(v, bit) 934 void *v; 935 u_int8_t bit; 936 { 937 tl_softc_t *sc = v; 938 939 switch (bit) { 940 case I2C_DATA: 941 return netsio_read(sc, TL_NETSIO_EDATA); 942 break; 943 case I2C_CLOCK: 944 return netsio_read(sc, TL_NETSIO_ECLOCK); 945 break; 946 case I2C_TXEN: 947 return netsio_read(sc, TL_NETSIO_ETXEN); 948 break; 949 default: 950 printf("tl_i2c_read: unknown bit %d\n", bit); 951 return -1; 952 } 953 } 954 955 static int 956 tl_intr(v) 957 void *v; 958 { 959 tl_softc_t *sc = v; 960 struct ifnet *ifp = &sc->tl_if; 961 struct Rx_list *Rx; 962 struct Tx_list *Tx; 963 struct mbuf *m; 964 u_int32_t int_type, int_reg; 965 int ack = 0; 966 int size; 967 968 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 969 int_type = int_reg & TL_INTR_MASK; 970 if (int_type == 0) 971 return 0; 972 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 973 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 974 int_type, int_reg); 975 #endif 976 /* disable interrupts */ 977 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 978 switch(int_type & TL_INTR_MASK) { 979 case TL_INTR_RxEOF: 980 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 981 sizeof(struct tl_Rx_list) * TL_NBUF, 982 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 983 while(le32toh(sc->active_Rx->hw_list->stat) & 984 TL_RX_CSTAT_CPLT) { 985 /* dequeue and requeue at end of list */ 986 ack++; 987 Rx = sc->active_Rx; 988 sc->active_Rx = Rx->next; 989 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 990 MCLBYTES, BUS_DMASYNC_POSTREAD); 991 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 992 m = Rx->m; 993 size = le32toh(Rx->hw_list->stat) >> 16; 994 #ifdef TLDEBUG_RX 995 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 996 Rx, size); 997 #endif 998 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 999 /* 1000 * No new mbuf, reuse the same. This means 1001 * that this packet 1002 * is lost 1003 */ 1004 m = NULL; 1005 #ifdef TL_PRIV_STATS 1006 sc->ierr_nomem++; 1007 #endif 1008 #ifdef TLDEBUG 1009 printf("%s: out of mbuf, lost input packet\n", 1010 sc->sc_dev.dv_xname); 1011 #endif 1012 } 1013 Rx->next = NULL; 1014 Rx->hw_list->fwd = 0; 1015 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1016 sc->last_Rx->next = Rx; 1017 sc->last_Rx = Rx; 1018 1019 /* deliver packet */ 1020 if (m) { 1021 if (size < sizeof(struct ether_header)) { 1022 m_freem(m); 1023 continue; 1024 } 1025 m->m_pkthdr.rcvif = ifp; 1026 m->m_pkthdr.len = m->m_len = size; 1027 #ifdef TLDEBUG_RX 1028 { struct ether_header *eh = 1029 mtod(m, struct ether_header *); 1030 printf("tl_intr: Rx packet:\n"); 1031 ether_printheader(eh); } 1032 #endif 1033 #if NBPFILTER > 0 1034 if (ifp->if_bpf) 1035 bpf_mtap(ifp->if_bpf, m); 1036 #endif /* NBPFILTER > 0 */ 1037 (*ifp->if_input)(ifp, m); 1038 } 1039 } 1040 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1041 sizeof(struct tl_Rx_list) * TL_NBUF, 1042 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1043 #ifdef TLDEBUG_RX 1044 printf("TL_INTR_RxEOF: ack %d\n", ack); 1045 #else 1046 if (ack == 0) { 1047 printf("%s: EOF intr without anything to read !\n", 1048 sc->sc_dev.dv_xname); 1049 tl_reset(sc); 1050 /* shedule reinit of the board */ 1051 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1052 return(1); 1053 } 1054 #endif 1055 break; 1056 case TL_INTR_RxEOC: 1057 ack++; 1058 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1059 sizeof(struct tl_Rx_list) * TL_NBUF, 1060 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1061 #ifdef TLDEBUG_RX 1062 printf("TL_INTR_RxEOC: ack %d\n", ack); 1063 #endif 1064 #ifdef DIAGNOSTIC 1065 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1066 printf("%s: Rx EOC interrupt and active Tx list not " 1067 "cleared\n", sc->sc_dev.dv_xname); 1068 return 0; 1069 } else 1070 #endif 1071 { 1072 /* 1073 * write adress of Rx list and send Rx GO command, ack 1074 * interrupt and enable interrupts in one command 1075 */ 1076 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1077 TL_HR_WRITE(sc, TL_HOST_CMD, 1078 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1079 HOST_CMD_ACK | HOST_CMD_IntOn); 1080 return 1; 1081 } 1082 case TL_INTR_TxEOF: 1083 case TL_INTR_TxEOC: 1084 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1085 sizeof(struct tl_Tx_list) * TL_NBUF, 1086 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1087 while ((Tx = sc->active_Tx) != NULL) { 1088 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1089 break; 1090 ack++; 1091 #ifdef TLDEBUG_TX 1092 printf("TL_INTR_TxEOC: list 0x%x done\n", 1093 (int)Tx->hw_listaddr); 1094 #endif 1095 Tx->hw_list->stat = 0; 1096 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1097 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1098 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1099 m_freem(Tx->m); 1100 Tx->m = NULL; 1101 sc->active_Tx = Tx->next; 1102 if (sc->active_Tx == NULL) 1103 sc->last_Tx = NULL; 1104 Tx->next = sc->Free_Tx; 1105 sc->Free_Tx = Tx; 1106 } 1107 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1108 sizeof(struct tl_Tx_list) * TL_NBUF, 1109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1110 /* if this was an EOC, ACK immediatly */ 1111 if (ack) 1112 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1113 if (int_type == TL_INTR_TxEOC) { 1114 #ifdef TLDEBUG_TX 1115 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1116 ack); 1117 #endif 1118 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1119 HOST_CMD_ACK | HOST_CMD_IntOn); 1120 if ( sc->active_Tx != NULL) { 1121 /* needs a Tx go command */ 1122 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1123 sc->active_Tx->hw_listaddr); 1124 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1125 } 1126 sc->tl_if.if_timer = 0; 1127 if (sc->tl_if.if_snd.ifq_head != NULL) 1128 tl_ifstart(&sc->tl_if); 1129 return 1; 1130 } 1131 #ifdef TLDEBUG 1132 else { 1133 printf("TL_INTR_TxEOF: ack %d\n", ack); 1134 } 1135 #endif 1136 sc->tl_if.if_timer = 0; 1137 if (sc->tl_if.if_snd.ifq_head != NULL) 1138 tl_ifstart(&sc->tl_if); 1139 break; 1140 case TL_INTR_Stat: 1141 ack++; 1142 #ifdef TLDEBUG 1143 printf("TL_INTR_Stat: ack %d\n", ack); 1144 #endif 1145 tl_read_stats(sc); 1146 break; 1147 case TL_INTR_Adc: 1148 if (int_reg & TL_INTVec_MASK) { 1149 /* adapter check conditions */ 1150 printf("%s: check condition, intvect=0x%x, " 1151 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1152 int_reg & TL_INTVec_MASK, 1153 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1154 tl_reset(sc); 1155 /* shedule reinit of the board */ 1156 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1157 return(1); 1158 } else { 1159 u_int8_t netstat; 1160 /* Network status */ 1161 netstat = 1162 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1163 printf("%s: network status, NetSts=%x\n", 1164 sc->sc_dev.dv_xname, netstat); 1165 /* Ack interrupts */ 1166 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1167 netstat); 1168 ack++; 1169 } 1170 break; 1171 default: 1172 printf("%s: unhandled interrupt code %x!\n", 1173 sc->sc_dev.dv_xname, int_type); 1174 ack++; 1175 } 1176 1177 if (ack) { 1178 /* Ack the interrupt and enable interrupts */ 1179 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1180 HOST_CMD_IntOn); 1181 return 1; 1182 } 1183 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1184 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1185 return 0; 1186 } 1187 1188 static int 1189 tl_ifioctl(ifp, cmd, data) 1190 struct ifnet *ifp; 1191 ioctl_cmd_t cmd; 1192 caddr_t data; 1193 { 1194 struct tl_softc *sc = ifp->if_softc; 1195 struct ifreq *ifr = (struct ifreq *)data; 1196 int s, error; 1197 1198 s = splnet(); 1199 switch(cmd) { 1200 case SIOCSIFMEDIA: 1201 case SIOCGIFMEDIA: 1202 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1203 break; 1204 default: 1205 error = ether_ioctl(ifp, cmd, data); 1206 if (error == ENETRESET) { 1207 tl_addr_filter(sc); 1208 error = 0; 1209 } 1210 } 1211 splx(s); 1212 return error; 1213 } 1214 1215 static void 1216 tl_ifstart(ifp) 1217 struct ifnet *ifp; 1218 { 1219 tl_softc_t *sc = ifp->if_softc; 1220 struct mbuf *mb_head; 1221 struct Tx_list *Tx; 1222 int segment, size; 1223 int again, error; 1224 1225 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1226 return; 1227 txloop: 1228 /* If we don't have more space ... */ 1229 if (sc->Free_Tx == NULL) { 1230 #ifdef TLDEBUG 1231 printf("tl_ifstart: No free TX list\n"); 1232 #endif 1233 sc->tl_if.if_flags |= IFF_OACTIVE; 1234 return; 1235 } 1236 /* Grab a paquet for output */ 1237 IF_DEQUEUE(&ifp->if_snd, mb_head); 1238 if (mb_head == NULL) { 1239 #ifdef TLDEBUG_TX 1240 printf("tl_ifstart: nothing to send\n"); 1241 #endif 1242 return; 1243 } 1244 Tx = sc->Free_Tx; 1245 sc->Free_Tx = Tx->next; 1246 Tx->next = NULL; 1247 again = 0; 1248 /* 1249 * Go through each of the mbufs in the chain and initialize 1250 * the transmit list descriptors with the physical address 1251 * and size of the mbuf. 1252 */ 1253 tbdinit: 1254 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1255 Tx->m = mb_head; 1256 size = mb_head->m_pkthdr.len; 1257 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1258 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1259 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1260 struct mbuf *mn; 1261 /* 1262 * We ran out of segments, or we will. We have to recopy this 1263 * mbuf chain first. 1264 */ 1265 if (error == 0) 1266 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1267 if (again) { 1268 /* already copyed, can't do much more */ 1269 m_freem(mb_head); 1270 goto bad; 1271 } 1272 again = 1; 1273 #ifdef TLDEBUG_TX 1274 printf("tl_ifstart: need to copy mbuf\n"); 1275 #endif 1276 #ifdef TL_PRIV_STATS 1277 sc->oerr_mcopy++; 1278 #endif 1279 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1280 if (mn == NULL) { 1281 m_freem(mb_head); 1282 goto bad; 1283 } 1284 if (mb_head->m_pkthdr.len > MHLEN) { 1285 MCLGET(mn, M_DONTWAIT); 1286 if ((mn->m_flags & M_EXT) == 0) { 1287 m_freem(mn); 1288 m_freem(mb_head); 1289 goto bad; 1290 } 1291 } 1292 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1293 mtod(mn, caddr_t)); 1294 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1295 m_freem(mb_head); 1296 mb_head = mn; 1297 goto tbdinit; 1298 } 1299 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1300 Tx->hw_list->seg[segment].data_addr = 1301 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1302 Tx->hw_list->seg[segment].data_count = 1303 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1304 } 1305 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1306 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1307 /* We are at end of mbuf chain. check the size and 1308 * see if it needs to be extended 1309 */ 1310 if (size < ETHER_MIN_TX) { 1311 #ifdef DIAGNOSTIC 1312 if (segment >= TL_NSEG) { 1313 panic("tl_ifstart: to much segmets (%d)\n", segment); 1314 } 1315 #endif 1316 /* 1317 * add the nullbuf in the seg 1318 */ 1319 Tx->hw_list->seg[segment].data_count = 1320 htole32(ETHER_MIN_TX - size); 1321 Tx->hw_list->seg[segment].data_addr = 1322 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1323 size = ETHER_MIN_TX; 1324 segment++; 1325 } 1326 /* The list is done, finish the list init */ 1327 Tx->hw_list->seg[segment-1].data_count |= 1328 htole32(TL_LAST_SEG); 1329 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1330 #ifdef TLDEBUG_TX 1331 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1332 le32toh(Tx->hw_list->stat)); 1333 #if 0 1334 for(segment = 0; segment < TL_NSEG; segment++) { 1335 printf(" seg %d addr 0x%x len 0x%x\n", 1336 segment, 1337 le32toh(Tx->hw_list->seg[segment].data_addr), 1338 le32toh(Tx->hw_list->seg[segment].data_count)); 1339 } 1340 #endif 1341 #endif 1342 if (sc->active_Tx == NULL) { 1343 sc->active_Tx = sc->last_Tx = Tx; 1344 #ifdef TLDEBUG_TX 1345 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1346 (int)Tx->hw_listaddr); 1347 #endif 1348 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1349 sizeof(struct tl_Tx_list) * TL_NBUF, 1350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1351 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1352 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1353 } else { 1354 #ifdef TLDEBUG_TX 1355 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1356 (int)Tx->hw_listaddr); 1357 #endif 1358 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1359 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1360 sizeof(struct tl_Tx_list) * TL_NBUF, 1361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1362 sc->last_Tx->next = Tx; 1363 sc->last_Tx = Tx; 1364 #ifdef DIAGNOSTIC 1365 if (sc->last_Tx->hw_list->fwd & 0x7) 1366 printf("%s: physical addr 0x%x of list not properly " 1367 "aligned\n", 1368 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1369 #endif 1370 } 1371 #if NBPFILTER > 0 1372 /* Pass packet to bpf if there is a listener */ 1373 if (ifp->if_bpf) 1374 bpf_mtap(ifp->if_bpf, mb_head); 1375 #endif 1376 /* 1377 * Set a 5 second timer just in case we don't hear from the card again. 1378 */ 1379 ifp->if_timer = 5; 1380 goto txloop; 1381 bad: 1382 #ifdef TLDEBUG 1383 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1384 #endif 1385 Tx->next = sc->Free_Tx; 1386 sc->Free_Tx = Tx; 1387 return; 1388 } 1389 1390 static void 1391 tl_ifwatchdog(ifp) 1392 struct ifnet *ifp; 1393 { 1394 tl_softc_t *sc = ifp->if_softc; 1395 1396 if ((ifp->if_flags & IFF_RUNNING) == 0) 1397 return; 1398 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1399 ifp->if_oerrors++; 1400 tl_init(ifp); 1401 } 1402 1403 static int 1404 tl_mediachange(ifp) 1405 struct ifnet *ifp; 1406 { 1407 1408 if (ifp->if_flags & IFF_UP) 1409 tl_init(ifp->if_softc); 1410 return (0); 1411 } 1412 1413 static void 1414 tl_mediastatus(ifp, ifmr) 1415 struct ifnet *ifp; 1416 struct ifmediareq *ifmr; 1417 { 1418 tl_softc_t *sc = ifp->if_softc; 1419 1420 mii_pollstat(&sc->tl_mii); 1421 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1422 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1423 } 1424 1425 static int tl_add_RxBuff(sc, Rx, oldm) 1426 tl_softc_t *sc; 1427 struct Rx_list *Rx; 1428 struct mbuf *oldm; 1429 { 1430 struct mbuf *m; 1431 int error; 1432 1433 MGETHDR(m, M_DONTWAIT, MT_DATA); 1434 if (m != NULL) { 1435 MCLGET(m, M_DONTWAIT); 1436 if ((m->m_flags & M_EXT) == 0) { 1437 m_freem(m); 1438 if (oldm == NULL) 1439 return 0; 1440 m = oldm; 1441 m->m_data = m->m_ext.ext_buf; 1442 } 1443 } else { 1444 if (oldm == NULL) 1445 return 0; 1446 m = oldm; 1447 m->m_data = m->m_ext.ext_buf; 1448 } 1449 1450 /* (re)init the Rx_list struct */ 1451 1452 Rx->m = m; 1453 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1454 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1455 printf("%s: bus_dmamap_load() failed (error %d) for " 1456 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1457 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1458 m_freem(m); 1459 Rx->m = NULL; 1460 return 0; 1461 } 1462 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1463 MCLBYTES, BUS_DMASYNC_PREREAD); 1464 /* 1465 * Move the data pointer up so that the incoming data packet 1466 * will be 32-bit aligned. 1467 */ 1468 m->m_data += 2; 1469 1470 Rx->hw_list->stat = 1471 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1472 Rx->hw_list->seg.data_count = 1473 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1474 Rx->hw_list->seg.data_addr = 1475 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1476 return (m != oldm); 1477 } 1478 1479 static void tl_ticks(v) 1480 void *v; 1481 { 1482 tl_softc_t *sc = v; 1483 1484 tl_read_stats(sc); 1485 1486 /* Tick the MII. */ 1487 mii_tick(&sc->tl_mii); 1488 1489 /* read statistics every seconds */ 1490 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1491 } 1492 1493 static void 1494 tl_read_stats(sc) 1495 tl_softc_t *sc; 1496 { 1497 u_int32_t reg; 1498 int ierr_overr; 1499 int ierr_code; 1500 int ierr_crc; 1501 int oerr_underr; 1502 int oerr_deffered; 1503 int oerr_coll; 1504 int oerr_multicoll; 1505 int oerr_exesscoll; 1506 int oerr_latecoll; 1507 int oerr_carrloss; 1508 struct ifnet *ifp = &sc->tl_if; 1509 1510 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1511 ifp->if_opackets += reg & 0x00ffffff; 1512 oerr_underr = reg >> 24; 1513 1514 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1515 ifp->if_ipackets += reg & 0x00ffffff; 1516 ierr_overr = reg >> 24; 1517 1518 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1519 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1520 ierr_code = (reg & TL_FERR_CODE) >> 24; 1521 oerr_deffered = (reg & TL_FERR_DEF); 1522 1523 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1524 oerr_multicoll = (reg & TL_COL_MULTI); 1525 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1526 1527 reg = tl_intreg_read(sc, TL_INT_LERR); 1528 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1529 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1530 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1531 1532 1533 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1534 oerr_carrloss; 1535 ifp->if_collisions += oerr_coll + oerr_multicoll; 1536 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1537 1538 if (ierr_overr) 1539 printf("%s: receiver ring buffer overrun\n", 1540 sc->sc_dev.dv_xname); 1541 if (oerr_underr) 1542 printf("%s: transmit buffer underrun\n", 1543 sc->sc_dev.dv_xname); 1544 #ifdef TL_PRIV_STATS 1545 sc->ierr_overr += ierr_overr; 1546 sc->ierr_code += ierr_code; 1547 sc->ierr_crc += ierr_crc; 1548 sc->oerr_underr += oerr_underr; 1549 sc->oerr_deffered += oerr_deffered; 1550 sc->oerr_coll += oerr_coll; 1551 sc->oerr_multicoll += oerr_multicoll; 1552 sc->oerr_exesscoll += oerr_exesscoll; 1553 sc->oerr_latecoll += oerr_latecoll; 1554 sc->oerr_carrloss += oerr_carrloss; 1555 #endif 1556 } 1557 1558 static void tl_addr_filter(sc) 1559 tl_softc_t *sc; 1560 { 1561 struct ether_multistep step; 1562 struct ether_multi *enm; 1563 u_int32_t hash[2] = {0, 0}; 1564 int i; 1565 1566 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1567 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1568 while (enm != NULL) { 1569 #ifdef TLDEBUG 1570 printf("tl_addr_filter: addrs %s %s\n", 1571 ether_sprintf(enm->enm_addrlo), 1572 ether_sprintf(enm->enm_addrhi)); 1573 #endif 1574 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1575 i = tl_multicast_hash(enm->enm_addrlo); 1576 hash[i/32] |= 1 << (i%32); 1577 } else { 1578 hash[0] = hash[1] = 0xffffffff; 1579 sc->tl_if.if_flags |= IFF_ALLMULTI; 1580 break; 1581 } 1582 ETHER_NEXT_MULTI(step, enm); 1583 } 1584 #ifdef TLDEBUG 1585 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1586 #endif 1587 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1588 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1589 } 1590 1591 static int tl_multicast_hash(a) 1592 u_int8_t *a; 1593 { 1594 int hash; 1595 1596 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1597 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1598 1599 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1600 DA(a,36), DA(a,42)); 1601 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1602 DA(a,37), DA(a,43)) << 1; 1603 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1604 DA(a,38), DA(a,44)) << 2; 1605 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1606 DA(a,39), DA(a,45)) << 3; 1607 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1608 DA(a,40), DA(a,46)) << 4; 1609 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1610 DA(a,41), DA(a,47)) << 5; 1611 1612 return hash; 1613 } 1614 1615 #if defined(TLDEBUG_RX) 1616 void 1617 ether_printheader(eh) 1618 struct ether_header *eh; 1619 { 1620 u_char *c = (char*)eh; 1621 int i; 1622 for (i=0; i<sizeof(struct ether_header); i++) 1623 printf("%x ", (u_int)c[i]); 1624 printf("\n"); 1625 } 1626 #endif 1627
Indexes created Thu Sep 25 14:09:45 GMT 2025