if_tl.c revision 1.52.4.1
1 /* $NetBSD: if_tl.c,v 1.52.4.1 2003/06/30 02:47:21 grant Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.52.4.1 2003/06/30 02:47:21 grant Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 /* number of transmit/receive buffers */ 116 #ifndef TL_NBUF 117 #define TL_NBUF 10 118 #endif 119 120 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 121 static void tl_pci_attach __P((struct device *, struct device *, void *)); 122 static int tl_intr __P((void *)); 123 124 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 125 static int tl_mediachange __P((struct ifnet *)); 126 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 127 static void tl_ifwatchdog __P((struct ifnet *)); 128 static void tl_shutdown __P((void*)); 129 130 static void tl_ifstart __P((struct ifnet *)); 131 static void tl_reset __P((tl_softc_t*)); 132 static int tl_init __P((struct ifnet *)); 133 static void tl_stop __P((struct ifnet *, int)); 134 static void tl_restart __P((void *)); 135 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 136 static void tl_read_stats __P((tl_softc_t*)); 137 static void tl_ticks __P((void*)); 138 static int tl_multicast_hash __P((u_int8_t*)); 139 static void tl_addr_filter __P((tl_softc_t*)); 140 141 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 143 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 145 146 void tl_mii_sync __P((struct tl_softc *)); 147 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader __P((struct ether_header*)); 152 #endif 153 154 int tl_mii_read __P((struct device *, int, int)); 155 void tl_mii_write __P((struct device *, int, int, int)); 156 157 void tl_statchg __P((struct device *)); 158 159 void tl_i2c_set __P((void*, u_int8_t)); 160 void tl_i2c_clr __P((void*, u_int8_t)); 161 int tl_i2c_read __P((void*, u_int8_t)); 162 163 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 165 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_clr(sc, bits) 167 tl_softc_t* sc; 168 u_int8_t bits; 169 { 170 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 171 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 172 } 173 static __inline void netsio_set(sc, bits) 174 tl_softc_t* sc; 175 u_int8_t bits; 176 { 177 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 178 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 179 } 180 static __inline u_int8_t netsio_read(sc, bits) 181 tl_softc_t* sc; 182 u_int8_t bits; 183 { 184 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 185 } 186 187 struct cfattach tl_ca = { 188 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 189 }; 190 191 const struct tl_product_desc tl_compaq_products[] = { 192 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 193 "Compaq Netelligent 10/100 TX" }, 194 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 195 "Compaq Netelligent 10 T" }, 196 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 197 "Compaq Integrated NetFlex 3/P" }, 198 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 199 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 200 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 201 "Compaq Dual Port Netelligent 10/100 TX" }, 202 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 203 "Compaq Deskpro 4000 5233MMX" }, 204 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 205 "Compaq NetFlex 3/P w/ BNC" }, 206 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 207 "Compaq NetFlex 3/P" }, 208 { 0, 0, NULL }, 209 }; 210 211 const struct tl_product_desc tl_ti_products[] = { 212 /* 213 * Built-in Ethernet on the TI TravelMate 5000 214 * docking station; better product description? 215 */ 216 { PCI_PRODUCT_TI_TLAN, 0, 217 "Texas Instruments ThunderLAN" }, 218 { 0, 0, NULL }, 219 }; 220 221 struct tl_vendor_desc { 222 u_int32_t tv_vendor; 223 const struct tl_product_desc *tv_products; 224 }; 225 226 const struct tl_vendor_desc tl_vendors[] = { 227 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 228 { PCI_VENDOR_TI, tl_ti_products }, 229 { 0, NULL }, 230 }; 231 232 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 233 234 const struct tl_product_desc * 235 tl_lookup_product(id) 236 u_int32_t id; 237 { 238 const struct tl_product_desc *tp; 239 const struct tl_vendor_desc *tv; 240 241 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 242 if (PCI_VENDOR(id) == tv->tv_vendor) 243 break; 244 245 if ((tp = tv->tv_products) == NULL) 246 return (NULL); 247 248 for (; tp->tp_desc != NULL; tp++) 249 if (PCI_PRODUCT(id) == tp->tp_product) 250 break; 251 252 if (tp->tp_desc == NULL) 253 return (NULL); 254 255 return (tp); 256 } 257 258 static int 259 tl_pci_match(parent, match, aux) 260 struct device *parent; 261 struct cfdata *match; 262 void *aux; 263 { 264 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 265 266 if (tl_lookup_product(pa->pa_id) != NULL) 267 return (1); 268 269 return (0); 270 } 271 272 static void 273 tl_pci_attach(parent, self, aux) 274 struct device * parent; 275 struct device * self; 276 void * aux; 277 { 278 tl_softc_t *sc = (tl_softc_t *)self; 279 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 280 const struct tl_product_desc *tp; 281 struct ifnet * const ifp = &sc->tl_if; 282 bus_space_tag_t iot, memt; 283 bus_space_handle_t ioh, memh; 284 pci_intr_handle_t intrhandle; 285 const char *intrstr; 286 int i, tmp, ioh_valid, memh_valid; 287 int reg_io, reg_mem; 288 pcireg_t reg10, reg14; 289 pcireg_t csr; 290 291 printf("\n"); 292 293 callout_init(&sc->tl_tick_ch); 294 callout_init(&sc->tl_restart_ch); 295 296 tp = tl_lookup_product(pa->pa_id); 297 if (tp == NULL) 298 panic("tl_pci_attach: impossible"); 299 sc->tl_product = tp; 300 301 /* 302 * Map the card space. First we have to find the I/O and MEM 303 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 304 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 305 * The ThunderLAN manual is not consistent about this either (there 306 * are both cases in code examples). 307 */ 308 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 309 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 310 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 311 reg_io = 0x10; 312 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 313 reg_io = 0x14; 314 else 315 reg_io = 0; 316 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 317 reg_mem = 0x10; 318 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 319 reg_mem = 0x14; 320 else 321 reg_mem = 0; 322 323 if (reg_io != 0) 324 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 325 0, &iot, &ioh, NULL, NULL) == 0); 326 else 327 ioh_valid = 0; 328 if (reg_mem != 0) 329 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 330 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 331 0, &memt, &memh, NULL, NULL) == 0); 332 else 333 memh_valid = 0; 334 335 if (ioh_valid) { 336 sc->tl_bustag = iot; 337 sc->tl_bushandle = ioh; 338 } else if (memh_valid) { 339 sc->tl_bustag = memt; 340 sc->tl_bushandle = memh; 341 } else { 342 printf("%s: unable to map device registers\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 sc->tl_dmatag = pa->pa_dmat; 347 348 /* Enable the device. */ 349 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 350 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 351 csr | PCI_COMMAND_MASTER_ENABLE); 352 353 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 354 355 tl_reset(sc); 356 357 /* fill in the i2c struct */ 358 sc->i2cbus.adapter_softc = sc; 359 sc->i2cbus.set_bit = tl_i2c_set; 360 sc->i2cbus.clr_bit = tl_i2c_clr; 361 sc->i2cbus.read_bit = tl_i2c_read; 362 363 #ifdef TLDEBUG 364 printf("default values of INTreg: 0x%x\n", 365 tl_intreg_read(sc, TL_INT_Defaults)); 366 #endif 367 368 /* read mac addr */ 369 for (i=0; i<ETHER_ADDR_LEN; i++) { 370 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 371 if (tmp < 0) { 372 printf("%s: error reading Ethernet adress\n", 373 sc->sc_dev.dv_xname); 374 return; 375 } else { 376 sc->tl_enaddr[i] = tmp; 377 } 378 } 379 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 380 ether_sprintf(sc->tl_enaddr)); 381 382 /* Map and establish interrupts */ 383 if (pci_intr_map(pa, &intrhandle)) { 384 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 385 return; 386 } 387 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 388 sc->tl_if.if_softc = sc; 389 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 390 tl_intr, sc); 391 if (sc->tl_ih == NULL) { 392 printf("%s: couldn't establish interrupt", 393 sc->sc_dev.dv_xname); 394 if (intrstr != NULL) 395 printf(" at %s", intrstr); 396 printf("\n"); 397 return; 398 } 399 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 400 401 /* init these pointers, so that tl_shutdown won't try to read them */ 402 sc->Rx_list = NULL; 403 sc->Tx_list = NULL; 404 405 /* allocate DMA-safe memory for control structs */ 406 if (bus_dmamem_alloc(sc->tl_dmatag, 407 PAGE_SIZE, 0, PAGE_SIZE, 408 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 409 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 410 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 411 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 412 printf("%s: can't allocate DMA memory for lists\n", 413 sc->sc_dev.dv_xname); 414 return; 415 } 416 /* 417 * Add shutdown hook so that DMA is disabled prior to reboot. Not 418 * doing 419 * reboot before the driver initializes. 420 */ 421 (void) shutdownhook_establish(tl_shutdown, ifp); 422 423 /* 424 * Initialize our media structures and probe the MII. 425 * 426 * Note that we don't care about the media instance. We 427 * are expecting to have multiple PHYs on the 10/100 cards, 428 * and on those cards we exclude the internal PHY from providing 429 * 10baseT. By ignoring the instance, it allows us to not have 430 * to specify it on the command line when switching media. 431 */ 432 sc->tl_mii.mii_ifp = ifp; 433 sc->tl_mii.mii_readreg = tl_mii_read; 434 sc->tl_mii.mii_writereg = tl_mii_write; 435 sc->tl_mii.mii_statchg = tl_statchg; 436 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 437 tl_mediastatus); 438 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 439 MII_OFFSET_ANY, 0); 440 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 441 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 442 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 443 } else 444 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 445 446 /* 447 * We can support 802.1Q VLAN-sized frames. 448 */ 449 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 450 451 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 452 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 453 ifp->if_ioctl = tl_ifioctl; 454 ifp->if_start = tl_ifstart; 455 ifp->if_watchdog = tl_ifwatchdog; 456 ifp->if_init = tl_init; 457 ifp->if_stop = tl_stop; 458 ifp->if_timer = 0; 459 IFQ_SET_READY(&ifp->if_snd); 460 if_attach(ifp); 461 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 462 } 463 464 static void 465 tl_reset(sc) 466 tl_softc_t *sc; 467 { 468 int i; 469 470 /* read stats */ 471 if (sc->tl_if.if_flags & IFF_RUNNING) { 472 callout_stop(&sc->tl_tick_ch); 473 tl_read_stats(sc); 474 } 475 /* Reset adapter */ 476 TL_HR_WRITE(sc, TL_HOST_CMD, 477 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 478 DELAY(100000); 479 /* Disable interrupts */ 480 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 481 /* setup aregs & hash */ 482 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 483 tl_intreg_write(sc, i, 0); 484 #ifdef TLDEBUG_ADDR 485 printf("Areg & hash registers: \n"); 486 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 487 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 488 #endif 489 /* Setup NetConfig */ 490 tl_intreg_write(sc, TL_INT_NetConfig, 491 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 492 /* Bsize: accept default */ 493 /* TX commit in Acommit: accept default */ 494 /* Load Ld_tmr and Ld_thr */ 495 /* Ld_tmr = 3 */ 496 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 497 /* Ld_thr = 0 */ 498 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 499 /* Unreset MII */ 500 netsio_set(sc, TL_NETSIO_NMRST); 501 DELAY(100000); 502 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 503 } 504 505 static void tl_shutdown(v) 506 void *v; 507 { 508 tl_stop(v, 1); 509 } 510 511 static void tl_stop(ifp, disable) 512 struct ifnet *ifp; 513 int disable; 514 { 515 tl_softc_t *sc = ifp->if_softc; 516 struct Tx_list *Tx; 517 int i; 518 519 if ((ifp->if_flags & IFF_RUNNING) == 0) 520 return; 521 /* disable interrupts */ 522 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 523 /* stop TX and RX channels */ 524 TL_HR_WRITE(sc, TL_HOST_CMD, 525 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 526 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 527 DELAY(100000); 528 529 /* stop statistics reading loop, read stats */ 530 callout_stop(&sc->tl_tick_ch); 531 tl_read_stats(sc); 532 533 /* Down the MII. */ 534 mii_down(&sc->tl_mii); 535 536 /* deallocate memory allocations */ 537 if (sc->Rx_list) { 538 for (i=0; i< TL_NBUF; i++) { 539 if (sc->Rx_list[i].m) { 540 bus_dmamap_unload(sc->tl_dmatag, 541 sc->Rx_list[i].m_dmamap); 542 m_freem(sc->Rx_list[i].m); 543 } 544 bus_dmamap_destroy(sc->tl_dmatag, 545 sc->Rx_list[i].m_dmamap); 546 sc->Rx_list[i].m = NULL; 547 } 548 free(sc->Rx_list, M_DEVBUF); 549 sc->Rx_list = NULL; 550 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 551 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 552 sc->hw_Rx_list = NULL; 553 while ((Tx = sc->active_Tx) != NULL) { 554 Tx->hw_list->stat = 0; 555 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 556 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 557 m_freem(Tx->m); 558 sc->active_Tx = Tx->next; 559 Tx->next = sc->Free_Tx; 560 sc->Free_Tx = Tx; 561 } 562 sc->last_Tx = NULL; 563 free(sc->Tx_list, M_DEVBUF); 564 sc->Tx_list = NULL; 565 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 566 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 567 sc->hw_Tx_list = NULL; 568 } 569 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 570 ifp->if_timer = 0; 571 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 572 } 573 574 static void tl_restart(v) 575 void *v; 576 { 577 tl_init(v); 578 } 579 580 static int tl_init(ifp) 581 struct ifnet *ifp; 582 { 583 tl_softc_t *sc = ifp->if_softc; 584 int i, s, error; 585 char *errstring; 586 char *nullbuf; 587 588 s = splnet(); 589 /* cancel any pending IO */ 590 tl_stop(ifp, 1); 591 tl_reset(sc); 592 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 593 splx(s); 594 return 0; 595 } 596 /* Set various register to reasonable value */ 597 /* setup NetCmd in promisc mode if needed */ 598 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 599 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 600 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 601 /* Max receive size : MCLBYTES */ 602 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 603 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 604 (MCLBYTES >> 8) & 0xff); 605 606 /* init MAC addr */ 607 for (i = 0; i < ETHER_ADDR_LEN; i++) 608 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 609 /* add multicast filters */ 610 tl_addr_filter(sc); 611 #ifdef TLDEBUG_ADDR 612 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 613 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 614 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 615 #endif 616 617 /* Pre-allocate receivers mbuf, make the lists */ 618 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 619 M_NOWAIT|M_ZERO); 620 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 621 M_NOWAIT|M_ZERO); 622 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 623 errstring = "out of memory for lists"; 624 error = ENOMEM; 625 goto bad; 626 } 627 error = bus_dmamap_create(sc->tl_dmatag, 628 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 629 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 630 &sc->Rx_dmamap); 631 if (error == 0) 632 error = bus_dmamap_create(sc->tl_dmatag, 633 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 634 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 635 &sc->Tx_dmamap); 636 if (error == 0) 637 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 638 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 639 &sc->null_dmamap); 640 if (error) { 641 errstring = "can't allocate DMA maps for lists"; 642 goto bad; 643 } 644 memset(sc->ctrl, 0, PAGE_SIZE); 645 sc->hw_Rx_list = (void *)sc->ctrl; 646 sc->hw_Tx_list = 647 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 648 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 649 sizeof(struct tl_Tx_list) * TL_NBUF; 650 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 651 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 652 BUS_DMA_WAITOK); 653 if (error == 0) 654 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 655 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 656 BUS_DMA_WAITOK); 657 if (error == 0) 658 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 659 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 660 if (error) { 661 errstring = "can't DMA map DMA memory for lists"; 662 goto bad; 663 } 664 for (i=0; i< TL_NBUF; i++) { 665 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 666 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 667 &sc->Rx_list[i].m_dmamap); 668 if (error == 0) { 669 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 670 TL_NSEG, MCLBYTES, 0, 671 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 672 &sc->Tx_list[i].m_dmamap); 673 } 674 if (error) { 675 errstring = "can't allocate DMA maps for mbufs"; 676 goto bad; 677 } 678 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 679 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 680 + sizeof(struct tl_Rx_list) * i; 681 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 682 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 683 + sizeof(struct tl_Tx_list) * i; 684 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 685 errstring = "out of mbuf for receive list"; 686 error = ENOMEM; 687 goto bad; 688 } 689 if (i > 0) { /* chain the list */ 690 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 691 sc->hw_Rx_list[i-1].fwd = 692 htole32(sc->Rx_list[i].hw_listaddr); 693 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 694 } 695 } 696 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 697 sc->Rx_list[TL_NBUF-1].next = NULL; 698 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 699 sc->Tx_list[TL_NBUF-1].next = NULL; 700 701 sc->active_Rx = &sc->Rx_list[0]; 702 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 703 sc->active_Tx = sc->last_Tx = NULL; 704 sc->Free_Tx = &sc->Tx_list[0]; 705 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 706 sizeof(struct tl_Rx_list) * TL_NBUF, 707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 708 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 709 sizeof(struct tl_Tx_list) * TL_NBUF, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 712 BUS_DMASYNC_PREWRITE); 713 714 /* set media */ 715 mii_mediachg(&sc->tl_mii); 716 717 /* start ticks calls */ 718 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 719 /* write adress of Rx list and enable interrupts */ 720 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 721 TL_HR_WRITE(sc, TL_HOST_CMD, 722 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 723 sc->tl_if.if_flags |= IFF_RUNNING; 724 sc->tl_if.if_flags &= ~IFF_OACTIVE; 725 return 0; 726 bad: 727 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 728 splx(s); 729 return error; 730 } 731 732 733 static u_int32_t 734 tl_intreg_read(sc, reg) 735 tl_softc_t *sc; 736 u_int32_t reg; 737 { 738 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 739 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 740 } 741 742 static u_int8_t 743 tl_intreg_read_byte(sc, reg) 744 tl_softc_t *sc; 745 u_int32_t reg; 746 { 747 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 748 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 749 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 750 } 751 752 static void 753 tl_intreg_write(sc, reg, val) 754 tl_softc_t *sc; 755 u_int32_t reg; 756 u_int32_t val; 757 { 758 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 759 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 760 } 761 762 static void 763 tl_intreg_write_byte(sc, reg, val) 764 tl_softc_t *sc; 765 u_int32_t reg; 766 u_int8_t val; 767 { 768 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 769 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 770 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 771 } 772 773 void 774 tl_mii_sync(sc) 775 struct tl_softc *sc; 776 { 777 int i; 778 779 netsio_clr(sc, TL_NETSIO_MTXEN); 780 for (i = 0; i < 32; i++) { 781 netsio_clr(sc, TL_NETSIO_MCLK); 782 netsio_set(sc, TL_NETSIO_MCLK); 783 } 784 } 785 786 void 787 tl_mii_sendbits(sc, data, nbits) 788 struct tl_softc *sc; 789 u_int32_t data; 790 int nbits; 791 { 792 int i; 793 794 netsio_set(sc, TL_NETSIO_MTXEN); 795 for (i = 1 << (nbits - 1); i; i = i >> 1) { 796 netsio_clr(sc, TL_NETSIO_MCLK); 797 netsio_read(sc, TL_NETSIO_MCLK); 798 if (data & i) 799 netsio_set(sc, TL_NETSIO_MDATA); 800 else 801 netsio_clr(sc, TL_NETSIO_MDATA); 802 netsio_set(sc, TL_NETSIO_MCLK); 803 netsio_read(sc, TL_NETSIO_MCLK); 804 } 805 } 806 807 int 808 tl_mii_read(self, phy, reg) 809 struct device *self; 810 int phy, reg; 811 { 812 struct tl_softc *sc = (struct tl_softc *)self; 813 int val = 0, i, err; 814 815 /* 816 * Read the PHY register by manually driving the MII control lines. 817 */ 818 819 tl_mii_sync(sc); 820 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 821 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 822 tl_mii_sendbits(sc, phy, 5); 823 tl_mii_sendbits(sc, reg, 5); 824 825 netsio_clr(sc, TL_NETSIO_MTXEN); 826 netsio_clr(sc, TL_NETSIO_MCLK); 827 netsio_set(sc, TL_NETSIO_MCLK); 828 netsio_clr(sc, TL_NETSIO_MCLK); 829 830 err = netsio_read(sc, TL_NETSIO_MDATA); 831 netsio_set(sc, TL_NETSIO_MCLK); 832 833 /* Even if an error occurs, must still clock out the cycle. */ 834 for (i = 0; i < 16; i++) { 835 val <<= 1; 836 netsio_clr(sc, TL_NETSIO_MCLK); 837 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 838 val |= 1; 839 netsio_set(sc, TL_NETSIO_MCLK); 840 } 841 netsio_clr(sc, TL_NETSIO_MCLK); 842 netsio_set(sc, TL_NETSIO_MCLK); 843 844 return (err ? 0 : val); 845 } 846 847 void 848 tl_mii_write(self, phy, reg, val) 849 struct device *self; 850 int phy, reg, val; 851 { 852 struct tl_softc *sc = (struct tl_softc *)self; 853 854 /* 855 * Write the PHY register by manually driving the MII control lines. 856 */ 857 858 tl_mii_sync(sc); 859 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 860 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 861 tl_mii_sendbits(sc, phy, 5); 862 tl_mii_sendbits(sc, reg, 5); 863 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 864 tl_mii_sendbits(sc, val, 16); 865 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 netsio_set(sc, TL_NETSIO_MCLK); 868 } 869 870 void 871 tl_statchg(self) 872 struct device *self; 873 { 874 tl_softc_t *sc = (struct tl_softc *)self; 875 u_int32_t reg; 876 877 #ifdef TLDEBUG 878 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 879 #endif 880 881 /* 882 * We must keep the ThunderLAN and the PHY in sync as 883 * to the status of full-duplex! 884 */ 885 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 886 if (sc->tl_mii.mii_media_active & IFM_FDX) 887 reg |= TL_NETCOMMAND_DUPLEX; 888 else 889 reg &= ~TL_NETCOMMAND_DUPLEX; 890 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 891 } 892 893 void tl_i2c_set(v, bit) 894 void *v; 895 u_int8_t bit; 896 { 897 tl_softc_t *sc = v; 898 899 switch (bit) { 900 case I2C_DATA: 901 netsio_set(sc, TL_NETSIO_EDATA); 902 break; 903 case I2C_CLOCK: 904 netsio_set(sc, TL_NETSIO_ECLOCK); 905 break; 906 case I2C_TXEN: 907 netsio_set(sc, TL_NETSIO_ETXEN); 908 break; 909 default: 910 printf("tl_i2c_set: unknown bit %d\n", bit); 911 } 912 return; 913 } 914 915 void tl_i2c_clr(v, bit) 916 void *v; 917 u_int8_t bit; 918 { 919 tl_softc_t *sc = v; 920 921 switch (bit) { 922 case I2C_DATA: 923 netsio_clr(sc, TL_NETSIO_EDATA); 924 break; 925 case I2C_CLOCK: 926 netsio_clr(sc, TL_NETSIO_ECLOCK); 927 break; 928 case I2C_TXEN: 929 netsio_clr(sc, TL_NETSIO_ETXEN); 930 break; 931 default: 932 printf("tl_i2c_clr: unknown bit %d\n", bit); 933 } 934 return; 935 } 936 937 int tl_i2c_read(v, bit) 938 void *v; 939 u_int8_t bit; 940 { 941 tl_softc_t *sc = v; 942 943 switch (bit) { 944 case I2C_DATA: 945 return netsio_read(sc, TL_NETSIO_EDATA); 946 break; 947 case I2C_CLOCK: 948 return netsio_read(sc, TL_NETSIO_ECLOCK); 949 break; 950 case I2C_TXEN: 951 return netsio_read(sc, TL_NETSIO_ETXEN); 952 break; 953 default: 954 printf("tl_i2c_read: unknown bit %d\n", bit); 955 return -1; 956 } 957 } 958 959 static int 960 tl_intr(v) 961 void *v; 962 { 963 tl_softc_t *sc = v; 964 struct ifnet *ifp = &sc->tl_if; 965 struct Rx_list *Rx; 966 struct Tx_list *Tx; 967 struct mbuf *m; 968 u_int32_t int_type, int_reg; 969 int ack = 0; 970 int size; 971 972 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 973 int_type = int_reg & TL_INTR_MASK; 974 if (int_type == 0) 975 return 0; 976 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 977 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 978 int_type, int_reg); 979 #endif 980 /* disable interrupts */ 981 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 982 switch(int_type & TL_INTR_MASK) { 983 case TL_INTR_RxEOF: 984 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 985 sizeof(struct tl_Rx_list) * TL_NBUF, 986 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 987 while(le32toh(sc->active_Rx->hw_list->stat) & 988 TL_RX_CSTAT_CPLT) { 989 /* dequeue and requeue at end of list */ 990 ack++; 991 Rx = sc->active_Rx; 992 sc->active_Rx = Rx->next; 993 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 994 MCLBYTES, BUS_DMASYNC_POSTREAD); 995 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 996 m = Rx->m; 997 size = le32toh(Rx->hw_list->stat) >> 16; 998 #ifdef TLDEBUG_RX 999 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1000 Rx, size); 1001 #endif 1002 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1003 /* 1004 * No new mbuf, reuse the same. This means 1005 * that this packet 1006 * is lost 1007 */ 1008 m = NULL; 1009 #ifdef TL_PRIV_STATS 1010 sc->ierr_nomem++; 1011 #endif 1012 #ifdef TLDEBUG 1013 printf("%s: out of mbuf, lost input packet\n", 1014 sc->sc_dev.dv_xname); 1015 #endif 1016 } 1017 Rx->next = NULL; 1018 Rx->hw_list->fwd = 0; 1019 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1020 sc->last_Rx->next = Rx; 1021 sc->last_Rx = Rx; 1022 1023 /* deliver packet */ 1024 if (m) { 1025 if (size < sizeof(struct ether_header)) { 1026 m_freem(m); 1027 continue; 1028 } 1029 m->m_pkthdr.rcvif = ifp; 1030 m->m_pkthdr.len = m->m_len = size; 1031 #ifdef TLDEBUG_RX 1032 { struct ether_header *eh = 1033 mtod(m, struct ether_header *); 1034 printf("tl_intr: Rx packet:\n"); 1035 ether_printheader(eh); } 1036 #endif 1037 #if NBPFILTER > 0 1038 if (ifp->if_bpf) 1039 bpf_mtap(ifp->if_bpf, m); 1040 #endif /* NBPFILTER > 0 */ 1041 (*ifp->if_input)(ifp, m); 1042 } 1043 } 1044 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1045 sizeof(struct tl_Rx_list) * TL_NBUF, 1046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1047 #ifdef TLDEBUG_RX 1048 printf("TL_INTR_RxEOF: ack %d\n", ack); 1049 #else 1050 if (ack == 0) { 1051 printf("%s: EOF intr without anything to read !\n", 1052 sc->sc_dev.dv_xname); 1053 tl_reset(sc); 1054 /* shedule reinit of the board */ 1055 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1056 return(1); 1057 } 1058 #endif 1059 break; 1060 case TL_INTR_RxEOC: 1061 ack++; 1062 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1063 sizeof(struct tl_Rx_list) * TL_NBUF, 1064 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1065 #ifdef TLDEBUG_RX 1066 printf("TL_INTR_RxEOC: ack %d\n", ack); 1067 #endif 1068 #ifdef DIAGNOSTIC 1069 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1070 printf("%s: Rx EOC interrupt and active Tx list not " 1071 "cleared\n", sc->sc_dev.dv_xname); 1072 return 0; 1073 } else 1074 #endif 1075 { 1076 /* 1077 * write adress of Rx list and send Rx GO command, ack 1078 * interrupt and enable interrupts in one command 1079 */ 1080 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1081 TL_HR_WRITE(sc, TL_HOST_CMD, 1082 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1083 HOST_CMD_ACK | HOST_CMD_IntOn); 1084 return 1; 1085 } 1086 case TL_INTR_TxEOF: 1087 case TL_INTR_TxEOC: 1088 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1089 sizeof(struct tl_Tx_list) * TL_NBUF, 1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1091 while ((Tx = sc->active_Tx) != NULL) { 1092 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1093 break; 1094 ack++; 1095 #ifdef TLDEBUG_TX 1096 printf("TL_INTR_TxEOC: list 0x%x done\n", 1097 (int)Tx->hw_listaddr); 1098 #endif 1099 Tx->hw_list->stat = 0; 1100 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1101 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1102 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1103 m_freem(Tx->m); 1104 Tx->m = NULL; 1105 sc->active_Tx = Tx->next; 1106 if (sc->active_Tx == NULL) 1107 sc->last_Tx = NULL; 1108 Tx->next = sc->Free_Tx; 1109 sc->Free_Tx = Tx; 1110 } 1111 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1112 sizeof(struct tl_Tx_list) * TL_NBUF, 1113 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1114 /* if this was an EOC, ACK immediatly */ 1115 if (ack) 1116 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1117 if (int_type == TL_INTR_TxEOC) { 1118 #ifdef TLDEBUG_TX 1119 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1120 ack); 1121 #endif 1122 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1123 HOST_CMD_ACK | HOST_CMD_IntOn); 1124 if ( sc->active_Tx != NULL) { 1125 /* needs a Tx go command */ 1126 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1127 sc->active_Tx->hw_listaddr); 1128 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1129 } 1130 sc->tl_if.if_timer = 0; 1131 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1132 tl_ifstart(&sc->tl_if); 1133 return 1; 1134 } 1135 #ifdef TLDEBUG 1136 else { 1137 printf("TL_INTR_TxEOF: ack %d\n", ack); 1138 } 1139 #endif 1140 sc->tl_if.if_timer = 0; 1141 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1142 tl_ifstart(&sc->tl_if); 1143 break; 1144 case TL_INTR_Stat: 1145 ack++; 1146 #ifdef TLDEBUG 1147 printf("TL_INTR_Stat: ack %d\n", ack); 1148 #endif 1149 tl_read_stats(sc); 1150 break; 1151 case TL_INTR_Adc: 1152 if (int_reg & TL_INTVec_MASK) { 1153 /* adapter check conditions */ 1154 printf("%s: check condition, intvect=0x%x, " 1155 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1156 int_reg & TL_INTVec_MASK, 1157 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1158 tl_reset(sc); 1159 /* shedule reinit of the board */ 1160 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1161 return(1); 1162 } else { 1163 u_int8_t netstat; 1164 /* Network status */ 1165 netstat = 1166 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1167 printf("%s: network status, NetSts=%x\n", 1168 sc->sc_dev.dv_xname, netstat); 1169 /* Ack interrupts */ 1170 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1171 netstat); 1172 ack++; 1173 } 1174 break; 1175 default: 1176 printf("%s: unhandled interrupt code %x!\n", 1177 sc->sc_dev.dv_xname, int_type); 1178 ack++; 1179 } 1180 1181 if (ack) { 1182 /* Ack the interrupt and enable interrupts */ 1183 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1184 HOST_CMD_IntOn); 1185 return 1; 1186 } 1187 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1188 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1189 return 0; 1190 } 1191 1192 static int 1193 tl_ifioctl(ifp, cmd, data) 1194 struct ifnet *ifp; 1195 ioctl_cmd_t cmd; 1196 caddr_t data; 1197 { 1198 struct tl_softc *sc = ifp->if_softc; 1199 struct ifreq *ifr = (struct ifreq *)data; 1200 int s, error; 1201 1202 s = splnet(); 1203 switch(cmd) { 1204 case SIOCSIFMEDIA: 1205 case SIOCGIFMEDIA: 1206 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1207 break; 1208 default: 1209 error = ether_ioctl(ifp, cmd, data); 1210 if (error == ENETRESET) { 1211 tl_addr_filter(sc); 1212 error = 0; 1213 } 1214 } 1215 splx(s); 1216 return error; 1217 } 1218 1219 static void 1220 tl_ifstart(ifp) 1221 struct ifnet *ifp; 1222 { 1223 tl_softc_t *sc = ifp->if_softc; 1224 struct mbuf *mb_head; 1225 struct Tx_list *Tx; 1226 int segment, size; 1227 int again, error; 1228 1229 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1230 return; 1231 txloop: 1232 /* If we don't have more space ... */ 1233 if (sc->Free_Tx == NULL) { 1234 #ifdef TLDEBUG 1235 printf("tl_ifstart: No free TX list\n"); 1236 #endif 1237 sc->tl_if.if_flags |= IFF_OACTIVE; 1238 return; 1239 } 1240 /* Grab a paquet for output */ 1241 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1242 if (mb_head == NULL) { 1243 #ifdef TLDEBUG_TX 1244 printf("tl_ifstart: nothing to send\n"); 1245 #endif 1246 return; 1247 } 1248 Tx = sc->Free_Tx; 1249 sc->Free_Tx = Tx->next; 1250 Tx->next = NULL; 1251 again = 0; 1252 /* 1253 * Go through each of the mbufs in the chain and initialize 1254 * the transmit list descriptors with the physical address 1255 * and size of the mbuf. 1256 */ 1257 tbdinit: 1258 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1259 Tx->m = mb_head; 1260 size = mb_head->m_pkthdr.len; 1261 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1262 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1263 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1264 struct mbuf *mn; 1265 /* 1266 * We ran out of segments, or we will. We have to recopy this 1267 * mbuf chain first. 1268 */ 1269 if (error == 0) 1270 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1271 if (again) { 1272 /* already copyed, can't do much more */ 1273 m_freem(mb_head); 1274 goto bad; 1275 } 1276 again = 1; 1277 #ifdef TLDEBUG_TX 1278 printf("tl_ifstart: need to copy mbuf\n"); 1279 #endif 1280 #ifdef TL_PRIV_STATS 1281 sc->oerr_mcopy++; 1282 #endif 1283 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1284 if (mn == NULL) { 1285 m_freem(mb_head); 1286 goto bad; 1287 } 1288 if (mb_head->m_pkthdr.len > MHLEN) { 1289 MCLGET(mn, M_DONTWAIT); 1290 if ((mn->m_flags & M_EXT) == 0) { 1291 m_freem(mn); 1292 m_freem(mb_head); 1293 goto bad; 1294 } 1295 } 1296 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1297 mtod(mn, caddr_t)); 1298 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1299 m_freem(mb_head); 1300 mb_head = mn; 1301 goto tbdinit; 1302 } 1303 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1304 Tx->hw_list->seg[segment].data_addr = 1305 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1306 Tx->hw_list->seg[segment].data_count = 1307 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1308 } 1309 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1310 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1311 /* We are at end of mbuf chain. check the size and 1312 * see if it needs to be extended 1313 */ 1314 if (size < ETHER_MIN_TX) { 1315 #ifdef DIAGNOSTIC 1316 if (segment >= TL_NSEG) { 1317 panic("tl_ifstart: to much segmets (%d)\n", segment); 1318 } 1319 #endif 1320 /* 1321 * add the nullbuf in the seg 1322 */ 1323 Tx->hw_list->seg[segment].data_count = 1324 htole32(ETHER_MIN_TX - size); 1325 Tx->hw_list->seg[segment].data_addr = 1326 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1327 size = ETHER_MIN_TX; 1328 segment++; 1329 } 1330 /* The list is done, finish the list init */ 1331 Tx->hw_list->seg[segment-1].data_count |= 1332 htole32(TL_LAST_SEG); 1333 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1334 #ifdef TLDEBUG_TX 1335 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1336 le32toh(Tx->hw_list->stat)); 1337 #if 0 1338 for(segment = 0; segment < TL_NSEG; segment++) { 1339 printf(" seg %d addr 0x%x len 0x%x\n", 1340 segment, 1341 le32toh(Tx->hw_list->seg[segment].data_addr), 1342 le32toh(Tx->hw_list->seg[segment].data_count)); 1343 } 1344 #endif 1345 #endif 1346 if (sc->active_Tx == NULL) { 1347 sc->active_Tx = sc->last_Tx = Tx; 1348 #ifdef TLDEBUG_TX 1349 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1350 (int)Tx->hw_listaddr); 1351 #endif 1352 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1353 sizeof(struct tl_Tx_list) * TL_NBUF, 1354 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1355 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1356 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1357 } else { 1358 #ifdef TLDEBUG_TX 1359 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1360 (int)Tx->hw_listaddr); 1361 #endif 1362 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1363 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1364 sizeof(struct tl_Tx_list) * TL_NBUF, 1365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1366 sc->last_Tx->next = Tx; 1367 sc->last_Tx = Tx; 1368 #ifdef DIAGNOSTIC 1369 if (sc->last_Tx->hw_list->fwd & 0x7) 1370 printf("%s: physical addr 0x%x of list not properly " 1371 "aligned\n", 1372 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1373 #endif 1374 } 1375 #if NBPFILTER > 0 1376 /* Pass packet to bpf if there is a listener */ 1377 if (ifp->if_bpf) 1378 bpf_mtap(ifp->if_bpf, mb_head); 1379 #endif 1380 /* 1381 * Set a 5 second timer just in case we don't hear from the card again. 1382 */ 1383 ifp->if_timer = 5; 1384 goto txloop; 1385 bad: 1386 #ifdef TLDEBUG 1387 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1388 #endif 1389 Tx->next = sc->Free_Tx; 1390 sc->Free_Tx = Tx; 1391 return; 1392 } 1393 1394 static void 1395 tl_ifwatchdog(ifp) 1396 struct ifnet *ifp; 1397 { 1398 tl_softc_t *sc = ifp->if_softc; 1399 1400 if ((ifp->if_flags & IFF_RUNNING) == 0) 1401 return; 1402 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1403 ifp->if_oerrors++; 1404 tl_init(ifp); 1405 } 1406 1407 static int 1408 tl_mediachange(ifp) 1409 struct ifnet *ifp; 1410 { 1411 1412 if (ifp->if_flags & IFF_UP) 1413 tl_init(ifp); 1414 return (0); 1415 } 1416 1417 static void 1418 tl_mediastatus(ifp, ifmr) 1419 struct ifnet *ifp; 1420 struct ifmediareq *ifmr; 1421 { 1422 tl_softc_t *sc = ifp->if_softc; 1423 1424 mii_pollstat(&sc->tl_mii); 1425 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1426 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1427 } 1428 1429 static int tl_add_RxBuff(sc, Rx, oldm) 1430 tl_softc_t *sc; 1431 struct Rx_list *Rx; 1432 struct mbuf *oldm; 1433 { 1434 struct mbuf *m; 1435 int error; 1436 1437 MGETHDR(m, M_DONTWAIT, MT_DATA); 1438 if (m != NULL) { 1439 MCLGET(m, M_DONTWAIT); 1440 if ((m->m_flags & M_EXT) == 0) { 1441 m_freem(m); 1442 if (oldm == NULL) 1443 return 0; 1444 m = oldm; 1445 m->m_data = m->m_ext.ext_buf; 1446 } 1447 } else { 1448 if (oldm == NULL) 1449 return 0; 1450 m = oldm; 1451 m->m_data = m->m_ext.ext_buf; 1452 } 1453 1454 /* (re)init the Rx_list struct */ 1455 1456 Rx->m = m; 1457 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1458 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1459 printf("%s: bus_dmamap_load() failed (error %d) for " 1460 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1461 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1462 m_freem(m); 1463 Rx->m = NULL; 1464 return 0; 1465 } 1466 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1467 MCLBYTES, BUS_DMASYNC_PREREAD); 1468 /* 1469 * Move the data pointer up so that the incoming data packet 1470 * will be 32-bit aligned. 1471 */ 1472 m->m_data += 2; 1473 1474 Rx->hw_list->stat = 1475 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1476 Rx->hw_list->seg.data_count = 1477 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1478 Rx->hw_list->seg.data_addr = 1479 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1480 return (m != oldm); 1481 } 1482 1483 static void tl_ticks(v) 1484 void *v; 1485 { 1486 tl_softc_t *sc = v; 1487 1488 tl_read_stats(sc); 1489 1490 /* Tick the MII. */ 1491 mii_tick(&sc->tl_mii); 1492 1493 /* read statistics every seconds */ 1494 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1495 } 1496 1497 static void 1498 tl_read_stats(sc) 1499 tl_softc_t *sc; 1500 { 1501 u_int32_t reg; 1502 int ierr_overr; 1503 int ierr_code; 1504 int ierr_crc; 1505 int oerr_underr; 1506 int oerr_deffered; 1507 int oerr_coll; 1508 int oerr_multicoll; 1509 int oerr_exesscoll; 1510 int oerr_latecoll; 1511 int oerr_carrloss; 1512 struct ifnet *ifp = &sc->tl_if; 1513 1514 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1515 ifp->if_opackets += reg & 0x00ffffff; 1516 oerr_underr = reg >> 24; 1517 1518 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1519 ifp->if_ipackets += reg & 0x00ffffff; 1520 ierr_overr = reg >> 24; 1521 1522 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1523 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1524 ierr_code = (reg & TL_FERR_CODE) >> 24; 1525 oerr_deffered = (reg & TL_FERR_DEF); 1526 1527 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1528 oerr_multicoll = (reg & TL_COL_MULTI); 1529 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1530 1531 reg = tl_intreg_read(sc, TL_INT_LERR); 1532 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1533 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1534 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1535 1536 1537 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1538 oerr_carrloss; 1539 ifp->if_collisions += oerr_coll + oerr_multicoll; 1540 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1541 1542 if (ierr_overr) 1543 printf("%s: receiver ring buffer overrun\n", 1544 sc->sc_dev.dv_xname); 1545 if (oerr_underr) 1546 printf("%s: transmit buffer underrun\n", 1547 sc->sc_dev.dv_xname); 1548 #ifdef TL_PRIV_STATS 1549 sc->ierr_overr += ierr_overr; 1550 sc->ierr_code += ierr_code; 1551 sc->ierr_crc += ierr_crc; 1552 sc->oerr_underr += oerr_underr; 1553 sc->oerr_deffered += oerr_deffered; 1554 sc->oerr_coll += oerr_coll; 1555 sc->oerr_multicoll += oerr_multicoll; 1556 sc->oerr_exesscoll += oerr_exesscoll; 1557 sc->oerr_latecoll += oerr_latecoll; 1558 sc->oerr_carrloss += oerr_carrloss; 1559 #endif 1560 } 1561 1562 static void tl_addr_filter(sc) 1563 tl_softc_t *sc; 1564 { 1565 struct ether_multistep step; 1566 struct ether_multi *enm; 1567 u_int32_t hash[2] = {0, 0}; 1568 int i; 1569 1570 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1571 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1572 while (enm != NULL) { 1573 #ifdef TLDEBUG 1574 printf("tl_addr_filter: addrs %s %s\n", 1575 ether_sprintf(enm->enm_addrlo), 1576 ether_sprintf(enm->enm_addrhi)); 1577 #endif 1578 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1579 i = tl_multicast_hash(enm->enm_addrlo); 1580 hash[i/32] |= 1 << (i%32); 1581 } else { 1582 hash[0] = hash[1] = 0xffffffff; 1583 sc->tl_if.if_flags |= IFF_ALLMULTI; 1584 break; 1585 } 1586 ETHER_NEXT_MULTI(step, enm); 1587 } 1588 #ifdef TLDEBUG 1589 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1590 #endif 1591 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1592 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1593 } 1594 1595 static int tl_multicast_hash(a) 1596 u_int8_t *a; 1597 { 1598 int hash; 1599 1600 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1601 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1602 1603 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1604 DA(a,36), DA(a,42)); 1605 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1606 DA(a,37), DA(a,43)) << 1; 1607 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1608 DA(a,38), DA(a,44)) << 2; 1609 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1610 DA(a,39), DA(a,45)) << 3; 1611 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1612 DA(a,40), DA(a,46)) << 4; 1613 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1614 DA(a,41), DA(a,47)) << 5; 1615 1616 return hash; 1617 } 1618 1619 #if defined(TLDEBUG_RX) 1620 void 1621 ether_printheader(eh) 1622 struct ether_header *eh; 1623 { 1624 u_char *c = (char*)eh; 1625 int i; 1626 for (i=0; i<sizeof(struct ether_header); i++) 1627 printf("%x ", (u_int)c[i]); 1628 printf("\n"); 1629 } 1630 #endif 1631
Indexes created Mon Oct 27 20:09:55 GMT 2025