if_tl.c revision 1.52.4.2
1 /* $NetBSD: if_tl.c,v 1.52.4.2 2004/06/22 15:16:39 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.52.4.2 2004/06/22 15:16:39 tron Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 /* number of transmit/receive buffers */ 116 #ifndef TL_NBUF 117 #define TL_NBUF 10 118 #endif 119 120 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 121 static void tl_pci_attach __P((struct device *, struct device *, void *)); 122 static int tl_intr __P((void *)); 123 124 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 125 static int tl_mediachange __P((struct ifnet *)); 126 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 127 static void tl_ifwatchdog __P((struct ifnet *)); 128 static void tl_shutdown __P((void*)); 129 130 static void tl_ifstart __P((struct ifnet *)); 131 static void tl_reset __P((tl_softc_t*)); 132 static int tl_init __P((struct ifnet *)); 133 static void tl_stop __P((struct ifnet *, int)); 134 static void tl_restart __P((void *)); 135 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 136 static void tl_read_stats __P((tl_softc_t*)); 137 static void tl_ticks __P((void*)); 138 static int tl_multicast_hash __P((u_int8_t*)); 139 static void tl_addr_filter __P((tl_softc_t*)); 140 141 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 143 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 145 146 void tl_mii_sync __P((struct tl_softc *)); 147 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader __P((struct ether_header*)); 152 #endif 153 154 int tl_mii_read __P((struct device *, int, int)); 155 void tl_mii_write __P((struct device *, int, int, int)); 156 157 void tl_statchg __P((struct device *)); 158 159 void tl_i2c_set __P((void*, u_int8_t)); 160 void tl_i2c_clr __P((void*, u_int8_t)); 161 int tl_i2c_read __P((void*, u_int8_t)); 162 163 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 165 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_clr(sc, bits) 167 tl_softc_t* sc; 168 u_int8_t bits; 169 { 170 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 171 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 172 } 173 static __inline void netsio_set(sc, bits) 174 tl_softc_t* sc; 175 u_int8_t bits; 176 { 177 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 178 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 179 } 180 static __inline u_int8_t netsio_read(sc, bits) 181 tl_softc_t* sc; 182 u_int8_t bits; 183 { 184 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 185 } 186 187 struct cfattach tl_ca = { 188 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 189 }; 190 191 const struct tl_product_desc tl_compaq_products[] = { 192 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 193 "Compaq Netelligent 10/100 TX" }, 194 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 195 "Integrated Compaq Netelligent 10/100 TX" }, 196 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 197 "Compaq Netelligent 10 T" }, 198 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 199 "Compaq Integrated NetFlex 3/P" }, 200 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 201 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 202 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 203 "Compaq Dual Port Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 205 "Compaq Deskpro 4000 5233MMX" }, 206 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 207 "Compaq NetFlex 3/P w/ BNC" }, 208 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 209 "Compaq NetFlex 3/P" }, 210 { 0, 0, NULL }, 211 }; 212 213 const struct tl_product_desc tl_ti_products[] = { 214 /* 215 * Built-in Ethernet on the TI TravelMate 5000 216 * docking station; better product description? 217 */ 218 { PCI_PRODUCT_TI_TLAN, 0, 219 "Texas Instruments ThunderLAN" }, 220 { 0, 0, NULL }, 221 }; 222 223 struct tl_vendor_desc { 224 u_int32_t tv_vendor; 225 const struct tl_product_desc *tv_products; 226 }; 227 228 const struct tl_vendor_desc tl_vendors[] = { 229 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 230 { PCI_VENDOR_TI, tl_ti_products }, 231 { 0, NULL }, 232 }; 233 234 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 235 236 const struct tl_product_desc * 237 tl_lookup_product(id) 238 u_int32_t id; 239 { 240 const struct tl_product_desc *tp; 241 const struct tl_vendor_desc *tv; 242 243 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 244 if (PCI_VENDOR(id) == tv->tv_vendor) 245 break; 246 247 if ((tp = tv->tv_products) == NULL) 248 return (NULL); 249 250 for (; tp->tp_desc != NULL; tp++) 251 if (PCI_PRODUCT(id) == tp->tp_product) 252 break; 253 254 if (tp->tp_desc == NULL) 255 return (NULL); 256 257 return (tp); 258 } 259 260 static int 261 tl_pci_match(parent, match, aux) 262 struct device *parent; 263 struct cfdata *match; 264 void *aux; 265 { 266 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 267 268 if (tl_lookup_product(pa->pa_id) != NULL) 269 return (1); 270 271 return (0); 272 } 273 274 static void 275 tl_pci_attach(parent, self, aux) 276 struct device * parent; 277 struct device * self; 278 void * aux; 279 { 280 tl_softc_t *sc = (tl_softc_t *)self; 281 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 282 const struct tl_product_desc *tp; 283 struct ifnet * const ifp = &sc->tl_if; 284 bus_space_tag_t iot, memt; 285 bus_space_handle_t ioh, memh; 286 pci_intr_handle_t intrhandle; 287 const char *intrstr; 288 int i, tmp, ioh_valid, memh_valid; 289 int reg_io, reg_mem; 290 pcireg_t reg10, reg14; 291 pcireg_t csr; 292 293 printf("\n"); 294 295 callout_init(&sc->tl_tick_ch); 296 callout_init(&sc->tl_restart_ch); 297 298 tp = tl_lookup_product(pa->pa_id); 299 if (tp == NULL) 300 panic("tl_pci_attach: impossible"); 301 sc->tl_product = tp; 302 303 /* 304 * Map the card space. First we have to find the I/O and MEM 305 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 306 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 307 * The ThunderLAN manual is not consistent about this either (there 308 * are both cases in code examples). 309 */ 310 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 311 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 312 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 313 reg_io = 0x10; 314 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 315 reg_io = 0x14; 316 else 317 reg_io = 0; 318 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 319 reg_mem = 0x10; 320 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 321 reg_mem = 0x14; 322 else 323 reg_mem = 0; 324 325 if (reg_io != 0) 326 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 327 0, &iot, &ioh, NULL, NULL) == 0); 328 else 329 ioh_valid = 0; 330 if (reg_mem != 0) 331 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 332 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 333 0, &memt, &memh, NULL, NULL) == 0); 334 else 335 memh_valid = 0; 336 337 if (ioh_valid) { 338 sc->tl_bustag = iot; 339 sc->tl_bushandle = ioh; 340 } else if (memh_valid) { 341 sc->tl_bustag = memt; 342 sc->tl_bushandle = memh; 343 } else { 344 printf("%s: unable to map device registers\n", 345 sc->sc_dev.dv_xname); 346 return; 347 } 348 sc->tl_dmatag = pa->pa_dmat; 349 350 /* Enable the device. */ 351 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 352 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 353 csr | PCI_COMMAND_MASTER_ENABLE); 354 355 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 356 357 tl_reset(sc); 358 359 /* fill in the i2c struct */ 360 sc->i2cbus.adapter_softc = sc; 361 sc->i2cbus.set_bit = tl_i2c_set; 362 sc->i2cbus.clr_bit = tl_i2c_clr; 363 sc->i2cbus.read_bit = tl_i2c_read; 364 365 #ifdef TLDEBUG 366 printf("default values of INTreg: 0x%x\n", 367 tl_intreg_read(sc, TL_INT_Defaults)); 368 #endif 369 370 /* read mac addr */ 371 for (i=0; i<ETHER_ADDR_LEN; i++) { 372 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 373 if (tmp < 0) { 374 printf("%s: error reading Ethernet adress\n", 375 sc->sc_dev.dv_xname); 376 return; 377 } else { 378 sc->tl_enaddr[i] = tmp; 379 } 380 } 381 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 382 ether_sprintf(sc->tl_enaddr)); 383 384 /* Map and establish interrupts */ 385 if (pci_intr_map(pa, &intrhandle)) { 386 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 387 return; 388 } 389 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 390 sc->tl_if.if_softc = sc; 391 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 392 tl_intr, sc); 393 if (sc->tl_ih == NULL) { 394 printf("%s: couldn't establish interrupt", 395 sc->sc_dev.dv_xname); 396 if (intrstr != NULL) 397 printf(" at %s", intrstr); 398 printf("\n"); 399 return; 400 } 401 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 402 403 /* init these pointers, so that tl_shutdown won't try to read them */ 404 sc->Rx_list = NULL; 405 sc->Tx_list = NULL; 406 407 /* allocate DMA-safe memory for control structs */ 408 if (bus_dmamem_alloc(sc->tl_dmatag, 409 PAGE_SIZE, 0, PAGE_SIZE, 410 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 411 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 412 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 413 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 414 printf("%s: can't allocate DMA memory for lists\n", 415 sc->sc_dev.dv_xname); 416 return; 417 } 418 /* 419 * Add shutdown hook so that DMA is disabled prior to reboot. Not 420 * doing 421 * reboot before the driver initializes. 422 */ 423 (void) shutdownhook_establish(tl_shutdown, ifp); 424 425 /* 426 * Initialize our media structures and probe the MII. 427 * 428 * Note that we don't care about the media instance. We 429 * are expecting to have multiple PHYs on the 10/100 cards, 430 * and on those cards we exclude the internal PHY from providing 431 * 10baseT. By ignoring the instance, it allows us to not have 432 * to specify it on the command line when switching media. 433 */ 434 sc->tl_mii.mii_ifp = ifp; 435 sc->tl_mii.mii_readreg = tl_mii_read; 436 sc->tl_mii.mii_writereg = tl_mii_write; 437 sc->tl_mii.mii_statchg = tl_statchg; 438 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 439 tl_mediastatus); 440 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 441 MII_OFFSET_ANY, 0); 442 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 443 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 444 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 445 } else 446 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 447 448 /* 449 * We can support 802.1Q VLAN-sized frames. 450 */ 451 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 452 453 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 454 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 455 ifp->if_ioctl = tl_ifioctl; 456 ifp->if_start = tl_ifstart; 457 ifp->if_watchdog = tl_ifwatchdog; 458 ifp->if_init = tl_init; 459 ifp->if_stop = tl_stop; 460 ifp->if_timer = 0; 461 IFQ_SET_READY(&ifp->if_snd); 462 if_attach(ifp); 463 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 464 } 465 466 static void 467 tl_reset(sc) 468 tl_softc_t *sc; 469 { 470 int i; 471 472 /* read stats */ 473 if (sc->tl_if.if_flags & IFF_RUNNING) { 474 callout_stop(&sc->tl_tick_ch); 475 tl_read_stats(sc); 476 } 477 /* Reset adapter */ 478 TL_HR_WRITE(sc, TL_HOST_CMD, 479 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 480 DELAY(100000); 481 /* Disable interrupts */ 482 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 483 /* setup aregs & hash */ 484 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 485 tl_intreg_write(sc, i, 0); 486 #ifdef TLDEBUG_ADDR 487 printf("Areg & hash registers: \n"); 488 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 489 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 490 #endif 491 /* Setup NetConfig */ 492 tl_intreg_write(sc, TL_INT_NetConfig, 493 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 494 /* Bsize: accept default */ 495 /* TX commit in Acommit: accept default */ 496 /* Load Ld_tmr and Ld_thr */ 497 /* Ld_tmr = 3 */ 498 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 499 /* Ld_thr = 0 */ 500 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 501 /* Unreset MII */ 502 netsio_set(sc, TL_NETSIO_NMRST); 503 DELAY(100000); 504 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 505 } 506 507 static void tl_shutdown(v) 508 void *v; 509 { 510 tl_stop(v, 1); 511 } 512 513 static void tl_stop(ifp, disable) 514 struct ifnet *ifp; 515 int disable; 516 { 517 tl_softc_t *sc = ifp->if_softc; 518 struct Tx_list *Tx; 519 int i; 520 521 if ((ifp->if_flags & IFF_RUNNING) == 0) 522 return; 523 /* disable interrupts */ 524 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 525 /* stop TX and RX channels */ 526 TL_HR_WRITE(sc, TL_HOST_CMD, 527 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 528 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 529 DELAY(100000); 530 531 /* stop statistics reading loop, read stats */ 532 callout_stop(&sc->tl_tick_ch); 533 tl_read_stats(sc); 534 535 /* Down the MII. */ 536 mii_down(&sc->tl_mii); 537 538 /* deallocate memory allocations */ 539 if (sc->Rx_list) { 540 for (i=0; i< TL_NBUF; i++) { 541 if (sc->Rx_list[i].m) { 542 bus_dmamap_unload(sc->tl_dmatag, 543 sc->Rx_list[i].m_dmamap); 544 m_freem(sc->Rx_list[i].m); 545 } 546 bus_dmamap_destroy(sc->tl_dmatag, 547 sc->Rx_list[i].m_dmamap); 548 sc->Rx_list[i].m = NULL; 549 } 550 free(sc->Rx_list, M_DEVBUF); 551 sc->Rx_list = NULL; 552 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 553 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 554 sc->hw_Rx_list = NULL; 555 while ((Tx = sc->active_Tx) != NULL) { 556 Tx->hw_list->stat = 0; 557 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 558 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 559 m_freem(Tx->m); 560 sc->active_Tx = Tx->next; 561 Tx->next = sc->Free_Tx; 562 sc->Free_Tx = Tx; 563 } 564 sc->last_Tx = NULL; 565 free(sc->Tx_list, M_DEVBUF); 566 sc->Tx_list = NULL; 567 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 568 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 569 sc->hw_Tx_list = NULL; 570 } 571 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 572 ifp->if_timer = 0; 573 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 574 } 575 576 static void tl_restart(v) 577 void *v; 578 { 579 tl_init(v); 580 } 581 582 static int tl_init(ifp) 583 struct ifnet *ifp; 584 { 585 tl_softc_t *sc = ifp->if_softc; 586 int i, s, error; 587 char *errstring; 588 char *nullbuf; 589 590 s = splnet(); 591 /* cancel any pending IO */ 592 tl_stop(ifp, 1); 593 tl_reset(sc); 594 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 595 splx(s); 596 return 0; 597 } 598 /* Set various register to reasonable value */ 599 /* setup NetCmd in promisc mode if needed */ 600 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 601 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 602 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 603 /* Max receive size : MCLBYTES */ 604 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 605 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 606 (MCLBYTES >> 8) & 0xff); 607 608 /* init MAC addr */ 609 for (i = 0; i < ETHER_ADDR_LEN; i++) 610 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 611 /* add multicast filters */ 612 tl_addr_filter(sc); 613 #ifdef TLDEBUG_ADDR 614 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 615 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 616 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 617 #endif 618 619 /* Pre-allocate receivers mbuf, make the lists */ 620 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 621 M_NOWAIT|M_ZERO); 622 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 623 M_NOWAIT|M_ZERO); 624 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 625 errstring = "out of memory for lists"; 626 error = ENOMEM; 627 goto bad; 628 } 629 error = bus_dmamap_create(sc->tl_dmatag, 630 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 631 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 632 &sc->Rx_dmamap); 633 if (error == 0) 634 error = bus_dmamap_create(sc->tl_dmatag, 635 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 636 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 637 &sc->Tx_dmamap); 638 if (error == 0) 639 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 640 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 641 &sc->null_dmamap); 642 if (error) { 643 errstring = "can't allocate DMA maps for lists"; 644 goto bad; 645 } 646 memset(sc->ctrl, 0, PAGE_SIZE); 647 sc->hw_Rx_list = (void *)sc->ctrl; 648 sc->hw_Tx_list = 649 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 650 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 651 sizeof(struct tl_Tx_list) * TL_NBUF; 652 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 653 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 654 BUS_DMA_WAITOK); 655 if (error == 0) 656 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 657 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 658 BUS_DMA_WAITOK); 659 if (error == 0) 660 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 661 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 662 if (error) { 663 errstring = "can't DMA map DMA memory for lists"; 664 goto bad; 665 } 666 for (i=0; i< TL_NBUF; i++) { 667 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 668 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 669 &sc->Rx_list[i].m_dmamap); 670 if (error == 0) { 671 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 672 TL_NSEG, MCLBYTES, 0, 673 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 674 &sc->Tx_list[i].m_dmamap); 675 } 676 if (error) { 677 errstring = "can't allocate DMA maps for mbufs"; 678 goto bad; 679 } 680 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 681 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 682 + sizeof(struct tl_Rx_list) * i; 683 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 684 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 685 + sizeof(struct tl_Tx_list) * i; 686 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 687 errstring = "out of mbuf for receive list"; 688 error = ENOMEM; 689 goto bad; 690 } 691 if (i > 0) { /* chain the list */ 692 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 693 sc->hw_Rx_list[i-1].fwd = 694 htole32(sc->Rx_list[i].hw_listaddr); 695 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 696 } 697 } 698 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 699 sc->Rx_list[TL_NBUF-1].next = NULL; 700 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 701 sc->Tx_list[TL_NBUF-1].next = NULL; 702 703 sc->active_Rx = &sc->Rx_list[0]; 704 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 705 sc->active_Tx = sc->last_Tx = NULL; 706 sc->Free_Tx = &sc->Tx_list[0]; 707 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 708 sizeof(struct tl_Rx_list) * TL_NBUF, 709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 710 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 711 sizeof(struct tl_Tx_list) * TL_NBUF, 712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 713 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 714 BUS_DMASYNC_PREWRITE); 715 716 /* set media */ 717 mii_mediachg(&sc->tl_mii); 718 719 /* start ticks calls */ 720 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 721 /* write adress of Rx list and enable interrupts */ 722 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 723 TL_HR_WRITE(sc, TL_HOST_CMD, 724 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 725 sc->tl_if.if_flags |= IFF_RUNNING; 726 sc->tl_if.if_flags &= ~IFF_OACTIVE; 727 return 0; 728 bad: 729 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 730 splx(s); 731 return error; 732 } 733 734 735 static u_int32_t 736 tl_intreg_read(sc, reg) 737 tl_softc_t *sc; 738 u_int32_t reg; 739 { 740 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 741 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 742 } 743 744 static u_int8_t 745 tl_intreg_read_byte(sc, reg) 746 tl_softc_t *sc; 747 u_int32_t reg; 748 { 749 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 750 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 751 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 752 } 753 754 static void 755 tl_intreg_write(sc, reg, val) 756 tl_softc_t *sc; 757 u_int32_t reg; 758 u_int32_t val; 759 { 760 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 761 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 762 } 763 764 static void 765 tl_intreg_write_byte(sc, reg, val) 766 tl_softc_t *sc; 767 u_int32_t reg; 768 u_int8_t val; 769 { 770 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 771 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 772 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 773 } 774 775 void 776 tl_mii_sync(sc) 777 struct tl_softc *sc; 778 { 779 int i; 780 781 netsio_clr(sc, TL_NETSIO_MTXEN); 782 for (i = 0; i < 32; i++) { 783 netsio_clr(sc, TL_NETSIO_MCLK); 784 netsio_set(sc, TL_NETSIO_MCLK); 785 } 786 } 787 788 void 789 tl_mii_sendbits(sc, data, nbits) 790 struct tl_softc *sc; 791 u_int32_t data; 792 int nbits; 793 { 794 int i; 795 796 netsio_set(sc, TL_NETSIO_MTXEN); 797 for (i = 1 << (nbits - 1); i; i = i >> 1) { 798 netsio_clr(sc, TL_NETSIO_MCLK); 799 netsio_read(sc, TL_NETSIO_MCLK); 800 if (data & i) 801 netsio_set(sc, TL_NETSIO_MDATA); 802 else 803 netsio_clr(sc, TL_NETSIO_MDATA); 804 netsio_set(sc, TL_NETSIO_MCLK); 805 netsio_read(sc, TL_NETSIO_MCLK); 806 } 807 } 808 809 int 810 tl_mii_read(self, phy, reg) 811 struct device *self; 812 int phy, reg; 813 { 814 struct tl_softc *sc = (struct tl_softc *)self; 815 int val = 0, i, err; 816 817 /* 818 * Read the PHY register by manually driving the MII control lines. 819 */ 820 821 tl_mii_sync(sc); 822 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 823 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 824 tl_mii_sendbits(sc, phy, 5); 825 tl_mii_sendbits(sc, reg, 5); 826 827 netsio_clr(sc, TL_NETSIO_MTXEN); 828 netsio_clr(sc, TL_NETSIO_MCLK); 829 netsio_set(sc, TL_NETSIO_MCLK); 830 netsio_clr(sc, TL_NETSIO_MCLK); 831 832 err = netsio_read(sc, TL_NETSIO_MDATA); 833 netsio_set(sc, TL_NETSIO_MCLK); 834 835 /* Even if an error occurs, must still clock out the cycle. */ 836 for (i = 0; i < 16; i++) { 837 val <<= 1; 838 netsio_clr(sc, TL_NETSIO_MCLK); 839 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 840 val |= 1; 841 netsio_set(sc, TL_NETSIO_MCLK); 842 } 843 netsio_clr(sc, TL_NETSIO_MCLK); 844 netsio_set(sc, TL_NETSIO_MCLK); 845 846 return (err ? 0 : val); 847 } 848 849 void 850 tl_mii_write(self, phy, reg, val) 851 struct device *self; 852 int phy, reg, val; 853 { 854 struct tl_softc *sc = (struct tl_softc *)self; 855 856 /* 857 * Write the PHY register by manually driving the MII control lines. 858 */ 859 860 tl_mii_sync(sc); 861 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 862 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 863 tl_mii_sendbits(sc, phy, 5); 864 tl_mii_sendbits(sc, reg, 5); 865 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 866 tl_mii_sendbits(sc, val, 16); 867 868 netsio_clr(sc, TL_NETSIO_MCLK); 869 netsio_set(sc, TL_NETSIO_MCLK); 870 } 871 872 void 873 tl_statchg(self) 874 struct device *self; 875 { 876 tl_softc_t *sc = (struct tl_softc *)self; 877 u_int32_t reg; 878 879 #ifdef TLDEBUG 880 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 881 #endif 882 883 /* 884 * We must keep the ThunderLAN and the PHY in sync as 885 * to the status of full-duplex! 886 */ 887 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 888 if (sc->tl_mii.mii_media_active & IFM_FDX) 889 reg |= TL_NETCOMMAND_DUPLEX; 890 else 891 reg &= ~TL_NETCOMMAND_DUPLEX; 892 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 893 } 894 895 void tl_i2c_set(v, bit) 896 void *v; 897 u_int8_t bit; 898 { 899 tl_softc_t *sc = v; 900 901 switch (bit) { 902 case I2C_DATA: 903 netsio_set(sc, TL_NETSIO_EDATA); 904 break; 905 case I2C_CLOCK: 906 netsio_set(sc, TL_NETSIO_ECLOCK); 907 break; 908 case I2C_TXEN: 909 netsio_set(sc, TL_NETSIO_ETXEN); 910 break; 911 default: 912 printf("tl_i2c_set: unknown bit %d\n", bit); 913 } 914 return; 915 } 916 917 void tl_i2c_clr(v, bit) 918 void *v; 919 u_int8_t bit; 920 { 921 tl_softc_t *sc = v; 922 923 switch (bit) { 924 case I2C_DATA: 925 netsio_clr(sc, TL_NETSIO_EDATA); 926 break; 927 case I2C_CLOCK: 928 netsio_clr(sc, TL_NETSIO_ECLOCK); 929 break; 930 case I2C_TXEN: 931 netsio_clr(sc, TL_NETSIO_ETXEN); 932 break; 933 default: 934 printf("tl_i2c_clr: unknown bit %d\n", bit); 935 } 936 return; 937 } 938 939 int tl_i2c_read(v, bit) 940 void *v; 941 u_int8_t bit; 942 { 943 tl_softc_t *sc = v; 944 945 switch (bit) { 946 case I2C_DATA: 947 return netsio_read(sc, TL_NETSIO_EDATA); 948 break; 949 case I2C_CLOCK: 950 return netsio_read(sc, TL_NETSIO_ECLOCK); 951 break; 952 case I2C_TXEN: 953 return netsio_read(sc, TL_NETSIO_ETXEN); 954 break; 955 default: 956 printf("tl_i2c_read: unknown bit %d\n", bit); 957 return -1; 958 } 959 } 960 961 static int 962 tl_intr(v) 963 void *v; 964 { 965 tl_softc_t *sc = v; 966 struct ifnet *ifp = &sc->tl_if; 967 struct Rx_list *Rx; 968 struct Tx_list *Tx; 969 struct mbuf *m; 970 u_int32_t int_type, int_reg; 971 int ack = 0; 972 int size; 973 974 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 975 int_type = int_reg & TL_INTR_MASK; 976 if (int_type == 0) 977 return 0; 978 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 979 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 980 int_type, int_reg); 981 #endif 982 /* disable interrupts */ 983 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 984 switch(int_type & TL_INTR_MASK) { 985 case TL_INTR_RxEOF: 986 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 987 sizeof(struct tl_Rx_list) * TL_NBUF, 988 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 989 while(le32toh(sc->active_Rx->hw_list->stat) & 990 TL_RX_CSTAT_CPLT) { 991 /* dequeue and requeue at end of list */ 992 ack++; 993 Rx = sc->active_Rx; 994 sc->active_Rx = Rx->next; 995 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 996 MCLBYTES, BUS_DMASYNC_POSTREAD); 997 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 998 m = Rx->m; 999 size = le32toh(Rx->hw_list->stat) >> 16; 1000 #ifdef TLDEBUG_RX 1001 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1002 Rx, size); 1003 #endif 1004 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1005 /* 1006 * No new mbuf, reuse the same. This means 1007 * that this packet 1008 * is lost 1009 */ 1010 m = NULL; 1011 #ifdef TL_PRIV_STATS 1012 sc->ierr_nomem++; 1013 #endif 1014 #ifdef TLDEBUG 1015 printf("%s: out of mbuf, lost input packet\n", 1016 sc->sc_dev.dv_xname); 1017 #endif 1018 } 1019 Rx->next = NULL; 1020 Rx->hw_list->fwd = 0; 1021 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1022 sc->last_Rx->next = Rx; 1023 sc->last_Rx = Rx; 1024 1025 /* deliver packet */ 1026 if (m) { 1027 if (size < sizeof(struct ether_header)) { 1028 m_freem(m); 1029 continue; 1030 } 1031 m->m_pkthdr.rcvif = ifp; 1032 m->m_pkthdr.len = m->m_len = size; 1033 #ifdef TLDEBUG_RX 1034 { struct ether_header *eh = 1035 mtod(m, struct ether_header *); 1036 printf("tl_intr: Rx packet:\n"); 1037 ether_printheader(eh); } 1038 #endif 1039 #if NBPFILTER > 0 1040 if (ifp->if_bpf) 1041 bpf_mtap(ifp->if_bpf, m); 1042 #endif /* NBPFILTER > 0 */ 1043 (*ifp->if_input)(ifp, m); 1044 } 1045 } 1046 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1047 sizeof(struct tl_Rx_list) * TL_NBUF, 1048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1049 #ifdef TLDEBUG_RX 1050 printf("TL_INTR_RxEOF: ack %d\n", ack); 1051 #else 1052 if (ack == 0) { 1053 printf("%s: EOF intr without anything to read !\n", 1054 sc->sc_dev.dv_xname); 1055 tl_reset(sc); 1056 /* shedule reinit of the board */ 1057 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1058 return(1); 1059 } 1060 #endif 1061 break; 1062 case TL_INTR_RxEOC: 1063 ack++; 1064 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1065 sizeof(struct tl_Rx_list) * TL_NBUF, 1066 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1067 #ifdef TLDEBUG_RX 1068 printf("TL_INTR_RxEOC: ack %d\n", ack); 1069 #endif 1070 #ifdef DIAGNOSTIC 1071 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1072 printf("%s: Rx EOC interrupt and active Tx list not " 1073 "cleared\n", sc->sc_dev.dv_xname); 1074 return 0; 1075 } else 1076 #endif 1077 { 1078 /* 1079 * write adress of Rx list and send Rx GO command, ack 1080 * interrupt and enable interrupts in one command 1081 */ 1082 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1083 TL_HR_WRITE(sc, TL_HOST_CMD, 1084 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1085 HOST_CMD_ACK | HOST_CMD_IntOn); 1086 return 1; 1087 } 1088 case TL_INTR_TxEOF: 1089 case TL_INTR_TxEOC: 1090 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1091 sizeof(struct tl_Tx_list) * TL_NBUF, 1092 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1093 while ((Tx = sc->active_Tx) != NULL) { 1094 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1095 break; 1096 ack++; 1097 #ifdef TLDEBUG_TX 1098 printf("TL_INTR_TxEOC: list 0x%x done\n", 1099 (int)Tx->hw_listaddr); 1100 #endif 1101 Tx->hw_list->stat = 0; 1102 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1103 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1104 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1105 m_freem(Tx->m); 1106 Tx->m = NULL; 1107 sc->active_Tx = Tx->next; 1108 if (sc->active_Tx == NULL) 1109 sc->last_Tx = NULL; 1110 Tx->next = sc->Free_Tx; 1111 sc->Free_Tx = Tx; 1112 } 1113 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1114 sizeof(struct tl_Tx_list) * TL_NBUF, 1115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1116 /* if this was an EOC, ACK immediatly */ 1117 if (ack) 1118 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1119 if (int_type == TL_INTR_TxEOC) { 1120 #ifdef TLDEBUG_TX 1121 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1122 ack); 1123 #endif 1124 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1125 HOST_CMD_ACK | HOST_CMD_IntOn); 1126 if ( sc->active_Tx != NULL) { 1127 /* needs a Tx go command */ 1128 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1129 sc->active_Tx->hw_listaddr); 1130 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1131 } 1132 sc->tl_if.if_timer = 0; 1133 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1134 tl_ifstart(&sc->tl_if); 1135 return 1; 1136 } 1137 #ifdef TLDEBUG 1138 else { 1139 printf("TL_INTR_TxEOF: ack %d\n", ack); 1140 } 1141 #endif 1142 sc->tl_if.if_timer = 0; 1143 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1144 tl_ifstart(&sc->tl_if); 1145 break; 1146 case TL_INTR_Stat: 1147 ack++; 1148 #ifdef TLDEBUG 1149 printf("TL_INTR_Stat: ack %d\n", ack); 1150 #endif 1151 tl_read_stats(sc); 1152 break; 1153 case TL_INTR_Adc: 1154 if (int_reg & TL_INTVec_MASK) { 1155 /* adapter check conditions */ 1156 printf("%s: check condition, intvect=0x%x, " 1157 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1158 int_reg & TL_INTVec_MASK, 1159 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1160 tl_reset(sc); 1161 /* shedule reinit of the board */ 1162 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1163 return(1); 1164 } else { 1165 u_int8_t netstat; 1166 /* Network status */ 1167 netstat = 1168 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1169 printf("%s: network status, NetSts=%x\n", 1170 sc->sc_dev.dv_xname, netstat); 1171 /* Ack interrupts */ 1172 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1173 netstat); 1174 ack++; 1175 } 1176 break; 1177 default: 1178 printf("%s: unhandled interrupt code %x!\n", 1179 sc->sc_dev.dv_xname, int_type); 1180 ack++; 1181 } 1182 1183 if (ack) { 1184 /* Ack the interrupt and enable interrupts */ 1185 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1186 HOST_CMD_IntOn); 1187 return 1; 1188 } 1189 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1190 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1191 return 0; 1192 } 1193 1194 static int 1195 tl_ifioctl(ifp, cmd, data) 1196 struct ifnet *ifp; 1197 ioctl_cmd_t cmd; 1198 caddr_t data; 1199 { 1200 struct tl_softc *sc = ifp->if_softc; 1201 struct ifreq *ifr = (struct ifreq *)data; 1202 int s, error; 1203 1204 s = splnet(); 1205 switch(cmd) { 1206 case SIOCSIFMEDIA: 1207 case SIOCGIFMEDIA: 1208 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1209 break; 1210 default: 1211 error = ether_ioctl(ifp, cmd, data); 1212 if (error == ENETRESET) { 1213 tl_addr_filter(sc); 1214 error = 0; 1215 } 1216 } 1217 splx(s); 1218 return error; 1219 } 1220 1221 static void 1222 tl_ifstart(ifp) 1223 struct ifnet *ifp; 1224 { 1225 tl_softc_t *sc = ifp->if_softc; 1226 struct mbuf *mb_head; 1227 struct Tx_list *Tx; 1228 int segment, size; 1229 int again, error; 1230 1231 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1232 return; 1233 txloop: 1234 /* If we don't have more space ... */ 1235 if (sc->Free_Tx == NULL) { 1236 #ifdef TLDEBUG 1237 printf("tl_ifstart: No free TX list\n"); 1238 #endif 1239 sc->tl_if.if_flags |= IFF_OACTIVE; 1240 return; 1241 } 1242 /* Grab a paquet for output */ 1243 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1244 if (mb_head == NULL) { 1245 #ifdef TLDEBUG_TX 1246 printf("tl_ifstart: nothing to send\n"); 1247 #endif 1248 return; 1249 } 1250 Tx = sc->Free_Tx; 1251 sc->Free_Tx = Tx->next; 1252 Tx->next = NULL; 1253 again = 0; 1254 /* 1255 * Go through each of the mbufs in the chain and initialize 1256 * the transmit list descriptors with the physical address 1257 * and size of the mbuf. 1258 */ 1259 tbdinit: 1260 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1261 Tx->m = mb_head; 1262 size = mb_head->m_pkthdr.len; 1263 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1264 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1265 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1266 struct mbuf *mn; 1267 /* 1268 * We ran out of segments, or we will. We have to recopy this 1269 * mbuf chain first. 1270 */ 1271 if (error == 0) 1272 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1273 if (again) { 1274 /* already copyed, can't do much more */ 1275 m_freem(mb_head); 1276 goto bad; 1277 } 1278 again = 1; 1279 #ifdef TLDEBUG_TX 1280 printf("tl_ifstart: need to copy mbuf\n"); 1281 #endif 1282 #ifdef TL_PRIV_STATS 1283 sc->oerr_mcopy++; 1284 #endif 1285 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1286 if (mn == NULL) { 1287 m_freem(mb_head); 1288 goto bad; 1289 } 1290 if (mb_head->m_pkthdr.len > MHLEN) { 1291 MCLGET(mn, M_DONTWAIT); 1292 if ((mn->m_flags & M_EXT) == 0) { 1293 m_freem(mn); 1294 m_freem(mb_head); 1295 goto bad; 1296 } 1297 } 1298 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1299 mtod(mn, caddr_t)); 1300 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1301 m_freem(mb_head); 1302 mb_head = mn; 1303 goto tbdinit; 1304 } 1305 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1306 Tx->hw_list->seg[segment].data_addr = 1307 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1308 Tx->hw_list->seg[segment].data_count = 1309 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1310 } 1311 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1313 /* We are at end of mbuf chain. check the size and 1314 * see if it needs to be extended 1315 */ 1316 if (size < ETHER_MIN_TX) { 1317 #ifdef DIAGNOSTIC 1318 if (segment >= TL_NSEG) { 1319 panic("tl_ifstart: to much segmets (%d)\n", segment); 1320 } 1321 #endif 1322 /* 1323 * add the nullbuf in the seg 1324 */ 1325 Tx->hw_list->seg[segment].data_count = 1326 htole32(ETHER_MIN_TX - size); 1327 Tx->hw_list->seg[segment].data_addr = 1328 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1329 size = ETHER_MIN_TX; 1330 segment++; 1331 } 1332 /* The list is done, finish the list init */ 1333 Tx->hw_list->seg[segment-1].data_count |= 1334 htole32(TL_LAST_SEG); 1335 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1336 #ifdef TLDEBUG_TX 1337 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1338 le32toh(Tx->hw_list->stat)); 1339 #if 0 1340 for(segment = 0; segment < TL_NSEG; segment++) { 1341 printf(" seg %d addr 0x%x len 0x%x\n", 1342 segment, 1343 le32toh(Tx->hw_list->seg[segment].data_addr), 1344 le32toh(Tx->hw_list->seg[segment].data_count)); 1345 } 1346 #endif 1347 #endif 1348 if (sc->active_Tx == NULL) { 1349 sc->active_Tx = sc->last_Tx = Tx; 1350 #ifdef TLDEBUG_TX 1351 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1352 (int)Tx->hw_listaddr); 1353 #endif 1354 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1355 sizeof(struct tl_Tx_list) * TL_NBUF, 1356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1357 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1358 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1359 } else { 1360 #ifdef TLDEBUG_TX 1361 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1362 (int)Tx->hw_listaddr); 1363 #endif 1364 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1365 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1366 sizeof(struct tl_Tx_list) * TL_NBUF, 1367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1368 sc->last_Tx->next = Tx; 1369 sc->last_Tx = Tx; 1370 #ifdef DIAGNOSTIC 1371 if (sc->last_Tx->hw_list->fwd & 0x7) 1372 printf("%s: physical addr 0x%x of list not properly " 1373 "aligned\n", 1374 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1375 #endif 1376 } 1377 #if NBPFILTER > 0 1378 /* Pass packet to bpf if there is a listener */ 1379 if (ifp->if_bpf) 1380 bpf_mtap(ifp->if_bpf, mb_head); 1381 #endif 1382 /* 1383 * Set a 5 second timer just in case we don't hear from the card again. 1384 */ 1385 ifp->if_timer = 5; 1386 goto txloop; 1387 bad: 1388 #ifdef TLDEBUG 1389 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1390 #endif 1391 Tx->next = sc->Free_Tx; 1392 sc->Free_Tx = Tx; 1393 return; 1394 } 1395 1396 static void 1397 tl_ifwatchdog(ifp) 1398 struct ifnet *ifp; 1399 { 1400 tl_softc_t *sc = ifp->if_softc; 1401 1402 if ((ifp->if_flags & IFF_RUNNING) == 0) 1403 return; 1404 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1405 ifp->if_oerrors++; 1406 tl_init(ifp); 1407 } 1408 1409 static int 1410 tl_mediachange(ifp) 1411 struct ifnet *ifp; 1412 { 1413 1414 if (ifp->if_flags & IFF_UP) 1415 tl_init(ifp); 1416 return (0); 1417 } 1418 1419 static void 1420 tl_mediastatus(ifp, ifmr) 1421 struct ifnet *ifp; 1422 struct ifmediareq *ifmr; 1423 { 1424 tl_softc_t *sc = ifp->if_softc; 1425 1426 mii_pollstat(&sc->tl_mii); 1427 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1428 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1429 } 1430 1431 static int tl_add_RxBuff(sc, Rx, oldm) 1432 tl_softc_t *sc; 1433 struct Rx_list *Rx; 1434 struct mbuf *oldm; 1435 { 1436 struct mbuf *m; 1437 int error; 1438 1439 MGETHDR(m, M_DONTWAIT, MT_DATA); 1440 if (m != NULL) { 1441 MCLGET(m, M_DONTWAIT); 1442 if ((m->m_flags & M_EXT) == 0) { 1443 m_freem(m); 1444 if (oldm == NULL) 1445 return 0; 1446 m = oldm; 1447 m->m_data = m->m_ext.ext_buf; 1448 } 1449 } else { 1450 if (oldm == NULL) 1451 return 0; 1452 m = oldm; 1453 m->m_data = m->m_ext.ext_buf; 1454 } 1455 1456 /* (re)init the Rx_list struct */ 1457 1458 Rx->m = m; 1459 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1460 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1461 printf("%s: bus_dmamap_load() failed (error %d) for " 1462 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1463 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1464 m_freem(m); 1465 Rx->m = NULL; 1466 return 0; 1467 } 1468 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1469 MCLBYTES, BUS_DMASYNC_PREREAD); 1470 /* 1471 * Move the data pointer up so that the incoming data packet 1472 * will be 32-bit aligned. 1473 */ 1474 m->m_data += 2; 1475 1476 Rx->hw_list->stat = 1477 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1478 Rx->hw_list->seg.data_count = 1479 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1480 Rx->hw_list->seg.data_addr = 1481 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1482 return (m != oldm); 1483 } 1484 1485 static void tl_ticks(v) 1486 void *v; 1487 { 1488 tl_softc_t *sc = v; 1489 1490 tl_read_stats(sc); 1491 1492 /* Tick the MII. */ 1493 mii_tick(&sc->tl_mii); 1494 1495 /* read statistics every seconds */ 1496 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1497 } 1498 1499 static void 1500 tl_read_stats(sc) 1501 tl_softc_t *sc; 1502 { 1503 u_int32_t reg; 1504 int ierr_overr; 1505 int ierr_code; 1506 int ierr_crc; 1507 int oerr_underr; 1508 int oerr_deffered; 1509 int oerr_coll; 1510 int oerr_multicoll; 1511 int oerr_exesscoll; 1512 int oerr_latecoll; 1513 int oerr_carrloss; 1514 struct ifnet *ifp = &sc->tl_if; 1515 1516 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1517 ifp->if_opackets += reg & 0x00ffffff; 1518 oerr_underr = reg >> 24; 1519 1520 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1521 ifp->if_ipackets += reg & 0x00ffffff; 1522 ierr_overr = reg >> 24; 1523 1524 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1525 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1526 ierr_code = (reg & TL_FERR_CODE) >> 24; 1527 oerr_deffered = (reg & TL_FERR_DEF); 1528 1529 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1530 oerr_multicoll = (reg & TL_COL_MULTI); 1531 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1532 1533 reg = tl_intreg_read(sc, TL_INT_LERR); 1534 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1535 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1536 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1537 1538 1539 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1540 oerr_carrloss; 1541 ifp->if_collisions += oerr_coll + oerr_multicoll; 1542 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1543 1544 if (ierr_overr) 1545 printf("%s: receiver ring buffer overrun\n", 1546 sc->sc_dev.dv_xname); 1547 if (oerr_underr) 1548 printf("%s: transmit buffer underrun\n", 1549 sc->sc_dev.dv_xname); 1550 #ifdef TL_PRIV_STATS 1551 sc->ierr_overr += ierr_overr; 1552 sc->ierr_code += ierr_code; 1553 sc->ierr_crc += ierr_crc; 1554 sc->oerr_underr += oerr_underr; 1555 sc->oerr_deffered += oerr_deffered; 1556 sc->oerr_coll += oerr_coll; 1557 sc->oerr_multicoll += oerr_multicoll; 1558 sc->oerr_exesscoll += oerr_exesscoll; 1559 sc->oerr_latecoll += oerr_latecoll; 1560 sc->oerr_carrloss += oerr_carrloss; 1561 #endif 1562 } 1563 1564 static void tl_addr_filter(sc) 1565 tl_softc_t *sc; 1566 { 1567 struct ether_multistep step; 1568 struct ether_multi *enm; 1569 u_int32_t hash[2] = {0, 0}; 1570 int i; 1571 1572 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1573 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1574 while (enm != NULL) { 1575 #ifdef TLDEBUG 1576 printf("tl_addr_filter: addrs %s %s\n", 1577 ether_sprintf(enm->enm_addrlo), 1578 ether_sprintf(enm->enm_addrhi)); 1579 #endif 1580 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1581 i = tl_multicast_hash(enm->enm_addrlo); 1582 hash[i/32] |= 1 << (i%32); 1583 } else { 1584 hash[0] = hash[1] = 0xffffffff; 1585 sc->tl_if.if_flags |= IFF_ALLMULTI; 1586 break; 1587 } 1588 ETHER_NEXT_MULTI(step, enm); 1589 } 1590 #ifdef TLDEBUG 1591 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1592 #endif 1593 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1594 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1595 } 1596 1597 static int tl_multicast_hash(a) 1598 u_int8_t *a; 1599 { 1600 int hash; 1601 1602 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1603 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1604 1605 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1606 DA(a,36), DA(a,42)); 1607 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1608 DA(a,37), DA(a,43)) << 1; 1609 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1610 DA(a,38), DA(a,44)) << 2; 1611 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1612 DA(a,39), DA(a,45)) << 3; 1613 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1614 DA(a,40), DA(a,46)) << 4; 1615 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1616 DA(a,41), DA(a,47)) << 5; 1617 1618 return hash; 1619 } 1620 1621 #if defined(TLDEBUG_RX) 1622 void 1623 ether_printheader(eh) 1624 struct ether_header *eh; 1625 { 1626 u_char *c = (char*)eh; 1627 int i; 1628 for (i=0; i<sizeof(struct ether_header); i++) 1629 printf("%x ", (u_int)c[i]); 1630 printf("\n"); 1631 } 1632 #endif 1633
Indexes created Sun Oct 19 02:09:48 GMT 2025