if_tl.c revision 1.52.4.3
1 /* $NetBSD: if_tl.c,v 1.52.4.3 2005/05/01 10:02:08 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.52.4.3 2005/05/01 10:02:08 tron Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 /* number of transmit/receive buffers */ 116 #ifndef TL_NBUF 117 #define TL_NBUF 10 118 #endif 119 120 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 121 static void tl_pci_attach __P((struct device *, struct device *, void *)); 122 static int tl_intr __P((void *)); 123 124 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 125 static int tl_mediachange __P((struct ifnet *)); 126 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 127 static void tl_ifwatchdog __P((struct ifnet *)); 128 static void tl_shutdown __P((void*)); 129 130 static void tl_ifstart __P((struct ifnet *)); 131 static void tl_reset __P((tl_softc_t*)); 132 static int tl_init __P((struct ifnet *)); 133 static void tl_stop __P((struct ifnet *, int)); 134 static void tl_restart __P((void *)); 135 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 136 static void tl_read_stats __P((tl_softc_t*)); 137 static void tl_ticks __P((void*)); 138 static int tl_multicast_hash __P((u_int8_t*)); 139 static void tl_addr_filter __P((tl_softc_t*)); 140 141 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 143 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 145 146 void tl_mii_sync __P((struct tl_softc *)); 147 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader __P((struct ether_header*)); 152 #endif 153 154 int tl_mii_read __P((struct device *, int, int)); 155 void tl_mii_write __P((struct device *, int, int, int)); 156 157 void tl_statchg __P((struct device *)); 158 159 void tl_i2c_set __P((void*, u_int8_t)); 160 void tl_i2c_clr __P((void*, u_int8_t)); 161 int tl_i2c_read __P((void*, u_int8_t)); 162 163 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 165 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_clr(sc, bits) 167 tl_softc_t* sc; 168 u_int8_t bits; 169 { 170 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 171 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 172 } 173 static __inline void netsio_set(sc, bits) 174 tl_softc_t* sc; 175 u_int8_t bits; 176 { 177 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 178 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 179 } 180 static __inline u_int8_t netsio_read(sc, bits) 181 tl_softc_t* sc; 182 u_int8_t bits; 183 { 184 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 185 } 186 187 struct cfattach tl_ca = { 188 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 189 }; 190 191 const struct tl_product_desc tl_compaq_products[] = { 192 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 193 "Compaq Netelligent 10/100 TX" }, 194 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 195 "Integrated Compaq Netelligent 10/100 TX" }, 196 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 197 "Compaq Netelligent 10 T" }, 198 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 199 "Compaq Netelligent 10 T/2 UTP/Coax" }, 200 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 201 "Compaq Integrated NetFlex 3/P" }, 202 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 203 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 205 "Compaq Dual Port Netelligent 10/100 TX" }, 206 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 207 "Compaq Deskpro 4000 5233MMX" }, 208 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 209 "Compaq NetFlex 3/P w/ BNC" }, 210 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 211 "Compaq NetFlex 3/P" }, 212 { 0, 0, NULL }, 213 }; 214 215 const struct tl_product_desc tl_ti_products[] = { 216 /* 217 * Built-in Ethernet on the TI TravelMate 5000 218 * docking station; better product description? 219 */ 220 { PCI_PRODUCT_TI_TLAN, 0, 221 "Texas Instruments ThunderLAN" }, 222 { 0, 0, NULL }, 223 }; 224 225 struct tl_vendor_desc { 226 u_int32_t tv_vendor; 227 const struct tl_product_desc *tv_products; 228 }; 229 230 const struct tl_vendor_desc tl_vendors[] = { 231 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 232 { PCI_VENDOR_TI, tl_ti_products }, 233 { 0, NULL }, 234 }; 235 236 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 237 238 const struct tl_product_desc * 239 tl_lookup_product(id) 240 u_int32_t id; 241 { 242 const struct tl_product_desc *tp; 243 const struct tl_vendor_desc *tv; 244 245 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 246 if (PCI_VENDOR(id) == tv->tv_vendor) 247 break; 248 249 if ((tp = tv->tv_products) == NULL) 250 return (NULL); 251 252 for (; tp->tp_desc != NULL; tp++) 253 if (PCI_PRODUCT(id) == tp->tp_product) 254 break; 255 256 if (tp->tp_desc == NULL) 257 return (NULL); 258 259 return (tp); 260 } 261 262 static int 263 tl_pci_match(parent, match, aux) 264 struct device *parent; 265 struct cfdata *match; 266 void *aux; 267 { 268 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 269 270 if (tl_lookup_product(pa->pa_id) != NULL) 271 return (1); 272 273 return (0); 274 } 275 276 static void 277 tl_pci_attach(parent, self, aux) 278 struct device * parent; 279 struct device * self; 280 void * aux; 281 { 282 tl_softc_t *sc = (tl_softc_t *)self; 283 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 284 const struct tl_product_desc *tp; 285 struct ifnet * const ifp = &sc->tl_if; 286 bus_space_tag_t iot, memt; 287 bus_space_handle_t ioh, memh; 288 pci_intr_handle_t intrhandle; 289 const char *intrstr; 290 int i, tmp, ioh_valid, memh_valid; 291 int reg_io, reg_mem; 292 pcireg_t reg10, reg14; 293 pcireg_t csr; 294 295 printf("\n"); 296 297 callout_init(&sc->tl_tick_ch); 298 callout_init(&sc->tl_restart_ch); 299 300 tp = tl_lookup_product(pa->pa_id); 301 if (tp == NULL) 302 panic("tl_pci_attach: impossible"); 303 sc->tl_product = tp; 304 305 /* 306 * Map the card space. First we have to find the I/O and MEM 307 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 308 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 309 * The ThunderLAN manual is not consistent about this either (there 310 * are both cases in code examples). 311 */ 312 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 313 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 314 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 315 reg_io = 0x10; 316 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 317 reg_io = 0x14; 318 else 319 reg_io = 0; 320 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 321 reg_mem = 0x10; 322 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 323 reg_mem = 0x14; 324 else 325 reg_mem = 0; 326 327 if (reg_io != 0) 328 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 329 0, &iot, &ioh, NULL, NULL) == 0); 330 else 331 ioh_valid = 0; 332 if (reg_mem != 0) 333 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 334 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 335 0, &memt, &memh, NULL, NULL) == 0); 336 else 337 memh_valid = 0; 338 339 if (ioh_valid) { 340 sc->tl_bustag = iot; 341 sc->tl_bushandle = ioh; 342 } else if (memh_valid) { 343 sc->tl_bustag = memt; 344 sc->tl_bushandle = memh; 345 } else { 346 printf("%s: unable to map device registers\n", 347 sc->sc_dev.dv_xname); 348 return; 349 } 350 sc->tl_dmatag = pa->pa_dmat; 351 352 /* Enable the device. */ 353 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 354 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 355 csr | PCI_COMMAND_MASTER_ENABLE); 356 357 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 358 359 tl_reset(sc); 360 361 /* fill in the i2c struct */ 362 sc->i2cbus.adapter_softc = sc; 363 sc->i2cbus.set_bit = tl_i2c_set; 364 sc->i2cbus.clr_bit = tl_i2c_clr; 365 sc->i2cbus.read_bit = tl_i2c_read; 366 367 #ifdef TLDEBUG 368 printf("default values of INTreg: 0x%x\n", 369 tl_intreg_read(sc, TL_INT_Defaults)); 370 #endif 371 372 /* read mac addr */ 373 for (i=0; i<ETHER_ADDR_LEN; i++) { 374 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 375 if (tmp < 0) { 376 printf("%s: error reading Ethernet adress\n", 377 sc->sc_dev.dv_xname); 378 return; 379 } else { 380 sc->tl_enaddr[i] = tmp; 381 } 382 } 383 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 384 ether_sprintf(sc->tl_enaddr)); 385 386 /* Map and establish interrupts */ 387 if (pci_intr_map(pa, &intrhandle)) { 388 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 389 return; 390 } 391 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 392 sc->tl_if.if_softc = sc; 393 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 394 tl_intr, sc); 395 if (sc->tl_ih == NULL) { 396 printf("%s: couldn't establish interrupt", 397 sc->sc_dev.dv_xname); 398 if (intrstr != NULL) 399 printf(" at %s", intrstr); 400 printf("\n"); 401 return; 402 } 403 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 404 405 /* init these pointers, so that tl_shutdown won't try to read them */ 406 sc->Rx_list = NULL; 407 sc->Tx_list = NULL; 408 409 /* allocate DMA-safe memory for control structs */ 410 if (bus_dmamem_alloc(sc->tl_dmatag, 411 PAGE_SIZE, 0, PAGE_SIZE, 412 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 413 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 414 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 415 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 416 printf("%s: can't allocate DMA memory for lists\n", 417 sc->sc_dev.dv_xname); 418 return; 419 } 420 /* 421 * Add shutdown hook so that DMA is disabled prior to reboot. Not 422 * doing 423 * reboot before the driver initializes. 424 */ 425 (void) shutdownhook_establish(tl_shutdown, ifp); 426 427 /* 428 * Initialize our media structures and probe the MII. 429 * 430 * Note that we don't care about the media instance. We 431 * are expecting to have multiple PHYs on the 10/100 cards, 432 * and on those cards we exclude the internal PHY from providing 433 * 10baseT. By ignoring the instance, it allows us to not have 434 * to specify it on the command line when switching media. 435 */ 436 sc->tl_mii.mii_ifp = ifp; 437 sc->tl_mii.mii_readreg = tl_mii_read; 438 sc->tl_mii.mii_writereg = tl_mii_write; 439 sc->tl_mii.mii_statchg = tl_statchg; 440 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 441 tl_mediastatus); 442 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 443 MII_OFFSET_ANY, 0); 444 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 445 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 446 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 447 } else 448 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 449 450 /* 451 * We can support 802.1Q VLAN-sized frames. 452 */ 453 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 454 455 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 456 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 457 ifp->if_ioctl = tl_ifioctl; 458 ifp->if_start = tl_ifstart; 459 ifp->if_watchdog = tl_ifwatchdog; 460 ifp->if_init = tl_init; 461 ifp->if_stop = tl_stop; 462 ifp->if_timer = 0; 463 IFQ_SET_READY(&ifp->if_snd); 464 if_attach(ifp); 465 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 466 } 467 468 static void 469 tl_reset(sc) 470 tl_softc_t *sc; 471 { 472 int i; 473 474 /* read stats */ 475 if (sc->tl_if.if_flags & IFF_RUNNING) { 476 callout_stop(&sc->tl_tick_ch); 477 tl_read_stats(sc); 478 } 479 /* Reset adapter */ 480 TL_HR_WRITE(sc, TL_HOST_CMD, 481 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 482 DELAY(100000); 483 /* Disable interrupts */ 484 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 485 /* setup aregs & hash */ 486 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 487 tl_intreg_write(sc, i, 0); 488 #ifdef TLDEBUG_ADDR 489 printf("Areg & hash registers: \n"); 490 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 491 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 492 #endif 493 /* Setup NetConfig */ 494 tl_intreg_write(sc, TL_INT_NetConfig, 495 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 496 /* Bsize: accept default */ 497 /* TX commit in Acommit: accept default */ 498 /* Load Ld_tmr and Ld_thr */ 499 /* Ld_tmr = 3 */ 500 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 501 /* Ld_thr = 0 */ 502 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 503 /* Unreset MII */ 504 netsio_set(sc, TL_NETSIO_NMRST); 505 DELAY(100000); 506 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 507 } 508 509 static void tl_shutdown(v) 510 void *v; 511 { 512 tl_stop(v, 1); 513 } 514 515 static void tl_stop(ifp, disable) 516 struct ifnet *ifp; 517 int disable; 518 { 519 tl_softc_t *sc = ifp->if_softc; 520 struct Tx_list *Tx; 521 int i; 522 523 if ((ifp->if_flags & IFF_RUNNING) == 0) 524 return; 525 /* disable interrupts */ 526 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 527 /* stop TX and RX channels */ 528 TL_HR_WRITE(sc, TL_HOST_CMD, 529 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 530 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 531 DELAY(100000); 532 533 /* stop statistics reading loop, read stats */ 534 callout_stop(&sc->tl_tick_ch); 535 tl_read_stats(sc); 536 537 /* Down the MII. */ 538 mii_down(&sc->tl_mii); 539 540 /* deallocate memory allocations */ 541 if (sc->Rx_list) { 542 for (i=0; i< TL_NBUF; i++) { 543 if (sc->Rx_list[i].m) { 544 bus_dmamap_unload(sc->tl_dmatag, 545 sc->Rx_list[i].m_dmamap); 546 m_freem(sc->Rx_list[i].m); 547 } 548 bus_dmamap_destroy(sc->tl_dmatag, 549 sc->Rx_list[i].m_dmamap); 550 sc->Rx_list[i].m = NULL; 551 } 552 free(sc->Rx_list, M_DEVBUF); 553 sc->Rx_list = NULL; 554 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 555 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 556 sc->hw_Rx_list = NULL; 557 while ((Tx = sc->active_Tx) != NULL) { 558 Tx->hw_list->stat = 0; 559 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 560 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 561 m_freem(Tx->m); 562 sc->active_Tx = Tx->next; 563 Tx->next = sc->Free_Tx; 564 sc->Free_Tx = Tx; 565 } 566 sc->last_Tx = NULL; 567 free(sc->Tx_list, M_DEVBUF); 568 sc->Tx_list = NULL; 569 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 570 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 571 sc->hw_Tx_list = NULL; 572 } 573 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 574 ifp->if_timer = 0; 575 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 576 } 577 578 static void tl_restart(v) 579 void *v; 580 { 581 tl_init(v); 582 } 583 584 static int tl_init(ifp) 585 struct ifnet *ifp; 586 { 587 tl_softc_t *sc = ifp->if_softc; 588 int i, s, error; 589 char *errstring; 590 char *nullbuf; 591 592 s = splnet(); 593 /* cancel any pending IO */ 594 tl_stop(ifp, 1); 595 tl_reset(sc); 596 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 597 splx(s); 598 return 0; 599 } 600 /* Set various register to reasonable value */ 601 /* setup NetCmd in promisc mode if needed */ 602 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 603 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 604 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 605 /* Max receive size : MCLBYTES */ 606 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 607 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 608 (MCLBYTES >> 8) & 0xff); 609 610 /* init MAC addr */ 611 for (i = 0; i < ETHER_ADDR_LEN; i++) 612 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 613 /* add multicast filters */ 614 tl_addr_filter(sc); 615 #ifdef TLDEBUG_ADDR 616 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 617 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 618 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 619 #endif 620 621 /* Pre-allocate receivers mbuf, make the lists */ 622 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 623 M_NOWAIT|M_ZERO); 624 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 625 M_NOWAIT|M_ZERO); 626 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 627 errstring = "out of memory for lists"; 628 error = ENOMEM; 629 goto bad; 630 } 631 error = bus_dmamap_create(sc->tl_dmatag, 632 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 633 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 634 &sc->Rx_dmamap); 635 if (error == 0) 636 error = bus_dmamap_create(sc->tl_dmatag, 637 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 638 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 639 &sc->Tx_dmamap); 640 if (error == 0) 641 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 642 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 643 &sc->null_dmamap); 644 if (error) { 645 errstring = "can't allocate DMA maps for lists"; 646 goto bad; 647 } 648 memset(sc->ctrl, 0, PAGE_SIZE); 649 sc->hw_Rx_list = (void *)sc->ctrl; 650 sc->hw_Tx_list = 651 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 652 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 653 sizeof(struct tl_Tx_list) * TL_NBUF; 654 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 655 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 656 BUS_DMA_WAITOK); 657 if (error == 0) 658 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 659 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 660 BUS_DMA_WAITOK); 661 if (error == 0) 662 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 663 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 664 if (error) { 665 errstring = "can't DMA map DMA memory for lists"; 666 goto bad; 667 } 668 for (i=0; i< TL_NBUF; i++) { 669 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 670 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 671 &sc->Rx_list[i].m_dmamap); 672 if (error == 0) { 673 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 674 TL_NSEG, MCLBYTES, 0, 675 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 676 &sc->Tx_list[i].m_dmamap); 677 } 678 if (error) { 679 errstring = "can't allocate DMA maps for mbufs"; 680 goto bad; 681 } 682 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 683 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 684 + sizeof(struct tl_Rx_list) * i; 685 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 686 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 687 + sizeof(struct tl_Tx_list) * i; 688 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 689 errstring = "out of mbuf for receive list"; 690 error = ENOMEM; 691 goto bad; 692 } 693 if (i > 0) { /* chain the list */ 694 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 695 sc->hw_Rx_list[i-1].fwd = 696 htole32(sc->Rx_list[i].hw_listaddr); 697 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 698 } 699 } 700 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 701 sc->Rx_list[TL_NBUF-1].next = NULL; 702 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 703 sc->Tx_list[TL_NBUF-1].next = NULL; 704 705 sc->active_Rx = &sc->Rx_list[0]; 706 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 707 sc->active_Tx = sc->last_Tx = NULL; 708 sc->Free_Tx = &sc->Tx_list[0]; 709 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 710 sizeof(struct tl_Rx_list) * TL_NBUF, 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 713 sizeof(struct tl_Tx_list) * TL_NBUF, 714 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 715 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 716 BUS_DMASYNC_PREWRITE); 717 718 /* set media */ 719 mii_mediachg(&sc->tl_mii); 720 721 /* start ticks calls */ 722 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 723 /* write adress of Rx list and enable interrupts */ 724 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 725 TL_HR_WRITE(sc, TL_HOST_CMD, 726 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 727 sc->tl_if.if_flags |= IFF_RUNNING; 728 sc->tl_if.if_flags &= ~IFF_OACTIVE; 729 return 0; 730 bad: 731 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 732 splx(s); 733 return error; 734 } 735 736 737 static u_int32_t 738 tl_intreg_read(sc, reg) 739 tl_softc_t *sc; 740 u_int32_t reg; 741 { 742 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 743 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 744 } 745 746 static u_int8_t 747 tl_intreg_read_byte(sc, reg) 748 tl_softc_t *sc; 749 u_int32_t reg; 750 { 751 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 752 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 753 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 754 } 755 756 static void 757 tl_intreg_write(sc, reg, val) 758 tl_softc_t *sc; 759 u_int32_t reg; 760 u_int32_t val; 761 { 762 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 763 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 764 } 765 766 static void 767 tl_intreg_write_byte(sc, reg, val) 768 tl_softc_t *sc; 769 u_int32_t reg; 770 u_int8_t val; 771 { 772 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 773 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 774 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 775 } 776 777 void 778 tl_mii_sync(sc) 779 struct tl_softc *sc; 780 { 781 int i; 782 783 netsio_clr(sc, TL_NETSIO_MTXEN); 784 for (i = 0; i < 32; i++) { 785 netsio_clr(sc, TL_NETSIO_MCLK); 786 netsio_set(sc, TL_NETSIO_MCLK); 787 } 788 } 789 790 void 791 tl_mii_sendbits(sc, data, nbits) 792 struct tl_softc *sc; 793 u_int32_t data; 794 int nbits; 795 { 796 int i; 797 798 netsio_set(sc, TL_NETSIO_MTXEN); 799 for (i = 1 << (nbits - 1); i; i = i >> 1) { 800 netsio_clr(sc, TL_NETSIO_MCLK); 801 netsio_read(sc, TL_NETSIO_MCLK); 802 if (data & i) 803 netsio_set(sc, TL_NETSIO_MDATA); 804 else 805 netsio_clr(sc, TL_NETSIO_MDATA); 806 netsio_set(sc, TL_NETSIO_MCLK); 807 netsio_read(sc, TL_NETSIO_MCLK); 808 } 809 } 810 811 int 812 tl_mii_read(self, phy, reg) 813 struct device *self; 814 int phy, reg; 815 { 816 struct tl_softc *sc = (struct tl_softc *)self; 817 int val = 0, i, err; 818 819 /* 820 * Read the PHY register by manually driving the MII control lines. 821 */ 822 823 tl_mii_sync(sc); 824 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 825 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 826 tl_mii_sendbits(sc, phy, 5); 827 tl_mii_sendbits(sc, reg, 5); 828 829 netsio_clr(sc, TL_NETSIO_MTXEN); 830 netsio_clr(sc, TL_NETSIO_MCLK); 831 netsio_set(sc, TL_NETSIO_MCLK); 832 netsio_clr(sc, TL_NETSIO_MCLK); 833 834 err = netsio_read(sc, TL_NETSIO_MDATA); 835 netsio_set(sc, TL_NETSIO_MCLK); 836 837 /* Even if an error occurs, must still clock out the cycle. */ 838 for (i = 0; i < 16; i++) { 839 val <<= 1; 840 netsio_clr(sc, TL_NETSIO_MCLK); 841 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 842 val |= 1; 843 netsio_set(sc, TL_NETSIO_MCLK); 844 } 845 netsio_clr(sc, TL_NETSIO_MCLK); 846 netsio_set(sc, TL_NETSIO_MCLK); 847 848 return (err ? 0 : val); 849 } 850 851 void 852 tl_mii_write(self, phy, reg, val) 853 struct device *self; 854 int phy, reg, val; 855 { 856 struct tl_softc *sc = (struct tl_softc *)self; 857 858 /* 859 * Write the PHY register by manually driving the MII control lines. 860 */ 861 862 tl_mii_sync(sc); 863 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 864 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 865 tl_mii_sendbits(sc, phy, 5); 866 tl_mii_sendbits(sc, reg, 5); 867 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 868 tl_mii_sendbits(sc, val, 16); 869 870 netsio_clr(sc, TL_NETSIO_MCLK); 871 netsio_set(sc, TL_NETSIO_MCLK); 872 } 873 874 void 875 tl_statchg(self) 876 struct device *self; 877 { 878 tl_softc_t *sc = (struct tl_softc *)self; 879 u_int32_t reg; 880 881 #ifdef TLDEBUG 882 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 883 #endif 884 885 /* 886 * We must keep the ThunderLAN and the PHY in sync as 887 * to the status of full-duplex! 888 */ 889 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 890 if (sc->tl_mii.mii_media_active & IFM_FDX) 891 reg |= TL_NETCOMMAND_DUPLEX; 892 else 893 reg &= ~TL_NETCOMMAND_DUPLEX; 894 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 895 } 896 897 void tl_i2c_set(v, bit) 898 void *v; 899 u_int8_t bit; 900 { 901 tl_softc_t *sc = v; 902 903 switch (bit) { 904 case I2C_DATA: 905 netsio_set(sc, TL_NETSIO_EDATA); 906 break; 907 case I2C_CLOCK: 908 netsio_set(sc, TL_NETSIO_ECLOCK); 909 break; 910 case I2C_TXEN: 911 netsio_set(sc, TL_NETSIO_ETXEN); 912 break; 913 default: 914 printf("tl_i2c_set: unknown bit %d\n", bit); 915 } 916 return; 917 } 918 919 void tl_i2c_clr(v, bit) 920 void *v; 921 u_int8_t bit; 922 { 923 tl_softc_t *sc = v; 924 925 switch (bit) { 926 case I2C_DATA: 927 netsio_clr(sc, TL_NETSIO_EDATA); 928 break; 929 case I2C_CLOCK: 930 netsio_clr(sc, TL_NETSIO_ECLOCK); 931 break; 932 case I2C_TXEN: 933 netsio_clr(sc, TL_NETSIO_ETXEN); 934 break; 935 default: 936 printf("tl_i2c_clr: unknown bit %d\n", bit); 937 } 938 return; 939 } 940 941 int tl_i2c_read(v, bit) 942 void *v; 943 u_int8_t bit; 944 { 945 tl_softc_t *sc = v; 946 947 switch (bit) { 948 case I2C_DATA: 949 return netsio_read(sc, TL_NETSIO_EDATA); 950 break; 951 case I2C_CLOCK: 952 return netsio_read(sc, TL_NETSIO_ECLOCK); 953 break; 954 case I2C_TXEN: 955 return netsio_read(sc, TL_NETSIO_ETXEN); 956 break; 957 default: 958 printf("tl_i2c_read: unknown bit %d\n", bit); 959 return -1; 960 } 961 } 962 963 static int 964 tl_intr(v) 965 void *v; 966 { 967 tl_softc_t *sc = v; 968 struct ifnet *ifp = &sc->tl_if; 969 struct Rx_list *Rx; 970 struct Tx_list *Tx; 971 struct mbuf *m; 972 u_int32_t int_type, int_reg; 973 int ack = 0; 974 int size; 975 976 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 977 int_type = int_reg & TL_INTR_MASK; 978 if (int_type == 0) 979 return 0; 980 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 981 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 982 int_type, int_reg); 983 #endif 984 /* disable interrupts */ 985 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 986 switch(int_type & TL_INTR_MASK) { 987 case TL_INTR_RxEOF: 988 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 989 sizeof(struct tl_Rx_list) * TL_NBUF, 990 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 991 while(le32toh(sc->active_Rx->hw_list->stat) & 992 TL_RX_CSTAT_CPLT) { 993 /* dequeue and requeue at end of list */ 994 ack++; 995 Rx = sc->active_Rx; 996 sc->active_Rx = Rx->next; 997 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 998 MCLBYTES, BUS_DMASYNC_POSTREAD); 999 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1000 m = Rx->m; 1001 size = le32toh(Rx->hw_list->stat) >> 16; 1002 #ifdef TLDEBUG_RX 1003 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1004 Rx, size); 1005 #endif 1006 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1007 /* 1008 * No new mbuf, reuse the same. This means 1009 * that this packet 1010 * is lost 1011 */ 1012 m = NULL; 1013 #ifdef TL_PRIV_STATS 1014 sc->ierr_nomem++; 1015 #endif 1016 #ifdef TLDEBUG 1017 printf("%s: out of mbuf, lost input packet\n", 1018 sc->sc_dev.dv_xname); 1019 #endif 1020 } 1021 Rx->next = NULL; 1022 Rx->hw_list->fwd = 0; 1023 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1024 sc->last_Rx->next = Rx; 1025 sc->last_Rx = Rx; 1026 1027 /* deliver packet */ 1028 if (m) { 1029 if (size < sizeof(struct ether_header)) { 1030 m_freem(m); 1031 continue; 1032 } 1033 m->m_pkthdr.rcvif = ifp; 1034 m->m_pkthdr.len = m->m_len = size; 1035 #ifdef TLDEBUG_RX 1036 { struct ether_header *eh = 1037 mtod(m, struct ether_header *); 1038 printf("tl_intr: Rx packet:\n"); 1039 ether_printheader(eh); } 1040 #endif 1041 #if NBPFILTER > 0 1042 if (ifp->if_bpf) 1043 bpf_mtap(ifp->if_bpf, m); 1044 #endif /* NBPFILTER > 0 */ 1045 (*ifp->if_input)(ifp, m); 1046 } 1047 } 1048 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1049 sizeof(struct tl_Rx_list) * TL_NBUF, 1050 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1051 #ifdef TLDEBUG_RX 1052 printf("TL_INTR_RxEOF: ack %d\n", ack); 1053 #else 1054 if (ack == 0) { 1055 printf("%s: EOF intr without anything to read !\n", 1056 sc->sc_dev.dv_xname); 1057 tl_reset(sc); 1058 /* shedule reinit of the board */ 1059 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1060 return(1); 1061 } 1062 #endif 1063 break; 1064 case TL_INTR_RxEOC: 1065 ack++; 1066 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1067 sizeof(struct tl_Rx_list) * TL_NBUF, 1068 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1069 #ifdef TLDEBUG_RX 1070 printf("TL_INTR_RxEOC: ack %d\n", ack); 1071 #endif 1072 #ifdef DIAGNOSTIC 1073 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1074 printf("%s: Rx EOC interrupt and active Tx list not " 1075 "cleared\n", sc->sc_dev.dv_xname); 1076 return 0; 1077 } else 1078 #endif 1079 { 1080 /* 1081 * write adress of Rx list and send Rx GO command, ack 1082 * interrupt and enable interrupts in one command 1083 */ 1084 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1085 TL_HR_WRITE(sc, TL_HOST_CMD, 1086 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1087 HOST_CMD_ACK | HOST_CMD_IntOn); 1088 return 1; 1089 } 1090 case TL_INTR_TxEOF: 1091 case TL_INTR_TxEOC: 1092 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1093 sizeof(struct tl_Tx_list) * TL_NBUF, 1094 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1095 while ((Tx = sc->active_Tx) != NULL) { 1096 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1097 break; 1098 ack++; 1099 #ifdef TLDEBUG_TX 1100 printf("TL_INTR_TxEOC: list 0x%x done\n", 1101 (int)Tx->hw_listaddr); 1102 #endif 1103 Tx->hw_list->stat = 0; 1104 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1105 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1106 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1107 m_freem(Tx->m); 1108 Tx->m = NULL; 1109 sc->active_Tx = Tx->next; 1110 if (sc->active_Tx == NULL) 1111 sc->last_Tx = NULL; 1112 Tx->next = sc->Free_Tx; 1113 sc->Free_Tx = Tx; 1114 } 1115 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1116 sizeof(struct tl_Tx_list) * TL_NBUF, 1117 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1118 /* if this was an EOC, ACK immediatly */ 1119 if (ack) 1120 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1121 if (int_type == TL_INTR_TxEOC) { 1122 #ifdef TLDEBUG_TX 1123 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1124 ack); 1125 #endif 1126 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1127 HOST_CMD_ACK | HOST_CMD_IntOn); 1128 if ( sc->active_Tx != NULL) { 1129 /* needs a Tx go command */ 1130 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1131 sc->active_Tx->hw_listaddr); 1132 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1133 } 1134 sc->tl_if.if_timer = 0; 1135 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1136 tl_ifstart(&sc->tl_if); 1137 return 1; 1138 } 1139 #ifdef TLDEBUG 1140 else { 1141 printf("TL_INTR_TxEOF: ack %d\n", ack); 1142 } 1143 #endif 1144 sc->tl_if.if_timer = 0; 1145 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1146 tl_ifstart(&sc->tl_if); 1147 break; 1148 case TL_INTR_Stat: 1149 ack++; 1150 #ifdef TLDEBUG 1151 printf("TL_INTR_Stat: ack %d\n", ack); 1152 #endif 1153 tl_read_stats(sc); 1154 break; 1155 case TL_INTR_Adc: 1156 if (int_reg & TL_INTVec_MASK) { 1157 /* adapter check conditions */ 1158 printf("%s: check condition, intvect=0x%x, " 1159 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1160 int_reg & TL_INTVec_MASK, 1161 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1162 tl_reset(sc); 1163 /* shedule reinit of the board */ 1164 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1165 return(1); 1166 } else { 1167 u_int8_t netstat; 1168 /* Network status */ 1169 netstat = 1170 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1171 printf("%s: network status, NetSts=%x\n", 1172 sc->sc_dev.dv_xname, netstat); 1173 /* Ack interrupts */ 1174 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1175 netstat); 1176 ack++; 1177 } 1178 break; 1179 default: 1180 printf("%s: unhandled interrupt code %x!\n", 1181 sc->sc_dev.dv_xname, int_type); 1182 ack++; 1183 } 1184 1185 if (ack) { 1186 /* Ack the interrupt and enable interrupts */ 1187 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1188 HOST_CMD_IntOn); 1189 return 1; 1190 } 1191 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1192 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1193 return 0; 1194 } 1195 1196 static int 1197 tl_ifioctl(ifp, cmd, data) 1198 struct ifnet *ifp; 1199 ioctl_cmd_t cmd; 1200 caddr_t data; 1201 { 1202 struct tl_softc *sc = ifp->if_softc; 1203 struct ifreq *ifr = (struct ifreq *)data; 1204 int s, error; 1205 1206 s = splnet(); 1207 switch(cmd) { 1208 case SIOCSIFMEDIA: 1209 case SIOCGIFMEDIA: 1210 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1211 break; 1212 default: 1213 error = ether_ioctl(ifp, cmd, data); 1214 if (error == ENETRESET) { 1215 tl_addr_filter(sc); 1216 error = 0; 1217 } 1218 } 1219 splx(s); 1220 return error; 1221 } 1222 1223 static void 1224 tl_ifstart(ifp) 1225 struct ifnet *ifp; 1226 { 1227 tl_softc_t *sc = ifp->if_softc; 1228 struct mbuf *mb_head; 1229 struct Tx_list *Tx; 1230 int segment, size; 1231 int again, error; 1232 1233 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1234 return; 1235 txloop: 1236 /* If we don't have more space ... */ 1237 if (sc->Free_Tx == NULL) { 1238 #ifdef TLDEBUG 1239 printf("tl_ifstart: No free TX list\n"); 1240 #endif 1241 sc->tl_if.if_flags |= IFF_OACTIVE; 1242 return; 1243 } 1244 /* Grab a paquet for output */ 1245 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1246 if (mb_head == NULL) { 1247 #ifdef TLDEBUG_TX 1248 printf("tl_ifstart: nothing to send\n"); 1249 #endif 1250 return; 1251 } 1252 Tx = sc->Free_Tx; 1253 sc->Free_Tx = Tx->next; 1254 Tx->next = NULL; 1255 again = 0; 1256 /* 1257 * Go through each of the mbufs in the chain and initialize 1258 * the transmit list descriptors with the physical address 1259 * and size of the mbuf. 1260 */ 1261 tbdinit: 1262 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1263 Tx->m = mb_head; 1264 size = mb_head->m_pkthdr.len; 1265 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1266 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1267 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1268 struct mbuf *mn; 1269 /* 1270 * We ran out of segments, or we will. We have to recopy this 1271 * mbuf chain first. 1272 */ 1273 if (error == 0) 1274 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1275 if (again) { 1276 /* already copyed, can't do much more */ 1277 m_freem(mb_head); 1278 goto bad; 1279 } 1280 again = 1; 1281 #ifdef TLDEBUG_TX 1282 printf("tl_ifstart: need to copy mbuf\n"); 1283 #endif 1284 #ifdef TL_PRIV_STATS 1285 sc->oerr_mcopy++; 1286 #endif 1287 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1288 if (mn == NULL) { 1289 m_freem(mb_head); 1290 goto bad; 1291 } 1292 if (mb_head->m_pkthdr.len > MHLEN) { 1293 MCLGET(mn, M_DONTWAIT); 1294 if ((mn->m_flags & M_EXT) == 0) { 1295 m_freem(mn); 1296 m_freem(mb_head); 1297 goto bad; 1298 } 1299 } 1300 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1301 mtod(mn, caddr_t)); 1302 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1303 m_freem(mb_head); 1304 mb_head = mn; 1305 goto tbdinit; 1306 } 1307 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1308 Tx->hw_list->seg[segment].data_addr = 1309 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1310 Tx->hw_list->seg[segment].data_count = 1311 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1312 } 1313 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1315 /* We are at end of mbuf chain. check the size and 1316 * see if it needs to be extended 1317 */ 1318 if (size < ETHER_MIN_TX) { 1319 #ifdef DIAGNOSTIC 1320 if (segment >= TL_NSEG) { 1321 panic("tl_ifstart: to much segmets (%d)\n", segment); 1322 } 1323 #endif 1324 /* 1325 * add the nullbuf in the seg 1326 */ 1327 Tx->hw_list->seg[segment].data_count = 1328 htole32(ETHER_MIN_TX - size); 1329 Tx->hw_list->seg[segment].data_addr = 1330 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1331 size = ETHER_MIN_TX; 1332 segment++; 1333 } 1334 /* The list is done, finish the list init */ 1335 Tx->hw_list->seg[segment-1].data_count |= 1336 htole32(TL_LAST_SEG); 1337 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1338 #ifdef TLDEBUG_TX 1339 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1340 le32toh(Tx->hw_list->stat)); 1341 #if 0 1342 for(segment = 0; segment < TL_NSEG; segment++) { 1343 printf(" seg %d addr 0x%x len 0x%x\n", 1344 segment, 1345 le32toh(Tx->hw_list->seg[segment].data_addr), 1346 le32toh(Tx->hw_list->seg[segment].data_count)); 1347 } 1348 #endif 1349 #endif 1350 if (sc->active_Tx == NULL) { 1351 sc->active_Tx = sc->last_Tx = Tx; 1352 #ifdef TLDEBUG_TX 1353 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1354 (int)Tx->hw_listaddr); 1355 #endif 1356 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1357 sizeof(struct tl_Tx_list) * TL_NBUF, 1358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1359 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1360 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1361 } else { 1362 #ifdef TLDEBUG_TX 1363 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1364 (int)Tx->hw_listaddr); 1365 #endif 1366 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1367 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1368 sizeof(struct tl_Tx_list) * TL_NBUF, 1369 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1370 sc->last_Tx->next = Tx; 1371 sc->last_Tx = Tx; 1372 #ifdef DIAGNOSTIC 1373 if (sc->last_Tx->hw_list->fwd & 0x7) 1374 printf("%s: physical addr 0x%x of list not properly " 1375 "aligned\n", 1376 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1377 #endif 1378 } 1379 #if NBPFILTER > 0 1380 /* Pass packet to bpf if there is a listener */ 1381 if (ifp->if_bpf) 1382 bpf_mtap(ifp->if_bpf, mb_head); 1383 #endif 1384 /* 1385 * Set a 5 second timer just in case we don't hear from the card again. 1386 */ 1387 ifp->if_timer = 5; 1388 goto txloop; 1389 bad: 1390 #ifdef TLDEBUG 1391 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1392 #endif 1393 Tx->next = sc->Free_Tx; 1394 sc->Free_Tx = Tx; 1395 return; 1396 } 1397 1398 static void 1399 tl_ifwatchdog(ifp) 1400 struct ifnet *ifp; 1401 { 1402 tl_softc_t *sc = ifp->if_softc; 1403 1404 if ((ifp->if_flags & IFF_RUNNING) == 0) 1405 return; 1406 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1407 ifp->if_oerrors++; 1408 tl_init(ifp); 1409 } 1410 1411 static int 1412 tl_mediachange(ifp) 1413 struct ifnet *ifp; 1414 { 1415 1416 if (ifp->if_flags & IFF_UP) 1417 tl_init(ifp); 1418 return (0); 1419 } 1420 1421 static void 1422 tl_mediastatus(ifp, ifmr) 1423 struct ifnet *ifp; 1424 struct ifmediareq *ifmr; 1425 { 1426 tl_softc_t *sc = ifp->if_softc; 1427 1428 mii_pollstat(&sc->tl_mii); 1429 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1430 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1431 } 1432 1433 static int tl_add_RxBuff(sc, Rx, oldm) 1434 tl_softc_t *sc; 1435 struct Rx_list *Rx; 1436 struct mbuf *oldm; 1437 { 1438 struct mbuf *m; 1439 int error; 1440 1441 MGETHDR(m, M_DONTWAIT, MT_DATA); 1442 if (m != NULL) { 1443 MCLGET(m, M_DONTWAIT); 1444 if ((m->m_flags & M_EXT) == 0) { 1445 m_freem(m); 1446 if (oldm == NULL) 1447 return 0; 1448 m = oldm; 1449 m->m_data = m->m_ext.ext_buf; 1450 } 1451 } else { 1452 if (oldm == NULL) 1453 return 0; 1454 m = oldm; 1455 m->m_data = m->m_ext.ext_buf; 1456 } 1457 1458 /* (re)init the Rx_list struct */ 1459 1460 Rx->m = m; 1461 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1462 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1463 printf("%s: bus_dmamap_load() failed (error %d) for " 1464 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1465 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1466 m_freem(m); 1467 Rx->m = NULL; 1468 return 0; 1469 } 1470 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1471 MCLBYTES, BUS_DMASYNC_PREREAD); 1472 /* 1473 * Move the data pointer up so that the incoming data packet 1474 * will be 32-bit aligned. 1475 */ 1476 m->m_data += 2; 1477 1478 Rx->hw_list->stat = 1479 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1480 Rx->hw_list->seg.data_count = 1481 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1482 Rx->hw_list->seg.data_addr = 1483 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1484 return (m != oldm); 1485 } 1486 1487 static void tl_ticks(v) 1488 void *v; 1489 { 1490 tl_softc_t *sc = v; 1491 1492 tl_read_stats(sc); 1493 1494 /* Tick the MII. */ 1495 mii_tick(&sc->tl_mii); 1496 1497 /* read statistics every seconds */ 1498 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1499 } 1500 1501 static void 1502 tl_read_stats(sc) 1503 tl_softc_t *sc; 1504 { 1505 u_int32_t reg; 1506 int ierr_overr; 1507 int ierr_code; 1508 int ierr_crc; 1509 int oerr_underr; 1510 int oerr_deffered; 1511 int oerr_coll; 1512 int oerr_multicoll; 1513 int oerr_exesscoll; 1514 int oerr_latecoll; 1515 int oerr_carrloss; 1516 struct ifnet *ifp = &sc->tl_if; 1517 1518 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1519 ifp->if_opackets += reg & 0x00ffffff; 1520 oerr_underr = reg >> 24; 1521 1522 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1523 ifp->if_ipackets += reg & 0x00ffffff; 1524 ierr_overr = reg >> 24; 1525 1526 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1527 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1528 ierr_code = (reg & TL_FERR_CODE) >> 24; 1529 oerr_deffered = (reg & TL_FERR_DEF); 1530 1531 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1532 oerr_multicoll = (reg & TL_COL_MULTI); 1533 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1534 1535 reg = tl_intreg_read(sc, TL_INT_LERR); 1536 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1537 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1538 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1539 1540 1541 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1542 oerr_carrloss; 1543 ifp->if_collisions += oerr_coll + oerr_multicoll; 1544 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1545 1546 if (ierr_overr) 1547 printf("%s: receiver ring buffer overrun\n", 1548 sc->sc_dev.dv_xname); 1549 if (oerr_underr) 1550 printf("%s: transmit buffer underrun\n", 1551 sc->sc_dev.dv_xname); 1552 #ifdef TL_PRIV_STATS 1553 sc->ierr_overr += ierr_overr; 1554 sc->ierr_code += ierr_code; 1555 sc->ierr_crc += ierr_crc; 1556 sc->oerr_underr += oerr_underr; 1557 sc->oerr_deffered += oerr_deffered; 1558 sc->oerr_coll += oerr_coll; 1559 sc->oerr_multicoll += oerr_multicoll; 1560 sc->oerr_exesscoll += oerr_exesscoll; 1561 sc->oerr_latecoll += oerr_latecoll; 1562 sc->oerr_carrloss += oerr_carrloss; 1563 #endif 1564 } 1565 1566 static void tl_addr_filter(sc) 1567 tl_softc_t *sc; 1568 { 1569 struct ether_multistep step; 1570 struct ether_multi *enm; 1571 u_int32_t hash[2] = {0, 0}; 1572 int i; 1573 1574 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1575 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1576 while (enm != NULL) { 1577 #ifdef TLDEBUG 1578 printf("tl_addr_filter: addrs %s %s\n", 1579 ether_sprintf(enm->enm_addrlo), 1580 ether_sprintf(enm->enm_addrhi)); 1581 #endif 1582 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1583 i = tl_multicast_hash(enm->enm_addrlo); 1584 hash[i/32] |= 1 << (i%32); 1585 } else { 1586 hash[0] = hash[1] = 0xffffffff; 1587 sc->tl_if.if_flags |= IFF_ALLMULTI; 1588 break; 1589 } 1590 ETHER_NEXT_MULTI(step, enm); 1591 } 1592 #ifdef TLDEBUG 1593 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1594 #endif 1595 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1596 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1597 } 1598 1599 static int tl_multicast_hash(a) 1600 u_int8_t *a; 1601 { 1602 int hash; 1603 1604 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1605 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1606 1607 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1608 DA(a,36), DA(a,42)); 1609 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1610 DA(a,37), DA(a,43)) << 1; 1611 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1612 DA(a,38), DA(a,44)) << 2; 1613 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1614 DA(a,39), DA(a,45)) << 3; 1615 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1616 DA(a,40), DA(a,46)) << 4; 1617 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1618 DA(a,41), DA(a,47)) << 5; 1619 1620 return hash; 1621 } 1622 1623 #if defined(TLDEBUG_RX) 1624 void 1625 ether_printheader(eh) 1626 struct ether_header *eh; 1627 { 1628 u_char *c = (char*)eh; 1629 int i; 1630 for (i=0; i<sizeof(struct ether_header); i++) 1631 printf("%x ", (u_int)c[i]); 1632 printf("\n"); 1633 } 1634 #endif 1635
Indexes created Wed Oct 22 13:09:56 GMT 2025