if_tl.c revision 1.62
1 /* $NetBSD: if_tl.c,v 1.62 2003/10/05 14:57:14 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.62 2003/10/05 14:57:14 tsutsui Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 122 static void tl_pci_attach __P((struct device *, struct device *, void *)); 123 static int tl_intr __P((void *)); 124 125 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 126 static int tl_mediachange __P((struct ifnet *)); 127 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 128 static void tl_ifwatchdog __P((struct ifnet *)); 129 static void tl_shutdown __P((void*)); 130 131 static void tl_ifstart __P((struct ifnet *)); 132 static void tl_reset __P((tl_softc_t*)); 133 static int tl_init __P((struct ifnet *)); 134 static void tl_stop __P((struct ifnet *, int)); 135 static void tl_restart __P((void *)); 136 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 137 static void tl_read_stats __P((tl_softc_t*)); 138 static void tl_ticks __P((void*)); 139 static int tl_multicast_hash __P((u_int8_t*)); 140 static void tl_addr_filter __P((tl_softc_t*)); 141 142 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 143 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 144 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 145 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 146 147 void tl_mii_sync __P((struct tl_softc *)); 148 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 149 150 151 #if defined(TLDEBUG_RX) 152 static void ether_printheader __P((struct ether_header*)); 153 #endif 154 155 int tl_mii_read __P((struct device *, int, int)); 156 void tl_mii_write __P((struct device *, int, int, int)); 157 158 void tl_statchg __P((struct device *)); 159 160 /* I2C glue */ 161 static int tl_i2c_acquire_bus(void *, int); 162 static void tl_i2c_release_bus(void *, int); 163 static int tl_i2c_send_start(void *, int); 164 static int tl_i2c_send_stop(void *, int); 165 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int tl_i2c_read_byte(void *, uint8_t *, int); 167 static int tl_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bit-bang glue */ 170 static void tl_i2cbb_set_bits(void *, uint32_t); 171 static void tl_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t tl_i2cbb_read(void *); 173 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 174 tl_i2cbb_set_bits, 175 tl_i2cbb_set_dir, 176 tl_i2cbb_read, 177 { 178 TL_NETSIO_EDATA, /* SDA */ 179 TL_NETSIO_ECLOCK, /* SCL */ 180 TL_NETSIO_ETXEN, /* SDA is output */ 181 0, /* SDA is input */ 182 } 183 }; 184 185 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 186 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 187 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 188 static __inline void netsio_clr(sc, bits) 189 tl_softc_t* sc; 190 u_int8_t bits; 191 { 192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 194 } 195 static __inline void netsio_set(sc, bits) 196 tl_softc_t* sc; 197 u_int8_t bits; 198 { 199 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 200 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 201 } 202 static __inline u_int8_t netsio_read(sc, bits) 203 tl_softc_t* sc; 204 u_int8_t bits; 205 { 206 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 207 } 208 209 CFATTACH_DECL(tl, sizeof(tl_softc_t), 210 tl_pci_match, tl_pci_attach, NULL, NULL); 211 212 const struct tl_product_desc tl_compaq_products[] = { 213 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 214 "Compaq Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 216 "Compaq Netelligent 10 T" }, 217 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 218 "Compaq Integrated NetFlex 3/P" }, 219 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 220 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 221 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 222 "Compaq Dual Port Netelligent 10/100 TX" }, 223 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 224 "Compaq Deskpro 4000 5233MMX" }, 225 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 226 "Compaq NetFlex 3/P w/ BNC" }, 227 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 228 "Compaq NetFlex 3/P" }, 229 { 0, 0, NULL }, 230 }; 231 232 const struct tl_product_desc tl_ti_products[] = { 233 /* 234 * Built-in Ethernet on the TI TravelMate 5000 235 * docking station; better product description? 236 */ 237 { PCI_PRODUCT_TI_TLAN, 0, 238 "Texas Instruments ThunderLAN" }, 239 { 0, 0, NULL }, 240 }; 241 242 struct tl_vendor_desc { 243 u_int32_t tv_vendor; 244 const struct tl_product_desc *tv_products; 245 }; 246 247 const struct tl_vendor_desc tl_vendors[] = { 248 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 249 { PCI_VENDOR_TI, tl_ti_products }, 250 { 0, NULL }, 251 }; 252 253 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 254 255 const struct tl_product_desc * 256 tl_lookup_product(id) 257 u_int32_t id; 258 { 259 const struct tl_product_desc *tp; 260 const struct tl_vendor_desc *tv; 261 262 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 263 if (PCI_VENDOR(id) == tv->tv_vendor) 264 break; 265 266 if ((tp = tv->tv_products) == NULL) 267 return (NULL); 268 269 for (; tp->tp_desc != NULL; tp++) 270 if (PCI_PRODUCT(id) == tp->tp_product) 271 break; 272 273 if (tp->tp_desc == NULL) 274 return (NULL); 275 276 return (tp); 277 } 278 279 static int 280 tl_pci_match(parent, match, aux) 281 struct device *parent; 282 struct cfdata *match; 283 void *aux; 284 { 285 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 286 287 if (tl_lookup_product(pa->pa_id) != NULL) 288 return (1); 289 290 return (0); 291 } 292 293 static void 294 tl_pci_attach(parent, self, aux) 295 struct device * parent; 296 struct device * self; 297 void * aux; 298 { 299 tl_softc_t *sc = (tl_softc_t *)self; 300 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 301 const struct tl_product_desc *tp; 302 struct ifnet * const ifp = &sc->tl_if; 303 bus_space_tag_t iot, memt; 304 bus_space_handle_t ioh, memh; 305 pci_intr_handle_t intrhandle; 306 const char *intrstr; 307 int ioh_valid, memh_valid; 308 int reg_io, reg_mem; 309 pcireg_t reg10, reg14; 310 pcireg_t csr; 311 312 printf("\n"); 313 314 callout_init(&sc->tl_tick_ch); 315 callout_init(&sc->tl_restart_ch); 316 317 tp = tl_lookup_product(pa->pa_id); 318 if (tp == NULL) 319 panic("tl_pci_attach: impossible"); 320 sc->tl_product = tp; 321 322 /* 323 * Map the card space. First we have to find the I/O and MEM 324 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 325 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 326 * The ThunderLAN manual is not consistent about this either (there 327 * are both cases in code examples). 328 */ 329 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 330 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 331 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 332 reg_io = 0x10; 333 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 334 reg_io = 0x14; 335 else 336 reg_io = 0; 337 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 338 reg_mem = 0x10; 339 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 340 reg_mem = 0x14; 341 else 342 reg_mem = 0; 343 344 if (reg_io != 0) 345 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 346 0, &iot, &ioh, NULL, NULL) == 0); 347 else 348 ioh_valid = 0; 349 if (reg_mem != 0) 350 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 351 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 352 0, &memt, &memh, NULL, NULL) == 0); 353 else 354 memh_valid = 0; 355 356 if (ioh_valid) { 357 sc->tl_bustag = iot; 358 sc->tl_bushandle = ioh; 359 } else if (memh_valid) { 360 sc->tl_bustag = memt; 361 sc->tl_bushandle = memh; 362 } else { 363 printf("%s: unable to map device registers\n", 364 sc->sc_dev.dv_xname); 365 return; 366 } 367 sc->tl_dmatag = pa->pa_dmat; 368 369 /* Enable the device. */ 370 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 371 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 372 csr | PCI_COMMAND_MASTER_ENABLE); 373 374 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 375 376 tl_reset(sc); 377 378 /* fill in the i2c tag */ 379 sc->sc_i2c.ic_cookie = sc; 380 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 381 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 382 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 383 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 384 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 385 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 386 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 387 388 #ifdef TLDEBUG 389 printf("default values of INTreg: 0x%x\n", 390 tl_intreg_read(sc, TL_INT_Defaults)); 391 #endif 392 393 /* read mac addr */ 394 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 395 sc->tl_enaddr, ETHER_ADDR_LEN)) { 396 printf("%s: error reading Ethernet adress\n", 397 sc->sc_dev.dv_xname); 398 return; 399 } 400 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 401 ether_sprintf(sc->tl_enaddr)); 402 403 /* Map and establish interrupts */ 404 if (pci_intr_map(pa, &intrhandle)) { 405 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 406 return; 407 } 408 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 409 sc->tl_if.if_softc = sc; 410 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 411 tl_intr, sc); 412 if (sc->tl_ih == NULL) { 413 printf("%s: couldn't establish interrupt", 414 sc->sc_dev.dv_xname); 415 if (intrstr != NULL) 416 printf(" at %s", intrstr); 417 printf("\n"); 418 return; 419 } 420 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 421 422 /* init these pointers, so that tl_shutdown won't try to read them */ 423 sc->Rx_list = NULL; 424 sc->Tx_list = NULL; 425 426 /* allocate DMA-safe memory for control structs */ 427 if (bus_dmamem_alloc(sc->tl_dmatag, 428 PAGE_SIZE, 0, PAGE_SIZE, 429 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 430 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 431 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 432 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 433 printf("%s: can't allocate DMA memory for lists\n", 434 sc->sc_dev.dv_xname); 435 return; 436 } 437 /* 438 * Add shutdown hook so that DMA is disabled prior to reboot. Not 439 * doing 440 * reboot before the driver initializes. 441 */ 442 (void) shutdownhook_establish(tl_shutdown, ifp); 443 444 /* 445 * Initialize our media structures and probe the MII. 446 * 447 * Note that we don't care about the media instance. We 448 * are expecting to have multiple PHYs on the 10/100 cards, 449 * and on those cards we exclude the internal PHY from providing 450 * 10baseT. By ignoring the instance, it allows us to not have 451 * to specify it on the command line when switching media. 452 */ 453 sc->tl_mii.mii_ifp = ifp; 454 sc->tl_mii.mii_readreg = tl_mii_read; 455 sc->tl_mii.mii_writereg = tl_mii_write; 456 sc->tl_mii.mii_statchg = tl_statchg; 457 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 458 tl_mediastatus); 459 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 460 MII_OFFSET_ANY, 0); 461 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 462 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 463 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 464 } else 465 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 466 467 /* 468 * We can support 802.1Q VLAN-sized frames. 469 */ 470 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 471 472 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 473 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 474 ifp->if_ioctl = tl_ifioctl; 475 ifp->if_start = tl_ifstart; 476 ifp->if_watchdog = tl_ifwatchdog; 477 ifp->if_init = tl_init; 478 ifp->if_stop = tl_stop; 479 ifp->if_timer = 0; 480 IFQ_SET_READY(&ifp->if_snd); 481 if_attach(ifp); 482 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 483 } 484 485 static void 486 tl_reset(sc) 487 tl_softc_t *sc; 488 { 489 int i; 490 491 /* read stats */ 492 if (sc->tl_if.if_flags & IFF_RUNNING) { 493 callout_stop(&sc->tl_tick_ch); 494 tl_read_stats(sc); 495 } 496 /* Reset adapter */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, 498 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 499 DELAY(100000); 500 /* Disable interrupts */ 501 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 502 /* setup aregs & hash */ 503 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 504 tl_intreg_write(sc, i, 0); 505 #ifdef TLDEBUG_ADDR 506 printf("Areg & hash registers: \n"); 507 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 508 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 509 #endif 510 /* Setup NetConfig */ 511 tl_intreg_write(sc, TL_INT_NetConfig, 512 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 513 /* Bsize: accept default */ 514 /* TX commit in Acommit: accept default */ 515 /* Load Ld_tmr and Ld_thr */ 516 /* Ld_tmr = 3 */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 518 /* Ld_thr = 0 */ 519 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 520 /* Unreset MII */ 521 netsio_set(sc, TL_NETSIO_NMRST); 522 DELAY(100000); 523 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 524 } 525 526 static void tl_shutdown(v) 527 void *v; 528 { 529 tl_stop(v, 1); 530 } 531 532 static void tl_stop(ifp, disable) 533 struct ifnet *ifp; 534 int disable; 535 { 536 tl_softc_t *sc = ifp->if_softc; 537 struct Tx_list *Tx; 538 int i; 539 540 if ((ifp->if_flags & IFF_RUNNING) == 0) 541 return; 542 /* disable interrupts */ 543 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 544 /* stop TX and RX channels */ 545 TL_HR_WRITE(sc, TL_HOST_CMD, 546 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 547 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 548 DELAY(100000); 549 550 /* stop statistics reading loop, read stats */ 551 callout_stop(&sc->tl_tick_ch); 552 tl_read_stats(sc); 553 554 /* Down the MII. */ 555 mii_down(&sc->tl_mii); 556 557 /* deallocate memory allocations */ 558 if (sc->Rx_list) { 559 for (i=0; i< TL_NBUF; i++) { 560 if (sc->Rx_list[i].m) { 561 bus_dmamap_unload(sc->tl_dmatag, 562 sc->Rx_list[i].m_dmamap); 563 m_freem(sc->Rx_list[i].m); 564 } 565 bus_dmamap_destroy(sc->tl_dmatag, 566 sc->Rx_list[i].m_dmamap); 567 sc->Rx_list[i].m = NULL; 568 } 569 free(sc->Rx_list, M_DEVBUF); 570 sc->Rx_list = NULL; 571 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 572 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 573 sc->hw_Rx_list = NULL; 574 while ((Tx = sc->active_Tx) != NULL) { 575 Tx->hw_list->stat = 0; 576 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 577 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 578 m_freem(Tx->m); 579 sc->active_Tx = Tx->next; 580 Tx->next = sc->Free_Tx; 581 sc->Free_Tx = Tx; 582 } 583 sc->last_Tx = NULL; 584 free(sc->Tx_list, M_DEVBUF); 585 sc->Tx_list = NULL; 586 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 587 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 588 sc->hw_Tx_list = NULL; 589 } 590 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 591 ifp->if_timer = 0; 592 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 593 } 594 595 static void tl_restart(v) 596 void *v; 597 { 598 tl_init(v); 599 } 600 601 static int tl_init(ifp) 602 struct ifnet *ifp; 603 { 604 tl_softc_t *sc = ifp->if_softc; 605 int i, s, error; 606 char *errstring; 607 char *nullbuf; 608 609 s = splnet(); 610 /* cancel any pending IO */ 611 tl_stop(ifp, 1); 612 tl_reset(sc); 613 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 614 splx(s); 615 return 0; 616 } 617 /* Set various register to reasonable value */ 618 /* setup NetCmd in promisc mode if needed */ 619 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 620 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 621 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 622 /* Max receive size : MCLBYTES */ 623 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 624 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 625 (MCLBYTES >> 8) & 0xff); 626 627 /* init MAC addr */ 628 for (i = 0; i < ETHER_ADDR_LEN; i++) 629 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 630 /* add multicast filters */ 631 tl_addr_filter(sc); 632 #ifdef TLDEBUG_ADDR 633 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 634 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 635 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 636 #endif 637 638 /* Pre-allocate receivers mbuf, make the lists */ 639 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 640 M_NOWAIT|M_ZERO); 641 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 642 M_NOWAIT|M_ZERO); 643 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 644 errstring = "out of memory for lists"; 645 error = ENOMEM; 646 goto bad; 647 } 648 error = bus_dmamap_create(sc->tl_dmatag, 649 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 650 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 651 &sc->Rx_dmamap); 652 if (error == 0) 653 error = bus_dmamap_create(sc->tl_dmatag, 654 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 655 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 656 &sc->Tx_dmamap); 657 if (error == 0) 658 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 659 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 660 &sc->null_dmamap); 661 if (error) { 662 errstring = "can't allocate DMA maps for lists"; 663 goto bad; 664 } 665 memset(sc->ctrl, 0, PAGE_SIZE); 666 sc->hw_Rx_list = (void *)sc->ctrl; 667 sc->hw_Tx_list = 668 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 669 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 670 sizeof(struct tl_Tx_list) * TL_NBUF; 671 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 672 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 673 BUS_DMA_WAITOK); 674 if (error == 0) 675 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 676 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 677 BUS_DMA_WAITOK); 678 if (error == 0) 679 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 680 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 681 if (error) { 682 errstring = "can't DMA map DMA memory for lists"; 683 goto bad; 684 } 685 for (i=0; i< TL_NBUF; i++) { 686 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 687 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 688 &sc->Rx_list[i].m_dmamap); 689 if (error == 0) { 690 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 691 TL_NSEG, MCLBYTES, 0, 692 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 693 &sc->Tx_list[i].m_dmamap); 694 } 695 if (error) { 696 errstring = "can't allocate DMA maps for mbufs"; 697 goto bad; 698 } 699 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 700 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 701 + sizeof(struct tl_Rx_list) * i; 702 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 703 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 704 + sizeof(struct tl_Tx_list) * i; 705 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 706 errstring = "out of mbuf for receive list"; 707 error = ENOMEM; 708 goto bad; 709 } 710 if (i > 0) { /* chain the list */ 711 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 712 sc->hw_Rx_list[i - 1].fwd = 713 htole32(sc->Rx_list[i].hw_listaddr); 714 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 715 } 716 } 717 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 718 sc->Rx_list[TL_NBUF - 1].next = NULL; 719 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 720 sc->Tx_list[TL_NBUF - 1].next = NULL; 721 722 sc->active_Rx = &sc->Rx_list[0]; 723 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 724 sc->active_Tx = sc->last_Tx = NULL; 725 sc->Free_Tx = &sc->Tx_list[0]; 726 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 727 sizeof(struct tl_Rx_list) * TL_NBUF, 728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 729 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 730 sizeof(struct tl_Tx_list) * TL_NBUF, 731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 733 BUS_DMASYNC_PREWRITE); 734 735 /* set media */ 736 mii_mediachg(&sc->tl_mii); 737 738 /* start ticks calls */ 739 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 740 /* write adress of Rx list and enable interrupts */ 741 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 742 TL_HR_WRITE(sc, TL_HOST_CMD, 743 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 744 sc->tl_if.if_flags |= IFF_RUNNING; 745 sc->tl_if.if_flags &= ~IFF_OACTIVE; 746 return 0; 747 bad: 748 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 749 splx(s); 750 return error; 751 } 752 753 754 static u_int32_t 755 tl_intreg_read(sc, reg) 756 tl_softc_t *sc; 757 u_int32_t reg; 758 { 759 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 760 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 761 } 762 763 static u_int8_t 764 tl_intreg_read_byte(sc, reg) 765 tl_softc_t *sc; 766 u_int32_t reg; 767 { 768 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 769 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 770 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 771 } 772 773 static void 774 tl_intreg_write(sc, reg, val) 775 tl_softc_t *sc; 776 u_int32_t reg; 777 u_int32_t val; 778 { 779 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 780 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 781 } 782 783 static void 784 tl_intreg_write_byte(sc, reg, val) 785 tl_softc_t *sc; 786 u_int32_t reg; 787 u_int8_t val; 788 { 789 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 790 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 791 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 792 } 793 794 void 795 tl_mii_sync(sc) 796 struct tl_softc *sc; 797 { 798 int i; 799 800 netsio_clr(sc, TL_NETSIO_MTXEN); 801 for (i = 0; i < 32; i++) { 802 netsio_clr(sc, TL_NETSIO_MCLK); 803 netsio_set(sc, TL_NETSIO_MCLK); 804 } 805 } 806 807 void 808 tl_mii_sendbits(sc, data, nbits) 809 struct tl_softc *sc; 810 u_int32_t data; 811 int nbits; 812 { 813 int i; 814 815 netsio_set(sc, TL_NETSIO_MTXEN); 816 for (i = 1 << (nbits - 1); i; i = i >> 1) { 817 netsio_clr(sc, TL_NETSIO_MCLK); 818 netsio_read(sc, TL_NETSIO_MCLK); 819 if (data & i) 820 netsio_set(sc, TL_NETSIO_MDATA); 821 else 822 netsio_clr(sc, TL_NETSIO_MDATA); 823 netsio_set(sc, TL_NETSIO_MCLK); 824 netsio_read(sc, TL_NETSIO_MCLK); 825 } 826 } 827 828 int 829 tl_mii_read(self, phy, reg) 830 struct device *self; 831 int phy, reg; 832 { 833 struct tl_softc *sc = (struct tl_softc *)self; 834 int val = 0, i, err; 835 836 /* 837 * Read the PHY register by manually driving the MII control lines. 838 */ 839 840 tl_mii_sync(sc); 841 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 842 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 843 tl_mii_sendbits(sc, phy, 5); 844 tl_mii_sendbits(sc, reg, 5); 845 846 netsio_clr(sc, TL_NETSIO_MTXEN); 847 netsio_clr(sc, TL_NETSIO_MCLK); 848 netsio_set(sc, TL_NETSIO_MCLK); 849 netsio_clr(sc, TL_NETSIO_MCLK); 850 851 err = netsio_read(sc, TL_NETSIO_MDATA); 852 netsio_set(sc, TL_NETSIO_MCLK); 853 854 /* Even if an error occurs, must still clock out the cycle. */ 855 for (i = 0; i < 16; i++) { 856 val <<= 1; 857 netsio_clr(sc, TL_NETSIO_MCLK); 858 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 859 val |= 1; 860 netsio_set(sc, TL_NETSIO_MCLK); 861 } 862 netsio_clr(sc, TL_NETSIO_MCLK); 863 netsio_set(sc, TL_NETSIO_MCLK); 864 865 return (err ? 0 : val); 866 } 867 868 void 869 tl_mii_write(self, phy, reg, val) 870 struct device *self; 871 int phy, reg, val; 872 { 873 struct tl_softc *sc = (struct tl_softc *)self; 874 875 /* 876 * Write the PHY register by manually driving the MII control lines. 877 */ 878 879 tl_mii_sync(sc); 880 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 881 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 882 tl_mii_sendbits(sc, phy, 5); 883 tl_mii_sendbits(sc, reg, 5); 884 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 885 tl_mii_sendbits(sc, val, 16); 886 887 netsio_clr(sc, TL_NETSIO_MCLK); 888 netsio_set(sc, TL_NETSIO_MCLK); 889 } 890 891 void 892 tl_statchg(self) 893 struct device *self; 894 { 895 tl_softc_t *sc = (struct tl_softc *)self; 896 u_int32_t reg; 897 898 #ifdef TLDEBUG 899 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 900 #endif 901 902 /* 903 * We must keep the ThunderLAN and the PHY in sync as 904 * to the status of full-duplex! 905 */ 906 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 907 if (sc->tl_mii.mii_media_active & IFM_FDX) 908 reg |= TL_NETCOMMAND_DUPLEX; 909 else 910 reg &= ~TL_NETCOMMAND_DUPLEX; 911 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 912 } 913 914 /********** I2C glue **********/ 915 916 static int 917 tl_i2c_acquire_bus(void *cookie, int flags) 918 { 919 920 /* private bus */ 921 return (0); 922 } 923 924 static void 925 tl_i2c_release_bus(void *cookie, int flags) 926 { 927 928 /* private bus */ 929 } 930 931 static int 932 tl_i2c_send_start(void *cookie, int flags) 933 { 934 935 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 936 } 937 938 static int 939 tl_i2c_send_stop(void *cookie, int flags) 940 { 941 942 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 943 } 944 945 static int 946 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 947 { 948 949 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 950 } 951 952 static int 953 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 954 { 955 956 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 957 } 958 959 static int 960 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 961 { 962 963 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 964 } 965 966 /********** I2C bit-bang glue **********/ 967 968 static void 969 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 970 { 971 struct tl_softc *sc = cookie; 972 uint8_t reg; 973 974 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 975 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 976 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 977 } 978 979 static void 980 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 981 { 982 struct tl_softc *sc = cookie; 983 uint8_t reg; 984 985 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 986 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 987 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 988 } 989 990 static uint32_t 991 tl_i2cbb_read(void *cookie) 992 { 993 994 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 995 } 996 997 /********** End of I2C stuff **********/ 998 999 static int 1000 tl_intr(v) 1001 void *v; 1002 { 1003 tl_softc_t *sc = v; 1004 struct ifnet *ifp = &sc->tl_if; 1005 struct Rx_list *Rx; 1006 struct Tx_list *Tx; 1007 struct mbuf *m; 1008 u_int32_t int_type, int_reg; 1009 int ack = 0; 1010 int size; 1011 1012 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1013 int_type = int_reg & TL_INTR_MASK; 1014 if (int_type == 0) 1015 return 0; 1016 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1017 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1018 int_type, int_reg); 1019 #endif 1020 /* disable interrupts */ 1021 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1022 switch(int_type & TL_INTR_MASK) { 1023 case TL_INTR_RxEOF: 1024 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1025 sizeof(struct tl_Rx_list) * TL_NBUF, 1026 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1027 while(le32toh(sc->active_Rx->hw_list->stat) & 1028 TL_RX_CSTAT_CPLT) { 1029 /* dequeue and requeue at end of list */ 1030 ack++; 1031 Rx = sc->active_Rx; 1032 sc->active_Rx = Rx->next; 1033 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1034 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1035 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1036 m = Rx->m; 1037 size = le32toh(Rx->hw_list->stat) >> 16; 1038 #ifdef TLDEBUG_RX 1039 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1040 Rx, size); 1041 #endif 1042 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1043 /* 1044 * No new mbuf, reuse the same. This means 1045 * that this packet 1046 * is lost 1047 */ 1048 m = NULL; 1049 #ifdef TL_PRIV_STATS 1050 sc->ierr_nomem++; 1051 #endif 1052 #ifdef TLDEBUG 1053 printf("%s: out of mbuf, lost input packet\n", 1054 sc->sc_dev.dv_xname); 1055 #endif 1056 } 1057 Rx->next = NULL; 1058 Rx->hw_list->fwd = 0; 1059 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1060 sc->last_Rx->next = Rx; 1061 sc->last_Rx = Rx; 1062 1063 /* deliver packet */ 1064 if (m) { 1065 if (size < sizeof(struct ether_header)) { 1066 m_freem(m); 1067 continue; 1068 } 1069 m->m_pkthdr.rcvif = ifp; 1070 m->m_pkthdr.len = m->m_len = size; 1071 #ifdef TLDEBUG_RX 1072 { struct ether_header *eh = 1073 mtod(m, struct ether_header *); 1074 printf("tl_intr: Rx packet:\n"); 1075 ether_printheader(eh); } 1076 #endif 1077 #if NBPFILTER > 0 1078 if (ifp->if_bpf) 1079 bpf_mtap(ifp->if_bpf, m); 1080 #endif /* NBPFILTER > 0 */ 1081 (*ifp->if_input)(ifp, m); 1082 } 1083 } 1084 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1085 sizeof(struct tl_Rx_list) * TL_NBUF, 1086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1087 #ifdef TLDEBUG_RX 1088 printf("TL_INTR_RxEOF: ack %d\n", ack); 1089 #else 1090 if (ack == 0) { 1091 printf("%s: EOF intr without anything to read !\n", 1092 sc->sc_dev.dv_xname); 1093 tl_reset(sc); 1094 /* shedule reinit of the board */ 1095 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1096 return(1); 1097 } 1098 #endif 1099 break; 1100 case TL_INTR_RxEOC: 1101 ack++; 1102 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1103 sizeof(struct tl_Rx_list) * TL_NBUF, 1104 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1105 #ifdef TLDEBUG_RX 1106 printf("TL_INTR_RxEOC: ack %d\n", ack); 1107 #endif 1108 #ifdef DIAGNOSTIC 1109 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1110 printf("%s: Rx EOC interrupt and active Tx list not " 1111 "cleared\n", sc->sc_dev.dv_xname); 1112 return 0; 1113 } else 1114 #endif 1115 { 1116 /* 1117 * write adress of Rx list and send Rx GO command, ack 1118 * interrupt and enable interrupts in one command 1119 */ 1120 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1121 TL_HR_WRITE(sc, TL_HOST_CMD, 1122 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1123 HOST_CMD_ACK | HOST_CMD_IntOn); 1124 return 1; 1125 } 1126 case TL_INTR_TxEOF: 1127 case TL_INTR_TxEOC: 1128 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1129 sizeof(struct tl_Tx_list) * TL_NBUF, 1130 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1131 while ((Tx = sc->active_Tx) != NULL) { 1132 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1133 break; 1134 ack++; 1135 #ifdef TLDEBUG_TX 1136 printf("TL_INTR_TxEOC: list 0x%x done\n", 1137 (int)Tx->hw_listaddr); 1138 #endif 1139 Tx->hw_list->stat = 0; 1140 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1141 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1142 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1143 m_freem(Tx->m); 1144 Tx->m = NULL; 1145 sc->active_Tx = Tx->next; 1146 if (sc->active_Tx == NULL) 1147 sc->last_Tx = NULL; 1148 Tx->next = sc->Free_Tx; 1149 sc->Free_Tx = Tx; 1150 } 1151 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1152 sizeof(struct tl_Tx_list) * TL_NBUF, 1153 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1154 /* if this was an EOC, ACK immediatly */ 1155 if (ack) 1156 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1157 if (int_type == TL_INTR_TxEOC) { 1158 #ifdef TLDEBUG_TX 1159 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1160 ack); 1161 #endif 1162 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1163 HOST_CMD_ACK | HOST_CMD_IntOn); 1164 if ( sc->active_Tx != NULL) { 1165 /* needs a Tx go command */ 1166 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1167 sc->active_Tx->hw_listaddr); 1168 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1169 } 1170 sc->tl_if.if_timer = 0; 1171 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1172 tl_ifstart(&sc->tl_if); 1173 return 1; 1174 } 1175 #ifdef TLDEBUG 1176 else { 1177 printf("TL_INTR_TxEOF: ack %d\n", ack); 1178 } 1179 #endif 1180 sc->tl_if.if_timer = 0; 1181 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1182 tl_ifstart(&sc->tl_if); 1183 break; 1184 case TL_INTR_Stat: 1185 ack++; 1186 #ifdef TLDEBUG 1187 printf("TL_INTR_Stat: ack %d\n", ack); 1188 #endif 1189 tl_read_stats(sc); 1190 break; 1191 case TL_INTR_Adc: 1192 if (int_reg & TL_INTVec_MASK) { 1193 /* adapter check conditions */ 1194 printf("%s: check condition, intvect=0x%x, " 1195 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1196 int_reg & TL_INTVec_MASK, 1197 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1198 tl_reset(sc); 1199 /* shedule reinit of the board */ 1200 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1201 return(1); 1202 } else { 1203 u_int8_t netstat; 1204 /* Network status */ 1205 netstat = 1206 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1207 printf("%s: network status, NetSts=%x\n", 1208 sc->sc_dev.dv_xname, netstat); 1209 /* Ack interrupts */ 1210 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1211 netstat); 1212 ack++; 1213 } 1214 break; 1215 default: 1216 printf("%s: unhandled interrupt code %x!\n", 1217 sc->sc_dev.dv_xname, int_type); 1218 ack++; 1219 } 1220 1221 if (ack) { 1222 /* Ack the interrupt and enable interrupts */ 1223 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1224 HOST_CMD_IntOn); 1225 return 1; 1226 } 1227 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1228 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1229 return 0; 1230 } 1231 1232 static int 1233 tl_ifioctl(ifp, cmd, data) 1234 struct ifnet *ifp; 1235 ioctl_cmd_t cmd; 1236 caddr_t data; 1237 { 1238 struct tl_softc *sc = ifp->if_softc; 1239 struct ifreq *ifr = (struct ifreq *)data; 1240 int s, error; 1241 1242 s = splnet(); 1243 switch(cmd) { 1244 case SIOCSIFMEDIA: 1245 case SIOCGIFMEDIA: 1246 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1247 break; 1248 default: 1249 error = ether_ioctl(ifp, cmd, data); 1250 if (error == ENETRESET) { 1251 tl_addr_filter(sc); 1252 error = 0; 1253 } 1254 } 1255 splx(s); 1256 return error; 1257 } 1258 1259 static void 1260 tl_ifstart(ifp) 1261 struct ifnet *ifp; 1262 { 1263 tl_softc_t *sc = ifp->if_softc; 1264 struct mbuf *mb_head; 1265 struct Tx_list *Tx; 1266 int segment, size; 1267 int again, error; 1268 1269 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1270 return; 1271 txloop: 1272 /* If we don't have more space ... */ 1273 if (sc->Free_Tx == NULL) { 1274 #ifdef TLDEBUG 1275 printf("tl_ifstart: No free TX list\n"); 1276 #endif 1277 sc->tl_if.if_flags |= IFF_OACTIVE; 1278 return; 1279 } 1280 /* Grab a paquet for output */ 1281 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1282 if (mb_head == NULL) { 1283 #ifdef TLDEBUG_TX 1284 printf("tl_ifstart: nothing to send\n"); 1285 #endif 1286 return; 1287 } 1288 Tx = sc->Free_Tx; 1289 sc->Free_Tx = Tx->next; 1290 Tx->next = NULL; 1291 again = 0; 1292 /* 1293 * Go through each of the mbufs in the chain and initialize 1294 * the transmit list descriptors with the physical address 1295 * and size of the mbuf. 1296 */ 1297 tbdinit: 1298 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1299 Tx->m = mb_head; 1300 size = mb_head->m_pkthdr.len; 1301 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1302 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1303 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1304 struct mbuf *mn; 1305 /* 1306 * We ran out of segments, or we will. We have to recopy this 1307 * mbuf chain first. 1308 */ 1309 if (error == 0) 1310 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1311 if (again) { 1312 /* already copyed, can't do much more */ 1313 m_freem(mb_head); 1314 goto bad; 1315 } 1316 again = 1; 1317 #ifdef TLDEBUG_TX 1318 printf("tl_ifstart: need to copy mbuf\n"); 1319 #endif 1320 #ifdef TL_PRIV_STATS 1321 sc->oerr_mcopy++; 1322 #endif 1323 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1324 if (mn == NULL) { 1325 m_freem(mb_head); 1326 goto bad; 1327 } 1328 if (mb_head->m_pkthdr.len > MHLEN) { 1329 MCLGET(mn, M_DONTWAIT); 1330 if ((mn->m_flags & M_EXT) == 0) { 1331 m_freem(mn); 1332 m_freem(mb_head); 1333 goto bad; 1334 } 1335 } 1336 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1337 mtod(mn, caddr_t)); 1338 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1339 m_freem(mb_head); 1340 mb_head = mn; 1341 goto tbdinit; 1342 } 1343 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1344 Tx->hw_list->seg[segment].data_addr = 1345 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1346 Tx->hw_list->seg[segment].data_count = 1347 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1348 } 1349 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1350 Tx->m_dmamap->dm_mapsize, 1351 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1352 /* We are at end of mbuf chain. check the size and 1353 * see if it needs to be extended 1354 */ 1355 if (size < ETHER_MIN_TX) { 1356 #ifdef DIAGNOSTIC 1357 if (segment >= TL_NSEG) { 1358 panic("tl_ifstart: to much segmets (%d)", segment); 1359 } 1360 #endif 1361 /* 1362 * add the nullbuf in the seg 1363 */ 1364 Tx->hw_list->seg[segment].data_count = 1365 htole32(ETHER_MIN_TX - size); 1366 Tx->hw_list->seg[segment].data_addr = 1367 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1368 size = ETHER_MIN_TX; 1369 segment++; 1370 } 1371 /* The list is done, finish the list init */ 1372 Tx->hw_list->seg[segment - 1].data_count |= 1373 htole32(TL_LAST_SEG); 1374 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1375 #ifdef TLDEBUG_TX 1376 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1377 le32toh(Tx->hw_list->stat)); 1378 #if 0 1379 for(segment = 0; segment < TL_NSEG; segment++) { 1380 printf(" seg %d addr 0x%x len 0x%x\n", 1381 segment, 1382 le32toh(Tx->hw_list->seg[segment].data_addr), 1383 le32toh(Tx->hw_list->seg[segment].data_count)); 1384 } 1385 #endif 1386 #endif 1387 if (sc->active_Tx == NULL) { 1388 sc->active_Tx = sc->last_Tx = Tx; 1389 #ifdef TLDEBUG_TX 1390 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1391 (int)Tx->hw_listaddr); 1392 #endif 1393 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1394 sizeof(struct tl_Tx_list) * TL_NBUF, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1397 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1398 } else { 1399 #ifdef TLDEBUG_TX 1400 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1401 (int)Tx->hw_listaddr); 1402 #endif 1403 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1404 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1405 sizeof(struct tl_Tx_list) * TL_NBUF, 1406 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1407 sc->last_Tx->next = Tx; 1408 sc->last_Tx = Tx; 1409 #ifdef DIAGNOSTIC 1410 if (sc->last_Tx->hw_list->fwd & 0x7) 1411 printf("%s: physical addr 0x%x of list not properly " 1412 "aligned\n", 1413 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1414 #endif 1415 } 1416 #if NBPFILTER > 0 1417 /* Pass packet to bpf if there is a listener */ 1418 if (ifp->if_bpf) 1419 bpf_mtap(ifp->if_bpf, mb_head); 1420 #endif 1421 /* 1422 * Set a 5 second timer just in case we don't hear from the card again. 1423 */ 1424 ifp->if_timer = 5; 1425 goto txloop; 1426 bad: 1427 #ifdef TLDEBUG 1428 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1429 #endif 1430 Tx->next = sc->Free_Tx; 1431 sc->Free_Tx = Tx; 1432 return; 1433 } 1434 1435 static void 1436 tl_ifwatchdog(ifp) 1437 struct ifnet *ifp; 1438 { 1439 tl_softc_t *sc = ifp->if_softc; 1440 1441 if ((ifp->if_flags & IFF_RUNNING) == 0) 1442 return; 1443 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1444 ifp->if_oerrors++; 1445 tl_init(ifp); 1446 } 1447 1448 static int 1449 tl_mediachange(ifp) 1450 struct ifnet *ifp; 1451 { 1452 1453 if (ifp->if_flags & IFF_UP) 1454 tl_init(ifp); 1455 return (0); 1456 } 1457 1458 static void 1459 tl_mediastatus(ifp, ifmr) 1460 struct ifnet *ifp; 1461 struct ifmediareq *ifmr; 1462 { 1463 tl_softc_t *sc = ifp->if_softc; 1464 1465 mii_pollstat(&sc->tl_mii); 1466 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1467 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1468 } 1469 1470 static int tl_add_RxBuff(sc, Rx, oldm) 1471 tl_softc_t *sc; 1472 struct Rx_list *Rx; 1473 struct mbuf *oldm; 1474 { 1475 struct mbuf *m; 1476 int error; 1477 1478 MGETHDR(m, M_DONTWAIT, MT_DATA); 1479 if (m != NULL) { 1480 MCLGET(m, M_DONTWAIT); 1481 if ((m->m_flags & M_EXT) == 0) { 1482 m_freem(m); 1483 if (oldm == NULL) 1484 return 0; 1485 m = oldm; 1486 m->m_data = m->m_ext.ext_buf; 1487 } 1488 } else { 1489 if (oldm == NULL) 1490 return 0; 1491 m = oldm; 1492 m->m_data = m->m_ext.ext_buf; 1493 } 1494 1495 /* (re)init the Rx_list struct */ 1496 1497 Rx->m = m; 1498 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1499 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1500 printf("%s: bus_dmamap_load() failed (error %d) for " 1501 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1502 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1503 m_freem(m); 1504 Rx->m = NULL; 1505 return 0; 1506 } 1507 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1508 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1509 /* 1510 * Move the data pointer up so that the incoming data packet 1511 * will be 32-bit aligned. 1512 */ 1513 m->m_data += 2; 1514 1515 Rx->hw_list->stat = 1516 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1517 Rx->hw_list->seg.data_count = 1518 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1519 Rx->hw_list->seg.data_addr = 1520 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1521 return (m != oldm); 1522 } 1523 1524 static void tl_ticks(v) 1525 void *v; 1526 { 1527 tl_softc_t *sc = v; 1528 1529 tl_read_stats(sc); 1530 1531 /* Tick the MII. */ 1532 mii_tick(&sc->tl_mii); 1533 1534 /* read statistics every seconds */ 1535 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1536 } 1537 1538 static void 1539 tl_read_stats(sc) 1540 tl_softc_t *sc; 1541 { 1542 u_int32_t reg; 1543 int ierr_overr; 1544 int ierr_code; 1545 int ierr_crc; 1546 int oerr_underr; 1547 int oerr_deffered; 1548 int oerr_coll; 1549 int oerr_multicoll; 1550 int oerr_exesscoll; 1551 int oerr_latecoll; 1552 int oerr_carrloss; 1553 struct ifnet *ifp = &sc->tl_if; 1554 1555 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1556 ifp->if_opackets += reg & 0x00ffffff; 1557 oerr_underr = reg >> 24; 1558 1559 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1560 ifp->if_ipackets += reg & 0x00ffffff; 1561 ierr_overr = reg >> 24; 1562 1563 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1564 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1565 ierr_code = (reg & TL_FERR_CODE) >> 24; 1566 oerr_deffered = (reg & TL_FERR_DEF); 1567 1568 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1569 oerr_multicoll = (reg & TL_COL_MULTI); 1570 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1571 1572 reg = tl_intreg_read(sc, TL_INT_LERR); 1573 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1574 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1575 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1576 1577 1578 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1579 oerr_carrloss; 1580 ifp->if_collisions += oerr_coll + oerr_multicoll; 1581 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1582 1583 if (ierr_overr) 1584 printf("%s: receiver ring buffer overrun\n", 1585 sc->sc_dev.dv_xname); 1586 if (oerr_underr) 1587 printf("%s: transmit buffer underrun\n", 1588 sc->sc_dev.dv_xname); 1589 #ifdef TL_PRIV_STATS 1590 sc->ierr_overr += ierr_overr; 1591 sc->ierr_code += ierr_code; 1592 sc->ierr_crc += ierr_crc; 1593 sc->oerr_underr += oerr_underr; 1594 sc->oerr_deffered += oerr_deffered; 1595 sc->oerr_coll += oerr_coll; 1596 sc->oerr_multicoll += oerr_multicoll; 1597 sc->oerr_exesscoll += oerr_exesscoll; 1598 sc->oerr_latecoll += oerr_latecoll; 1599 sc->oerr_carrloss += oerr_carrloss; 1600 #endif 1601 } 1602 1603 static void tl_addr_filter(sc) 1604 tl_softc_t *sc; 1605 { 1606 struct ether_multistep step; 1607 struct ether_multi *enm; 1608 u_int32_t hash[2] = {0, 0}; 1609 int i; 1610 1611 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1612 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1613 while (enm != NULL) { 1614 #ifdef TLDEBUG 1615 printf("tl_addr_filter: addrs %s %s\n", 1616 ether_sprintf(enm->enm_addrlo), 1617 ether_sprintf(enm->enm_addrhi)); 1618 #endif 1619 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1620 i = tl_multicast_hash(enm->enm_addrlo); 1621 hash[i/32] |= 1 << (i%32); 1622 } else { 1623 hash[0] = hash[1] = 0xffffffff; 1624 sc->tl_if.if_flags |= IFF_ALLMULTI; 1625 break; 1626 } 1627 ETHER_NEXT_MULTI(step, enm); 1628 } 1629 #ifdef TLDEBUG 1630 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1631 #endif 1632 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1633 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1634 } 1635 1636 static int tl_multicast_hash(a) 1637 u_int8_t *a; 1638 { 1639 int hash; 1640 1641 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1642 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1643 1644 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1645 DA(a,36), DA(a,42)); 1646 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1647 DA(a,37), DA(a,43)) << 1; 1648 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1649 DA(a,38), DA(a,44)) << 2; 1650 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1651 DA(a,39), DA(a,45)) << 3; 1652 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1653 DA(a,40), DA(a,46)) << 4; 1654 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1655 DA(a,41), DA(a,47)) << 5; 1656 1657 return hash; 1658 } 1659 1660 #if defined(TLDEBUG_RX) 1661 void 1662 ether_printheader(eh) 1663 struct ether_header *eh; 1664 { 1665 u_char *c = (char*)eh; 1666 int i; 1667 for (i=0; i<sizeof(struct ether_header); i++) 1668 printf("%x ", (u_int)c[i]); 1669 printf("\n"); 1670 } 1671 #endif 1672
Indexes created Mon Sep 22 21:09:42 GMT 2025