if_tl.c revision 1.68
1 /* $NetBSD: if_tl.c,v 1.68 2005/02/04 02:10:45 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.68 2005/02/04 02:10:45 perry Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #include "rnd.h" 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #ifdef INET 83 #include <netinet/in.h> 84 #include <netinet/in_systm.h> 85 #include <netinet/in_var.h> 86 #include <netinet/ip.h> 87 #endif 88 89 #ifdef NS 90 #include <netns/ns.h> 91 #include <netns/ns_if.h> 92 #endif 93 94 #if defined(__NetBSD__) 95 #include <net/if_ether.h> 96 #include <uvm/uvm_extern.h> 97 #if defined(INET) 98 #include <netinet/if_inarp.h> 99 #endif 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/i2c/i2cvar.h> 109 #include <dev/i2c/i2c_bitbang.h> 110 #include <dev/i2c/at24cxxvar.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 115 #include <dev/mii/tlphyvar.h> 116 117 #include <dev/pci/if_tlregs.h> 118 #include <dev/pci/if_tlvar.h> 119 #endif /* __NetBSD__ */ 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 32 124 #endif 125 126 static int tl_pci_match(struct device *, struct cfdata *, void *); 127 static void tl_pci_attach(struct device *, struct device *, void *); 128 static int tl_intr(void *); 129 130 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, caddr_t); 131 static int tl_mediachange(struct ifnet *); 132 static void tl_mediastatus(struct ifnet *, struct ifmediareq *); 133 static void tl_ifwatchdog(struct ifnet *); 134 static void tl_shutdown(void*); 135 136 static void tl_ifstart(struct ifnet *); 137 static void tl_reset(tl_softc_t*); 138 static int tl_init(struct ifnet *); 139 static void tl_stop(struct ifnet *, int); 140 static void tl_restart(void *); 141 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 142 static void tl_read_stats(tl_softc_t*); 143 static void tl_ticks(void*); 144 static int tl_multicast_hash(u_int8_t*); 145 static void tl_addr_filter(tl_softc_t*); 146 147 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 148 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 149 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 150 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 151 152 void tl_mii_sync(struct tl_softc *); 153 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 154 155 156 #if defined(TLDEBUG_RX) 157 static void ether_printheader(struct ether_header*); 158 #endif 159 160 int tl_mii_read(struct device *, int, int); 161 void tl_mii_write(struct device *, int, int, int); 162 163 void tl_statchg(struct device *); 164 165 /* I2C glue */ 166 static int tl_i2c_acquire_bus(void *, int); 167 static void tl_i2c_release_bus(void *, int); 168 static int tl_i2c_send_start(void *, int); 169 static int tl_i2c_send_stop(void *, int); 170 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 171 static int tl_i2c_read_byte(void *, uint8_t *, int); 172 static int tl_i2c_write_byte(void *, uint8_t, int); 173 174 /* I2C bit-bang glue */ 175 static void tl_i2cbb_set_bits(void *, uint32_t); 176 static void tl_i2cbb_set_dir(void *, uint32_t); 177 static uint32_t tl_i2cbb_read(void *); 178 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 179 tl_i2cbb_set_bits, 180 tl_i2cbb_set_dir, 181 tl_i2cbb_read, 182 { 183 TL_NETSIO_EDATA, /* SDA */ 184 TL_NETSIO_ECLOCK, /* SCL */ 185 TL_NETSIO_ETXEN, /* SDA is output */ 186 0, /* SDA is input */ 187 } 188 }; 189 190 static __inline void netsio_clr(tl_softc_t*, u_int8_t); 191 static __inline void netsio_set(tl_softc_t*, u_int8_t); 192 static __inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 193 static __inline void netsio_clr(sc, bits) 194 tl_softc_t* sc; 195 u_int8_t bits; 196 { 197 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 198 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 199 } 200 static __inline void netsio_set(sc, bits) 201 tl_softc_t* sc; 202 u_int8_t bits; 203 { 204 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 205 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 206 } 207 static __inline u_int8_t netsio_read(sc, bits) 208 tl_softc_t* sc; 209 u_int8_t bits; 210 { 211 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 212 } 213 214 CFATTACH_DECL(tl, sizeof(tl_softc_t), 215 tl_pci_match, tl_pci_attach, NULL, NULL); 216 217 const struct tl_product_desc tl_compaq_products[] = { 218 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 219 "Compaq Netelligent 10/100 TX" }, 220 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 221 "Integrated Compaq Netelligent 10/100 TX" }, 222 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 223 "Compaq Netelligent 10 T" }, 224 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 225 "Compaq Integrated NetFlex 3/P" }, 226 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 227 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 228 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 229 "Compaq Dual Port Netelligent 10/100 TX" }, 230 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 231 "Compaq Deskpro 4000 5233MMX" }, 232 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 233 "Compaq NetFlex 3/P w/ BNC" }, 234 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 235 "Compaq NetFlex 3/P" }, 236 { 0, 0, NULL }, 237 }; 238 239 const struct tl_product_desc tl_ti_products[] = { 240 /* 241 * Built-in Ethernet on the TI TravelMate 5000 242 * docking station; better product description? 243 */ 244 { PCI_PRODUCT_TI_TLAN, 0, 245 "Texas Instruments ThunderLAN" }, 246 { 0, 0, NULL }, 247 }; 248 249 struct tl_vendor_desc { 250 u_int32_t tv_vendor; 251 const struct tl_product_desc *tv_products; 252 }; 253 254 const struct tl_vendor_desc tl_vendors[] = { 255 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 256 { PCI_VENDOR_TI, tl_ti_products }, 257 { 0, NULL }, 258 }; 259 260 const struct tl_product_desc *tl_lookup_product(u_int32_t); 261 262 const struct tl_product_desc * 263 tl_lookup_product(id) 264 u_int32_t id; 265 { 266 const struct tl_product_desc *tp; 267 const struct tl_vendor_desc *tv; 268 269 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 270 if (PCI_VENDOR(id) == tv->tv_vendor) 271 break; 272 273 if ((tp = tv->tv_products) == NULL) 274 return (NULL); 275 276 for (; tp->tp_desc != NULL; tp++) 277 if (PCI_PRODUCT(id) == tp->tp_product) 278 break; 279 280 if (tp->tp_desc == NULL) 281 return (NULL); 282 283 return (tp); 284 } 285 286 static int 287 tl_pci_match(parent, match, aux) 288 struct device *parent; 289 struct cfdata *match; 290 void *aux; 291 { 292 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 293 294 if (tl_lookup_product(pa->pa_id) != NULL) 295 return (1); 296 297 return (0); 298 } 299 300 static void 301 tl_pci_attach(parent, self, aux) 302 struct device * parent; 303 struct device * self; 304 void * aux; 305 { 306 tl_softc_t *sc = (tl_softc_t *)self; 307 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 308 const struct tl_product_desc *tp; 309 struct ifnet * const ifp = &sc->tl_if; 310 bus_space_tag_t iot, memt; 311 bus_space_handle_t ioh, memh; 312 pci_intr_handle_t intrhandle; 313 const char *intrstr; 314 int ioh_valid, memh_valid; 315 int reg_io, reg_mem; 316 pcireg_t reg10, reg14; 317 pcireg_t csr; 318 319 printf("\n"); 320 321 callout_init(&sc->tl_tick_ch); 322 callout_init(&sc->tl_restart_ch); 323 324 tp = tl_lookup_product(pa->pa_id); 325 if (tp == NULL) 326 panic("tl_pci_attach: impossible"); 327 sc->tl_product = tp; 328 329 /* 330 * Map the card space. First we have to find the I/O and MEM 331 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 332 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 333 * The ThunderLAN manual is not consistent about this either (there 334 * are both cases in code examples). 335 */ 336 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 337 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 338 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 339 reg_io = 0x10; 340 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 341 reg_io = 0x14; 342 else 343 reg_io = 0; 344 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 345 reg_mem = 0x10; 346 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 347 reg_mem = 0x14; 348 else 349 reg_mem = 0; 350 351 if (reg_io != 0) 352 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 353 0, &iot, &ioh, NULL, NULL) == 0); 354 else 355 ioh_valid = 0; 356 if (reg_mem != 0) 357 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 358 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 359 0, &memt, &memh, NULL, NULL) == 0); 360 else 361 memh_valid = 0; 362 363 if (ioh_valid) { 364 sc->tl_bustag = iot; 365 sc->tl_bushandle = ioh; 366 } else if (memh_valid) { 367 sc->tl_bustag = memt; 368 sc->tl_bushandle = memh; 369 } else { 370 printf("%s: unable to map device registers\n", 371 sc->sc_dev.dv_xname); 372 return; 373 } 374 sc->tl_dmatag = pa->pa_dmat; 375 376 /* Enable the device. */ 377 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 378 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 379 csr | PCI_COMMAND_MASTER_ENABLE); 380 381 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 382 383 tl_reset(sc); 384 385 /* fill in the i2c tag */ 386 sc->sc_i2c.ic_cookie = sc; 387 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 388 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 389 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 390 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 391 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 392 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 393 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 394 395 #ifdef TLDEBUG 396 printf("default values of INTreg: 0x%x\n", 397 tl_intreg_read(sc, TL_INT_Defaults)); 398 #endif 399 400 /* read mac addr */ 401 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 402 sc->tl_enaddr, ETHER_ADDR_LEN)) { 403 printf("%s: error reading Ethernet address\n", 404 sc->sc_dev.dv_xname); 405 return; 406 } 407 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 408 ether_sprintf(sc->tl_enaddr)); 409 410 /* Map and establish interrupts */ 411 if (pci_intr_map(pa, &intrhandle)) { 412 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 413 return; 414 } 415 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 416 sc->tl_if.if_softc = sc; 417 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 418 tl_intr, sc); 419 if (sc->tl_ih == NULL) { 420 printf("%s: couldn't establish interrupt", 421 sc->sc_dev.dv_xname); 422 if (intrstr != NULL) 423 printf(" at %s", intrstr); 424 printf("\n"); 425 return; 426 } 427 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 428 429 /* init these pointers, so that tl_shutdown won't try to read them */ 430 sc->Rx_list = NULL; 431 sc->Tx_list = NULL; 432 433 /* allocate DMA-safe memory for control structs */ 434 if (bus_dmamem_alloc(sc->tl_dmatag, 435 PAGE_SIZE, 0, PAGE_SIZE, 436 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 437 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 438 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 439 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 440 printf("%s: can't allocate DMA memory for lists\n", 441 sc->sc_dev.dv_xname); 442 return; 443 } 444 /* 445 * Add shutdown hook so that DMA is disabled prior to reboot. Not 446 * doing 447 * reboot before the driver initializes. 448 */ 449 (void) shutdownhook_establish(tl_shutdown, ifp); 450 451 /* 452 * Initialize our media structures and probe the MII. 453 * 454 * Note that we don't care about the media instance. We 455 * are expecting to have multiple PHYs on the 10/100 cards, 456 * and on those cards we exclude the internal PHY from providing 457 * 10baseT. By ignoring the instance, it allows us to not have 458 * to specify it on the command line when switching media. 459 */ 460 sc->tl_mii.mii_ifp = ifp; 461 sc->tl_mii.mii_readreg = tl_mii_read; 462 sc->tl_mii.mii_writereg = tl_mii_write; 463 sc->tl_mii.mii_statchg = tl_statchg; 464 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 465 tl_mediastatus); 466 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 467 MII_OFFSET_ANY, 0); 468 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 469 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 470 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 471 } else 472 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 473 474 /* 475 * We can support 802.1Q VLAN-sized frames. 476 */ 477 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 478 479 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 480 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 481 ifp->if_ioctl = tl_ifioctl; 482 ifp->if_start = tl_ifstart; 483 ifp->if_watchdog = tl_ifwatchdog; 484 ifp->if_init = tl_init; 485 ifp->if_stop = tl_stop; 486 ifp->if_timer = 0; 487 IFQ_SET_READY(&ifp->if_snd); 488 if_attach(ifp); 489 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 490 491 #if NRND > 0 492 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 493 RND_TYPE_NET, 0); 494 #endif 495 } 496 497 static void 498 tl_reset(sc) 499 tl_softc_t *sc; 500 { 501 int i; 502 503 /* read stats */ 504 if (sc->tl_if.if_flags & IFF_RUNNING) { 505 callout_stop(&sc->tl_tick_ch); 506 tl_read_stats(sc); 507 } 508 /* Reset adapter */ 509 TL_HR_WRITE(sc, TL_HOST_CMD, 510 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 511 DELAY(100000); 512 /* Disable interrupts */ 513 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 514 /* setup aregs & hash */ 515 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 516 tl_intreg_write(sc, i, 0); 517 #ifdef TLDEBUG_ADDR 518 printf("Areg & hash registers: \n"); 519 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 520 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 521 #endif 522 /* Setup NetConfig */ 523 tl_intreg_write(sc, TL_INT_NetConfig, 524 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 525 /* Bsize: accept default */ 526 /* TX commit in Acommit: accept default */ 527 /* Load Ld_tmr and Ld_thr */ 528 /* Ld_tmr = 3 */ 529 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 530 /* Ld_thr = 0 */ 531 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 532 /* Unreset MII */ 533 netsio_set(sc, TL_NETSIO_NMRST); 534 DELAY(100000); 535 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 536 } 537 538 static void tl_shutdown(v) 539 void *v; 540 { 541 tl_stop(v, 1); 542 } 543 544 static void tl_stop(ifp, disable) 545 struct ifnet *ifp; 546 int disable; 547 { 548 tl_softc_t *sc = ifp->if_softc; 549 struct Tx_list *Tx; 550 int i; 551 552 if ((ifp->if_flags & IFF_RUNNING) == 0) 553 return; 554 /* disable interrupts */ 555 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 556 /* stop TX and RX channels */ 557 TL_HR_WRITE(sc, TL_HOST_CMD, 558 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 559 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 560 DELAY(100000); 561 562 /* stop statistics reading loop, read stats */ 563 callout_stop(&sc->tl_tick_ch); 564 tl_read_stats(sc); 565 566 /* Down the MII. */ 567 mii_down(&sc->tl_mii); 568 569 /* deallocate memory allocations */ 570 if (sc->Rx_list) { 571 for (i=0; i< TL_NBUF; i++) { 572 if (sc->Rx_list[i].m) { 573 bus_dmamap_unload(sc->tl_dmatag, 574 sc->Rx_list[i].m_dmamap); 575 m_freem(sc->Rx_list[i].m); 576 } 577 bus_dmamap_destroy(sc->tl_dmatag, 578 sc->Rx_list[i].m_dmamap); 579 sc->Rx_list[i].m = NULL; 580 } 581 free(sc->Rx_list, M_DEVBUF); 582 sc->Rx_list = NULL; 583 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 584 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 585 sc->hw_Rx_list = NULL; 586 while ((Tx = sc->active_Tx) != NULL) { 587 Tx->hw_list->stat = 0; 588 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 589 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 590 m_freem(Tx->m); 591 sc->active_Tx = Tx->next; 592 Tx->next = sc->Free_Tx; 593 sc->Free_Tx = Tx; 594 } 595 sc->last_Tx = NULL; 596 free(sc->Tx_list, M_DEVBUF); 597 sc->Tx_list = NULL; 598 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 599 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 600 sc->hw_Tx_list = NULL; 601 } 602 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 603 ifp->if_timer = 0; 604 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 605 } 606 607 static void tl_restart(v) 608 void *v; 609 { 610 tl_init(v); 611 } 612 613 static int tl_init(ifp) 614 struct ifnet *ifp; 615 { 616 tl_softc_t *sc = ifp->if_softc; 617 int i, s, error; 618 char *errstring; 619 char *nullbuf; 620 621 s = splnet(); 622 /* cancel any pending IO */ 623 tl_stop(ifp, 1); 624 tl_reset(sc); 625 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 626 splx(s); 627 return 0; 628 } 629 /* Set various register to reasonable value */ 630 /* setup NetCmd in promisc mode if needed */ 631 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 632 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 633 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 634 /* Max receive size : MCLBYTES */ 635 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 636 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 637 (MCLBYTES >> 8) & 0xff); 638 639 /* init MAC addr */ 640 for (i = 0; i < ETHER_ADDR_LEN; i++) 641 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 642 /* add multicast filters */ 643 tl_addr_filter(sc); 644 #ifdef TLDEBUG_ADDR 645 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 646 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 647 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 648 #endif 649 650 /* Pre-allocate receivers mbuf, make the lists */ 651 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 652 M_NOWAIT|M_ZERO); 653 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 654 M_NOWAIT|M_ZERO); 655 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 656 errstring = "out of memory for lists"; 657 error = ENOMEM; 658 goto bad; 659 } 660 error = bus_dmamap_create(sc->tl_dmatag, 661 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 662 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 663 &sc->Rx_dmamap); 664 if (error == 0) 665 error = bus_dmamap_create(sc->tl_dmatag, 666 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 667 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 668 &sc->Tx_dmamap); 669 if (error == 0) 670 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 671 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 672 &sc->null_dmamap); 673 if (error) { 674 errstring = "can't allocate DMA maps for lists"; 675 goto bad; 676 } 677 memset(sc->ctrl, 0, PAGE_SIZE); 678 sc->hw_Rx_list = (void *)sc->ctrl; 679 sc->hw_Tx_list = 680 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 681 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 682 sizeof(struct tl_Tx_list) * TL_NBUF; 683 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 684 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 685 BUS_DMA_WAITOK); 686 if (error == 0) 687 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 688 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 689 BUS_DMA_WAITOK); 690 if (error == 0) 691 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 692 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 693 if (error) { 694 errstring = "can't DMA map DMA memory for lists"; 695 goto bad; 696 } 697 for (i=0; i< TL_NBUF; i++) { 698 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 699 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 700 &sc->Rx_list[i].m_dmamap); 701 if (error == 0) { 702 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 703 TL_NSEG, MCLBYTES, 0, 704 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 705 &sc->Tx_list[i].m_dmamap); 706 } 707 if (error) { 708 errstring = "can't allocate DMA maps for mbufs"; 709 goto bad; 710 } 711 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 712 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 713 + sizeof(struct tl_Rx_list) * i; 714 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 715 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 716 + sizeof(struct tl_Tx_list) * i; 717 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 718 errstring = "out of mbuf for receive list"; 719 error = ENOMEM; 720 goto bad; 721 } 722 if (i > 0) { /* chain the list */ 723 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 724 sc->hw_Rx_list[i - 1].fwd = 725 htole32(sc->Rx_list[i].hw_listaddr); 726 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 727 } 728 } 729 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 730 sc->Rx_list[TL_NBUF - 1].next = NULL; 731 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 732 sc->Tx_list[TL_NBUF - 1].next = NULL; 733 734 sc->active_Rx = &sc->Rx_list[0]; 735 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 736 sc->active_Tx = sc->last_Tx = NULL; 737 sc->Free_Tx = &sc->Tx_list[0]; 738 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 739 sizeof(struct tl_Rx_list) * TL_NBUF, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 742 sizeof(struct tl_Tx_list) * TL_NBUF, 743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 745 BUS_DMASYNC_PREWRITE); 746 747 /* set media */ 748 mii_mediachg(&sc->tl_mii); 749 750 /* start ticks calls */ 751 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 752 /* write address of Rx list and enable interrupts */ 753 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 754 TL_HR_WRITE(sc, TL_HOST_CMD, 755 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 756 sc->tl_if.if_flags |= IFF_RUNNING; 757 sc->tl_if.if_flags &= ~IFF_OACTIVE; 758 return 0; 759 bad: 760 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 761 splx(s); 762 return error; 763 } 764 765 766 static u_int32_t 767 tl_intreg_read(sc, reg) 768 tl_softc_t *sc; 769 u_int32_t reg; 770 { 771 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 772 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 773 } 774 775 static u_int8_t 776 tl_intreg_read_byte(sc, reg) 777 tl_softc_t *sc; 778 u_int32_t reg; 779 { 780 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 781 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 782 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 783 } 784 785 static void 786 tl_intreg_write(sc, reg, val) 787 tl_softc_t *sc; 788 u_int32_t reg; 789 u_int32_t val; 790 { 791 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 792 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 793 } 794 795 static void 796 tl_intreg_write_byte(sc, reg, val) 797 tl_softc_t *sc; 798 u_int32_t reg; 799 u_int8_t val; 800 { 801 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 802 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 803 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 804 } 805 806 void 807 tl_mii_sync(sc) 808 struct tl_softc *sc; 809 { 810 int i; 811 812 netsio_clr(sc, TL_NETSIO_MTXEN); 813 for (i = 0; i < 32; i++) { 814 netsio_clr(sc, TL_NETSIO_MCLK); 815 netsio_set(sc, TL_NETSIO_MCLK); 816 } 817 } 818 819 void 820 tl_mii_sendbits(sc, data, nbits) 821 struct tl_softc *sc; 822 u_int32_t data; 823 int nbits; 824 { 825 int i; 826 827 netsio_set(sc, TL_NETSIO_MTXEN); 828 for (i = 1 << (nbits - 1); i; i = i >> 1) { 829 netsio_clr(sc, TL_NETSIO_MCLK); 830 netsio_read(sc, TL_NETSIO_MCLK); 831 if (data & i) 832 netsio_set(sc, TL_NETSIO_MDATA); 833 else 834 netsio_clr(sc, TL_NETSIO_MDATA); 835 netsio_set(sc, TL_NETSIO_MCLK); 836 netsio_read(sc, TL_NETSIO_MCLK); 837 } 838 } 839 840 int 841 tl_mii_read(self, phy, reg) 842 struct device *self; 843 int phy, reg; 844 { 845 struct tl_softc *sc = (struct tl_softc *)self; 846 int val = 0, i, err; 847 848 /* 849 * Read the PHY register by manually driving the MII control lines. 850 */ 851 852 tl_mii_sync(sc); 853 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 854 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 855 tl_mii_sendbits(sc, phy, 5); 856 tl_mii_sendbits(sc, reg, 5); 857 858 netsio_clr(sc, TL_NETSIO_MTXEN); 859 netsio_clr(sc, TL_NETSIO_MCLK); 860 netsio_set(sc, TL_NETSIO_MCLK); 861 netsio_clr(sc, TL_NETSIO_MCLK); 862 863 err = netsio_read(sc, TL_NETSIO_MDATA); 864 netsio_set(sc, TL_NETSIO_MCLK); 865 866 /* Even if an error occurs, must still clock out the cycle. */ 867 for (i = 0; i < 16; i++) { 868 val <<= 1; 869 netsio_clr(sc, TL_NETSIO_MCLK); 870 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 871 val |= 1; 872 netsio_set(sc, TL_NETSIO_MCLK); 873 } 874 netsio_clr(sc, TL_NETSIO_MCLK); 875 netsio_set(sc, TL_NETSIO_MCLK); 876 877 return (err ? 0 : val); 878 } 879 880 void 881 tl_mii_write(self, phy, reg, val) 882 struct device *self; 883 int phy, reg, val; 884 { 885 struct tl_softc *sc = (struct tl_softc *)self; 886 887 /* 888 * Write the PHY register by manually driving the MII control lines. 889 */ 890 891 tl_mii_sync(sc); 892 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 893 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 894 tl_mii_sendbits(sc, phy, 5); 895 tl_mii_sendbits(sc, reg, 5); 896 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 897 tl_mii_sendbits(sc, val, 16); 898 899 netsio_clr(sc, TL_NETSIO_MCLK); 900 netsio_set(sc, TL_NETSIO_MCLK); 901 } 902 903 void 904 tl_statchg(self) 905 struct device *self; 906 { 907 tl_softc_t *sc = (struct tl_softc *)self; 908 u_int32_t reg; 909 910 #ifdef TLDEBUG 911 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 912 #endif 913 914 /* 915 * We must keep the ThunderLAN and the PHY in sync as 916 * to the status of full-duplex! 917 */ 918 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 919 if (sc->tl_mii.mii_media_active & IFM_FDX) 920 reg |= TL_NETCOMMAND_DUPLEX; 921 else 922 reg &= ~TL_NETCOMMAND_DUPLEX; 923 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 924 } 925 926 /********** I2C glue **********/ 927 928 static int 929 tl_i2c_acquire_bus(void *cookie, int flags) 930 { 931 932 /* private bus */ 933 return (0); 934 } 935 936 static void 937 tl_i2c_release_bus(void *cookie, int flags) 938 { 939 940 /* private bus */ 941 } 942 943 static int 944 tl_i2c_send_start(void *cookie, int flags) 945 { 946 947 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 948 } 949 950 static int 951 tl_i2c_send_stop(void *cookie, int flags) 952 { 953 954 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 955 } 956 957 static int 958 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 959 { 960 961 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 962 } 963 964 static int 965 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 966 { 967 968 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 969 } 970 971 static int 972 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 973 { 974 975 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 976 } 977 978 /********** I2C bit-bang glue **********/ 979 980 static void 981 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 982 { 983 struct tl_softc *sc = cookie; 984 uint8_t reg; 985 986 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 987 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 988 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 989 } 990 991 static void 992 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 993 { 994 struct tl_softc *sc = cookie; 995 uint8_t reg; 996 997 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 998 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 999 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1000 } 1001 1002 static uint32_t 1003 tl_i2cbb_read(void *cookie) 1004 { 1005 1006 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1007 } 1008 1009 /********** End of I2C stuff **********/ 1010 1011 static int 1012 tl_intr(v) 1013 void *v; 1014 { 1015 tl_softc_t *sc = v; 1016 struct ifnet *ifp = &sc->tl_if; 1017 struct Rx_list *Rx; 1018 struct Tx_list *Tx; 1019 struct mbuf *m; 1020 u_int32_t int_type, int_reg; 1021 int ack = 0; 1022 int size; 1023 1024 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1025 int_type = int_reg & TL_INTR_MASK; 1026 if (int_type == 0) 1027 return 0; 1028 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1029 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1030 int_type, int_reg); 1031 #endif 1032 /* disable interrupts */ 1033 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1034 switch(int_type & TL_INTR_MASK) { 1035 case TL_INTR_RxEOF: 1036 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1037 sizeof(struct tl_Rx_list) * TL_NBUF, 1038 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1039 while(le32toh(sc->active_Rx->hw_list->stat) & 1040 TL_RX_CSTAT_CPLT) { 1041 /* dequeue and requeue at end of list */ 1042 ack++; 1043 Rx = sc->active_Rx; 1044 sc->active_Rx = Rx->next; 1045 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1046 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1047 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1048 m = Rx->m; 1049 size = le32toh(Rx->hw_list->stat) >> 16; 1050 #ifdef TLDEBUG_RX 1051 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1052 Rx, size); 1053 #endif 1054 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1055 /* 1056 * No new mbuf, reuse the same. This means 1057 * that this packet 1058 * is lost 1059 */ 1060 m = NULL; 1061 #ifdef TL_PRIV_STATS 1062 sc->ierr_nomem++; 1063 #endif 1064 #ifdef TLDEBUG 1065 printf("%s: out of mbuf, lost input packet\n", 1066 sc->sc_dev.dv_xname); 1067 #endif 1068 } 1069 Rx->next = NULL; 1070 Rx->hw_list->fwd = 0; 1071 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1072 sc->last_Rx->next = Rx; 1073 sc->last_Rx = Rx; 1074 1075 /* deliver packet */ 1076 if (m) { 1077 if (size < sizeof(struct ether_header)) { 1078 m_freem(m); 1079 continue; 1080 } 1081 m->m_pkthdr.rcvif = ifp; 1082 m->m_pkthdr.len = m->m_len = size; 1083 #ifdef TLDEBUG_RX 1084 { struct ether_header *eh = 1085 mtod(m, struct ether_header *); 1086 printf("tl_intr: Rx packet:\n"); 1087 ether_printheader(eh); } 1088 #endif 1089 #if NBPFILTER > 0 1090 if (ifp->if_bpf) 1091 bpf_mtap(ifp->if_bpf, m); 1092 #endif /* NBPFILTER > 0 */ 1093 (*ifp->if_input)(ifp, m); 1094 } 1095 } 1096 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1097 sizeof(struct tl_Rx_list) * TL_NBUF, 1098 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1099 #ifdef TLDEBUG_RX 1100 printf("TL_INTR_RxEOF: ack %d\n", ack); 1101 #else 1102 if (ack == 0) { 1103 printf("%s: EOF intr without anything to read !\n", 1104 sc->sc_dev.dv_xname); 1105 tl_reset(sc); 1106 /* shedule reinit of the board */ 1107 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1108 return(1); 1109 } 1110 #endif 1111 break; 1112 case TL_INTR_RxEOC: 1113 ack++; 1114 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1115 sizeof(struct tl_Rx_list) * TL_NBUF, 1116 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1117 #ifdef TLDEBUG_RX 1118 printf("TL_INTR_RxEOC: ack %d\n", ack); 1119 #endif 1120 #ifdef DIAGNOSTIC 1121 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1122 printf("%s: Rx EOC interrupt and active Tx list not " 1123 "cleared\n", sc->sc_dev.dv_xname); 1124 return 0; 1125 } else 1126 #endif 1127 { 1128 /* 1129 * write address of Rx list and send Rx GO command, ack 1130 * interrupt and enable interrupts in one command 1131 */ 1132 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1133 TL_HR_WRITE(sc, TL_HOST_CMD, 1134 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1135 HOST_CMD_ACK | HOST_CMD_IntOn); 1136 return 1; 1137 } 1138 case TL_INTR_TxEOF: 1139 case TL_INTR_TxEOC: 1140 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1141 sizeof(struct tl_Tx_list) * TL_NBUF, 1142 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1143 while ((Tx = sc->active_Tx) != NULL) { 1144 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1145 break; 1146 ack++; 1147 #ifdef TLDEBUG_TX 1148 printf("TL_INTR_TxEOC: list 0x%x done\n", 1149 (int)Tx->hw_listaddr); 1150 #endif 1151 Tx->hw_list->stat = 0; 1152 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1153 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1154 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1155 m_freem(Tx->m); 1156 Tx->m = NULL; 1157 sc->active_Tx = Tx->next; 1158 if (sc->active_Tx == NULL) 1159 sc->last_Tx = NULL; 1160 Tx->next = sc->Free_Tx; 1161 sc->Free_Tx = Tx; 1162 } 1163 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1164 sizeof(struct tl_Tx_list) * TL_NBUF, 1165 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1166 /* if this was an EOC, ACK immediatly */ 1167 if (ack) 1168 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1169 if (int_type == TL_INTR_TxEOC) { 1170 #ifdef TLDEBUG_TX 1171 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1172 ack); 1173 #endif 1174 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1175 HOST_CMD_ACK | HOST_CMD_IntOn); 1176 if ( sc->active_Tx != NULL) { 1177 /* needs a Tx go command */ 1178 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1179 sc->active_Tx->hw_listaddr); 1180 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1181 } 1182 sc->tl_if.if_timer = 0; 1183 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1184 tl_ifstart(&sc->tl_if); 1185 return 1; 1186 } 1187 #ifdef TLDEBUG 1188 else { 1189 printf("TL_INTR_TxEOF: ack %d\n", ack); 1190 } 1191 #endif 1192 sc->tl_if.if_timer = 0; 1193 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1194 tl_ifstart(&sc->tl_if); 1195 break; 1196 case TL_INTR_Stat: 1197 ack++; 1198 #ifdef TLDEBUG 1199 printf("TL_INTR_Stat: ack %d\n", ack); 1200 #endif 1201 tl_read_stats(sc); 1202 break; 1203 case TL_INTR_Adc: 1204 if (int_reg & TL_INTVec_MASK) { 1205 /* adapter check conditions */ 1206 printf("%s: check condition, intvect=0x%x, " 1207 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1208 int_reg & TL_INTVec_MASK, 1209 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1210 tl_reset(sc); 1211 /* shedule reinit of the board */ 1212 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1213 return(1); 1214 } else { 1215 u_int8_t netstat; 1216 /* Network status */ 1217 netstat = 1218 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1219 printf("%s: network status, NetSts=%x\n", 1220 sc->sc_dev.dv_xname, netstat); 1221 /* Ack interrupts */ 1222 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1223 netstat); 1224 ack++; 1225 } 1226 break; 1227 default: 1228 printf("%s: unhandled interrupt code %x!\n", 1229 sc->sc_dev.dv_xname, int_type); 1230 ack++; 1231 } 1232 1233 if (ack) { 1234 /* Ack the interrupt and enable interrupts */ 1235 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1236 HOST_CMD_IntOn); 1237 #if NRND > 0 1238 if (RND_ENABLED(&sc->rnd_source)) 1239 rnd_add_uint32(&sc->rnd_source, int_reg); 1240 #endif 1241 return 1; 1242 } 1243 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1244 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1245 return 0; 1246 } 1247 1248 static int 1249 tl_ifioctl(ifp, cmd, data) 1250 struct ifnet *ifp; 1251 ioctl_cmd_t cmd; 1252 caddr_t data; 1253 { 1254 struct tl_softc *sc = ifp->if_softc; 1255 struct ifreq *ifr = (struct ifreq *)data; 1256 int s, error; 1257 1258 s = splnet(); 1259 switch(cmd) { 1260 case SIOCSIFMEDIA: 1261 case SIOCGIFMEDIA: 1262 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1263 break; 1264 default: 1265 error = ether_ioctl(ifp, cmd, data); 1266 if (error == ENETRESET) { 1267 if (ifp->if_flags & IFF_RUNNING) 1268 tl_addr_filter(sc); 1269 error = 0; 1270 } 1271 } 1272 splx(s); 1273 return error; 1274 } 1275 1276 static void 1277 tl_ifstart(ifp) 1278 struct ifnet *ifp; 1279 { 1280 tl_softc_t *sc = ifp->if_softc; 1281 struct mbuf *mb_head; 1282 struct Tx_list *Tx; 1283 int segment, size; 1284 int again, error; 1285 1286 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1287 return; 1288 txloop: 1289 /* If we don't have more space ... */ 1290 if (sc->Free_Tx == NULL) { 1291 #ifdef TLDEBUG 1292 printf("tl_ifstart: No free TX list\n"); 1293 #endif 1294 sc->tl_if.if_flags |= IFF_OACTIVE; 1295 return; 1296 } 1297 /* Grab a paquet for output */ 1298 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1299 if (mb_head == NULL) { 1300 #ifdef TLDEBUG_TX 1301 printf("tl_ifstart: nothing to send\n"); 1302 #endif 1303 return; 1304 } 1305 Tx = sc->Free_Tx; 1306 sc->Free_Tx = Tx->next; 1307 Tx->next = NULL; 1308 again = 0; 1309 /* 1310 * Go through each of the mbufs in the chain and initialize 1311 * the transmit list descriptors with the physical address 1312 * and size of the mbuf. 1313 */ 1314 tbdinit: 1315 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1316 Tx->m = mb_head; 1317 size = mb_head->m_pkthdr.len; 1318 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1319 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1320 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1321 struct mbuf *mn; 1322 /* 1323 * We ran out of segments, or we will. We have to recopy this 1324 * mbuf chain first. 1325 */ 1326 if (error == 0) 1327 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1328 if (again) { 1329 /* already copyed, can't do much more */ 1330 m_freem(mb_head); 1331 goto bad; 1332 } 1333 again = 1; 1334 #ifdef TLDEBUG_TX 1335 printf("tl_ifstart: need to copy mbuf\n"); 1336 #endif 1337 #ifdef TL_PRIV_STATS 1338 sc->oerr_mcopy++; 1339 #endif 1340 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1341 if (mn == NULL) { 1342 m_freem(mb_head); 1343 goto bad; 1344 } 1345 if (mb_head->m_pkthdr.len > MHLEN) { 1346 MCLGET(mn, M_DONTWAIT); 1347 if ((mn->m_flags & M_EXT) == 0) { 1348 m_freem(mn); 1349 m_freem(mb_head); 1350 goto bad; 1351 } 1352 } 1353 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1354 mtod(mn, caddr_t)); 1355 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1356 m_freem(mb_head); 1357 mb_head = mn; 1358 goto tbdinit; 1359 } 1360 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1361 Tx->hw_list->seg[segment].data_addr = 1362 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1363 Tx->hw_list->seg[segment].data_count = 1364 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1365 } 1366 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1367 Tx->m_dmamap->dm_mapsize, 1368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1369 /* We are at end of mbuf chain. check the size and 1370 * see if it needs to be extended 1371 */ 1372 if (size < ETHER_MIN_TX) { 1373 #ifdef DIAGNOSTIC 1374 if (segment >= TL_NSEG) { 1375 panic("tl_ifstart: to much segmets (%d)", segment); 1376 } 1377 #endif 1378 /* 1379 * add the nullbuf in the seg 1380 */ 1381 Tx->hw_list->seg[segment].data_count = 1382 htole32(ETHER_MIN_TX - size); 1383 Tx->hw_list->seg[segment].data_addr = 1384 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1385 size = ETHER_MIN_TX; 1386 segment++; 1387 } 1388 /* The list is done, finish the list init */ 1389 Tx->hw_list->seg[segment - 1].data_count |= 1390 htole32(TL_LAST_SEG); 1391 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1392 #ifdef TLDEBUG_TX 1393 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1394 le32toh(Tx->hw_list->stat)); 1395 #if 0 1396 for(segment = 0; segment < TL_NSEG; segment++) { 1397 printf(" seg %d addr 0x%x len 0x%x\n", 1398 segment, 1399 le32toh(Tx->hw_list->seg[segment].data_addr), 1400 le32toh(Tx->hw_list->seg[segment].data_count)); 1401 } 1402 #endif 1403 #endif 1404 if (sc->active_Tx == NULL) { 1405 sc->active_Tx = sc->last_Tx = Tx; 1406 #ifdef TLDEBUG_TX 1407 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1408 (int)Tx->hw_listaddr); 1409 #endif 1410 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1411 sizeof(struct tl_Tx_list) * TL_NBUF, 1412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1413 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1414 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1415 } else { 1416 #ifdef TLDEBUG_TX 1417 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1418 (int)Tx->hw_listaddr); 1419 #endif 1420 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1421 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1422 sizeof(struct tl_Tx_list) * TL_NBUF, 1423 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1424 sc->last_Tx->next = Tx; 1425 sc->last_Tx = Tx; 1426 #ifdef DIAGNOSTIC 1427 if (sc->last_Tx->hw_list->fwd & 0x7) 1428 printf("%s: physical addr 0x%x of list not properly " 1429 "aligned\n", 1430 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1431 #endif 1432 } 1433 #if NBPFILTER > 0 1434 /* Pass packet to bpf if there is a listener */ 1435 if (ifp->if_bpf) 1436 bpf_mtap(ifp->if_bpf, mb_head); 1437 #endif 1438 /* 1439 * Set a 5 second timer just in case we don't hear from the card again. 1440 */ 1441 ifp->if_timer = 5; 1442 goto txloop; 1443 bad: 1444 #ifdef TLDEBUG 1445 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1446 #endif 1447 Tx->next = sc->Free_Tx; 1448 sc->Free_Tx = Tx; 1449 return; 1450 } 1451 1452 static void 1453 tl_ifwatchdog(ifp) 1454 struct ifnet *ifp; 1455 { 1456 tl_softc_t *sc = ifp->if_softc; 1457 1458 if ((ifp->if_flags & IFF_RUNNING) == 0) 1459 return; 1460 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1461 ifp->if_oerrors++; 1462 tl_init(ifp); 1463 } 1464 1465 static int 1466 tl_mediachange(ifp) 1467 struct ifnet *ifp; 1468 { 1469 1470 if (ifp->if_flags & IFF_UP) 1471 tl_init(ifp); 1472 return (0); 1473 } 1474 1475 static void 1476 tl_mediastatus(ifp, ifmr) 1477 struct ifnet *ifp; 1478 struct ifmediareq *ifmr; 1479 { 1480 tl_softc_t *sc = ifp->if_softc; 1481 1482 mii_pollstat(&sc->tl_mii); 1483 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1484 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1485 } 1486 1487 static int tl_add_RxBuff(sc, Rx, oldm) 1488 tl_softc_t *sc; 1489 struct Rx_list *Rx; 1490 struct mbuf *oldm; 1491 { 1492 struct mbuf *m; 1493 int error; 1494 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m != NULL) { 1497 MCLGET(m, M_DONTWAIT); 1498 if ((m->m_flags & M_EXT) == 0) { 1499 m_freem(m); 1500 if (oldm == NULL) 1501 return 0; 1502 m = oldm; 1503 m->m_data = m->m_ext.ext_buf; 1504 } 1505 } else { 1506 if (oldm == NULL) 1507 return 0; 1508 m = oldm; 1509 m->m_data = m->m_ext.ext_buf; 1510 } 1511 1512 /* (re)init the Rx_list struct */ 1513 1514 Rx->m = m; 1515 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1516 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1517 printf("%s: bus_dmamap_load() failed (error %d) for " 1518 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1519 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1520 m_freem(m); 1521 Rx->m = NULL; 1522 return 0; 1523 } 1524 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1525 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1526 /* 1527 * Move the data pointer up so that the incoming data packet 1528 * will be 32-bit aligned. 1529 */ 1530 m->m_data += 2; 1531 1532 Rx->hw_list->stat = 1533 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1534 Rx->hw_list->seg.data_count = 1535 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1536 Rx->hw_list->seg.data_addr = 1537 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1538 return (m != oldm); 1539 } 1540 1541 static void tl_ticks(v) 1542 void *v; 1543 { 1544 tl_softc_t *sc = v; 1545 1546 tl_read_stats(sc); 1547 1548 /* Tick the MII. */ 1549 mii_tick(&sc->tl_mii); 1550 1551 /* read statistics every seconds */ 1552 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1553 } 1554 1555 static void 1556 tl_read_stats(sc) 1557 tl_softc_t *sc; 1558 { 1559 u_int32_t reg; 1560 int ierr_overr; 1561 int ierr_code; 1562 int ierr_crc; 1563 int oerr_underr; 1564 int oerr_deferred; 1565 int oerr_coll; 1566 int oerr_multicoll; 1567 int oerr_exesscoll; 1568 int oerr_latecoll; 1569 int oerr_carrloss; 1570 struct ifnet *ifp = &sc->tl_if; 1571 1572 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1573 ifp->if_opackets += reg & 0x00ffffff; 1574 oerr_underr = reg >> 24; 1575 1576 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1577 ifp->if_ipackets += reg & 0x00ffffff; 1578 ierr_overr = reg >> 24; 1579 1580 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1581 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1582 ierr_code = (reg & TL_FERR_CODE) >> 24; 1583 oerr_deferred = (reg & TL_FERR_DEF); 1584 1585 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1586 oerr_multicoll = (reg & TL_COL_MULTI); 1587 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1588 1589 reg = tl_intreg_read(sc, TL_INT_LERR); 1590 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1591 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1592 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1593 1594 1595 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1596 oerr_carrloss; 1597 ifp->if_collisions += oerr_coll + oerr_multicoll; 1598 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1599 1600 if (ierr_overr) 1601 printf("%s: receiver ring buffer overrun\n", 1602 sc->sc_dev.dv_xname); 1603 if (oerr_underr) 1604 printf("%s: transmit buffer underrun\n", 1605 sc->sc_dev.dv_xname); 1606 #ifdef TL_PRIV_STATS 1607 sc->ierr_overr += ierr_overr; 1608 sc->ierr_code += ierr_code; 1609 sc->ierr_crc += ierr_crc; 1610 sc->oerr_underr += oerr_underr; 1611 sc->oerr_deferred += oerr_deferred; 1612 sc->oerr_coll += oerr_coll; 1613 sc->oerr_multicoll += oerr_multicoll; 1614 sc->oerr_exesscoll += oerr_exesscoll; 1615 sc->oerr_latecoll += oerr_latecoll; 1616 sc->oerr_carrloss += oerr_carrloss; 1617 #endif 1618 } 1619 1620 static void tl_addr_filter(sc) 1621 tl_softc_t *sc; 1622 { 1623 struct ether_multistep step; 1624 struct ether_multi *enm; 1625 u_int32_t hash[2] = {0, 0}; 1626 int i; 1627 1628 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1629 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1630 while (enm != NULL) { 1631 #ifdef TLDEBUG 1632 printf("tl_addr_filter: addrs %s %s\n", 1633 ether_sprintf(enm->enm_addrlo), 1634 ether_sprintf(enm->enm_addrhi)); 1635 #endif 1636 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1637 i = tl_multicast_hash(enm->enm_addrlo); 1638 hash[i/32] |= 1 << (i%32); 1639 } else { 1640 hash[0] = hash[1] = 0xffffffff; 1641 sc->tl_if.if_flags |= IFF_ALLMULTI; 1642 break; 1643 } 1644 ETHER_NEXT_MULTI(step, enm); 1645 } 1646 #ifdef TLDEBUG 1647 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1648 #endif 1649 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1650 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1651 } 1652 1653 static int tl_multicast_hash(a) 1654 u_int8_t *a; 1655 { 1656 int hash; 1657 1658 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1659 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1660 1661 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1662 DA(a,36), DA(a,42)); 1663 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1664 DA(a,37), DA(a,43)) << 1; 1665 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1666 DA(a,38), DA(a,44)) << 2; 1667 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1668 DA(a,39), DA(a,45)) << 3; 1669 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1670 DA(a,40), DA(a,46)) << 4; 1671 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1672 DA(a,41), DA(a,47)) << 5; 1673 1674 return hash; 1675 } 1676 1677 #if defined(TLDEBUG_RX) 1678 void 1679 ether_printheader(eh) 1680 struct ether_header *eh; 1681 { 1682 u_char *c = (char*)eh; 1683 int i; 1684 for (i=0; i<sizeof(struct ether_header); i++) 1685 printf("%x ", (u_int)c[i]); 1686 printf("\n"); 1687 } 1688 #endif 1689
Indexes created Tue Sep 23 07:09:52 GMT 2025