if_tl.c revision 1.7
1 /* $NetBSD: if_tl.c,v 1.7 1997/11/30 15:18:58 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include "bpfilter.h" 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #include <net/bpfdesc.h> 69 #endif 70 71 #ifdef INET 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/in_var.h> 75 #include <netinet/ip.h> 76 #endif 77 78 #ifdef NS 79 #include <netns/ns.h> 80 #include <netns/ns_if.h> 81 #endif 82 83 #include <vm/vm.h> 84 #include <vm/vm_param.h> 85 #include <vm/vm_kern.h> 86 87 #if defined(__NetBSD__) 88 #include <net/if_ether.h> 89 #if defined(INET) 90 #include <netinet/if_inarp.h> 91 #endif 92 93 #include <machine/bus.h> 94 #include <machine/intr.h> 95 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcidevs.h> 99 #include <dev/i2c/i2c_bus.h> 100 #include <dev/i2c/i2c_eeprom.h> 101 #include <dev/mii/mii_adapter.h> 102 #include <dev/mii/mii_adapters_id.h> 103 #include <dev/pci/if_tlregs.h> 104 #endif /* __NetBSD__ */ 105 106 /* number of transmit/receive buffers */ 107 #ifndef TL_NBUF 108 #define TL_NBUF 10 109 #endif 110 111 /* number of seconds the link can be idle */ 112 #ifndef TL_IDLETIME 113 #define TL_IDLETIME 10 114 #endif 115 116 struct tl_softc { 117 struct device sc_dev; /* base device */ 118 bus_space_tag_t tl_bustag; 119 bus_space_handle_t tl_bushandle; /* CSR region handle */ 120 void* tl_ih; 121 struct ethercom tl_ec; 122 u_int8_t tl_enaddr[ETHER_ADDR_LEN]; /* hardware adress */ 123 struct ifmedia tl_ifmedia; 124 u_int16_t tl_flags; 125 #define TL_IFACT 0x0001 /* chip has interface activity */ 126 u_int8_t tl_lasttx; /* we were without input this many seconds */ 127 i2c_adapter_t i2cbus; /* i2c bus, for eeprom */ 128 mii_data_t mii; /* mii bus */ 129 struct Rx_list *Rx_list; /* Receive and transmit lists */ 130 struct Tx_list *Tx_list; 131 struct Rx_list *active_Rx, *last_Rx; 132 struct Tx_list *active_Tx, *last_Tx; 133 struct Tx_list *Free_Tx; 134 int opkt; /* used to detect link up/down for AUI/BNC */ 135 int stats_exesscoll; /* idem */ 136 #ifdef TL_PRIV_STATS 137 int ierr_overr; 138 int ierr_code; 139 int ierr_crc; 140 int ierr_nomem; 141 int oerr_underr; 142 int oerr_deffered; 143 int oerr_coll; 144 int oerr_multicoll; 145 int oerr_latecoll; 146 int oerr_exesscoll; 147 int oerr_carrloss; 148 int oerr_mcopy; 149 #endif 150 }; 151 #define tl_if tl_ec.ec_if 152 #define tl_bpf tl_if.if_bpf 153 154 typedef struct tl_softc tl_softc_t; 155 typedef u_long ioctl_cmd_t; 156 157 #define TL_HR_READ(sc, reg) \ 158 bus_space_read_4(sc->tl_bustag, sc->tl_bushandle, (reg)) 159 #define TL_HR_READ_BYTE(sc, reg) \ 160 bus_space_read_1(sc->tl_bustag, sc->tl_bushandle, (reg)) 161 #define TL_HR_WRITE(sc, reg, data) \ 162 bus_space_write_4(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 163 #define TL_HR_WRITE_BYTE(sc, reg, data) \ 164 bus_space_write_1(sc->tl_bustag, sc->tl_bushandle, (reg), (data)) 165 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 166 167 #ifdef __BROKEN_INDIRECT_CONFIG 168 static int tl_pci_match __P((struct device *, void *, void *)); 169 #else 170 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 171 #endif 172 static void tl_pci_attach __P((struct device *, struct device *, void *)); 173 static int tl_intr __P((void *)); 174 175 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 176 static int tl_mediachange __P((struct ifnet *)); 177 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 178 static void tl_ifwatchdog __P((struct ifnet *)); 179 static void tl_shutdown __P((void*)); 180 181 static void tl_ifstart __P((struct ifnet *)); 182 static void tl_reset __P((tl_softc_t*)); 183 static int tl_init __P((tl_softc_t*)); 184 static void tl_restart __P((void *)); 185 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 186 static void tl_read_stats __P((tl_softc_t*)); 187 static void tl_ticks __P((void*)); 188 static int tl_multicast_hash __P((u_int8_t*)); 189 static void tl_addr_filter __P((tl_softc_t*)); 190 191 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 192 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 193 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 194 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 195 196 197 #if defined(TLDEBUG_RX) 198 static void ether_printheader __P((struct ether_header*)); 199 #endif 200 201 void tl_mii_set __P((void*, u_int8_t)); 202 void tl_mii_clr __P((void*, u_int8_t)); 203 int tl_mii_read __P((void*, u_int8_t)); 204 205 void tl_i2c_set __P((void*, u_int8_t)); 206 void tl_i2c_clr __P((void*, u_int8_t)); 207 int tl_i2c_read __P((void*, u_int8_t)); 208 209 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 210 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 211 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 212 static __inline void netsio_clr(sc, bits) 213 tl_softc_t* sc; 214 u_int8_t bits; 215 { 216 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 217 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 218 } 219 static __inline void netsio_set(sc, bits) 220 tl_softc_t* sc; 221 u_int8_t bits; 222 { 223 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 224 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 225 } 226 static __inline u_int8_t netsio_read(sc, bits) 227 tl_softc_t* sc; 228 u_int8_t bits; 229 { 230 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 231 } 232 233 struct cfattach tl_ca = { 234 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 235 }; 236 237 struct cfdriver tl_cd = { 238 0, "tl", DV_IFNET 239 }; 240 241 struct tl_product_desc { 242 u_int32_t tp_product; 243 u_int32_t tp_adapter; 244 const char *tp_desc; 245 }; 246 247 const struct tl_product_desc tl_compaq_products[] = { 248 { PCI_PRODUCT_COMPAQ_N100TX, COMPAQ_NETLIGENT_10_100, 249 "Compaq Netelligent 10/100 TX" }, 250 { PCI_PRODUCT_COMPAQ_N10T, COMPAQ_NETLIGENT_10, 251 "Compaq Netelligent 10 T" }, 252 { PCI_PRODUCT_COMPAQ_IntNF3P, COMPAQ_INT_NETFLEX, 253 "Compaq Integrated NetFlex 3/P" }, 254 { PCI_PRODUCT_COMPAQ_IntPL100TX, COMPAQ_INT_NETLIGENT_10_100, 255 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 256 { PCI_PRODUCT_COMPAQ_DPNet100TX, COMPAQ_DUAL_NETLIGENT_10_100, 257 "Compaq Dual Port Netelligent 10/100 TX" }, 258 { PCI_PRODUCT_COMPAQ_DP4000, COMPAQ_DSKP4000, 259 "Compaq Deskpro 4000 5233MMX" }, 260 { PCI_PRODUCT_COMPAQ_NF3P_BNC, COMPAQ_NETFLEX_BNC, 261 "Compaq NetFlex 3/P w/ BNC" }, 262 { PCI_PRODUCT_COMPAQ_NF3P, COMPAQ_NETFLEX, 263 "Compaq NetFlex 3/P" }, 264 { 0, 0, NULL }, 265 }; 266 267 const struct tl_product_desc tl_ti_products[] = { 268 { PCI_PRODUCT_TI_TLAN, TI_TLAN, 269 "Texas Instruments ThunderLAN" }, 270 { 0, 0, NULL }, 271 }; 272 273 struct tl_vendor_desc { 274 u_int32_t tv_vendor; 275 const struct tl_product_desc *tv_products; 276 }; 277 278 const struct tl_vendor_desc tl_vendors[] = { 279 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 280 { PCI_VENDOR_TI, tl_ti_products }, 281 { 0, NULL }, 282 }; 283 284 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 285 286 const struct tl_product_desc * 287 tl_lookup_product(id) 288 u_int32_t id; 289 { 290 const struct tl_product_desc *tp; 291 const struct tl_vendor_desc *tv; 292 293 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 294 if (PCI_VENDOR(id) == tv->tv_vendor) 295 break; 296 297 if ((tp = tv->tv_products) == NULL) 298 return (NULL); 299 300 for (; tp->tp_desc != NULL; tp++) 301 if (PCI_PRODUCT(id) == tp->tp_product) 302 break; 303 304 if (tp->tp_desc == NULL) 305 return (NULL); 306 307 return (tp); 308 } 309 310 static char *nullbuf = NULL; 311 312 static int 313 tl_pci_match(parent, match, aux) 314 struct device *parent; 315 #ifdef __BROKEN_INDIRECT_CONFIG 316 void *match; 317 #else 318 struct cfdata *match; 319 #endif 320 void *aux; 321 { 322 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 323 324 if (tl_lookup_product(pa->pa_id) != NULL) 325 return (1); 326 327 return (0); 328 } 329 330 static void 331 tl_pci_attach(parent, self, aux) 332 struct device * parent; 333 struct device * self; 334 void * aux; 335 { 336 tl_softc_t *sc = (tl_softc_t *)self; 337 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 338 const struct tl_product_desc *tp; 339 struct ifnet * const ifp = &sc->tl_if; 340 bus_space_tag_t iot, memt; 341 bus_space_handle_t ioh, memh; 342 pci_intr_handle_t intrhandle; 343 const char *intrstr; 344 int i, tmp, ioh_valid, memh_valid; 345 pcireg_t csr; 346 347 printf("\n"); 348 349 /* Map the card space. */ 350 ioh_valid = (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 351 &iot, &ioh, NULL, NULL) == 0); 352 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 353 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 354 0, &memt, &memh, NULL, NULL) == 0); 355 356 #if 1 357 /* 358 * XXX HACK! Due to a bug in a previous revision of this driver, 359 * XXX i/o space was always selected. Now that this bug is fixed, 360 * XXX we discover that memory mapped use fails on at least one 361 * XXX ThunderLAN variant - the built-in Ethernet on TI Travelmate 362 * XXX docking stations. We hack around this by "prefering" i/o 363 * XXX access for now. 364 */ 365 if (ioh_valid) { 366 sc->tl_bustag = iot; 367 sc->tl_bushandle = ioh; 368 } else if (memh_valid) { 369 sc->tl_bustag = memt; 370 sc->tl_bushandle = memh; 371 } else { 372 printf("%s: unable to map device registers\n", 373 sc->sc_dev.dv_xname); 374 return; 375 } 376 #else 377 if (memh_valid) { 378 sc->tl_bustag = memt; 379 sc->tl_bushandle = memh; 380 } else if (ioh_valid) { 381 sc->tl_bustag = iot; 382 sc->tl_bushandle = ioh; 383 } else { 384 printf("%s: unable to map device registers\n", 385 sc->sc_dev.dv_xname); 386 return; 387 } 388 #endif 389 390 /* Enable the device. */ 391 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 392 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 393 csr | PCI_COMMAND_MASTER_ENABLE); 394 395 tp = tl_lookup_product(pa->pa_id); 396 if (tp == NULL) 397 panic("tl_pci_attach: impossible"); 398 399 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 400 sc->mii.adapter_id = tp->tp_adapter; 401 402 tl_reset(sc); 403 404 /* fill in the i2c struct */ 405 sc->i2cbus.adapter_softc = sc; 406 sc->i2cbus.set_bit = tl_i2c_set; 407 sc->i2cbus.clr_bit = tl_i2c_clr; 408 sc->i2cbus.read_bit = tl_i2c_read; 409 410 #ifdef TLDEBUG 411 printf("default values of INTreg: 0x%x\n", 412 tl_intreg_read(sc, TL_INT_Defaults)); 413 #endif 414 415 /* read mac addr */ 416 for (i=0; i<ETHER_ADDR_LEN; i++) { 417 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 418 if (tmp < 0) { 419 printf("%s: error reading Ethernet adress\n", 420 sc->sc_dev.dv_xname); 421 return; 422 } else { 423 sc->tl_enaddr[i] = tmp; 424 } 425 } 426 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 427 ether_sprintf(sc->tl_enaddr)); 428 429 /* Map and establish interrupts */ 430 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 431 pa->pa_intrline, &intrhandle)) { 432 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 433 return; 434 } 435 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 436 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 437 tl_intr, sc); 438 if (sc->tl_ih == NULL) { 439 printf("%s: couldn't establish interrupt", 440 sc->sc_dev.dv_xname); 441 if (intrstr != NULL) 442 printf(" at %s", intrstr); 443 printf("\n"); 444 return; 445 } 446 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 447 448 /* 449 * Add shutdown hook so that DMA is disabled prior to reboot. Not 450 * doing do could allow DMA to corrupt kernel memory during the 451 * reboot before the driver initializes. 452 */ 453 (void) shutdownhook_establish(tl_shutdown, sc); 454 455 sc->mii.adapter_softc = sc; 456 sc->mii.mii_setbit = tl_mii_set; 457 sc->mii.mii_clrbit = tl_mii_clr; 458 sc->mii.mii_readbit = tl_mii_read; 459 sc->mii.mii_readreg = NULL; /* Let generic MII function handle that */ 460 sc->mii.mii_writereg = NULL; 461 if (config_found(self, (void*)&sc->mii, NULL) == NULL) { 462 printf("%s: no mii configured\n", sc->sc_dev.dv_xname); 463 return; 464 } 465 466 ifmedia_init(&sc->tl_ifmedia, 0, tl_mediachange, tl_mediastatus); 467 mii_media_add(&sc->tl_ifmedia, &sc->mii); 468 ifmedia_set(&sc->tl_ifmedia, IFM_ETHER | IFM_NONE); 469 470 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 471 sc->tl_if.if_softc = sc; 472 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 473 ifp->if_ioctl = tl_ifioctl; 474 ifp->if_start = tl_ifstart; 475 ifp->if_watchdog = tl_ifwatchdog; 476 ifp->if_timer = 0; 477 if_attach(ifp); 478 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 479 #if NBPFILTER > 0 480 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 481 sizeof(struct ether_header)); 482 #endif 483 sc->mii.mii_media_active = IFM_NONE; 484 } 485 486 static void 487 tl_reset(sc) 488 tl_softc_t *sc; 489 { 490 int i; 491 492 /* read stats */ 493 if (sc->tl_if.if_flags & IFF_RUNNING) { 494 untimeout(tl_ticks, sc); 495 tl_read_stats(sc); 496 } 497 /* Reset adapter */ 498 TL_HR_WRITE(sc, TL_HOST_CMD, 499 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 500 DELAY(100000); 501 /* Disable interrupts */ 502 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 503 /* setup aregs & hash */ 504 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 505 tl_intreg_write(sc, i, 0); 506 #ifdef TLDEBUG_ADDR 507 printf("Areg & hash registers: \n"); 508 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 509 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 510 #endif 511 /* Setup NetConfig */ 512 tl_intreg_write(sc, TL_INT_NetConfig, 513 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 514 /* Bsize: accept default */ 515 /* TX commit in Acommit: accept default */ 516 /* Load Ld_tmr and Ld_thr */ 517 /* Ld_tmr = 3 */ 518 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 519 /* Ld_thr = 0 */ 520 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 521 /* Unreset MII */ 522 netsio_set(sc, TL_NETSIO_NMRST); 523 DELAY(100000); 524 sc->mii.mii_media_status &= ~IFM_ACTIVE; 525 sc->tl_flags = 0; 526 sc->opkt = 0; 527 sc->stats_exesscoll = 0; 528 } 529 530 static void tl_shutdown(v) 531 void *v; 532 { 533 tl_softc_t *sc = v; 534 struct Tx_list *Tx; 535 int i; 536 537 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 538 return; 539 /* disable interrupts */ 540 TL_HR_WRITE(sc, TL_HOST_CMD, 541 HOST_CMD_IntOff); 542 /* stop TX and RX channels */ 543 TL_HR_WRITE(sc, TL_HOST_CMD, 544 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 546 DELAY(100000); 547 548 /* stop statistics reading loop, read stats */ 549 untimeout(tl_ticks, sc); 550 tl_read_stats(sc); 551 552 /* deallocate memory allocations */ 553 for (i=0; i< TL_NBUF; i++) { 554 if (sc->Rx_list[i].m) 555 m_freem(sc->Rx_list[i].m); 556 sc->Rx_list[i].m = NULL; 557 } 558 free(sc->Rx_list, M_DEVBUF); 559 sc->Rx_list = NULL; 560 while ((Tx = sc->active_Tx) != NULL) { 561 Tx->hw_list.stat = 0; 562 m_freem(Tx->m); 563 sc->active_Tx = Tx->next; 564 Tx->next = sc->Free_Tx; 565 sc->Free_Tx = Tx; 566 } 567 sc->last_Tx = NULL; 568 free(sc->Tx_list, M_DEVBUF); 569 sc->Tx_list = NULL; 570 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 571 sc->mii.mii_media_status &= ~IFM_ACTIVE; 572 sc->tl_flags = 0; 573 } 574 575 static void tl_restart(v) 576 void *v; 577 { 578 tl_init(v); 579 } 580 581 static int tl_init(sc) 582 tl_softc_t *sc; 583 { 584 struct ifnet *ifp = &sc->tl_if; 585 int i, s; 586 587 s = splimp(); 588 /* cancel any pending IO */ 589 tl_shutdown(sc); 590 tl_reset(sc); 591 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 592 splx(s); 593 return 0; 594 } 595 /* Set various register to reasonable value */ 596 /* setup NetCmd in promisc mode if needed */ 597 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 598 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 599 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 600 /* Max receive size : MCLBYTES */ 601 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 602 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 603 (MCLBYTES >> 8) & 0xff); 604 605 /* init MAC addr */ 606 for (i = 0; i < ETHER_ADDR_LEN; i++) 607 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 608 /* add multicast filters */ 609 tl_addr_filter(sc); 610 #ifdef TLDEBUG_ADDR 611 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 612 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 613 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 614 #endif 615 616 /* Pre-allocate receivers mbuf, make the lists */ 617 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 618 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, M_NOWAIT); 619 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 620 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 621 sc->tl_if.if_flags &= ~IFF_UP; 622 splx(s); 623 return ENOMEM; 624 } 625 for (i=0; i< TL_NBUF; i++) { 626 if(tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 627 printf("%s: out of mbuf for receive list\n", sc->sc_dev.dv_xname); 628 sc->tl_if.if_flags &= ~IFF_UP; 629 splx(s); 630 return ENOMEM; 631 } 632 if (i > 0) { /* chain the list */ 633 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 634 sc->Rx_list[i-1].hw_list.fwd = vtophys(&sc->Rx_list[i].hw_list); 635 #ifdef DIAGNOSTIC 636 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 637 printf("%s: physical addr 0x%x of list not properly aligned\n", 638 sc->sc_dev.dv_xname, sc->Rx_list[i-1].hw_list.fwd); 639 #endif 640 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 641 } 642 } 643 sc->Rx_list[TL_NBUF-1].next = NULL; 644 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 645 sc->Tx_list[TL_NBUF-1].next = NULL; 646 647 sc->active_Rx = &sc->Rx_list[0]; 648 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 649 sc->active_Tx = sc->last_Tx = NULL; 650 sc->Free_Tx = &sc->Tx_list[0]; 651 652 if (nullbuf == NULL) 653 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 654 if (nullbuf == NULL) { 655 printf("%s: can't allocate space for pad buffer\n", 656 sc->sc_dev.dv_xname); 657 sc->tl_if.if_flags &= ~IFF_UP; 658 splx(s); 659 return ENOMEM; 660 } 661 bzero(nullbuf, ETHER_MIN_TX); 662 663 /* set media if needed */ 664 if (IFM_SUBTYPE(sc->mii.mii_media_active) != IFM_NONE) { 665 mii_mediachg(&sc->mii); 666 } 667 668 /* start ticks calls */ 669 timeout(tl_ticks, sc, hz); 670 /* write adress of Rx list and enable interrupts */ 671 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 672 TL_HR_WRITE(sc, TL_HOST_CMD, 673 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 674 sc->tl_if.if_flags |= IFF_RUNNING; 675 sc->tl_if.if_flags &= ~IFF_OACTIVE; 676 return 0; 677 } 678 679 680 static u_int32_t 681 tl_intreg_read(sc, reg) 682 tl_softc_t *sc; 683 u_int32_t reg; 684 { 685 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 686 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 687 } 688 689 static u_int8_t 690 tl_intreg_read_byte(sc, reg) 691 tl_softc_t *sc; 692 u_int32_t reg; 693 { 694 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 695 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 696 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 697 } 698 699 static void 700 tl_intreg_write(sc, reg, val) 701 tl_softc_t *sc; 702 u_int32_t reg; 703 u_int32_t val; 704 { 705 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 706 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 707 } 708 709 static void 710 tl_intreg_write_byte(sc, reg, val) 711 tl_softc_t *sc; 712 u_int32_t reg; 713 u_int8_t val; 714 { 715 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 716 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 717 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 718 } 719 720 void tl_mii_set(v, bit) 721 void *v; 722 u_int8_t bit; 723 { 724 tl_softc_t *sc = v; 725 726 switch (bit) { 727 case MII_DATA: 728 netsio_set(sc, TL_NETSIO_MDATA); 729 break; 730 case MII_CLOCK: 731 netsio_set(sc, TL_NETSIO_MCLK); 732 break; 733 case MII_TXEN: 734 netsio_set(sc, TL_NETSIO_MTXEN); 735 break; 736 default: 737 printf("tl_mii_set: unknown bit %d\n", bit); 738 } 739 } 740 741 void tl_mii_clr(v, bit) 742 void *v; 743 u_int8_t bit; 744 { 745 tl_softc_t *sc = v; 746 747 switch (bit) { 748 case MII_DATA: 749 netsio_clr(sc, TL_NETSIO_MDATA); 750 break; 751 case MII_CLOCK: 752 netsio_clr(sc, TL_NETSIO_MCLK); 753 break; 754 case MII_TXEN: 755 netsio_clr(sc, TL_NETSIO_MTXEN); 756 break; 757 default: 758 printf("tl_mii_clr: unknown bit %d\n", bit); 759 } 760 return; 761 } 762 763 int tl_mii_read(v, bit) 764 void *v; 765 u_int8_t bit; 766 { 767 tl_softc_t *sc = v; 768 769 switch (bit) { 770 case MII_DATA: 771 return netsio_read(sc, TL_NETSIO_MDATA); 772 break; 773 case MII_CLOCK: 774 return netsio_read(sc, TL_NETSIO_MCLK); 775 break; 776 case MII_TXEN: 777 return netsio_read(sc, TL_NETSIO_MTXEN); 778 break; 779 default: 780 printf("tl_mii_read: unknown bit %d\n", bit); 781 return -1; 782 } 783 } 784 785 void tl_i2c_set(v, bit) 786 void *v; 787 u_int8_t bit; 788 { 789 tl_softc_t *sc = v; 790 791 switch (bit) { 792 case I2C_DATA: 793 netsio_set(sc, TL_NETSIO_EDATA); 794 break; 795 case I2C_CLOCK: 796 netsio_set(sc, TL_NETSIO_ECLOCK); 797 break; 798 case I2C_TXEN: 799 netsio_set(sc, TL_NETSIO_ETXEN); 800 break; 801 default: 802 printf("tl_i2c_set: unknown bit %d\n", bit); 803 } 804 return; 805 } 806 807 void tl_i2c_clr(v, bit) 808 void *v; 809 u_int8_t bit; 810 { 811 tl_softc_t *sc = v; 812 813 switch (bit) { 814 case I2C_DATA: 815 netsio_clr(sc, TL_NETSIO_EDATA); 816 break; 817 case I2C_CLOCK: 818 netsio_clr(sc, TL_NETSIO_ECLOCK); 819 break; 820 case I2C_TXEN: 821 netsio_clr(sc, TL_NETSIO_ETXEN); 822 break; 823 default: 824 printf("tl_i2c_clr: unknown bit %d\n", bit); 825 } 826 return; 827 } 828 829 int tl_i2c_read(v, bit) 830 void *v; 831 u_int8_t bit; 832 { 833 tl_softc_t *sc = v; 834 835 switch (bit) { 836 case I2C_DATA: 837 return netsio_read(sc, TL_NETSIO_EDATA); 838 break; 839 case I2C_CLOCK: 840 return netsio_read(sc, TL_NETSIO_ECLOCK); 841 break; 842 case I2C_TXEN: 843 return netsio_read(sc, TL_NETSIO_ETXEN); 844 break; 845 default: 846 printf("tl_i2c_read: unknown bit %d\n", bit); 847 return -1; 848 } 849 } 850 851 static int 852 tl_intr(v) 853 void *v; 854 { 855 tl_softc_t *sc = v; 856 struct ifnet *ifp = &sc->tl_if; 857 struct Rx_list *Rx; 858 struct Tx_list *Tx; 859 struct mbuf *m; 860 u_int32_t int_type, int_reg; 861 int ack = 0; 862 int size; 863 864 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 865 int_type = int_reg & TL_INTR_MASK; 866 if (int_type == 0) 867 return 0; 868 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 869 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 870 int_type, int_reg); 871 #endif 872 /* disable interrupts */ 873 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 874 switch(int_type & TL_INTR_MASK) { 875 case TL_INTR_RxEOF: 876 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 877 /* dequeue and requeue at end of list */ 878 ack++; 879 Rx = sc->active_Rx; 880 sc->active_Rx = Rx->next; 881 m = Rx->m; 882 size = Rx->hw_list.stat >> 16; 883 #ifdef TLDEBUG_RX 884 printf("tl_intr: RX list complete, Rx %p, size=%d\n", Rx, size); 885 #endif 886 if (tl_add_RxBuff(Rx, m ) == 0) { 887 /* No new mbuf, reuse the same. This means that this packet 888 is lost */ 889 m = NULL; 890 #ifdef TL_PRIV_STATS 891 sc->ierr_nomem++; 892 #endif 893 #ifdef TLDEBUG 894 printf("%s: out of mbuf, lost input packet\n", 895 sc->sc_dev.dv_xname); 896 #endif 897 } 898 Rx->next = NULL; 899 Rx->hw_list.fwd = 0; 900 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 901 #ifdef DIAGNOSTIC 902 if (sc->last_Rx->hw_list.fwd & 0x7) 903 printf("%s: physical addr 0x%x of list not properly aligned\n", 904 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 905 #endif 906 sc->last_Rx->next = Rx; 907 sc->last_Rx = Rx; 908 909 /* deliver packet */ 910 if (m) { 911 struct ether_header *eh; 912 if (size < sizeof(struct ether_header)) { 913 m_freem(m); 914 continue; 915 } 916 m->m_pkthdr.rcvif = ifp; 917 m->m_pkthdr.len = m->m_len = 918 size - sizeof(struct ether_header); 919 eh = mtod(m, struct ether_header *); 920 #ifdef TLDEBUG_RX 921 printf("tl_intr: Rx packet:\n"); 922 ether_printheader(eh); 923 #endif 924 #if NBPFILTER > 0 925 if (ifp->if_bpf) { 926 bpf_tap(ifp->if_bpf, 927 mtod(m, caddr_t), 928 size); 929 /* 930 * Only pass this packet up 931 * if it is for us. 932 */ 933 if ((ifp->if_flags & IFF_PROMISC) && 934 (eh->ether_dhost[0] & 1) == 0 && /* !mcast and !bcast */ 935 bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 936 sizeof(eh->ether_dhost)) != 0) { 937 m_freem(m); 938 continue; 939 } 940 } 941 #endif /* NBPFILTER > 0 */ 942 m->m_data += sizeof(struct ether_header); 943 ether_input(ifp, eh, m); 944 } 945 } 946 #ifdef TLDEBUG_RX 947 printf("TL_INTR_RxEOF: ack %d\n", ack); 948 #else 949 if (ack == 0) { 950 printf("%s: EOF intr without anything to read !\n", 951 sc->sc_dev.dv_xname); 952 tl_reset(sc); 953 /* shedule reinit of the board */ 954 timeout(tl_restart, sc, 1); 955 return(1); 956 } 957 #endif 958 break; 959 case TL_INTR_RxEOC: 960 ack++; 961 #ifdef TLDEBUG_RX 962 printf("TL_INTR_RxEOC: ack %d\n", ack); 963 #endif 964 #ifdef DIAGNOSTIC 965 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 966 printf("%s: Rx EOC interrupt and active Rx list not cleared\n", 967 sc->sc_dev.dv_xname); 968 return 0; 969 } else 970 #endif 971 { 972 /* write adress of Rx list and send Rx GO command, ack interrupt 973 and enable interrupts in one command */ 974 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 975 vtophys(&sc->active_Rx->hw_list)); 976 TL_HR_WRITE(sc, TL_HOST_CMD, 977 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 978 HOST_CMD_ACK | HOST_CMD_IntOn); 979 return 1; 980 } 981 case TL_INTR_TxEOF: 982 case TL_INTR_TxEOC: 983 while ((Tx = sc->active_Tx) != NULL) { 984 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 985 break; 986 ack++; 987 #ifdef TLDEBUG_TX 988 printf("TL_INTR_TxEOC: list 0x%xp done\n", vtophys(&Tx->hw_list)); 989 #endif 990 Tx->hw_list.stat = 0; 991 m_freem(Tx->m); 992 Tx->m = NULL; 993 sc->active_Tx = Tx->next; 994 if (sc->active_Tx == NULL) 995 sc->last_Tx = NULL; 996 Tx->next = sc->Free_Tx; 997 sc->Free_Tx = Tx; 998 } 999 /* if this was an EOC, ACK immediatly */ 1000 if (int_type == TL_INTR_TxEOC) { 1001 #ifdef TLDEBUG_TX 1002 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", ack); 1003 #endif 1004 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | HOST_CMD_ACK | 1005 HOST_CMD_IntOn); 1006 if ( sc->active_Tx != NULL) { /* needs a Tx go command */ 1007 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1008 vtophys(&sc->active_Tx->hw_list)); 1009 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1010 } 1011 sc->tl_if.if_timer = 0; 1012 if (sc->tl_if.if_snd.ifq_head != NULL) 1013 tl_ifstart(&sc->tl_if); 1014 return 1; 1015 } 1016 #ifdef TLDEBUG 1017 else { 1018 printf("TL_INTR_TxEOF: ack %d\n", ack); 1019 } 1020 #endif 1021 sc->tl_if.if_timer = 0; 1022 if (sc->tl_if.if_snd.ifq_head != NULL) 1023 tl_ifstart(&sc->tl_if); 1024 break; 1025 case TL_INTR_Stat: 1026 ack++; 1027 #ifdef TLDEBUG 1028 printf("TL_INTR_Stat: ack %d\n", ack); 1029 #endif 1030 tl_read_stats(sc); 1031 break; 1032 case TL_INTR_Adc: 1033 if (int_reg & TL_INTVec_MASK) { 1034 /* adapter check conditions */ 1035 printf("%s: check condition, intvect=0x%x, ch_param=0x%x\n", 1036 sc->sc_dev.dv_xname, int_reg & TL_INTVec_MASK, 1037 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1038 tl_reset(sc); 1039 /* shedule reinit of the board */ 1040 timeout(tl_restart, sc, 1); 1041 return(1); 1042 } else { 1043 u_int8_t netstat; 1044 /* Network status */ 1045 netstat = tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1046 printf("%s: network status, NetSts=%x\n", 1047 sc->sc_dev.dv_xname, netstat); 1048 /* Ack interrupts */ 1049 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, netstat); 1050 ack++; 1051 } 1052 break; 1053 default: 1054 printf("%s: unhandled interrupt code %x!\n", 1055 sc->sc_dev.dv_xname, int_type); 1056 ack++; 1057 } 1058 1059 if (ack) { 1060 /* Ack the interrupt and enable interrupts */ 1061 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1062 HOST_CMD_IntOn); 1063 return 1; 1064 } 1065 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1066 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1067 return 0; 1068 } 1069 1070 static int 1071 tl_ifioctl(ifp, cmd, data) 1072 struct ifnet *ifp; 1073 ioctl_cmd_t cmd; 1074 caddr_t data; 1075 { 1076 struct tl_softc *sc = ifp->if_softc; 1077 struct ifreq *ifr = (struct ifreq *)data; 1078 int s, error; 1079 1080 s = splimp(); 1081 switch(cmd) { 1082 case SIOCSIFADDR: { 1083 struct ifaddr *ifa = (struct ifaddr *)data; 1084 sc->tl_if.if_flags |= IFF_UP; 1085 if ((error = tl_init(sc)) != NULL) { 1086 sc->tl_if.if_flags &= ~IFF_UP; 1087 break; 1088 } 1089 switch (ifa->ifa_addr->sa_family) { 1090 #ifdef INET 1091 case AF_INET: 1092 arp_ifinit(ifp, ifa); 1093 break; 1094 #endif 1095 #ifdef NS 1096 case AF_NS: { 1097 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1098 1099 if (ns_nullhost(*ina)) 1100 ina->x_host = *(union ns_host*) LLADDR(ifp->if_sadl); 1101 else 1102 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1103 ifp->if_addrlen); 1104 break; 1105 } 1106 #endif 1107 default: 1108 break; 1109 } 1110 break; 1111 } 1112 case SIOCSIFFLAGS: 1113 { 1114 u_int8_t reg; 1115 /* 1116 * If interface is marked up and not running, then start it. 1117 * If it is marked down and running, stop it. 1118 */ 1119 if (ifp->if_flags & IFF_UP) { 1120 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1121 error = tl_init(sc); 1122 /* all flags have been handled by init */ 1123 break; 1124 } 1125 error = 0; 1126 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1127 if (ifp->if_flags & IFF_PROMISC) 1128 reg |= TL_NETCOMMAND_CAF; 1129 else 1130 reg &= ~TL_NETCOMMAND_CAF; 1131 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1132 #ifdef TL_PRIV_STATS 1133 if (ifp->if_flags & IFF_LINK0) { 1134 ifp->if_flags &= ~IFF_LINK0; 1135 printf("%s errors statistics\n", sc->sc_dev.dv_xname); 1136 printf(" %4d RX buffer overrun\n",sc->ierr_overr); 1137 printf(" %4d RX code error\n", sc->ierr_code); 1138 printf(" %4d RX crc error\n", sc->ierr_crc); 1139 printf(" %4d RX out of memory\n", sc->ierr_nomem); 1140 printf(" %4d TX buffer underrun\n", sc->oerr_underr); 1141 printf(" %4d TX deffered frames\n", sc->oerr_deffered); 1142 printf(" %4d TX single collisions\n", sc->oerr_coll); 1143 printf(" %4d TX multi collisions\n", sc->oerr_multicoll); 1144 printf(" %4d TX exessive collisions\n", sc->oerr_exesscoll); 1145 printf(" %4d TX late collisions\n", sc->oerr_latecoll); 1146 printf(" %4d TX carrier loss\n", sc->oerr_carrloss); 1147 printf(" %4d TX mbuf copy\n", sc->oerr_mcopy); 1148 } 1149 #endif 1150 } else { 1151 if (ifp->if_flags & IFF_RUNNING) 1152 tl_shutdown(sc); 1153 error = 0; 1154 } 1155 break; 1156 } 1157 case SIOCADDMULTI: 1158 case SIOCDELMULTI: 1159 /* 1160 * Update multicast listeners 1161 */ 1162 if (cmd == SIOCADDMULTI) 1163 error = ether_addmulti(ifr, &sc->tl_ec); 1164 else 1165 error = ether_delmulti(ifr, &sc->tl_ec); 1166 if (error == ENETRESET) { 1167 tl_addr_filter(sc); 1168 error = 0; 1169 } 1170 break; 1171 case SIOCSIFMEDIA: 1172 case SIOCGIFMEDIA: 1173 error = ifmedia_ioctl(ifp, ifr, &sc->tl_ifmedia, cmd); 1174 break; 1175 default: 1176 error = EINVAL; 1177 } 1178 splx(s); 1179 return error; 1180 } 1181 1182 static void 1183 tl_ifstart(ifp) 1184 struct ifnet *ifp; 1185 { 1186 tl_softc_t *sc = ifp->if_softc; 1187 struct mbuf *m, *mb_head; 1188 struct Tx_list *Tx; 1189 int segment, size; 1190 1191 txloop: 1192 /* If we don't have more space ... */ 1193 if (sc->Free_Tx == NULL) { 1194 #ifdef TLDEBUG 1195 printf("tl_ifstart: No free TX list\n"); 1196 #endif 1197 return; 1198 } 1199 /* Grab a paquet for output */ 1200 IF_DEQUEUE(&ifp->if_snd, mb_head); 1201 if (mb_head == NULL) { 1202 #ifdef TLDEBUG_TX 1203 printf("tl_ifstart: nothing to send\n"); 1204 #endif 1205 return; 1206 } 1207 Tx = sc->Free_Tx; 1208 sc->Free_Tx = Tx->next; 1209 /* 1210 * Go through each of the mbufs in the chain and initialize 1211 * the transmit list descriptors with the physical address 1212 * and size of the mbuf. 1213 */ 1214 tbdinit: 1215 bzero(Tx, sizeof(struct Tx_list)); 1216 Tx->m = mb_head; 1217 size = 0; 1218 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1219 if (m->m_len != 0) { 1220 if (segment == TL_NSEG) 1221 break; 1222 size += m->m_len; 1223 Tx->hw_list.seg[segment].data_addr = 1224 vtophys(mtod(m, vm_offset_t)); 1225 Tx->hw_list.seg[segment].data_count = m->m_len; 1226 segment++; 1227 } 1228 } 1229 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1230 /* 1231 * We ran out of segments, or we will. We have to recopy this mbuf 1232 * chain first. 1233 */ 1234 struct mbuf *mn; 1235 #ifdef TLDEBUG_TX 1236 printf("tl_ifstart: need to copy mbuf\n"); 1237 #endif 1238 #ifdef TL_PRIV_STATS 1239 sc->oerr_mcopy++; 1240 #endif 1241 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1242 if (mn == NULL) { 1243 m_freem(mb_head); 1244 goto bad; 1245 } 1246 if (mb_head->m_pkthdr.len > MHLEN) { 1247 MCLGET(mn, M_DONTWAIT); 1248 if ((mn->m_flags & M_EXT) == 0) { 1249 m_freem(mn); 1250 m_freem(mb_head); 1251 goto bad; 1252 } 1253 } 1254 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1255 mtod(mn, caddr_t)); 1256 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1257 m_freem(mb_head); 1258 mb_head = mn; 1259 goto tbdinit; 1260 } 1261 /* We are at end of mbuf chain. check the size and 1262 * see if it needs to be extended 1263 */ 1264 if (size < ETHER_MIN_TX) { 1265 #ifdef DIAGNOSTIC 1266 if (segment >= TL_NSEG) { 1267 panic("tl_ifstart: to much segmets (%d)\n", segment); 1268 } 1269 #endif 1270 /* 1271 * add the nullbuf in the seg 1272 */ 1273 Tx->hw_list.seg[segment].data_count = 1274 ETHER_MIN_TX - size; 1275 Tx->hw_list.seg[segment].data_addr = 1276 vtophys(nullbuf); 1277 size = ETHER_MIN_TX; 1278 segment++; 1279 } 1280 /* The list is done, finish the list init */ 1281 Tx->hw_list.seg[segment-1].data_count |= 1282 TL_LAST_SEG; 1283 Tx->hw_list.stat = (size << 16) | 0x3000; 1284 #ifdef TLDEBUG_TX 1285 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1286 Tx->hw_list.stat); 1287 #if 0 1288 for(segment = 0; segment < TL_NSEG; segment++) { 1289 printf(" seg %d addr 0x%x len 0x%x\n", 1290 segment, 1291 Tx->hw_list.seg[segment].data_addr, 1292 Tx->hw_list.seg[segment].data_count); 1293 } 1294 #endif 1295 #endif 1296 sc->opkt++; 1297 if (sc->active_Tx == NULL) { 1298 sc->active_Tx = sc->last_Tx = Tx; 1299 #ifdef TLDEBUG_TX 1300 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1301 vtophys(&Tx->hw_list)); 1302 #endif 1303 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1304 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1305 } else { 1306 #ifdef TLDEBUG_TX 1307 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1308 vtophys(&Tx->hw_list)); 1309 #endif 1310 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1311 sc->last_Tx->next = Tx; 1312 sc->last_Tx = Tx; 1313 #ifdef DIAGNOSTIC 1314 if (sc->last_Tx->hw_list.fwd & 0x7) 1315 printf("%s: physical addr 0x%x of list not properly aligned\n", 1316 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1317 #endif 1318 } 1319 #if NBPFILTER > 0 1320 /* Pass packet to bpf if there is a listener */ 1321 if (ifp->if_bpf) 1322 bpf_mtap(ifp->if_bpf, mb_head); 1323 #endif 1324 /* Set a 5 second timer just in case we don't hear from the card again. */ 1325 ifp->if_timer = 5; 1326 1327 goto txloop; 1328 bad: 1329 #ifdef TLDEBUG 1330 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1331 #endif 1332 Tx->next = sc->Free_Tx; 1333 sc->Free_Tx = Tx; 1334 return; 1335 } 1336 1337 static void 1338 tl_ifwatchdog(ifp) 1339 struct ifnet *ifp; 1340 { 1341 tl_softc_t *sc = ifp->if_softc; 1342 1343 if ((ifp->if_flags & IFF_RUNNING) == 0) 1344 return; 1345 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1346 ifp->if_oerrors++; 1347 tl_init(sc); 1348 } 1349 1350 static int 1351 tl_mediachange(ifp) 1352 struct ifnet *ifp; 1353 { 1354 1355 tl_softc_t *sc = ifp->if_softc; 1356 int err; 1357 u_int32_t reg; 1358 int oldmedia; 1359 #ifdef TLDEBUG 1360 printf("tl_mediachange, media %x\n", sc->tl_ifmedia.ifm_media); 1361 #endif 1362 oldmedia = sc->mii.mii_media_active; 1363 sc->mii.mii_media_active = sc->tl_ifmedia.ifm_media; 1364 if ((err = mii_mediachg(&sc->mii)) != 0) 1365 sc->mii.mii_media_active = oldmedia; 1366 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 1367 if (sc->mii.mii_media_active & IFM_FDX) 1368 reg |= TL_NETCOMMAND_DUPLEX; 1369 else 1370 reg &= ~TL_NETCOMMAND_DUPLEX; 1371 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 1372 return err; 1373 } 1374 1375 static void 1376 tl_mediastatus(ifp, ifmr) 1377 struct ifnet *ifp; 1378 struct ifmediareq *ifmr; 1379 { 1380 tl_softc_t *sc = ifp->if_softc; 1381 if (IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_2 || 1382 IFM_SUBTYPE(sc->mii.mii_media_active) == IFM_10_5) 1383 if (sc->tl_flags & TL_IFACT) 1384 sc->mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 1385 else 1386 sc->mii.mii_media_status = IFM_AVALID; 1387 else 1388 mii_pollstat(&sc->mii); 1389 1390 ifmr->ifm_active = sc->mii.mii_media_active; 1391 ifmr->ifm_status = sc->mii.mii_media_status; 1392 } 1393 1394 static int tl_add_RxBuff(Rx, oldm) 1395 struct Rx_list *Rx; 1396 struct mbuf *oldm; 1397 { 1398 struct mbuf *m; 1399 1400 MGETHDR(m, M_DONTWAIT, MT_DATA); 1401 if (m != NULL) { 1402 MCLGET(m, M_DONTWAIT); 1403 if ((m->m_flags & M_EXT) == 0) { 1404 m_freem(m); 1405 if (oldm == NULL) 1406 return 0; 1407 m = oldm; 1408 m->m_data = m->m_ext.ext_buf; 1409 } 1410 } else { 1411 if (oldm == NULL) 1412 return 0; 1413 m = oldm; 1414 m->m_data = m->m_ext.ext_buf; 1415 } 1416 /* 1417 * Move the data pointer up so that the incoming data packet 1418 * will be 32-bit aligned. 1419 */ 1420 m->m_data += 2; 1421 1422 /* (re)init the Rx_list struct */ 1423 1424 Rx->m = m; 1425 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1426 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1427 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1428 return (m != oldm); 1429 } 1430 1431 static void tl_ticks(v) 1432 void *v; 1433 { 1434 tl_softc_t *sc = v; 1435 1436 tl_read_stats(sc); 1437 if (sc->opkt > 0) { 1438 if (sc->oerr_exesscoll > sc->opkt / 100) { /* exess collisions */ 1439 if (sc->tl_flags & TL_IFACT) /* only print once */ 1440 printf("%s: no carrier\n", sc->sc_dev.dv_xname); 1441 sc->tl_flags &= ~TL_IFACT; 1442 } else 1443 sc->tl_flags |= TL_IFACT; 1444 sc->oerr_exesscoll = sc->opkt = 0; 1445 sc->tl_lasttx = 0; 1446 } else { 1447 sc->tl_lasttx++; 1448 if (sc->tl_lasttx >= TL_IDLETIME) { 1449 /* 1450 * No TX activity in the last TL_IDLETIME seconds. 1451 * sends a LLC Class1 TEST pkt 1452 */ 1453 struct mbuf *m; 1454 int s; 1455 MGETHDR(m, M_DONTWAIT, MT_DATA); 1456 if (m != NULL) { 1457 #ifdef TLDEBUG 1458 printf("tl_ticks: sending LLC test pkt\n"); 1459 #endif 1460 bcopy(sc->tl_enaddr, 1461 mtod(m, struct ether_header *)->ether_dhost, 6); 1462 bcopy(sc->tl_enaddr, 1463 mtod(m, struct ether_header *)->ether_shost, 6); 1464 mtod(m, struct ether_header *)->ether_type = htons(3); 1465 mtod(m, unsigned char *)[14] = 0; 1466 mtod(m, unsigned char *)[15] = 0; 1467 mtod(m, unsigned char *)[16] = 0xE3; 1468 /* LLC Class1 TEST (no poll) */ 1469 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3; 1470 s = splnet(); 1471 IF_PREPEND(&sc->tl_if.if_snd, m); 1472 tl_ifstart(&sc->tl_if); 1473 splx(s); 1474 } 1475 } 1476 } 1477 1478 /* read statistics every seconds */ 1479 timeout(tl_ticks, v, hz); 1480 } 1481 1482 static void 1483 tl_read_stats(sc) 1484 tl_softc_t *sc; 1485 { 1486 u_int32_t reg; 1487 int ierr_overr; 1488 int ierr_code; 1489 int ierr_crc; 1490 int oerr_underr; 1491 int oerr_deffered; 1492 int oerr_coll; 1493 int oerr_multicoll; 1494 int oerr_exesscoll; 1495 int oerr_latecoll; 1496 int oerr_carrloss; 1497 struct ifnet *ifp = &sc->tl_if; 1498 1499 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1500 ifp->if_opackets += reg & 0x00ffffff; 1501 oerr_underr = reg >> 24; 1502 1503 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1504 ifp->if_ipackets += reg & 0x00ffffff; 1505 ierr_overr = reg >> 24; 1506 1507 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1508 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1509 ierr_code = (reg & TL_FERR_CODE) >> 24; 1510 oerr_deffered = (reg & TL_FERR_DEF); 1511 1512 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1513 oerr_multicoll = (reg & TL_COL_MULTI); 1514 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1515 1516 reg = tl_intreg_read(sc, TL_INT_LERR); 1517 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1518 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1519 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1520 1521 1522 sc->stats_exesscoll += oerr_exesscoll; 1523 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1524 oerr_carrloss; 1525 ifp->if_collisions += oerr_coll + oerr_multicoll; 1526 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1527 1528 if (ierr_overr) 1529 printf("%s: receiver ring buffer overrun\n", sc->sc_dev.dv_xname); 1530 if (oerr_underr) 1531 printf("%s: transmit buffer underrun\n", sc->sc_dev.dv_xname); 1532 #ifdef TL_PRIV_STATS 1533 sc->ierr_overr += ierr_overr; 1534 sc->ierr_code += ierr_code; 1535 sc->ierr_crc += ierr_crc; 1536 sc->oerr_underr += oerr_underr; 1537 sc->oerr_deffered += oerr_deffered; 1538 sc->oerr_coll += oerr_coll; 1539 sc->oerr_multicoll += oerr_multicoll; 1540 sc->oerr_exesscoll += oerr_exesscoll; 1541 sc->oerr_latecoll += oerr_latecoll; 1542 sc->oerr_carrloss += oerr_carrloss; 1543 #endif 1544 } 1545 1546 static void tl_addr_filter(sc) 1547 tl_softc_t *sc; 1548 { 1549 struct ether_multistep step; 1550 struct ether_multi *enm; 1551 u_int32_t hash[2] = {0, 0}; 1552 int i; 1553 1554 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1555 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1556 while (enm != NULL) { 1557 #ifdef TLDEBUG 1558 printf("tl_addr_filter: addrs %s %s\n", ether_sprintf(enm->enm_addrlo), ether_sprintf(enm->enm_addrhi)); 1559 #endif 1560 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1561 i = tl_multicast_hash(enm->enm_addrlo); 1562 hash[i/32] |= 1 << (i%32); 1563 } else { 1564 hash[0] = hash[1] = 0xffffffff; 1565 sc->tl_if.if_flags |= IFF_ALLMULTI; 1566 break; 1567 } 1568 ETHER_NEXT_MULTI(step, enm); 1569 } 1570 #ifdef TLDEBUG 1571 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1572 #endif 1573 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1574 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1575 } 1576 1577 static int tl_multicast_hash(a) 1578 u_int8_t *a; 1579 { 1580 int hash; 1581 1582 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1583 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1584 1585 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1586 DA(a,36), DA(a,42)); 1587 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1588 DA(a,37), DA(a,43)) << 1; 1589 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1590 DA(a,38), DA(a,44)) << 2; 1591 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1592 DA(a,39), DA(a,45)) << 3; 1593 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1594 DA(a,40), DA(a,46)) << 4; 1595 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1596 DA(a,41), DA(a,47)) << 5; 1597 1598 return hash; 1599 } 1600 1601 #if defined(TLDEBUG_RX) 1602 void ether_printheader(eh) 1603 struct ether_header *eh; 1604 { 1605 u_char *c = (char*)eh; 1606 int i; 1607 for (i=0; i<sizeof(struct ether_header); i++) 1608 printf("%x ", (u_int)c[i]); 1609 printf("\n"); 1610 } 1611 #endif 1612
Indexes created Wed Sep 24 05:09:52 GMT 2025