if_tl.c revision 1.70
1 /* $NetBSD: if_tl.c,v 1.70 2005/05/30 04:35:22 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.70 2005/05/30 04:35:22 christos Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #include "rnd.h" 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #ifdef INET 83 #include <netinet/in.h> 84 #include <netinet/in_systm.h> 85 #include <netinet/in_var.h> 86 #include <netinet/ip.h> 87 #endif 88 89 #ifdef NS 90 #include <netns/ns.h> 91 #include <netns/ns_if.h> 92 #endif 93 94 #if defined(__NetBSD__) 95 #include <net/if_ether.h> 96 #include <uvm/uvm_extern.h> 97 #if defined(INET) 98 #include <netinet/if_inarp.h> 99 #endif 100 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/i2c/i2cvar.h> 109 #include <dev/i2c/i2c_bitbang.h> 110 #include <dev/i2c/at24cxxvar.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 115 #include <dev/mii/tlphyvar.h> 116 117 #include <dev/pci/if_tlregs.h> 118 #include <dev/pci/if_tlvar.h> 119 #endif /* __NetBSD__ */ 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 32 124 #endif 125 126 static int tl_pci_match(struct device *, struct cfdata *, void *); 127 static void tl_pci_attach(struct device *, struct device *, void *); 128 static int tl_intr(void *); 129 130 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, caddr_t); 131 static int tl_mediachange(struct ifnet *); 132 static void tl_mediastatus(struct ifnet *, struct ifmediareq *); 133 static void tl_ifwatchdog(struct ifnet *); 134 static void tl_shutdown(void*); 135 136 static void tl_ifstart(struct ifnet *); 137 static void tl_reset(tl_softc_t*); 138 static int tl_init(struct ifnet *); 139 static void tl_stop(struct ifnet *, int); 140 static void tl_restart(void *); 141 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 142 static void tl_read_stats(tl_softc_t*); 143 static void tl_ticks(void*); 144 static int tl_multicast_hash(u_int8_t*); 145 static void tl_addr_filter(tl_softc_t*); 146 147 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 148 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 149 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 150 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 151 152 void tl_mii_sync(struct tl_softc *); 153 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 154 155 156 #if defined(TLDEBUG_RX) 157 static void ether_printheader(struct ether_header*); 158 #endif 159 160 int tl_mii_read(struct device *, int, int); 161 void tl_mii_write(struct device *, int, int, int); 162 163 void tl_statchg(struct device *); 164 165 /* I2C glue */ 166 static int tl_i2c_acquire_bus(void *, int); 167 static void tl_i2c_release_bus(void *, int); 168 static int tl_i2c_send_start(void *, int); 169 static int tl_i2c_send_stop(void *, int); 170 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 171 static int tl_i2c_read_byte(void *, uint8_t *, int); 172 static int tl_i2c_write_byte(void *, uint8_t, int); 173 174 /* I2C bit-bang glue */ 175 static void tl_i2cbb_set_bits(void *, uint32_t); 176 static void tl_i2cbb_set_dir(void *, uint32_t); 177 static uint32_t tl_i2cbb_read(void *); 178 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 179 tl_i2cbb_set_bits, 180 tl_i2cbb_set_dir, 181 tl_i2cbb_read, 182 { 183 TL_NETSIO_EDATA, /* SDA */ 184 TL_NETSIO_ECLOCK, /* SCL */ 185 TL_NETSIO_ETXEN, /* SDA is output */ 186 0, /* SDA is input */ 187 } 188 }; 189 190 static __inline void netsio_clr(tl_softc_t*, u_int8_t); 191 static __inline void netsio_set(tl_softc_t*, u_int8_t); 192 static __inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 193 static __inline void netsio_clr(sc, bits) 194 tl_softc_t* sc; 195 u_int8_t bits; 196 { 197 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 198 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 199 } 200 static __inline void netsio_set(sc, bits) 201 tl_softc_t* sc; 202 u_int8_t bits; 203 { 204 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 205 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 206 } 207 static __inline u_int8_t netsio_read(sc, bits) 208 tl_softc_t* sc; 209 u_int8_t bits; 210 { 211 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 212 } 213 214 CFATTACH_DECL(tl, sizeof(tl_softc_t), 215 tl_pci_match, tl_pci_attach, NULL, NULL); 216 217 const struct tl_product_desc tl_compaq_products[] = { 218 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 219 "Compaq Netelligent 10/100 TX" }, 220 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 221 "Integrated Compaq Netelligent 10/100 TX" }, 222 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 223 "Compaq Netelligent 10 T" }, 224 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 225 "Compaq Netelligent 10 T/2 UTP/Coax" }, 226 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 227 "Compaq Integrated NetFlex 3/P" }, 228 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 229 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 230 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 231 "Compaq Dual Port Netelligent 10/100 TX" }, 232 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 233 "Compaq Deskpro 4000 5233MMX" }, 234 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 235 "Compaq NetFlex 3/P w/ BNC" }, 236 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 237 "Compaq NetFlex 3/P" }, 238 { 0, 0, NULL }, 239 }; 240 241 const struct tl_product_desc tl_ti_products[] = { 242 /* 243 * Built-in Ethernet on the TI TravelMate 5000 244 * docking station; better product description? 245 */ 246 { PCI_PRODUCT_TI_TLAN, 0, 247 "Texas Instruments ThunderLAN" }, 248 { 0, 0, NULL }, 249 }; 250 251 struct tl_vendor_desc { 252 u_int32_t tv_vendor; 253 const struct tl_product_desc *tv_products; 254 }; 255 256 const struct tl_vendor_desc tl_vendors[] = { 257 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 258 { PCI_VENDOR_TI, tl_ti_products }, 259 { 0, NULL }, 260 }; 261 262 const struct tl_product_desc *tl_lookup_product(u_int32_t); 263 264 const struct tl_product_desc * 265 tl_lookup_product(id) 266 u_int32_t id; 267 { 268 const struct tl_product_desc *tp; 269 const struct tl_vendor_desc *tv; 270 271 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 272 if (PCI_VENDOR(id) == tv->tv_vendor) 273 break; 274 275 if ((tp = tv->tv_products) == NULL) 276 return (NULL); 277 278 for (; tp->tp_desc != NULL; tp++) 279 if (PCI_PRODUCT(id) == tp->tp_product) 280 break; 281 282 if (tp->tp_desc == NULL) 283 return (NULL); 284 285 return (tp); 286 } 287 288 static int 289 tl_pci_match(parent, match, aux) 290 struct device *parent; 291 struct cfdata *match; 292 void *aux; 293 { 294 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 295 296 if (tl_lookup_product(pa->pa_id) != NULL) 297 return (1); 298 299 return (0); 300 } 301 302 static void 303 tl_pci_attach(parent, self, aux) 304 struct device * parent; 305 struct device * self; 306 void * aux; 307 { 308 tl_softc_t *sc = (tl_softc_t *)self; 309 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 310 const struct tl_product_desc *tp; 311 struct ifnet * const ifp = &sc->tl_if; 312 bus_space_tag_t iot, memt; 313 bus_space_handle_t ioh, memh; 314 pci_intr_handle_t intrhandle; 315 const char *intrstr; 316 int ioh_valid, memh_valid; 317 int reg_io, reg_mem; 318 pcireg_t reg10, reg14; 319 pcireg_t csr; 320 321 printf("\n"); 322 323 callout_init(&sc->tl_tick_ch); 324 callout_init(&sc->tl_restart_ch); 325 326 tp = tl_lookup_product(pa->pa_id); 327 if (tp == NULL) 328 panic("tl_pci_attach: impossible"); 329 sc->tl_product = tp; 330 331 /* 332 * Map the card space. First we have to find the I/O and MEM 333 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 334 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 335 * The ThunderLAN manual is not consistent about this either (there 336 * are both cases in code examples). 337 */ 338 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 339 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 340 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 341 reg_io = 0x10; 342 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 343 reg_io = 0x14; 344 else 345 reg_io = 0; 346 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 347 reg_mem = 0x10; 348 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 349 reg_mem = 0x14; 350 else 351 reg_mem = 0; 352 353 if (reg_io != 0) 354 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 355 0, &iot, &ioh, NULL, NULL) == 0); 356 else 357 ioh_valid = 0; 358 if (reg_mem != 0) 359 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 360 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 361 0, &memt, &memh, NULL, NULL) == 0); 362 else 363 memh_valid = 0; 364 365 if (ioh_valid) { 366 sc->tl_bustag = iot; 367 sc->tl_bushandle = ioh; 368 } else if (memh_valid) { 369 sc->tl_bustag = memt; 370 sc->tl_bushandle = memh; 371 } else { 372 printf("%s: unable to map device registers\n", 373 sc->sc_dev.dv_xname); 374 return; 375 } 376 sc->tl_dmatag = pa->pa_dmat; 377 378 /* Enable the device. */ 379 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 380 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 381 csr | PCI_COMMAND_MASTER_ENABLE); 382 383 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 384 385 tl_reset(sc); 386 387 /* fill in the i2c tag */ 388 sc->sc_i2c.ic_cookie = sc; 389 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 390 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 391 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 392 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 393 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 394 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 395 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 396 397 #ifdef TLDEBUG 398 printf("default values of INTreg: 0x%x\n", 399 tl_intreg_read(sc, TL_INT_Defaults)); 400 #endif 401 402 /* read mac addr */ 403 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 404 sc->tl_enaddr, ETHER_ADDR_LEN)) { 405 printf("%s: error reading Ethernet address\n", 406 sc->sc_dev.dv_xname); 407 return; 408 } 409 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 410 ether_sprintf(sc->tl_enaddr)); 411 412 /* Map and establish interrupts */ 413 if (pci_intr_map(pa, &intrhandle)) { 414 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 415 return; 416 } 417 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 418 sc->tl_if.if_softc = sc; 419 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 420 tl_intr, sc); 421 if (sc->tl_ih == NULL) { 422 printf("%s: couldn't establish interrupt", 423 sc->sc_dev.dv_xname); 424 if (intrstr != NULL) 425 printf(" at %s", intrstr); 426 printf("\n"); 427 return; 428 } 429 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 430 431 /* init these pointers, so that tl_shutdown won't try to read them */ 432 sc->Rx_list = NULL; 433 sc->Tx_list = NULL; 434 435 /* allocate DMA-safe memory for control structs */ 436 if (bus_dmamem_alloc(sc->tl_dmatag, 437 PAGE_SIZE, 0, PAGE_SIZE, 438 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 439 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 440 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 441 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 442 printf("%s: can't allocate DMA memory for lists\n", 443 sc->sc_dev.dv_xname); 444 return; 445 } 446 /* 447 * Add shutdown hook so that DMA is disabled prior to reboot. Not 448 * doing 449 * reboot before the driver initializes. 450 */ 451 (void) shutdownhook_establish(tl_shutdown, ifp); 452 453 /* 454 * Initialize our media structures and probe the MII. 455 * 456 * Note that we don't care about the media instance. We 457 * are expecting to have multiple PHYs on the 10/100 cards, 458 * and on those cards we exclude the internal PHY from providing 459 * 10baseT. By ignoring the instance, it allows us to not have 460 * to specify it on the command line when switching media. 461 */ 462 sc->tl_mii.mii_ifp = ifp; 463 sc->tl_mii.mii_readreg = tl_mii_read; 464 sc->tl_mii.mii_writereg = tl_mii_write; 465 sc->tl_mii.mii_statchg = tl_statchg; 466 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 467 tl_mediastatus); 468 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 469 MII_OFFSET_ANY, 0); 470 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 471 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 472 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 473 } else 474 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 475 476 /* 477 * We can support 802.1Q VLAN-sized frames. 478 */ 479 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 480 481 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 482 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 483 ifp->if_ioctl = tl_ifioctl; 484 ifp->if_start = tl_ifstart; 485 ifp->if_watchdog = tl_ifwatchdog; 486 ifp->if_init = tl_init; 487 ifp->if_stop = tl_stop; 488 ifp->if_timer = 0; 489 IFQ_SET_READY(&ifp->if_snd); 490 if_attach(ifp); 491 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 492 493 #if NRND > 0 494 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 495 RND_TYPE_NET, 0); 496 #endif 497 } 498 499 static void 500 tl_reset(sc) 501 tl_softc_t *sc; 502 { 503 int i; 504 505 /* read stats */ 506 if (sc->tl_if.if_flags & IFF_RUNNING) { 507 callout_stop(&sc->tl_tick_ch); 508 tl_read_stats(sc); 509 } 510 /* Reset adapter */ 511 TL_HR_WRITE(sc, TL_HOST_CMD, 512 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 513 DELAY(100000); 514 /* Disable interrupts */ 515 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 516 /* setup aregs & hash */ 517 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 518 tl_intreg_write(sc, i, 0); 519 #ifdef TLDEBUG_ADDR 520 printf("Areg & hash registers: \n"); 521 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 522 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 523 #endif 524 /* Setup NetConfig */ 525 tl_intreg_write(sc, TL_INT_NetConfig, 526 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 527 /* Bsize: accept default */ 528 /* TX commit in Acommit: accept default */ 529 /* Load Ld_tmr and Ld_thr */ 530 /* Ld_tmr = 3 */ 531 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 532 /* Ld_thr = 0 */ 533 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 534 /* Unreset MII */ 535 netsio_set(sc, TL_NETSIO_NMRST); 536 DELAY(100000); 537 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 538 } 539 540 static void tl_shutdown(v) 541 void *v; 542 { 543 tl_stop(v, 1); 544 } 545 546 static void tl_stop(ifp, disable) 547 struct ifnet *ifp; 548 int disable; 549 { 550 tl_softc_t *sc = ifp->if_softc; 551 struct Tx_list *Tx; 552 int i; 553 554 if ((ifp->if_flags & IFF_RUNNING) == 0) 555 return; 556 /* disable interrupts */ 557 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 558 /* stop TX and RX channels */ 559 TL_HR_WRITE(sc, TL_HOST_CMD, 560 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 561 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 562 DELAY(100000); 563 564 /* stop statistics reading loop, read stats */ 565 callout_stop(&sc->tl_tick_ch); 566 tl_read_stats(sc); 567 568 /* Down the MII. */ 569 mii_down(&sc->tl_mii); 570 571 /* deallocate memory allocations */ 572 if (sc->Rx_list) { 573 for (i=0; i< TL_NBUF; i++) { 574 if (sc->Rx_list[i].m) { 575 bus_dmamap_unload(sc->tl_dmatag, 576 sc->Rx_list[i].m_dmamap); 577 m_freem(sc->Rx_list[i].m); 578 } 579 bus_dmamap_destroy(sc->tl_dmatag, 580 sc->Rx_list[i].m_dmamap); 581 sc->Rx_list[i].m = NULL; 582 } 583 free(sc->Rx_list, M_DEVBUF); 584 sc->Rx_list = NULL; 585 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 586 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 587 sc->hw_Rx_list = NULL; 588 while ((Tx = sc->active_Tx) != NULL) { 589 Tx->hw_list->stat = 0; 590 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 591 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 592 m_freem(Tx->m); 593 sc->active_Tx = Tx->next; 594 Tx->next = sc->Free_Tx; 595 sc->Free_Tx = Tx; 596 } 597 sc->last_Tx = NULL; 598 free(sc->Tx_list, M_DEVBUF); 599 sc->Tx_list = NULL; 600 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 601 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 602 sc->hw_Tx_list = NULL; 603 } 604 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 605 ifp->if_timer = 0; 606 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 607 } 608 609 static void tl_restart(v) 610 void *v; 611 { 612 tl_init(v); 613 } 614 615 static int tl_init(ifp) 616 struct ifnet *ifp; 617 { 618 tl_softc_t *sc = ifp->if_softc; 619 int i, s, error; 620 const char *errstring; 621 char *nullbuf; 622 623 s = splnet(); 624 /* cancel any pending IO */ 625 tl_stop(ifp, 1); 626 tl_reset(sc); 627 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 628 splx(s); 629 return 0; 630 } 631 /* Set various register to reasonable value */ 632 /* setup NetCmd in promisc mode if needed */ 633 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 634 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 635 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 636 /* Max receive size : MCLBYTES */ 637 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 638 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 639 (MCLBYTES >> 8) & 0xff); 640 641 /* init MAC addr */ 642 for (i = 0; i < ETHER_ADDR_LEN; i++) 643 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 644 /* add multicast filters */ 645 tl_addr_filter(sc); 646 #ifdef TLDEBUG_ADDR 647 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 648 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 649 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 650 #endif 651 652 /* Pre-allocate receivers mbuf, make the lists */ 653 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 654 M_NOWAIT|M_ZERO); 655 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 656 M_NOWAIT|M_ZERO); 657 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 658 errstring = "out of memory for lists"; 659 error = ENOMEM; 660 goto bad; 661 } 662 error = bus_dmamap_create(sc->tl_dmatag, 663 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 664 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 665 &sc->Rx_dmamap); 666 if (error == 0) 667 error = bus_dmamap_create(sc->tl_dmatag, 668 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 669 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 670 &sc->Tx_dmamap); 671 if (error == 0) 672 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 673 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 674 &sc->null_dmamap); 675 if (error) { 676 errstring = "can't allocate DMA maps for lists"; 677 goto bad; 678 } 679 memset(sc->ctrl, 0, PAGE_SIZE); 680 sc->hw_Rx_list = (void *)sc->ctrl; 681 sc->hw_Tx_list = 682 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 683 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 684 sizeof(struct tl_Tx_list) * TL_NBUF; 685 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 686 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 687 BUS_DMA_WAITOK); 688 if (error == 0) 689 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 690 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 691 BUS_DMA_WAITOK); 692 if (error == 0) 693 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 694 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 695 if (error) { 696 errstring = "can't DMA map DMA memory for lists"; 697 goto bad; 698 } 699 for (i=0; i< TL_NBUF; i++) { 700 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 701 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 702 &sc->Rx_list[i].m_dmamap); 703 if (error == 0) { 704 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 705 TL_NSEG, MCLBYTES, 0, 706 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 707 &sc->Tx_list[i].m_dmamap); 708 } 709 if (error) { 710 errstring = "can't allocate DMA maps for mbufs"; 711 goto bad; 712 } 713 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 714 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 715 + sizeof(struct tl_Rx_list) * i; 716 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 717 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 718 + sizeof(struct tl_Tx_list) * i; 719 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 720 errstring = "out of mbuf for receive list"; 721 error = ENOMEM; 722 goto bad; 723 } 724 if (i > 0) { /* chain the list */ 725 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 726 sc->hw_Rx_list[i - 1].fwd = 727 htole32(sc->Rx_list[i].hw_listaddr); 728 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 729 } 730 } 731 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 732 sc->Rx_list[TL_NBUF - 1].next = NULL; 733 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 734 sc->Tx_list[TL_NBUF - 1].next = NULL; 735 736 sc->active_Rx = &sc->Rx_list[0]; 737 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 738 sc->active_Tx = sc->last_Tx = NULL; 739 sc->Free_Tx = &sc->Tx_list[0]; 740 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 741 sizeof(struct tl_Rx_list) * TL_NBUF, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 744 sizeof(struct tl_Tx_list) * TL_NBUF, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 747 BUS_DMASYNC_PREWRITE); 748 749 /* set media */ 750 mii_mediachg(&sc->tl_mii); 751 752 /* start ticks calls */ 753 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 754 /* write address of Rx list and enable interrupts */ 755 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 756 TL_HR_WRITE(sc, TL_HOST_CMD, 757 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 758 sc->tl_if.if_flags |= IFF_RUNNING; 759 sc->tl_if.if_flags &= ~IFF_OACTIVE; 760 return 0; 761 bad: 762 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 763 splx(s); 764 return error; 765 } 766 767 768 static u_int32_t 769 tl_intreg_read(sc, reg) 770 tl_softc_t *sc; 771 u_int32_t reg; 772 { 773 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 774 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 775 } 776 777 static u_int8_t 778 tl_intreg_read_byte(sc, reg) 779 tl_softc_t *sc; 780 u_int32_t reg; 781 { 782 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 783 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 784 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 785 } 786 787 static void 788 tl_intreg_write(sc, reg, val) 789 tl_softc_t *sc; 790 u_int32_t reg; 791 u_int32_t val; 792 { 793 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 794 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 795 } 796 797 static void 798 tl_intreg_write_byte(sc, reg, val) 799 tl_softc_t *sc; 800 u_int32_t reg; 801 u_int8_t val; 802 { 803 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 804 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 805 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 806 } 807 808 void 809 tl_mii_sync(sc) 810 struct tl_softc *sc; 811 { 812 int i; 813 814 netsio_clr(sc, TL_NETSIO_MTXEN); 815 for (i = 0; i < 32; i++) { 816 netsio_clr(sc, TL_NETSIO_MCLK); 817 netsio_set(sc, TL_NETSIO_MCLK); 818 } 819 } 820 821 void 822 tl_mii_sendbits(sc, data, nbits) 823 struct tl_softc *sc; 824 u_int32_t data; 825 int nbits; 826 { 827 int i; 828 829 netsio_set(sc, TL_NETSIO_MTXEN); 830 for (i = 1 << (nbits - 1); i; i = i >> 1) { 831 netsio_clr(sc, TL_NETSIO_MCLK); 832 netsio_read(sc, TL_NETSIO_MCLK); 833 if (data & i) 834 netsio_set(sc, TL_NETSIO_MDATA); 835 else 836 netsio_clr(sc, TL_NETSIO_MDATA); 837 netsio_set(sc, TL_NETSIO_MCLK); 838 netsio_read(sc, TL_NETSIO_MCLK); 839 } 840 } 841 842 int 843 tl_mii_read(self, phy, reg) 844 struct device *self; 845 int phy, reg; 846 { 847 struct tl_softc *sc = (struct tl_softc *)self; 848 int val = 0, i, err; 849 850 /* 851 * Read the PHY register by manually driving the MII control lines. 852 */ 853 854 tl_mii_sync(sc); 855 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 856 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 857 tl_mii_sendbits(sc, phy, 5); 858 tl_mii_sendbits(sc, reg, 5); 859 860 netsio_clr(sc, TL_NETSIO_MTXEN); 861 netsio_clr(sc, TL_NETSIO_MCLK); 862 netsio_set(sc, TL_NETSIO_MCLK); 863 netsio_clr(sc, TL_NETSIO_MCLK); 864 865 err = netsio_read(sc, TL_NETSIO_MDATA); 866 netsio_set(sc, TL_NETSIO_MCLK); 867 868 /* Even if an error occurs, must still clock out the cycle. */ 869 for (i = 0; i < 16; i++) { 870 val <<= 1; 871 netsio_clr(sc, TL_NETSIO_MCLK); 872 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 873 val |= 1; 874 netsio_set(sc, TL_NETSIO_MCLK); 875 } 876 netsio_clr(sc, TL_NETSIO_MCLK); 877 netsio_set(sc, TL_NETSIO_MCLK); 878 879 return (err ? 0 : val); 880 } 881 882 void 883 tl_mii_write(self, phy, reg, val) 884 struct device *self; 885 int phy, reg, val; 886 { 887 struct tl_softc *sc = (struct tl_softc *)self; 888 889 /* 890 * Write the PHY register by manually driving the MII control lines. 891 */ 892 893 tl_mii_sync(sc); 894 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 895 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 896 tl_mii_sendbits(sc, phy, 5); 897 tl_mii_sendbits(sc, reg, 5); 898 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 899 tl_mii_sendbits(sc, val, 16); 900 901 netsio_clr(sc, TL_NETSIO_MCLK); 902 netsio_set(sc, TL_NETSIO_MCLK); 903 } 904 905 void 906 tl_statchg(self) 907 struct device *self; 908 { 909 tl_softc_t *sc = (struct tl_softc *)self; 910 u_int32_t reg; 911 912 #ifdef TLDEBUG 913 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 914 #endif 915 916 /* 917 * We must keep the ThunderLAN and the PHY in sync as 918 * to the status of full-duplex! 919 */ 920 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 921 if (sc->tl_mii.mii_media_active & IFM_FDX) 922 reg |= TL_NETCOMMAND_DUPLEX; 923 else 924 reg &= ~TL_NETCOMMAND_DUPLEX; 925 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 926 } 927 928 /********** I2C glue **********/ 929 930 static int 931 tl_i2c_acquire_bus(void *cookie, int flags) 932 { 933 934 /* private bus */ 935 return (0); 936 } 937 938 static void 939 tl_i2c_release_bus(void *cookie, int flags) 940 { 941 942 /* private bus */ 943 } 944 945 static int 946 tl_i2c_send_start(void *cookie, int flags) 947 { 948 949 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 950 } 951 952 static int 953 tl_i2c_send_stop(void *cookie, int flags) 954 { 955 956 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 957 } 958 959 static int 960 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 961 { 962 963 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 964 } 965 966 static int 967 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 968 { 969 970 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 971 } 972 973 static int 974 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 975 { 976 977 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 978 } 979 980 /********** I2C bit-bang glue **********/ 981 982 static void 983 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 984 { 985 struct tl_softc *sc = cookie; 986 uint8_t reg; 987 988 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 989 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 990 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 991 } 992 993 static void 994 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 995 { 996 struct tl_softc *sc = cookie; 997 uint8_t reg; 998 999 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 1000 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 1001 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1002 } 1003 1004 static uint32_t 1005 tl_i2cbb_read(void *cookie) 1006 { 1007 1008 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1009 } 1010 1011 /********** End of I2C stuff **********/ 1012 1013 static int 1014 tl_intr(v) 1015 void *v; 1016 { 1017 tl_softc_t *sc = v; 1018 struct ifnet *ifp = &sc->tl_if; 1019 struct Rx_list *Rx; 1020 struct Tx_list *Tx; 1021 struct mbuf *m; 1022 u_int32_t int_type, int_reg; 1023 int ack = 0; 1024 int size; 1025 1026 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1027 int_type = int_reg & TL_INTR_MASK; 1028 if (int_type == 0) 1029 return 0; 1030 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1031 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1032 int_type, int_reg); 1033 #endif 1034 /* disable interrupts */ 1035 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1036 switch(int_type & TL_INTR_MASK) { 1037 case TL_INTR_RxEOF: 1038 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1039 sizeof(struct tl_Rx_list) * TL_NBUF, 1040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1041 while(le32toh(sc->active_Rx->hw_list->stat) & 1042 TL_RX_CSTAT_CPLT) { 1043 /* dequeue and requeue at end of list */ 1044 ack++; 1045 Rx = sc->active_Rx; 1046 sc->active_Rx = Rx->next; 1047 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1048 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1049 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1050 m = Rx->m; 1051 size = le32toh(Rx->hw_list->stat) >> 16; 1052 #ifdef TLDEBUG_RX 1053 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1054 Rx, size); 1055 #endif 1056 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1057 /* 1058 * No new mbuf, reuse the same. This means 1059 * that this packet 1060 * is lost 1061 */ 1062 m = NULL; 1063 #ifdef TL_PRIV_STATS 1064 sc->ierr_nomem++; 1065 #endif 1066 #ifdef TLDEBUG 1067 printf("%s: out of mbuf, lost input packet\n", 1068 sc->sc_dev.dv_xname); 1069 #endif 1070 } 1071 Rx->next = NULL; 1072 Rx->hw_list->fwd = 0; 1073 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1074 sc->last_Rx->next = Rx; 1075 sc->last_Rx = Rx; 1076 1077 /* deliver packet */ 1078 if (m) { 1079 if (size < sizeof(struct ether_header)) { 1080 m_freem(m); 1081 continue; 1082 } 1083 m->m_pkthdr.rcvif = ifp; 1084 m->m_pkthdr.len = m->m_len = size; 1085 #ifdef TLDEBUG_RX 1086 { struct ether_header *eh = 1087 mtod(m, struct ether_header *); 1088 printf("tl_intr: Rx packet:\n"); 1089 ether_printheader(eh); } 1090 #endif 1091 #if NBPFILTER > 0 1092 if (ifp->if_bpf) 1093 bpf_mtap(ifp->if_bpf, m); 1094 #endif /* NBPFILTER > 0 */ 1095 (*ifp->if_input)(ifp, m); 1096 } 1097 } 1098 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1099 sizeof(struct tl_Rx_list) * TL_NBUF, 1100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1101 #ifdef TLDEBUG_RX 1102 printf("TL_INTR_RxEOF: ack %d\n", ack); 1103 #else 1104 if (ack == 0) { 1105 printf("%s: EOF intr without anything to read !\n", 1106 sc->sc_dev.dv_xname); 1107 tl_reset(sc); 1108 /* shedule reinit of the board */ 1109 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1110 return(1); 1111 } 1112 #endif 1113 break; 1114 case TL_INTR_RxEOC: 1115 ack++; 1116 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1117 sizeof(struct tl_Rx_list) * TL_NBUF, 1118 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1119 #ifdef TLDEBUG_RX 1120 printf("TL_INTR_RxEOC: ack %d\n", ack); 1121 #endif 1122 #ifdef DIAGNOSTIC 1123 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1124 printf("%s: Rx EOC interrupt and active Tx list not " 1125 "cleared\n", sc->sc_dev.dv_xname); 1126 return 0; 1127 } else 1128 #endif 1129 { 1130 /* 1131 * write address of Rx list and send Rx GO command, ack 1132 * interrupt and enable interrupts in one command 1133 */ 1134 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1135 TL_HR_WRITE(sc, TL_HOST_CMD, 1136 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1137 HOST_CMD_ACK | HOST_CMD_IntOn); 1138 return 1; 1139 } 1140 case TL_INTR_TxEOF: 1141 case TL_INTR_TxEOC: 1142 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1143 sizeof(struct tl_Tx_list) * TL_NBUF, 1144 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1145 while ((Tx = sc->active_Tx) != NULL) { 1146 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1147 break; 1148 ack++; 1149 #ifdef TLDEBUG_TX 1150 printf("TL_INTR_TxEOC: list 0x%x done\n", 1151 (int)Tx->hw_listaddr); 1152 #endif 1153 Tx->hw_list->stat = 0; 1154 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1155 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1156 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1157 m_freem(Tx->m); 1158 Tx->m = NULL; 1159 sc->active_Tx = Tx->next; 1160 if (sc->active_Tx == NULL) 1161 sc->last_Tx = NULL; 1162 Tx->next = sc->Free_Tx; 1163 sc->Free_Tx = Tx; 1164 } 1165 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1166 sizeof(struct tl_Tx_list) * TL_NBUF, 1167 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1168 /* if this was an EOC, ACK immediatly */ 1169 if (ack) 1170 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1171 if (int_type == TL_INTR_TxEOC) { 1172 #ifdef TLDEBUG_TX 1173 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1174 ack); 1175 #endif 1176 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1177 HOST_CMD_ACK | HOST_CMD_IntOn); 1178 if ( sc->active_Tx != NULL) { 1179 /* needs a Tx go command */ 1180 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1181 sc->active_Tx->hw_listaddr); 1182 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1183 } 1184 sc->tl_if.if_timer = 0; 1185 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1186 tl_ifstart(&sc->tl_if); 1187 return 1; 1188 } 1189 #ifdef TLDEBUG 1190 else { 1191 printf("TL_INTR_TxEOF: ack %d\n", ack); 1192 } 1193 #endif 1194 sc->tl_if.if_timer = 0; 1195 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1196 tl_ifstart(&sc->tl_if); 1197 break; 1198 case TL_INTR_Stat: 1199 ack++; 1200 #ifdef TLDEBUG 1201 printf("TL_INTR_Stat: ack %d\n", ack); 1202 #endif 1203 tl_read_stats(sc); 1204 break; 1205 case TL_INTR_Adc: 1206 if (int_reg & TL_INTVec_MASK) { 1207 /* adapter check conditions */ 1208 printf("%s: check condition, intvect=0x%x, " 1209 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1210 int_reg & TL_INTVec_MASK, 1211 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1212 tl_reset(sc); 1213 /* shedule reinit of the board */ 1214 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1215 return(1); 1216 } else { 1217 u_int8_t netstat; 1218 /* Network status */ 1219 netstat = 1220 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1221 printf("%s: network status, NetSts=%x\n", 1222 sc->sc_dev.dv_xname, netstat); 1223 /* Ack interrupts */ 1224 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1225 netstat); 1226 ack++; 1227 } 1228 break; 1229 default: 1230 printf("%s: unhandled interrupt code %x!\n", 1231 sc->sc_dev.dv_xname, int_type); 1232 ack++; 1233 } 1234 1235 if (ack) { 1236 /* Ack the interrupt and enable interrupts */ 1237 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1238 HOST_CMD_IntOn); 1239 #if NRND > 0 1240 if (RND_ENABLED(&sc->rnd_source)) 1241 rnd_add_uint32(&sc->rnd_source, int_reg); 1242 #endif 1243 return 1; 1244 } 1245 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1246 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1247 return 0; 1248 } 1249 1250 static int 1251 tl_ifioctl(ifp, cmd, data) 1252 struct ifnet *ifp; 1253 ioctl_cmd_t cmd; 1254 caddr_t data; 1255 { 1256 struct tl_softc *sc = ifp->if_softc; 1257 struct ifreq *ifr = (struct ifreq *)data; 1258 int s, error; 1259 1260 s = splnet(); 1261 switch(cmd) { 1262 case SIOCSIFMEDIA: 1263 case SIOCGIFMEDIA: 1264 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1265 break; 1266 default: 1267 error = ether_ioctl(ifp, cmd, data); 1268 if (error == ENETRESET) { 1269 if (ifp->if_flags & IFF_RUNNING) 1270 tl_addr_filter(sc); 1271 error = 0; 1272 } 1273 } 1274 splx(s); 1275 return error; 1276 } 1277 1278 static void 1279 tl_ifstart(ifp) 1280 struct ifnet *ifp; 1281 { 1282 tl_softc_t *sc = ifp->if_softc; 1283 struct mbuf *mb_head; 1284 struct Tx_list *Tx; 1285 int segment, size; 1286 int again, error; 1287 1288 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1289 return; 1290 txloop: 1291 /* If we don't have more space ... */ 1292 if (sc->Free_Tx == NULL) { 1293 #ifdef TLDEBUG 1294 printf("tl_ifstart: No free TX list\n"); 1295 #endif 1296 sc->tl_if.if_flags |= IFF_OACTIVE; 1297 return; 1298 } 1299 /* Grab a paquet for output */ 1300 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1301 if (mb_head == NULL) { 1302 #ifdef TLDEBUG_TX 1303 printf("tl_ifstart: nothing to send\n"); 1304 #endif 1305 return; 1306 } 1307 Tx = sc->Free_Tx; 1308 sc->Free_Tx = Tx->next; 1309 Tx->next = NULL; 1310 again = 0; 1311 /* 1312 * Go through each of the mbufs in the chain and initialize 1313 * the transmit list descriptors with the physical address 1314 * and size of the mbuf. 1315 */ 1316 tbdinit: 1317 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1318 Tx->m = mb_head; 1319 size = mb_head->m_pkthdr.len; 1320 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1321 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1322 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1323 struct mbuf *mn; 1324 /* 1325 * We ran out of segments, or we will. We have to recopy this 1326 * mbuf chain first. 1327 */ 1328 if (error == 0) 1329 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1330 if (again) { 1331 /* already copyed, can't do much more */ 1332 m_freem(mb_head); 1333 goto bad; 1334 } 1335 again = 1; 1336 #ifdef TLDEBUG_TX 1337 printf("tl_ifstart: need to copy mbuf\n"); 1338 #endif 1339 #ifdef TL_PRIV_STATS 1340 sc->oerr_mcopy++; 1341 #endif 1342 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1343 if (mn == NULL) { 1344 m_freem(mb_head); 1345 goto bad; 1346 } 1347 if (mb_head->m_pkthdr.len > MHLEN) { 1348 MCLGET(mn, M_DONTWAIT); 1349 if ((mn->m_flags & M_EXT) == 0) { 1350 m_freem(mn); 1351 m_freem(mb_head); 1352 goto bad; 1353 } 1354 } 1355 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1356 mtod(mn, caddr_t)); 1357 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1358 m_freem(mb_head); 1359 mb_head = mn; 1360 goto tbdinit; 1361 } 1362 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1363 Tx->hw_list->seg[segment].data_addr = 1364 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1365 Tx->hw_list->seg[segment].data_count = 1366 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1367 } 1368 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1369 Tx->m_dmamap->dm_mapsize, 1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1371 /* We are at end of mbuf chain. check the size and 1372 * see if it needs to be extended 1373 */ 1374 if (size < ETHER_MIN_TX) { 1375 #ifdef DIAGNOSTIC 1376 if (segment >= TL_NSEG) { 1377 panic("tl_ifstart: to much segmets (%d)", segment); 1378 } 1379 #endif 1380 /* 1381 * add the nullbuf in the seg 1382 */ 1383 Tx->hw_list->seg[segment].data_count = 1384 htole32(ETHER_MIN_TX - size); 1385 Tx->hw_list->seg[segment].data_addr = 1386 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1387 size = ETHER_MIN_TX; 1388 segment++; 1389 } 1390 /* The list is done, finish the list init */ 1391 Tx->hw_list->seg[segment - 1].data_count |= 1392 htole32(TL_LAST_SEG); 1393 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1394 #ifdef TLDEBUG_TX 1395 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1396 le32toh(Tx->hw_list->stat)); 1397 #if 0 1398 for(segment = 0; segment < TL_NSEG; segment++) { 1399 printf(" seg %d addr 0x%x len 0x%x\n", 1400 segment, 1401 le32toh(Tx->hw_list->seg[segment].data_addr), 1402 le32toh(Tx->hw_list->seg[segment].data_count)); 1403 } 1404 #endif 1405 #endif 1406 if (sc->active_Tx == NULL) { 1407 sc->active_Tx = sc->last_Tx = Tx; 1408 #ifdef TLDEBUG_TX 1409 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1410 (int)Tx->hw_listaddr); 1411 #endif 1412 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1413 sizeof(struct tl_Tx_list) * TL_NBUF, 1414 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1415 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1416 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1417 } else { 1418 #ifdef TLDEBUG_TX 1419 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1420 (int)Tx->hw_listaddr); 1421 #endif 1422 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1423 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1424 sizeof(struct tl_Tx_list) * TL_NBUF, 1425 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1426 sc->last_Tx->next = Tx; 1427 sc->last_Tx = Tx; 1428 #ifdef DIAGNOSTIC 1429 if (sc->last_Tx->hw_list->fwd & 0x7) 1430 printf("%s: physical addr 0x%x of list not properly " 1431 "aligned\n", 1432 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1433 #endif 1434 } 1435 #if NBPFILTER > 0 1436 /* Pass packet to bpf if there is a listener */ 1437 if (ifp->if_bpf) 1438 bpf_mtap(ifp->if_bpf, mb_head); 1439 #endif 1440 /* 1441 * Set a 5 second timer just in case we don't hear from the card again. 1442 */ 1443 ifp->if_timer = 5; 1444 goto txloop; 1445 bad: 1446 #ifdef TLDEBUG 1447 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1448 #endif 1449 Tx->next = sc->Free_Tx; 1450 sc->Free_Tx = Tx; 1451 return; 1452 } 1453 1454 static void 1455 tl_ifwatchdog(ifp) 1456 struct ifnet *ifp; 1457 { 1458 tl_softc_t *sc = ifp->if_softc; 1459 1460 if ((ifp->if_flags & IFF_RUNNING) == 0) 1461 return; 1462 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1463 ifp->if_oerrors++; 1464 tl_init(ifp); 1465 } 1466 1467 static int 1468 tl_mediachange(ifp) 1469 struct ifnet *ifp; 1470 { 1471 1472 if (ifp->if_flags & IFF_UP) 1473 tl_init(ifp); 1474 return (0); 1475 } 1476 1477 static void 1478 tl_mediastatus(ifp, ifmr) 1479 struct ifnet *ifp; 1480 struct ifmediareq *ifmr; 1481 { 1482 tl_softc_t *sc = ifp->if_softc; 1483 1484 mii_pollstat(&sc->tl_mii); 1485 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1486 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1487 } 1488 1489 static int tl_add_RxBuff(sc, Rx, oldm) 1490 tl_softc_t *sc; 1491 struct Rx_list *Rx; 1492 struct mbuf *oldm; 1493 { 1494 struct mbuf *m; 1495 int error; 1496 1497 MGETHDR(m, M_DONTWAIT, MT_DATA); 1498 if (m != NULL) { 1499 MCLGET(m, M_DONTWAIT); 1500 if ((m->m_flags & M_EXT) == 0) { 1501 m_freem(m); 1502 if (oldm == NULL) 1503 return 0; 1504 m = oldm; 1505 m->m_data = m->m_ext.ext_buf; 1506 } 1507 } else { 1508 if (oldm == NULL) 1509 return 0; 1510 m = oldm; 1511 m->m_data = m->m_ext.ext_buf; 1512 } 1513 1514 /* (re)init the Rx_list struct */ 1515 1516 Rx->m = m; 1517 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1518 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1519 printf("%s: bus_dmamap_load() failed (error %d) for " 1520 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1521 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1522 m_freem(m); 1523 Rx->m = NULL; 1524 return 0; 1525 } 1526 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1527 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1528 /* 1529 * Move the data pointer up so that the incoming data packet 1530 * will be 32-bit aligned. 1531 */ 1532 m->m_data += 2; 1533 1534 Rx->hw_list->stat = 1535 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1536 Rx->hw_list->seg.data_count = 1537 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1538 Rx->hw_list->seg.data_addr = 1539 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1540 return (m != oldm); 1541 } 1542 1543 static void tl_ticks(v) 1544 void *v; 1545 { 1546 tl_softc_t *sc = v; 1547 1548 tl_read_stats(sc); 1549 1550 /* Tick the MII. */ 1551 mii_tick(&sc->tl_mii); 1552 1553 /* read statistics every seconds */ 1554 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1555 } 1556 1557 static void 1558 tl_read_stats(sc) 1559 tl_softc_t *sc; 1560 { 1561 u_int32_t reg; 1562 int ierr_overr; 1563 int ierr_code; 1564 int ierr_crc; 1565 int oerr_underr; 1566 int oerr_deferred; 1567 int oerr_coll; 1568 int oerr_multicoll; 1569 int oerr_exesscoll; 1570 int oerr_latecoll; 1571 int oerr_carrloss; 1572 struct ifnet *ifp = &sc->tl_if; 1573 1574 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1575 ifp->if_opackets += reg & 0x00ffffff; 1576 oerr_underr = reg >> 24; 1577 1578 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1579 ifp->if_ipackets += reg & 0x00ffffff; 1580 ierr_overr = reg >> 24; 1581 1582 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1583 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1584 ierr_code = (reg & TL_FERR_CODE) >> 24; 1585 oerr_deferred = (reg & TL_FERR_DEF); 1586 1587 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1588 oerr_multicoll = (reg & TL_COL_MULTI); 1589 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1590 1591 reg = tl_intreg_read(sc, TL_INT_LERR); 1592 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1593 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1594 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1595 1596 1597 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1598 oerr_carrloss; 1599 ifp->if_collisions += oerr_coll + oerr_multicoll; 1600 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1601 1602 if (ierr_overr) 1603 printf("%s: receiver ring buffer overrun\n", 1604 sc->sc_dev.dv_xname); 1605 if (oerr_underr) 1606 printf("%s: transmit buffer underrun\n", 1607 sc->sc_dev.dv_xname); 1608 #ifdef TL_PRIV_STATS 1609 sc->ierr_overr += ierr_overr; 1610 sc->ierr_code += ierr_code; 1611 sc->ierr_crc += ierr_crc; 1612 sc->oerr_underr += oerr_underr; 1613 sc->oerr_deferred += oerr_deferred; 1614 sc->oerr_coll += oerr_coll; 1615 sc->oerr_multicoll += oerr_multicoll; 1616 sc->oerr_exesscoll += oerr_exesscoll; 1617 sc->oerr_latecoll += oerr_latecoll; 1618 sc->oerr_carrloss += oerr_carrloss; 1619 #endif 1620 } 1621 1622 static void tl_addr_filter(sc) 1623 tl_softc_t *sc; 1624 { 1625 struct ether_multistep step; 1626 struct ether_multi *enm; 1627 u_int32_t hash[2] = {0, 0}; 1628 int i; 1629 1630 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1631 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1632 while (enm != NULL) { 1633 #ifdef TLDEBUG 1634 printf("tl_addr_filter: addrs %s %s\n", 1635 ether_sprintf(enm->enm_addrlo), 1636 ether_sprintf(enm->enm_addrhi)); 1637 #endif 1638 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1639 i = tl_multicast_hash(enm->enm_addrlo); 1640 hash[i/32] |= 1 << (i%32); 1641 } else { 1642 hash[0] = hash[1] = 0xffffffff; 1643 sc->tl_if.if_flags |= IFF_ALLMULTI; 1644 break; 1645 } 1646 ETHER_NEXT_MULTI(step, enm); 1647 } 1648 #ifdef TLDEBUG 1649 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1650 #endif 1651 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1652 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1653 } 1654 1655 static int tl_multicast_hash(a) 1656 u_int8_t *a; 1657 { 1658 int hash; 1659 1660 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1661 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1662 1663 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1664 DA(a,36), DA(a,42)); 1665 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1666 DA(a,37), DA(a,43)) << 1; 1667 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1668 DA(a,38), DA(a,44)) << 2; 1669 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1670 DA(a,39), DA(a,45)) << 3; 1671 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1672 DA(a,40), DA(a,46)) << 4; 1673 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1674 DA(a,41), DA(a,47)) << 5; 1675 1676 return hash; 1677 } 1678 1679 #if defined(TLDEBUG_RX) 1680 void 1681 ether_printheader(eh) 1682 struct ether_header *eh; 1683 { 1684 u_char *c = (char*)eh; 1685 int i; 1686 for (i=0; i<sizeof(struct ether_header); i++) 1687 printf("%x ", (u_int)c[i]); 1688 printf("\n"); 1689 } 1690 #endif 1691
Indexes created Tue Sep 23 07:09:52 GMT 2025