if_tl.c revision 1.72.4.1
1 /* $NetBSD: if_tl.c,v 1.72.4.1 2006/09/09 02:52:18 rpaulo Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.72.4.1 2006/09/09 02:52:18 rpaulo Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #include "rnd.h" 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #endif 87 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match(struct device *, struct cfdata *, void *); 122 static void tl_pci_attach(struct device *, struct device *, void *); 123 static int tl_intr(void *); 124 125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, caddr_t); 126 static int tl_mediachange(struct ifnet *); 127 static void tl_mediastatus(struct ifnet *, struct ifmediareq *); 128 static void tl_ifwatchdog(struct ifnet *); 129 static void tl_shutdown(void*); 130 131 static void tl_ifstart(struct ifnet *); 132 static void tl_reset(tl_softc_t*); 133 static int tl_init(struct ifnet *); 134 static void tl_stop(struct ifnet *, int); 135 static void tl_restart(void *); 136 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 137 static void tl_read_stats(tl_softc_t*); 138 static void tl_ticks(void*); 139 static int tl_multicast_hash(u_int8_t*); 140 static void tl_addr_filter(tl_softc_t*); 141 142 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 143 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 144 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 145 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 146 147 void tl_mii_sync(struct tl_softc *); 148 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 149 150 151 #if defined(TLDEBUG_RX) 152 static void ether_printheader(struct ether_header*); 153 #endif 154 155 int tl_mii_read(struct device *, int, int); 156 void tl_mii_write(struct device *, int, int, int); 157 158 void tl_statchg(struct device *); 159 160 /* I2C glue */ 161 static int tl_i2c_acquire_bus(void *, int); 162 static void tl_i2c_release_bus(void *, int); 163 static int tl_i2c_send_start(void *, int); 164 static int tl_i2c_send_stop(void *, int); 165 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int tl_i2c_read_byte(void *, uint8_t *, int); 167 static int tl_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bit-bang glue */ 170 static void tl_i2cbb_set_bits(void *, uint32_t); 171 static void tl_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t tl_i2cbb_read(void *); 173 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 174 tl_i2cbb_set_bits, 175 tl_i2cbb_set_dir, 176 tl_i2cbb_read, 177 { 178 TL_NETSIO_EDATA, /* SDA */ 179 TL_NETSIO_ECLOCK, /* SCL */ 180 TL_NETSIO_ETXEN, /* SDA is output */ 181 0, /* SDA is input */ 182 } 183 }; 184 185 static inline void netsio_clr(tl_softc_t*, u_int8_t); 186 static inline void netsio_set(tl_softc_t*, u_int8_t); 187 static inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 188 static inline void netsio_clr(sc, bits) 189 tl_softc_t* sc; 190 u_int8_t bits; 191 { 192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 194 } 195 static inline void netsio_set(sc, bits) 196 tl_softc_t* sc; 197 u_int8_t bits; 198 { 199 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 200 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 201 } 202 static inline u_int8_t netsio_read(sc, bits) 203 tl_softc_t* sc; 204 u_int8_t bits; 205 { 206 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 207 } 208 209 CFATTACH_DECL(tl, sizeof(tl_softc_t), 210 tl_pci_match, tl_pci_attach, NULL, NULL); 211 212 const struct tl_product_desc tl_compaq_products[] = { 213 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 214 "Compaq Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 216 "Integrated Compaq Netelligent 10/100 TX" }, 217 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 218 "Compaq Netelligent 10 T" }, 219 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 220 "Compaq Netelligent 10 T/2 UTP/Coax" }, 221 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 222 "Compaq Integrated NetFlex 3/P" }, 223 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 224 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 225 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 226 "Compaq Dual Port Netelligent 10/100 TX" }, 227 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 228 "Compaq Deskpro 4000 5233MMX" }, 229 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 230 "Compaq NetFlex 3/P w/ BNC" }, 231 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 232 "Compaq NetFlex 3/P" }, 233 { 0, 0, NULL }, 234 }; 235 236 const struct tl_product_desc tl_ti_products[] = { 237 /* 238 * Built-in Ethernet on the TI TravelMate 5000 239 * docking station; better product description? 240 */ 241 { PCI_PRODUCT_TI_TLAN, 0, 242 "Texas Instruments ThunderLAN" }, 243 { 0, 0, NULL }, 244 }; 245 246 struct tl_vendor_desc { 247 u_int32_t tv_vendor; 248 const struct tl_product_desc *tv_products; 249 }; 250 251 const struct tl_vendor_desc tl_vendors[] = { 252 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 253 { PCI_VENDOR_TI, tl_ti_products }, 254 { 0, NULL }, 255 }; 256 257 const struct tl_product_desc *tl_lookup_product(u_int32_t); 258 259 const struct tl_product_desc * 260 tl_lookup_product(id) 261 u_int32_t id; 262 { 263 const struct tl_product_desc *tp; 264 const struct tl_vendor_desc *tv; 265 266 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 267 if (PCI_VENDOR(id) == tv->tv_vendor) 268 break; 269 270 if ((tp = tv->tv_products) == NULL) 271 return (NULL); 272 273 for (; tp->tp_desc != NULL; tp++) 274 if (PCI_PRODUCT(id) == tp->tp_product) 275 break; 276 277 if (tp->tp_desc == NULL) 278 return (NULL); 279 280 return (tp); 281 } 282 283 static int 284 tl_pci_match(parent, match, aux) 285 struct device *parent; 286 struct cfdata *match; 287 void *aux; 288 { 289 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 290 291 if (tl_lookup_product(pa->pa_id) != NULL) 292 return (1); 293 294 return (0); 295 } 296 297 static void 298 tl_pci_attach(parent, self, aux) 299 struct device * parent; 300 struct device * self; 301 void * aux; 302 { 303 tl_softc_t *sc = (tl_softc_t *)self; 304 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 305 const struct tl_product_desc *tp; 306 struct ifnet * const ifp = &sc->tl_if; 307 bus_space_tag_t iot, memt; 308 bus_space_handle_t ioh, memh; 309 pci_intr_handle_t intrhandle; 310 const char *intrstr; 311 int ioh_valid, memh_valid; 312 int reg_io, reg_mem; 313 pcireg_t reg10, reg14; 314 pcireg_t csr; 315 316 printf("\n"); 317 318 callout_init(&sc->tl_tick_ch); 319 callout_init(&sc->tl_restart_ch); 320 321 tp = tl_lookup_product(pa->pa_id); 322 if (tp == NULL) 323 panic("tl_pci_attach: impossible"); 324 sc->tl_product = tp; 325 326 /* 327 * Map the card space. First we have to find the I/O and MEM 328 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 329 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 330 * The ThunderLAN manual is not consistent about this either (there 331 * are both cases in code examples). 332 */ 333 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 334 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 335 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 336 reg_io = 0x10; 337 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 338 reg_io = 0x14; 339 else 340 reg_io = 0; 341 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 342 reg_mem = 0x10; 343 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 344 reg_mem = 0x14; 345 else 346 reg_mem = 0; 347 348 if (reg_io != 0) 349 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 350 0, &iot, &ioh, NULL, NULL) == 0); 351 else 352 ioh_valid = 0; 353 if (reg_mem != 0) 354 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 355 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 356 0, &memt, &memh, NULL, NULL) == 0); 357 else 358 memh_valid = 0; 359 360 if (ioh_valid) { 361 sc->tl_bustag = iot; 362 sc->tl_bushandle = ioh; 363 } else if (memh_valid) { 364 sc->tl_bustag = memt; 365 sc->tl_bushandle = memh; 366 } else { 367 printf("%s: unable to map device registers\n", 368 sc->sc_dev.dv_xname); 369 return; 370 } 371 sc->tl_dmatag = pa->pa_dmat; 372 373 /* Enable the device. */ 374 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 375 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 376 csr | PCI_COMMAND_MASTER_ENABLE); 377 378 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 379 380 tl_reset(sc); 381 382 /* fill in the i2c tag */ 383 sc->sc_i2c.ic_cookie = sc; 384 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 385 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 386 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 387 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 388 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 389 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 390 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 391 392 #ifdef TLDEBUG 393 printf("default values of INTreg: 0x%x\n", 394 tl_intreg_read(sc, TL_INT_Defaults)); 395 #endif 396 397 /* read mac addr */ 398 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 399 sc->tl_enaddr, ETHER_ADDR_LEN)) { 400 printf("%s: error reading Ethernet address\n", 401 sc->sc_dev.dv_xname); 402 return; 403 } 404 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 405 ether_sprintf(sc->tl_enaddr)); 406 407 /* Map and establish interrupts */ 408 if (pci_intr_map(pa, &intrhandle)) { 409 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 410 return; 411 } 412 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 413 sc->tl_if.if_softc = sc; 414 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 415 tl_intr, sc); 416 if (sc->tl_ih == NULL) { 417 printf("%s: couldn't establish interrupt", 418 sc->sc_dev.dv_xname); 419 if (intrstr != NULL) 420 printf(" at %s", intrstr); 421 printf("\n"); 422 return; 423 } 424 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 425 426 /* init these pointers, so that tl_shutdown won't try to read them */ 427 sc->Rx_list = NULL; 428 sc->Tx_list = NULL; 429 430 /* allocate DMA-safe memory for control structs */ 431 if (bus_dmamem_alloc(sc->tl_dmatag, 432 PAGE_SIZE, 0, PAGE_SIZE, 433 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 434 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 435 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 436 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 437 printf("%s: can't allocate DMA memory for lists\n", 438 sc->sc_dev.dv_xname); 439 return; 440 } 441 /* 442 * Add shutdown hook so that DMA is disabled prior to reboot. Not 443 * doing 444 * reboot before the driver initializes. 445 */ 446 (void) shutdownhook_establish(tl_shutdown, ifp); 447 448 /* 449 * Initialize our media structures and probe the MII. 450 * 451 * Note that we don't care about the media instance. We 452 * are expecting to have multiple PHYs on the 10/100 cards, 453 * and on those cards we exclude the internal PHY from providing 454 * 10baseT. By ignoring the instance, it allows us to not have 455 * to specify it on the command line when switching media. 456 */ 457 sc->tl_mii.mii_ifp = ifp; 458 sc->tl_mii.mii_readreg = tl_mii_read; 459 sc->tl_mii.mii_writereg = tl_mii_write; 460 sc->tl_mii.mii_statchg = tl_statchg; 461 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 462 tl_mediastatus); 463 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 464 MII_OFFSET_ANY, 0); 465 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 466 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 467 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 468 } else 469 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 470 471 /* 472 * We can support 802.1Q VLAN-sized frames. 473 */ 474 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 475 476 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 477 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 478 ifp->if_ioctl = tl_ifioctl; 479 ifp->if_start = tl_ifstart; 480 ifp->if_watchdog = tl_ifwatchdog; 481 ifp->if_init = tl_init; 482 ifp->if_stop = tl_stop; 483 ifp->if_timer = 0; 484 IFQ_SET_READY(&ifp->if_snd); 485 if_attach(ifp); 486 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 487 488 #if NRND > 0 489 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 490 RND_TYPE_NET, 0); 491 #endif 492 } 493 494 static void 495 tl_reset(sc) 496 tl_softc_t *sc; 497 { 498 int i; 499 500 /* read stats */ 501 if (sc->tl_if.if_flags & IFF_RUNNING) { 502 callout_stop(&sc->tl_tick_ch); 503 tl_read_stats(sc); 504 } 505 /* Reset adapter */ 506 TL_HR_WRITE(sc, TL_HOST_CMD, 507 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 508 DELAY(100000); 509 /* Disable interrupts */ 510 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 511 /* setup aregs & hash */ 512 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 513 tl_intreg_write(sc, i, 0); 514 #ifdef TLDEBUG_ADDR 515 printf("Areg & hash registers: \n"); 516 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 517 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 518 #endif 519 /* Setup NetConfig */ 520 tl_intreg_write(sc, TL_INT_NetConfig, 521 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 522 /* Bsize: accept default */ 523 /* TX commit in Acommit: accept default */ 524 /* Load Ld_tmr and Ld_thr */ 525 /* Ld_tmr = 3 */ 526 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 527 /* Ld_thr = 0 */ 528 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 529 /* Unreset MII */ 530 netsio_set(sc, TL_NETSIO_NMRST); 531 DELAY(100000); 532 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 533 } 534 535 static void tl_shutdown(v) 536 void *v; 537 { 538 tl_stop(v, 1); 539 } 540 541 static void tl_stop(ifp, disable) 542 struct ifnet *ifp; 543 int disable; 544 { 545 tl_softc_t *sc = ifp->if_softc; 546 struct Tx_list *Tx; 547 int i; 548 549 if ((ifp->if_flags & IFF_RUNNING) == 0) 550 return; 551 /* disable interrupts */ 552 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 553 /* stop TX and RX channels */ 554 TL_HR_WRITE(sc, TL_HOST_CMD, 555 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 556 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 557 DELAY(100000); 558 559 /* stop statistics reading loop, read stats */ 560 callout_stop(&sc->tl_tick_ch); 561 tl_read_stats(sc); 562 563 /* Down the MII. */ 564 mii_down(&sc->tl_mii); 565 566 /* deallocate memory allocations */ 567 if (sc->Rx_list) { 568 for (i=0; i< TL_NBUF; i++) { 569 if (sc->Rx_list[i].m) { 570 bus_dmamap_unload(sc->tl_dmatag, 571 sc->Rx_list[i].m_dmamap); 572 m_freem(sc->Rx_list[i].m); 573 } 574 bus_dmamap_destroy(sc->tl_dmatag, 575 sc->Rx_list[i].m_dmamap); 576 sc->Rx_list[i].m = NULL; 577 } 578 free(sc->Rx_list, M_DEVBUF); 579 sc->Rx_list = NULL; 580 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 581 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 582 sc->hw_Rx_list = NULL; 583 while ((Tx = sc->active_Tx) != NULL) { 584 Tx->hw_list->stat = 0; 585 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 586 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 587 m_freem(Tx->m); 588 sc->active_Tx = Tx->next; 589 Tx->next = sc->Free_Tx; 590 sc->Free_Tx = Tx; 591 } 592 sc->last_Tx = NULL; 593 free(sc->Tx_list, M_DEVBUF); 594 sc->Tx_list = NULL; 595 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 596 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 597 sc->hw_Tx_list = NULL; 598 } 599 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 600 ifp->if_timer = 0; 601 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 602 } 603 604 static void tl_restart(v) 605 void *v; 606 { 607 tl_init(v); 608 } 609 610 static int tl_init(ifp) 611 struct ifnet *ifp; 612 { 613 tl_softc_t *sc = ifp->if_softc; 614 int i, s, error; 615 const char *errstring; 616 char *nullbuf; 617 618 s = splnet(); 619 /* cancel any pending IO */ 620 tl_stop(ifp, 1); 621 tl_reset(sc); 622 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 623 splx(s); 624 return 0; 625 } 626 /* Set various register to reasonable value */ 627 /* setup NetCmd in promisc mode if needed */ 628 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 629 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 630 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 631 /* Max receive size : MCLBYTES */ 632 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 633 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 634 (MCLBYTES >> 8) & 0xff); 635 636 /* init MAC addr */ 637 for (i = 0; i < ETHER_ADDR_LEN; i++) 638 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 639 /* add multicast filters */ 640 tl_addr_filter(sc); 641 #ifdef TLDEBUG_ADDR 642 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 643 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 644 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 645 #endif 646 647 /* Pre-allocate receivers mbuf, make the lists */ 648 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 649 M_NOWAIT|M_ZERO); 650 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 651 M_NOWAIT|M_ZERO); 652 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 653 errstring = "out of memory for lists"; 654 error = ENOMEM; 655 goto bad; 656 } 657 error = bus_dmamap_create(sc->tl_dmatag, 658 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 659 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 660 &sc->Rx_dmamap); 661 if (error == 0) 662 error = bus_dmamap_create(sc->tl_dmatag, 663 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 664 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 665 &sc->Tx_dmamap); 666 if (error == 0) 667 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 668 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 669 &sc->null_dmamap); 670 if (error) { 671 errstring = "can't allocate DMA maps for lists"; 672 goto bad; 673 } 674 memset(sc->ctrl, 0, PAGE_SIZE); 675 sc->hw_Rx_list = (void *)sc->ctrl; 676 sc->hw_Tx_list = 677 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 678 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 679 sizeof(struct tl_Tx_list) * TL_NBUF; 680 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 681 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 682 BUS_DMA_WAITOK); 683 if (error == 0) 684 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 685 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 686 BUS_DMA_WAITOK); 687 if (error == 0) 688 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 689 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 690 if (error) { 691 errstring = "can't DMA map DMA memory for lists"; 692 goto bad; 693 } 694 for (i=0; i< TL_NBUF; i++) { 695 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 696 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 697 &sc->Rx_list[i].m_dmamap); 698 if (error == 0) { 699 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 700 TL_NSEG, MCLBYTES, 0, 701 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 702 &sc->Tx_list[i].m_dmamap); 703 } 704 if (error) { 705 errstring = "can't allocate DMA maps for mbufs"; 706 goto bad; 707 } 708 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 709 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 710 + sizeof(struct tl_Rx_list) * i; 711 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 712 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 713 + sizeof(struct tl_Tx_list) * i; 714 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 715 errstring = "out of mbuf for receive list"; 716 error = ENOMEM; 717 goto bad; 718 } 719 if (i > 0) { /* chain the list */ 720 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 721 sc->hw_Rx_list[i - 1].fwd = 722 htole32(sc->Rx_list[i].hw_listaddr); 723 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 724 } 725 } 726 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 727 sc->Rx_list[TL_NBUF - 1].next = NULL; 728 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 729 sc->Tx_list[TL_NBUF - 1].next = NULL; 730 731 sc->active_Rx = &sc->Rx_list[0]; 732 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 733 sc->active_Tx = sc->last_Tx = NULL; 734 sc->Free_Tx = &sc->Tx_list[0]; 735 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 736 sizeof(struct tl_Rx_list) * TL_NBUF, 737 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 738 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 739 sizeof(struct tl_Tx_list) * TL_NBUF, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 742 BUS_DMASYNC_PREWRITE); 743 744 /* set media */ 745 mii_mediachg(&sc->tl_mii); 746 747 /* start ticks calls */ 748 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 749 /* write address of Rx list and enable interrupts */ 750 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 751 TL_HR_WRITE(sc, TL_HOST_CMD, 752 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 753 sc->tl_if.if_flags |= IFF_RUNNING; 754 sc->tl_if.if_flags &= ~IFF_OACTIVE; 755 return 0; 756 bad: 757 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 758 splx(s); 759 return error; 760 } 761 762 763 static u_int32_t 764 tl_intreg_read(sc, reg) 765 tl_softc_t *sc; 766 u_int32_t reg; 767 { 768 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 769 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 770 } 771 772 static u_int8_t 773 tl_intreg_read_byte(sc, reg) 774 tl_softc_t *sc; 775 u_int32_t reg; 776 { 777 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 778 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 779 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 780 } 781 782 static void 783 tl_intreg_write(sc, reg, val) 784 tl_softc_t *sc; 785 u_int32_t reg; 786 u_int32_t val; 787 { 788 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 789 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 790 } 791 792 static void 793 tl_intreg_write_byte(sc, reg, val) 794 tl_softc_t *sc; 795 u_int32_t reg; 796 u_int8_t val; 797 { 798 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 799 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 800 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 801 } 802 803 void 804 tl_mii_sync(sc) 805 struct tl_softc *sc; 806 { 807 int i; 808 809 netsio_clr(sc, TL_NETSIO_MTXEN); 810 for (i = 0; i < 32; i++) { 811 netsio_clr(sc, TL_NETSIO_MCLK); 812 netsio_set(sc, TL_NETSIO_MCLK); 813 } 814 } 815 816 void 817 tl_mii_sendbits(sc, data, nbits) 818 struct tl_softc *sc; 819 u_int32_t data; 820 int nbits; 821 { 822 int i; 823 824 netsio_set(sc, TL_NETSIO_MTXEN); 825 for (i = 1 << (nbits - 1); i; i = i >> 1) { 826 netsio_clr(sc, TL_NETSIO_MCLK); 827 netsio_read(sc, TL_NETSIO_MCLK); 828 if (data & i) 829 netsio_set(sc, TL_NETSIO_MDATA); 830 else 831 netsio_clr(sc, TL_NETSIO_MDATA); 832 netsio_set(sc, TL_NETSIO_MCLK); 833 netsio_read(sc, TL_NETSIO_MCLK); 834 } 835 } 836 837 int 838 tl_mii_read(self, phy, reg) 839 struct device *self; 840 int phy, reg; 841 { 842 struct tl_softc *sc = (struct tl_softc *)self; 843 int val = 0, i, err; 844 845 /* 846 * Read the PHY register by manually driving the MII control lines. 847 */ 848 849 tl_mii_sync(sc); 850 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 851 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 852 tl_mii_sendbits(sc, phy, 5); 853 tl_mii_sendbits(sc, reg, 5); 854 855 netsio_clr(sc, TL_NETSIO_MTXEN); 856 netsio_clr(sc, TL_NETSIO_MCLK); 857 netsio_set(sc, TL_NETSIO_MCLK); 858 netsio_clr(sc, TL_NETSIO_MCLK); 859 860 err = netsio_read(sc, TL_NETSIO_MDATA); 861 netsio_set(sc, TL_NETSIO_MCLK); 862 863 /* Even if an error occurs, must still clock out the cycle. */ 864 for (i = 0; i < 16; i++) { 865 val <<= 1; 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 868 val |= 1; 869 netsio_set(sc, TL_NETSIO_MCLK); 870 } 871 netsio_clr(sc, TL_NETSIO_MCLK); 872 netsio_set(sc, TL_NETSIO_MCLK); 873 874 return (err ? 0 : val); 875 } 876 877 void 878 tl_mii_write(self, phy, reg, val) 879 struct device *self; 880 int phy, reg, val; 881 { 882 struct tl_softc *sc = (struct tl_softc *)self; 883 884 /* 885 * Write the PHY register by manually driving the MII control lines. 886 */ 887 888 tl_mii_sync(sc); 889 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 890 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 891 tl_mii_sendbits(sc, phy, 5); 892 tl_mii_sendbits(sc, reg, 5); 893 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 894 tl_mii_sendbits(sc, val, 16); 895 896 netsio_clr(sc, TL_NETSIO_MCLK); 897 netsio_set(sc, TL_NETSIO_MCLK); 898 } 899 900 void 901 tl_statchg(self) 902 struct device *self; 903 { 904 tl_softc_t *sc = (struct tl_softc *)self; 905 u_int32_t reg; 906 907 #ifdef TLDEBUG 908 printf("tl_statchg, media %x\n", sc->tl_mii.mii_media.ifm_media); 909 #endif 910 911 /* 912 * We must keep the ThunderLAN and the PHY in sync as 913 * to the status of full-duplex! 914 */ 915 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 916 if (sc->tl_mii.mii_media_active & IFM_FDX) 917 reg |= TL_NETCOMMAND_DUPLEX; 918 else 919 reg &= ~TL_NETCOMMAND_DUPLEX; 920 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 921 } 922 923 /********** I2C glue **********/ 924 925 static int 926 tl_i2c_acquire_bus(void *cookie, int flags) 927 { 928 929 /* private bus */ 930 return (0); 931 } 932 933 static void 934 tl_i2c_release_bus(void *cookie, int flags) 935 { 936 937 /* private bus */ 938 } 939 940 static int 941 tl_i2c_send_start(void *cookie, int flags) 942 { 943 944 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 945 } 946 947 static int 948 tl_i2c_send_stop(void *cookie, int flags) 949 { 950 951 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 952 } 953 954 static int 955 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 956 { 957 958 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 959 } 960 961 static int 962 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 963 { 964 965 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 966 } 967 968 static int 969 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 970 { 971 972 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 973 } 974 975 /********** I2C bit-bang glue **********/ 976 977 static void 978 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 979 { 980 struct tl_softc *sc = cookie; 981 uint8_t reg; 982 983 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 984 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 985 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 986 } 987 988 static void 989 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 990 { 991 struct tl_softc *sc = cookie; 992 uint8_t reg; 993 994 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 995 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 996 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 997 } 998 999 static uint32_t 1000 tl_i2cbb_read(void *cookie) 1001 { 1002 1003 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1004 } 1005 1006 /********** End of I2C stuff **********/ 1007 1008 static int 1009 tl_intr(v) 1010 void *v; 1011 { 1012 tl_softc_t *sc = v; 1013 struct ifnet *ifp = &sc->tl_if; 1014 struct Rx_list *Rx; 1015 struct Tx_list *Tx; 1016 struct mbuf *m; 1017 u_int32_t int_type, int_reg; 1018 int ack = 0; 1019 int size; 1020 1021 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1022 int_type = int_reg & TL_INTR_MASK; 1023 if (int_type == 0) 1024 return 0; 1025 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1026 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1027 int_type, int_reg); 1028 #endif 1029 /* disable interrupts */ 1030 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1031 switch(int_type & TL_INTR_MASK) { 1032 case TL_INTR_RxEOF: 1033 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1034 sizeof(struct tl_Rx_list) * TL_NBUF, 1035 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1036 while(le32toh(sc->active_Rx->hw_list->stat) & 1037 TL_RX_CSTAT_CPLT) { 1038 /* dequeue and requeue at end of list */ 1039 ack++; 1040 Rx = sc->active_Rx; 1041 sc->active_Rx = Rx->next; 1042 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1043 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1044 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1045 m = Rx->m; 1046 size = le32toh(Rx->hw_list->stat) >> 16; 1047 #ifdef TLDEBUG_RX 1048 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1049 Rx, size); 1050 #endif 1051 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1052 /* 1053 * No new mbuf, reuse the same. This means 1054 * that this packet 1055 * is lost 1056 */ 1057 m = NULL; 1058 #ifdef TL_PRIV_STATS 1059 sc->ierr_nomem++; 1060 #endif 1061 #ifdef TLDEBUG 1062 printf("%s: out of mbuf, lost input packet\n", 1063 sc->sc_dev.dv_xname); 1064 #endif 1065 } 1066 Rx->next = NULL; 1067 Rx->hw_list->fwd = 0; 1068 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1069 sc->last_Rx->next = Rx; 1070 sc->last_Rx = Rx; 1071 1072 /* deliver packet */ 1073 if (m) { 1074 if (size < sizeof(struct ether_header)) { 1075 m_freem(m); 1076 continue; 1077 } 1078 m->m_pkthdr.rcvif = ifp; 1079 m->m_pkthdr.len = m->m_len = size; 1080 #ifdef TLDEBUG_RX 1081 { struct ether_header *eh = 1082 mtod(m, struct ether_header *); 1083 printf("tl_intr: Rx packet:\n"); 1084 ether_printheader(eh); } 1085 #endif 1086 #if NBPFILTER > 0 1087 if (ifp->if_bpf) 1088 bpf_mtap(ifp->if_bpf, m); 1089 #endif /* NBPFILTER > 0 */ 1090 (*ifp->if_input)(ifp, m); 1091 } 1092 } 1093 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1094 sizeof(struct tl_Rx_list) * TL_NBUF, 1095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1096 #ifdef TLDEBUG_RX 1097 printf("TL_INTR_RxEOF: ack %d\n", ack); 1098 #else 1099 if (ack == 0) { 1100 printf("%s: EOF intr without anything to read !\n", 1101 sc->sc_dev.dv_xname); 1102 tl_reset(sc); 1103 /* shedule reinit of the board */ 1104 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1105 return(1); 1106 } 1107 #endif 1108 break; 1109 case TL_INTR_RxEOC: 1110 ack++; 1111 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1112 sizeof(struct tl_Rx_list) * TL_NBUF, 1113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1114 #ifdef TLDEBUG_RX 1115 printf("TL_INTR_RxEOC: ack %d\n", ack); 1116 #endif 1117 #ifdef DIAGNOSTIC 1118 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1119 printf("%s: Rx EOC interrupt and active Tx list not " 1120 "cleared\n", sc->sc_dev.dv_xname); 1121 return 0; 1122 } else 1123 #endif 1124 { 1125 /* 1126 * write address of Rx list and send Rx GO command, ack 1127 * interrupt and enable interrupts in one command 1128 */ 1129 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1130 TL_HR_WRITE(sc, TL_HOST_CMD, 1131 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1132 HOST_CMD_ACK | HOST_CMD_IntOn); 1133 return 1; 1134 } 1135 case TL_INTR_TxEOF: 1136 case TL_INTR_TxEOC: 1137 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1138 sizeof(struct tl_Tx_list) * TL_NBUF, 1139 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1140 while ((Tx = sc->active_Tx) != NULL) { 1141 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1142 break; 1143 ack++; 1144 #ifdef TLDEBUG_TX 1145 printf("TL_INTR_TxEOC: list 0x%x done\n", 1146 (int)Tx->hw_listaddr); 1147 #endif 1148 Tx->hw_list->stat = 0; 1149 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1150 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1152 m_freem(Tx->m); 1153 Tx->m = NULL; 1154 sc->active_Tx = Tx->next; 1155 if (sc->active_Tx == NULL) 1156 sc->last_Tx = NULL; 1157 Tx->next = sc->Free_Tx; 1158 sc->Free_Tx = Tx; 1159 } 1160 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1161 sizeof(struct tl_Tx_list) * TL_NBUF, 1162 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1163 /* if this was an EOC, ACK immediatly */ 1164 if (ack) 1165 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1166 if (int_type == TL_INTR_TxEOC) { 1167 #ifdef TLDEBUG_TX 1168 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1169 ack); 1170 #endif 1171 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1172 HOST_CMD_ACK | HOST_CMD_IntOn); 1173 if ( sc->active_Tx != NULL) { 1174 /* needs a Tx go command */ 1175 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1176 sc->active_Tx->hw_listaddr); 1177 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1178 } 1179 sc->tl_if.if_timer = 0; 1180 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1181 tl_ifstart(&sc->tl_if); 1182 return 1; 1183 } 1184 #ifdef TLDEBUG 1185 else { 1186 printf("TL_INTR_TxEOF: ack %d\n", ack); 1187 } 1188 #endif 1189 sc->tl_if.if_timer = 0; 1190 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1191 tl_ifstart(&sc->tl_if); 1192 break; 1193 case TL_INTR_Stat: 1194 ack++; 1195 #ifdef TLDEBUG 1196 printf("TL_INTR_Stat: ack %d\n", ack); 1197 #endif 1198 tl_read_stats(sc); 1199 break; 1200 case TL_INTR_Adc: 1201 if (int_reg & TL_INTVec_MASK) { 1202 /* adapter check conditions */ 1203 printf("%s: check condition, intvect=0x%x, " 1204 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1205 int_reg & TL_INTVec_MASK, 1206 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1207 tl_reset(sc); 1208 /* shedule reinit of the board */ 1209 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1210 return(1); 1211 } else { 1212 u_int8_t netstat; 1213 /* Network status */ 1214 netstat = 1215 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1216 printf("%s: network status, NetSts=%x\n", 1217 sc->sc_dev.dv_xname, netstat); 1218 /* Ack interrupts */ 1219 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1220 netstat); 1221 ack++; 1222 } 1223 break; 1224 default: 1225 printf("%s: unhandled interrupt code %x!\n", 1226 sc->sc_dev.dv_xname, int_type); 1227 ack++; 1228 } 1229 1230 if (ack) { 1231 /* Ack the interrupt and enable interrupts */ 1232 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1233 HOST_CMD_IntOn); 1234 #if NRND > 0 1235 if (RND_ENABLED(&sc->rnd_source)) 1236 rnd_add_uint32(&sc->rnd_source, int_reg); 1237 #endif 1238 return 1; 1239 } 1240 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1241 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1242 return 0; 1243 } 1244 1245 static int 1246 tl_ifioctl(ifp, cmd, data) 1247 struct ifnet *ifp; 1248 ioctl_cmd_t cmd; 1249 caddr_t data; 1250 { 1251 struct tl_softc *sc = ifp->if_softc; 1252 struct ifreq *ifr = (struct ifreq *)data; 1253 int s, error; 1254 1255 s = splnet(); 1256 switch(cmd) { 1257 case SIOCSIFMEDIA: 1258 case SIOCGIFMEDIA: 1259 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1260 break; 1261 default: 1262 error = ether_ioctl(ifp, cmd, data); 1263 if (error == ENETRESET) { 1264 if (ifp->if_flags & IFF_RUNNING) 1265 tl_addr_filter(sc); 1266 error = 0; 1267 } 1268 } 1269 splx(s); 1270 return error; 1271 } 1272 1273 static void 1274 tl_ifstart(ifp) 1275 struct ifnet *ifp; 1276 { 1277 tl_softc_t *sc = ifp->if_softc; 1278 struct mbuf *mb_head; 1279 struct Tx_list *Tx; 1280 int segment, size; 1281 int again, error; 1282 1283 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1284 return; 1285 txloop: 1286 /* If we don't have more space ... */ 1287 if (sc->Free_Tx == NULL) { 1288 #ifdef TLDEBUG 1289 printf("tl_ifstart: No free TX list\n"); 1290 #endif 1291 sc->tl_if.if_flags |= IFF_OACTIVE; 1292 return; 1293 } 1294 /* Grab a paquet for output */ 1295 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1296 if (mb_head == NULL) { 1297 #ifdef TLDEBUG_TX 1298 printf("tl_ifstart: nothing to send\n"); 1299 #endif 1300 return; 1301 } 1302 Tx = sc->Free_Tx; 1303 sc->Free_Tx = Tx->next; 1304 Tx->next = NULL; 1305 again = 0; 1306 /* 1307 * Go through each of the mbufs in the chain and initialize 1308 * the transmit list descriptors with the physical address 1309 * and size of the mbuf. 1310 */ 1311 tbdinit: 1312 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1313 Tx->m = mb_head; 1314 size = mb_head->m_pkthdr.len; 1315 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1316 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1317 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1318 struct mbuf *mn; 1319 /* 1320 * We ran out of segments, or we will. We have to recopy this 1321 * mbuf chain first. 1322 */ 1323 if (error == 0) 1324 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1325 if (again) { 1326 /* already copyed, can't do much more */ 1327 m_freem(mb_head); 1328 goto bad; 1329 } 1330 again = 1; 1331 #ifdef TLDEBUG_TX 1332 printf("tl_ifstart: need to copy mbuf\n"); 1333 #endif 1334 #ifdef TL_PRIV_STATS 1335 sc->oerr_mcopy++; 1336 #endif 1337 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1338 if (mn == NULL) { 1339 m_freem(mb_head); 1340 goto bad; 1341 } 1342 if (mb_head->m_pkthdr.len > MHLEN) { 1343 MCLGET(mn, M_DONTWAIT); 1344 if ((mn->m_flags & M_EXT) == 0) { 1345 m_freem(mn); 1346 m_freem(mb_head); 1347 goto bad; 1348 } 1349 } 1350 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1351 mtod(mn, caddr_t)); 1352 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1353 m_freem(mb_head); 1354 mb_head = mn; 1355 goto tbdinit; 1356 } 1357 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1358 Tx->hw_list->seg[segment].data_addr = 1359 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1360 Tx->hw_list->seg[segment].data_count = 1361 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1362 } 1363 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1364 Tx->m_dmamap->dm_mapsize, 1365 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1366 /* We are at end of mbuf chain. check the size and 1367 * see if it needs to be extended 1368 */ 1369 if (size < ETHER_MIN_TX) { 1370 #ifdef DIAGNOSTIC 1371 if (segment >= TL_NSEG) { 1372 panic("tl_ifstart: to much segmets (%d)", segment); 1373 } 1374 #endif 1375 /* 1376 * add the nullbuf in the seg 1377 */ 1378 Tx->hw_list->seg[segment].data_count = 1379 htole32(ETHER_MIN_TX - size); 1380 Tx->hw_list->seg[segment].data_addr = 1381 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1382 size = ETHER_MIN_TX; 1383 segment++; 1384 } 1385 /* The list is done, finish the list init */ 1386 Tx->hw_list->seg[segment - 1].data_count |= 1387 htole32(TL_LAST_SEG); 1388 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1389 #ifdef TLDEBUG_TX 1390 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1391 le32toh(Tx->hw_list->stat)); 1392 #if 0 1393 for(segment = 0; segment < TL_NSEG; segment++) { 1394 printf(" seg %d addr 0x%x len 0x%x\n", 1395 segment, 1396 le32toh(Tx->hw_list->seg[segment].data_addr), 1397 le32toh(Tx->hw_list->seg[segment].data_count)); 1398 } 1399 #endif 1400 #endif 1401 if (sc->active_Tx == NULL) { 1402 sc->active_Tx = sc->last_Tx = Tx; 1403 #ifdef TLDEBUG_TX 1404 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1405 (int)Tx->hw_listaddr); 1406 #endif 1407 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1408 sizeof(struct tl_Tx_list) * TL_NBUF, 1409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1410 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1411 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1412 } else { 1413 #ifdef TLDEBUG_TX 1414 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1415 (int)Tx->hw_listaddr); 1416 #endif 1417 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1418 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1419 sizeof(struct tl_Tx_list) * TL_NBUF, 1420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1421 sc->last_Tx->next = Tx; 1422 sc->last_Tx = Tx; 1423 #ifdef DIAGNOSTIC 1424 if (sc->last_Tx->hw_list->fwd & 0x7) 1425 printf("%s: physical addr 0x%x of list not properly " 1426 "aligned\n", 1427 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1428 #endif 1429 } 1430 #if NBPFILTER > 0 1431 /* Pass packet to bpf if there is a listener */ 1432 if (ifp->if_bpf) 1433 bpf_mtap(ifp->if_bpf, mb_head); 1434 #endif 1435 /* 1436 * Set a 5 second timer just in case we don't hear from the card again. 1437 */ 1438 ifp->if_timer = 5; 1439 goto txloop; 1440 bad: 1441 #ifdef TLDEBUG 1442 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1443 #endif 1444 Tx->next = sc->Free_Tx; 1445 sc->Free_Tx = Tx; 1446 return; 1447 } 1448 1449 static void 1450 tl_ifwatchdog(ifp) 1451 struct ifnet *ifp; 1452 { 1453 tl_softc_t *sc = ifp->if_softc; 1454 1455 if ((ifp->if_flags & IFF_RUNNING) == 0) 1456 return; 1457 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1458 ifp->if_oerrors++; 1459 tl_init(ifp); 1460 } 1461 1462 static int 1463 tl_mediachange(ifp) 1464 struct ifnet *ifp; 1465 { 1466 1467 if (ifp->if_flags & IFF_UP) 1468 tl_init(ifp); 1469 return (0); 1470 } 1471 1472 static void 1473 tl_mediastatus(ifp, ifmr) 1474 struct ifnet *ifp; 1475 struct ifmediareq *ifmr; 1476 { 1477 tl_softc_t *sc = ifp->if_softc; 1478 1479 mii_pollstat(&sc->tl_mii); 1480 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1481 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1482 } 1483 1484 static int tl_add_RxBuff(sc, Rx, oldm) 1485 tl_softc_t *sc; 1486 struct Rx_list *Rx; 1487 struct mbuf *oldm; 1488 { 1489 struct mbuf *m; 1490 int error; 1491 1492 MGETHDR(m, M_DONTWAIT, MT_DATA); 1493 if (m != NULL) { 1494 MCLGET(m, M_DONTWAIT); 1495 if ((m->m_flags & M_EXT) == 0) { 1496 m_freem(m); 1497 if (oldm == NULL) 1498 return 0; 1499 m = oldm; 1500 m->m_data = m->m_ext.ext_buf; 1501 } 1502 } else { 1503 if (oldm == NULL) 1504 return 0; 1505 m = oldm; 1506 m->m_data = m->m_ext.ext_buf; 1507 } 1508 1509 /* (re)init the Rx_list struct */ 1510 1511 Rx->m = m; 1512 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1513 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1514 printf("%s: bus_dmamap_load() failed (error %d) for " 1515 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1516 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1517 m_freem(m); 1518 Rx->m = NULL; 1519 return 0; 1520 } 1521 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1522 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1523 /* 1524 * Move the data pointer up so that the incoming data packet 1525 * will be 32-bit aligned. 1526 */ 1527 m->m_data += 2; 1528 1529 Rx->hw_list->stat = 1530 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1531 Rx->hw_list->seg.data_count = 1532 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1533 Rx->hw_list->seg.data_addr = 1534 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1535 return (m != oldm); 1536 } 1537 1538 static void tl_ticks(v) 1539 void *v; 1540 { 1541 tl_softc_t *sc = v; 1542 1543 tl_read_stats(sc); 1544 1545 /* Tick the MII. */ 1546 mii_tick(&sc->tl_mii); 1547 1548 /* read statistics every seconds */ 1549 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1550 } 1551 1552 static void 1553 tl_read_stats(sc) 1554 tl_softc_t *sc; 1555 { 1556 u_int32_t reg; 1557 int ierr_overr; 1558 int ierr_code; 1559 int ierr_crc; 1560 int oerr_underr; 1561 int oerr_deferred; 1562 int oerr_coll; 1563 int oerr_multicoll; 1564 int oerr_exesscoll; 1565 int oerr_latecoll; 1566 int oerr_carrloss; 1567 struct ifnet *ifp = &sc->tl_if; 1568 1569 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1570 ifp->if_opackets += reg & 0x00ffffff; 1571 oerr_underr = reg >> 24; 1572 1573 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1574 ifp->if_ipackets += reg & 0x00ffffff; 1575 ierr_overr = reg >> 24; 1576 1577 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1578 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1579 ierr_code = (reg & TL_FERR_CODE) >> 24; 1580 oerr_deferred = (reg & TL_FERR_DEF); 1581 1582 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1583 oerr_multicoll = (reg & TL_COL_MULTI); 1584 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1585 1586 reg = tl_intreg_read(sc, TL_INT_LERR); 1587 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1588 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1589 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1590 1591 1592 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1593 oerr_carrloss; 1594 ifp->if_collisions += oerr_coll + oerr_multicoll; 1595 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1596 1597 if (ierr_overr) 1598 printf("%s: receiver ring buffer overrun\n", 1599 sc->sc_dev.dv_xname); 1600 if (oerr_underr) 1601 printf("%s: transmit buffer underrun\n", 1602 sc->sc_dev.dv_xname); 1603 #ifdef TL_PRIV_STATS 1604 sc->ierr_overr += ierr_overr; 1605 sc->ierr_code += ierr_code; 1606 sc->ierr_crc += ierr_crc; 1607 sc->oerr_underr += oerr_underr; 1608 sc->oerr_deferred += oerr_deferred; 1609 sc->oerr_coll += oerr_coll; 1610 sc->oerr_multicoll += oerr_multicoll; 1611 sc->oerr_exesscoll += oerr_exesscoll; 1612 sc->oerr_latecoll += oerr_latecoll; 1613 sc->oerr_carrloss += oerr_carrloss; 1614 #endif 1615 } 1616 1617 static void tl_addr_filter(sc) 1618 tl_softc_t *sc; 1619 { 1620 struct ether_multistep step; 1621 struct ether_multi *enm; 1622 u_int32_t hash[2] = {0, 0}; 1623 int i; 1624 1625 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1626 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1627 while (enm != NULL) { 1628 #ifdef TLDEBUG 1629 printf("tl_addr_filter: addrs %s %s\n", 1630 ether_sprintf(enm->enm_addrlo), 1631 ether_sprintf(enm->enm_addrhi)); 1632 #endif 1633 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1634 i = tl_multicast_hash(enm->enm_addrlo); 1635 hash[i/32] |= 1 << (i%32); 1636 } else { 1637 hash[0] = hash[1] = 0xffffffff; 1638 sc->tl_if.if_flags |= IFF_ALLMULTI; 1639 break; 1640 } 1641 ETHER_NEXT_MULTI(step, enm); 1642 } 1643 #ifdef TLDEBUG 1644 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1645 #endif 1646 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1647 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1648 } 1649 1650 static int tl_multicast_hash(a) 1651 u_int8_t *a; 1652 { 1653 int hash; 1654 1655 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1656 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1657 1658 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1659 DA(a,36), DA(a,42)); 1660 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1661 DA(a,37), DA(a,43)) << 1; 1662 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1663 DA(a,38), DA(a,44)) << 2; 1664 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1665 DA(a,39), DA(a,45)) << 3; 1666 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1667 DA(a,40), DA(a,46)) << 4; 1668 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1669 DA(a,41), DA(a,47)) << 5; 1670 1671 return hash; 1672 } 1673 1674 #if defined(TLDEBUG_RX) 1675 void 1676 ether_printheader(eh) 1677 struct ether_header *eh; 1678 { 1679 u_char *c = (char*)eh; 1680 int i; 1681 for (i=0; i<sizeof(struct ether_header); i++) 1682 printf("%x ", (u_int)c[i]); 1683 printf("\n"); 1684 } 1685 #endif 1686
Indexes created Sun Oct 19 02:09:48 GMT 2025