if_tl.c revision 1.79
1 /* $NetBSD: if_tl.c,v 1.79 2006/12/24 01:49:45 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.79 2006/12/24 01:49:45 rumble Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #include "rnd.h" 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #endif 87 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match(struct device *, struct cfdata *, void *); 122 static void tl_pci_attach(struct device *, struct device *, void *); 123 static int tl_intr(void *); 124 125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, caddr_t); 126 static int tl_mediachange(struct ifnet *); 127 static void tl_mediastatus(struct ifnet *, struct ifmediareq *); 128 static void tl_ifwatchdog(struct ifnet *); 129 static void tl_shutdown(void*); 130 131 static void tl_ifstart(struct ifnet *); 132 static void tl_reset(tl_softc_t*); 133 static int tl_init(struct ifnet *); 134 static void tl_stop(struct ifnet *, int); 135 static void tl_restart(void *); 136 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 137 static void tl_read_stats(tl_softc_t*); 138 static void tl_ticks(void*); 139 static int tl_multicast_hash(u_int8_t*); 140 static void tl_addr_filter(tl_softc_t*); 141 142 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 143 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 144 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 145 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 146 147 void tl_mii_sync(struct tl_softc *); 148 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 149 150 151 #if defined(TLDEBUG_RX) 152 static void ether_printheader(struct ether_header*); 153 #endif 154 155 int tl_mii_read(struct device *, int, int); 156 void tl_mii_write(struct device *, int, int, int); 157 158 void tl_statchg(struct device *); 159 160 /* I2C glue */ 161 static int tl_i2c_acquire_bus(void *, int); 162 static void tl_i2c_release_bus(void *, int); 163 static int tl_i2c_send_start(void *, int); 164 static int tl_i2c_send_stop(void *, int); 165 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int tl_i2c_read_byte(void *, uint8_t *, int); 167 static int tl_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bit-bang glue */ 170 static void tl_i2cbb_set_bits(void *, uint32_t); 171 static void tl_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t tl_i2cbb_read(void *); 173 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 174 tl_i2cbb_set_bits, 175 tl_i2cbb_set_dir, 176 tl_i2cbb_read, 177 { 178 TL_NETSIO_EDATA, /* SDA */ 179 TL_NETSIO_ECLOCK, /* SCL */ 180 TL_NETSIO_ETXEN, /* SDA is output */ 181 0, /* SDA is input */ 182 } 183 }; 184 185 static inline void netsio_clr(tl_softc_t*, u_int8_t); 186 static inline void netsio_set(tl_softc_t*, u_int8_t); 187 static inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 188 static inline void netsio_clr(sc, bits) 189 tl_softc_t* sc; 190 u_int8_t bits; 191 { 192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 194 } 195 static inline void netsio_set(sc, bits) 196 tl_softc_t* sc; 197 u_int8_t bits; 198 { 199 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 200 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 201 } 202 static inline u_int8_t netsio_read(sc, bits) 203 tl_softc_t* sc; 204 u_int8_t bits; 205 { 206 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 207 } 208 209 CFATTACH_DECL(tl, sizeof(tl_softc_t), 210 tl_pci_match, tl_pci_attach, NULL, NULL); 211 212 const struct tl_product_desc tl_compaq_products[] = { 213 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 214 "Compaq Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 216 "Integrated Compaq Netelligent 10/100 TX" }, 217 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 218 "Compaq Netelligent 10 T" }, 219 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 220 "Compaq Netelligent 10 T/2 UTP/Coax" }, 221 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 222 "Compaq Integrated NetFlex 3/P" }, 223 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 224 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 225 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 226 "Compaq Dual Port Netelligent 10/100 TX" }, 227 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 228 "Compaq Deskpro 4000 5233MMX" }, 229 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 230 "Compaq NetFlex 3/P w/ BNC" }, 231 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 232 "Compaq NetFlex 3/P" }, 233 { 0, 0, NULL }, 234 }; 235 236 const struct tl_product_desc tl_ti_products[] = { 237 /* 238 * Built-in Ethernet on the TI TravelMate 5000 239 * docking station; better product description? 240 */ 241 { PCI_PRODUCT_TI_TLAN, 0, 242 "Texas Instruments ThunderLAN" }, 243 { 0, 0, NULL }, 244 }; 245 246 struct tl_vendor_desc { 247 u_int32_t tv_vendor; 248 const struct tl_product_desc *tv_products; 249 }; 250 251 const struct tl_vendor_desc tl_vendors[] = { 252 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 253 { PCI_VENDOR_TI, tl_ti_products }, 254 { 0, NULL }, 255 }; 256 257 const struct tl_product_desc *tl_lookup_product(u_int32_t); 258 259 const struct tl_product_desc * 260 tl_lookup_product(id) 261 u_int32_t id; 262 { 263 const struct tl_product_desc *tp; 264 const struct tl_vendor_desc *tv; 265 266 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 267 if (PCI_VENDOR(id) == tv->tv_vendor) 268 break; 269 270 if ((tp = tv->tv_products) == NULL) 271 return (NULL); 272 273 for (; tp->tp_desc != NULL; tp++) 274 if (PCI_PRODUCT(id) == tp->tp_product) 275 break; 276 277 if (tp->tp_desc == NULL) 278 return (NULL); 279 280 return (tp); 281 } 282 283 static int 284 tl_pci_match(struct device *parent, struct cfdata *match, 285 void *aux) 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 288 289 if (tl_lookup_product(pa->pa_id) != NULL) 290 return (1); 291 292 return (0); 293 } 294 295 static void 296 tl_pci_attach(struct device *parent, struct device *self, void *aux) 297 { 298 tl_softc_t *sc = (tl_softc_t *)self; 299 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 300 const struct tl_product_desc *tp; 301 struct ifnet * const ifp = &sc->tl_if; 302 bus_space_tag_t iot, memt; 303 bus_space_handle_t ioh, memh; 304 pci_intr_handle_t intrhandle; 305 const char *intrstr; 306 int ioh_valid, memh_valid; 307 int reg_io, reg_mem; 308 pcireg_t reg10, reg14; 309 pcireg_t csr; 310 311 printf("\n"); 312 313 callout_init(&sc->tl_tick_ch); 314 callout_init(&sc->tl_restart_ch); 315 316 tp = tl_lookup_product(pa->pa_id); 317 if (tp == NULL) 318 panic("tl_pci_attach: impossible"); 319 sc->tl_product = tp; 320 321 /* 322 * Map the card space. First we have to find the I/O and MEM 323 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 324 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 325 * The ThunderLAN manual is not consistent about this either (there 326 * are both cases in code examples). 327 */ 328 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 329 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 330 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 331 reg_io = 0x10; 332 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 333 reg_io = 0x14; 334 else 335 reg_io = 0; 336 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 337 reg_mem = 0x10; 338 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 339 reg_mem = 0x14; 340 else 341 reg_mem = 0; 342 343 if (reg_io != 0) 344 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 345 0, &iot, &ioh, NULL, NULL) == 0); 346 else 347 ioh_valid = 0; 348 if (reg_mem != 0) 349 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 350 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 351 0, &memt, &memh, NULL, NULL) == 0); 352 else 353 memh_valid = 0; 354 355 if (ioh_valid) { 356 sc->tl_bustag = iot; 357 sc->tl_bushandle = ioh; 358 } else if (memh_valid) { 359 sc->tl_bustag = memt; 360 sc->tl_bushandle = memh; 361 } else { 362 printf("%s: unable to map device registers\n", 363 sc->sc_dev.dv_xname); 364 return; 365 } 366 sc->tl_dmatag = pa->pa_dmat; 367 368 /* Enable the device. */ 369 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 370 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 371 csr | PCI_COMMAND_MASTER_ENABLE); 372 373 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 374 375 tl_reset(sc); 376 377 /* fill in the i2c tag */ 378 sc->sc_i2c.ic_cookie = sc; 379 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 380 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 381 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 382 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 383 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 384 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 385 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 386 387 #ifdef TLDEBUG 388 printf("default values of INTreg: 0x%x\n", 389 tl_intreg_read(sc, TL_INT_Defaults)); 390 #endif 391 392 /* read mac addr */ 393 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 394 sc->tl_enaddr, ETHER_ADDR_LEN)) { 395 printf("%s: error reading Ethernet address\n", 396 sc->sc_dev.dv_xname); 397 return; 398 } 399 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 400 ether_sprintf(sc->tl_enaddr)); 401 402 /* Map and establish interrupts */ 403 if (pci_intr_map(pa, &intrhandle)) { 404 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 405 return; 406 } 407 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 408 sc->tl_if.if_softc = sc; 409 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 410 tl_intr, sc); 411 if (sc->tl_ih == NULL) { 412 printf("%s: couldn't establish interrupt", 413 sc->sc_dev.dv_xname); 414 if (intrstr != NULL) 415 printf(" at %s", intrstr); 416 printf("\n"); 417 return; 418 } 419 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 420 421 /* init these pointers, so that tl_shutdown won't try to read them */ 422 sc->Rx_list = NULL; 423 sc->Tx_list = NULL; 424 425 /* allocate DMA-safe memory for control structs */ 426 if (bus_dmamem_alloc(sc->tl_dmatag, 427 PAGE_SIZE, 0, PAGE_SIZE, 428 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 429 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 430 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 431 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 432 printf("%s: can't allocate DMA memory for lists\n", 433 sc->sc_dev.dv_xname); 434 return; 435 } 436 /* 437 * Add shutdown hook so that DMA is disabled prior to reboot. Not 438 * doing 439 * reboot before the driver initializes. 440 */ 441 (void) shutdownhook_establish(tl_shutdown, ifp); 442 443 /* 444 * Initialize our media structures and probe the MII. 445 * 446 * Note that we don't care about the media instance. We 447 * are expecting to have multiple PHYs on the 10/100 cards, 448 * and on those cards we exclude the internal PHY from providing 449 * 10baseT. By ignoring the instance, it allows us to not have 450 * to specify it on the command line when switching media. 451 */ 452 sc->tl_mii.mii_ifp = ifp; 453 sc->tl_mii.mii_readreg = tl_mii_read; 454 sc->tl_mii.mii_writereg = tl_mii_write; 455 sc->tl_mii.mii_statchg = tl_statchg; 456 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 457 tl_mediastatus); 458 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 459 MII_OFFSET_ANY, 0); 460 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 461 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 462 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 463 } else 464 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 465 466 /* 467 * We can support 802.1Q VLAN-sized frames. 468 */ 469 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 470 471 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 472 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 473 ifp->if_ioctl = tl_ifioctl; 474 ifp->if_start = tl_ifstart; 475 ifp->if_watchdog = tl_ifwatchdog; 476 ifp->if_init = tl_init; 477 ifp->if_stop = tl_stop; 478 ifp->if_timer = 0; 479 IFQ_SET_READY(&ifp->if_snd); 480 if_attach(ifp); 481 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 482 483 #if NRND > 0 484 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 485 RND_TYPE_NET, 0); 486 #endif 487 } 488 489 static void 490 tl_reset(sc) 491 tl_softc_t *sc; 492 { 493 int i; 494 495 /* read stats */ 496 if (sc->tl_if.if_flags & IFF_RUNNING) { 497 callout_stop(&sc->tl_tick_ch); 498 tl_read_stats(sc); 499 } 500 /* Reset adapter */ 501 TL_HR_WRITE(sc, TL_HOST_CMD, 502 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 503 DELAY(100000); 504 /* Disable interrupts */ 505 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 506 /* setup aregs & hash */ 507 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 508 tl_intreg_write(sc, i, 0); 509 #ifdef TLDEBUG_ADDR 510 printf("Areg & hash registers: \n"); 511 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 512 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 513 #endif 514 /* Setup NetConfig */ 515 tl_intreg_write(sc, TL_INT_NetConfig, 516 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 517 /* Bsize: accept default */ 518 /* TX commit in Acommit: accept default */ 519 /* Load Ld_tmr and Ld_thr */ 520 /* Ld_tmr = 3 */ 521 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 522 /* Ld_thr = 0 */ 523 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 524 /* Unreset MII */ 525 netsio_set(sc, TL_NETSIO_NMRST); 526 DELAY(100000); 527 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 528 } 529 530 static void tl_shutdown(v) 531 void *v; 532 { 533 tl_stop(v, 1); 534 } 535 536 static void tl_stop(struct ifnet *ifp, int disable) 537 { 538 tl_softc_t *sc = ifp->if_softc; 539 struct Tx_list *Tx; 540 int i; 541 542 if ((ifp->if_flags & IFF_RUNNING) == 0) 543 return; 544 /* disable interrupts */ 545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 546 /* stop TX and RX channels */ 547 TL_HR_WRITE(sc, TL_HOST_CMD, 548 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 549 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 550 DELAY(100000); 551 552 /* stop statistics reading loop, read stats */ 553 callout_stop(&sc->tl_tick_ch); 554 tl_read_stats(sc); 555 556 /* Down the MII. */ 557 mii_down(&sc->tl_mii); 558 559 /* deallocate memory allocations */ 560 if (sc->Rx_list) { 561 for (i=0; i< TL_NBUF; i++) { 562 if (sc->Rx_list[i].m) { 563 bus_dmamap_unload(sc->tl_dmatag, 564 sc->Rx_list[i].m_dmamap); 565 m_freem(sc->Rx_list[i].m); 566 } 567 bus_dmamap_destroy(sc->tl_dmatag, 568 sc->Rx_list[i].m_dmamap); 569 sc->Rx_list[i].m = NULL; 570 } 571 free(sc->Rx_list, M_DEVBUF); 572 sc->Rx_list = NULL; 573 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 574 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 575 sc->hw_Rx_list = NULL; 576 while ((Tx = sc->active_Tx) != NULL) { 577 Tx->hw_list->stat = 0; 578 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 579 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 580 m_freem(Tx->m); 581 sc->active_Tx = Tx->next; 582 Tx->next = sc->Free_Tx; 583 sc->Free_Tx = Tx; 584 } 585 sc->last_Tx = NULL; 586 free(sc->Tx_list, M_DEVBUF); 587 sc->Tx_list = NULL; 588 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 589 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 590 sc->hw_Tx_list = NULL; 591 } 592 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 593 ifp->if_timer = 0; 594 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 595 } 596 597 static void tl_restart(v) 598 void *v; 599 { 600 tl_init(v); 601 } 602 603 static int tl_init(ifp) 604 struct ifnet *ifp; 605 { 606 tl_softc_t *sc = ifp->if_softc; 607 int i, s, error; 608 bus_size_t boundary; 609 prop_number_t prop_boundary; 610 const char *errstring; 611 char *nullbuf; 612 613 s = splnet(); 614 /* cancel any pending IO */ 615 tl_stop(ifp, 1); 616 tl_reset(sc); 617 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 618 splx(s); 619 return 0; 620 } 621 /* Set various register to reasonable value */ 622 /* setup NetCmd in promisc mode if needed */ 623 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 624 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 625 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 626 /* Max receive size : MCLBYTES */ 627 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 628 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 629 (MCLBYTES >> 8) & 0xff); 630 631 /* init MAC addr */ 632 for (i = 0; i < ETHER_ADDR_LEN; i++) 633 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 634 /* add multicast filters */ 635 tl_addr_filter(sc); 636 #ifdef TLDEBUG_ADDR 637 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 638 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 639 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 640 #endif 641 642 /* Pre-allocate receivers mbuf, make the lists */ 643 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 644 M_NOWAIT|M_ZERO); 645 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 646 M_NOWAIT|M_ZERO); 647 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 648 errstring = "out of memory for lists"; 649 error = ENOMEM; 650 goto bad; 651 } 652 653 /* 654 * Some boards (Set Engineering GFE) do not permit DMA transfers 655 * across page boundaries. 656 */ 657 prop_boundary = prop_dictionary_get(device_properties(&sc->sc_dev), 658 "tl-dma-page-boundary"); 659 if (prop_boundary != NULL) { 660 KASSERT(prop_object_type(usetd) == PROP_TYPE_INTEGER); 661 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 662 } else { 663 boundary = 0; 664 } 665 666 error = bus_dmamap_create(sc->tl_dmatag, 667 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 668 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 669 &sc->Rx_dmamap); 670 if (error == 0) 671 error = bus_dmamap_create(sc->tl_dmatag, 672 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 673 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 674 BUS_DMA_WAITOK, &sc->Tx_dmamap); 675 if (error == 0) 676 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 677 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 678 &sc->null_dmamap); 679 if (error) { 680 errstring = "can't allocate DMA maps for lists"; 681 goto bad; 682 } 683 memset(sc->ctrl, 0, PAGE_SIZE); 684 sc->hw_Rx_list = (void *)sc->ctrl; 685 sc->hw_Tx_list = 686 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 687 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 688 sizeof(struct tl_Tx_list) * TL_NBUF; 689 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 690 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 691 BUS_DMA_WAITOK); 692 if (error == 0) 693 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 694 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 695 BUS_DMA_WAITOK); 696 if (error == 0) 697 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 698 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 699 if (error) { 700 errstring = "can't DMA map DMA memory for lists"; 701 goto bad; 702 } 703 for (i=0; i< TL_NBUF; i++) { 704 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 705 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 706 &sc->Rx_list[i].m_dmamap); 707 if (error == 0) { 708 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 709 TL_NSEG, MCLBYTES, boundary, 710 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 711 &sc->Tx_list[i].m_dmamap); 712 } 713 if (error) { 714 errstring = "can't allocate DMA maps for mbufs"; 715 goto bad; 716 } 717 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 718 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 719 + sizeof(struct tl_Rx_list) * i; 720 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 721 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 722 + sizeof(struct tl_Tx_list) * i; 723 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 724 errstring = "out of mbuf for receive list"; 725 error = ENOMEM; 726 goto bad; 727 } 728 if (i > 0) { /* chain the list */ 729 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 730 sc->hw_Rx_list[i - 1].fwd = 731 htole32(sc->Rx_list[i].hw_listaddr); 732 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 733 } 734 } 735 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 736 sc->Rx_list[TL_NBUF - 1].next = NULL; 737 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 738 sc->Tx_list[TL_NBUF - 1].next = NULL; 739 740 sc->active_Rx = &sc->Rx_list[0]; 741 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 742 sc->active_Tx = sc->last_Tx = NULL; 743 sc->Free_Tx = &sc->Tx_list[0]; 744 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 745 sizeof(struct tl_Rx_list) * TL_NBUF, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 748 sizeof(struct tl_Tx_list) * TL_NBUF, 749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 750 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 751 BUS_DMASYNC_PREWRITE); 752 753 /* set media */ 754 mii_mediachg(&sc->tl_mii); 755 756 /* start ticks calls */ 757 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 758 /* write address of Rx list and enable interrupts */ 759 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 760 TL_HR_WRITE(sc, TL_HOST_CMD, 761 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 762 sc->tl_if.if_flags |= IFF_RUNNING; 763 sc->tl_if.if_flags &= ~IFF_OACTIVE; 764 return 0; 765 bad: 766 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 767 splx(s); 768 return error; 769 } 770 771 772 static u_int32_t 773 tl_intreg_read(sc, reg) 774 tl_softc_t *sc; 775 u_int32_t reg; 776 { 777 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 778 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 779 } 780 781 static u_int8_t 782 tl_intreg_read_byte(sc, reg) 783 tl_softc_t *sc; 784 u_int32_t reg; 785 { 786 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 787 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 788 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 789 } 790 791 static void 792 tl_intreg_write(sc, reg, val) 793 tl_softc_t *sc; 794 u_int32_t reg; 795 u_int32_t val; 796 { 797 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 798 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 799 } 800 801 static void 802 tl_intreg_write_byte(sc, reg, val) 803 tl_softc_t *sc; 804 u_int32_t reg; 805 u_int8_t val; 806 { 807 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 808 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 809 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 810 } 811 812 void 813 tl_mii_sync(sc) 814 struct tl_softc *sc; 815 { 816 int i; 817 818 netsio_clr(sc, TL_NETSIO_MTXEN); 819 for (i = 0; i < 32; i++) { 820 netsio_clr(sc, TL_NETSIO_MCLK); 821 netsio_set(sc, TL_NETSIO_MCLK); 822 } 823 } 824 825 void 826 tl_mii_sendbits(sc, data, nbits) 827 struct tl_softc *sc; 828 u_int32_t data; 829 int nbits; 830 { 831 int i; 832 833 netsio_set(sc, TL_NETSIO_MTXEN); 834 for (i = 1 << (nbits - 1); i; i = i >> 1) { 835 netsio_clr(sc, TL_NETSIO_MCLK); 836 netsio_read(sc, TL_NETSIO_MCLK); 837 if (data & i) 838 netsio_set(sc, TL_NETSIO_MDATA); 839 else 840 netsio_clr(sc, TL_NETSIO_MDATA); 841 netsio_set(sc, TL_NETSIO_MCLK); 842 netsio_read(sc, TL_NETSIO_MCLK); 843 } 844 } 845 846 int 847 tl_mii_read(self, phy, reg) 848 struct device *self; 849 int phy, reg; 850 { 851 struct tl_softc *sc = (struct tl_softc *)self; 852 int val = 0, i, err; 853 854 /* 855 * Read the PHY register by manually driving the MII control lines. 856 */ 857 858 tl_mii_sync(sc); 859 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 860 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 861 tl_mii_sendbits(sc, phy, 5); 862 tl_mii_sendbits(sc, reg, 5); 863 864 netsio_clr(sc, TL_NETSIO_MTXEN); 865 netsio_clr(sc, TL_NETSIO_MCLK); 866 netsio_set(sc, TL_NETSIO_MCLK); 867 netsio_clr(sc, TL_NETSIO_MCLK); 868 869 err = netsio_read(sc, TL_NETSIO_MDATA); 870 netsio_set(sc, TL_NETSIO_MCLK); 871 872 /* Even if an error occurs, must still clock out the cycle. */ 873 for (i = 0; i < 16; i++) { 874 val <<= 1; 875 netsio_clr(sc, TL_NETSIO_MCLK); 876 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 877 val |= 1; 878 netsio_set(sc, TL_NETSIO_MCLK); 879 } 880 netsio_clr(sc, TL_NETSIO_MCLK); 881 netsio_set(sc, TL_NETSIO_MCLK); 882 883 return (err ? 0 : val); 884 } 885 886 void 887 tl_mii_write(self, phy, reg, val) 888 struct device *self; 889 int phy, reg, val; 890 { 891 struct tl_softc *sc = (struct tl_softc *)self; 892 893 /* 894 * Write the PHY register by manually driving the MII control lines. 895 */ 896 897 tl_mii_sync(sc); 898 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 899 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 900 tl_mii_sendbits(sc, phy, 5); 901 tl_mii_sendbits(sc, reg, 5); 902 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 903 tl_mii_sendbits(sc, val, 16); 904 905 netsio_clr(sc, TL_NETSIO_MCLK); 906 netsio_set(sc, TL_NETSIO_MCLK); 907 } 908 909 void 910 tl_statchg(self) 911 struct device *self; 912 { 913 tl_softc_t *sc = (struct tl_softc *)self; 914 u_int32_t reg; 915 916 #ifdef TLDEBUG 917 printf("tl_statchg, media %x\n", sc->tl_mii.mii_media.ifm_media); 918 #endif 919 920 /* 921 * We must keep the ThunderLAN and the PHY in sync as 922 * to the status of full-duplex! 923 */ 924 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 925 if (sc->tl_mii.mii_media_active & IFM_FDX) 926 reg |= TL_NETCOMMAND_DUPLEX; 927 else 928 reg &= ~TL_NETCOMMAND_DUPLEX; 929 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 930 } 931 932 /********** I2C glue **********/ 933 934 static int 935 tl_i2c_acquire_bus(void *cookie, int flags) 936 { 937 938 /* private bus */ 939 return (0); 940 } 941 942 static void 943 tl_i2c_release_bus(void *cookie, int flags) 944 { 945 946 /* private bus */ 947 } 948 949 static int 950 tl_i2c_send_start(void *cookie, int flags) 951 { 952 953 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 954 } 955 956 static int 957 tl_i2c_send_stop(void *cookie, int flags) 958 { 959 960 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 961 } 962 963 static int 964 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 965 { 966 967 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 968 } 969 970 static int 971 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 972 { 973 974 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 975 } 976 977 static int 978 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 979 { 980 981 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 982 } 983 984 /********** I2C bit-bang glue **********/ 985 986 static void 987 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 988 { 989 struct tl_softc *sc = cookie; 990 uint8_t reg; 991 992 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 993 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 994 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 995 } 996 997 static void 998 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 999 { 1000 struct tl_softc *sc = cookie; 1001 uint8_t reg; 1002 1003 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 1004 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 1005 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1006 } 1007 1008 static uint32_t 1009 tl_i2cbb_read(void *cookie) 1010 { 1011 1012 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1013 } 1014 1015 /********** End of I2C stuff **********/ 1016 1017 static int 1018 tl_intr(v) 1019 void *v; 1020 { 1021 tl_softc_t *sc = v; 1022 struct ifnet *ifp = &sc->tl_if; 1023 struct Rx_list *Rx; 1024 struct Tx_list *Tx; 1025 struct mbuf *m; 1026 u_int32_t int_type, int_reg; 1027 int ack = 0; 1028 int size; 1029 1030 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1031 int_type = int_reg & TL_INTR_MASK; 1032 if (int_type == 0) 1033 return 0; 1034 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1035 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1036 int_type, int_reg); 1037 #endif 1038 /* disable interrupts */ 1039 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1040 switch(int_type & TL_INTR_MASK) { 1041 case TL_INTR_RxEOF: 1042 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1043 sizeof(struct tl_Rx_list) * TL_NBUF, 1044 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1045 while(le32toh(sc->active_Rx->hw_list->stat) & 1046 TL_RX_CSTAT_CPLT) { 1047 /* dequeue and requeue at end of list */ 1048 ack++; 1049 Rx = sc->active_Rx; 1050 sc->active_Rx = Rx->next; 1051 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1052 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1053 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1054 m = Rx->m; 1055 size = le32toh(Rx->hw_list->stat) >> 16; 1056 #ifdef TLDEBUG_RX 1057 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1058 Rx, size); 1059 #endif 1060 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1061 /* 1062 * No new mbuf, reuse the same. This means 1063 * that this packet 1064 * is lost 1065 */ 1066 m = NULL; 1067 #ifdef TL_PRIV_STATS 1068 sc->ierr_nomem++; 1069 #endif 1070 #ifdef TLDEBUG 1071 printf("%s: out of mbuf, lost input packet\n", 1072 sc->sc_dev.dv_xname); 1073 #endif 1074 } 1075 Rx->next = NULL; 1076 Rx->hw_list->fwd = 0; 1077 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1078 sc->last_Rx->next = Rx; 1079 sc->last_Rx = Rx; 1080 1081 /* deliver packet */ 1082 if (m) { 1083 if (size < sizeof(struct ether_header)) { 1084 m_freem(m); 1085 continue; 1086 } 1087 m->m_pkthdr.rcvif = ifp; 1088 m->m_pkthdr.len = m->m_len = size; 1089 #ifdef TLDEBUG_RX 1090 { struct ether_header *eh = 1091 mtod(m, struct ether_header *); 1092 printf("tl_intr: Rx packet:\n"); 1093 ether_printheader(eh); } 1094 #endif 1095 #if NBPFILTER > 0 1096 if (ifp->if_bpf) 1097 bpf_mtap(ifp->if_bpf, m); 1098 #endif /* NBPFILTER > 0 */ 1099 (*ifp->if_input)(ifp, m); 1100 } 1101 } 1102 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1103 sizeof(struct tl_Rx_list) * TL_NBUF, 1104 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1105 #ifdef TLDEBUG_RX 1106 printf("TL_INTR_RxEOF: ack %d\n", ack); 1107 #else 1108 if (ack == 0) { 1109 printf("%s: EOF intr without anything to read !\n", 1110 sc->sc_dev.dv_xname); 1111 tl_reset(sc); 1112 /* shedule reinit of the board */ 1113 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1114 return(1); 1115 } 1116 #endif 1117 break; 1118 case TL_INTR_RxEOC: 1119 ack++; 1120 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1121 sizeof(struct tl_Rx_list) * TL_NBUF, 1122 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1123 #ifdef TLDEBUG_RX 1124 printf("TL_INTR_RxEOC: ack %d\n", ack); 1125 #endif 1126 #ifdef DIAGNOSTIC 1127 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1128 printf("%s: Rx EOC interrupt and active Tx list not " 1129 "cleared\n", sc->sc_dev.dv_xname); 1130 return 0; 1131 } else 1132 #endif 1133 { 1134 /* 1135 * write address of Rx list and send Rx GO command, ack 1136 * interrupt and enable interrupts in one command 1137 */ 1138 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1139 TL_HR_WRITE(sc, TL_HOST_CMD, 1140 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1141 HOST_CMD_ACK | HOST_CMD_IntOn); 1142 return 1; 1143 } 1144 case TL_INTR_TxEOF: 1145 case TL_INTR_TxEOC: 1146 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1147 sizeof(struct tl_Tx_list) * TL_NBUF, 1148 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1149 while ((Tx = sc->active_Tx) != NULL) { 1150 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1151 break; 1152 ack++; 1153 #ifdef TLDEBUG_TX 1154 printf("TL_INTR_TxEOC: list 0x%x done\n", 1155 (int)Tx->hw_listaddr); 1156 #endif 1157 Tx->hw_list->stat = 0; 1158 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1159 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1160 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1161 m_freem(Tx->m); 1162 Tx->m = NULL; 1163 sc->active_Tx = Tx->next; 1164 if (sc->active_Tx == NULL) 1165 sc->last_Tx = NULL; 1166 Tx->next = sc->Free_Tx; 1167 sc->Free_Tx = Tx; 1168 } 1169 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1170 sizeof(struct tl_Tx_list) * TL_NBUF, 1171 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1172 /* if this was an EOC, ACK immediatly */ 1173 if (ack) 1174 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1175 if (int_type == TL_INTR_TxEOC) { 1176 #ifdef TLDEBUG_TX 1177 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1178 ack); 1179 #endif 1180 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1181 HOST_CMD_ACK | HOST_CMD_IntOn); 1182 if ( sc->active_Tx != NULL) { 1183 /* needs a Tx go command */ 1184 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1185 sc->active_Tx->hw_listaddr); 1186 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1187 } 1188 sc->tl_if.if_timer = 0; 1189 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1190 tl_ifstart(&sc->tl_if); 1191 return 1; 1192 } 1193 #ifdef TLDEBUG 1194 else { 1195 printf("TL_INTR_TxEOF: ack %d\n", ack); 1196 } 1197 #endif 1198 sc->tl_if.if_timer = 0; 1199 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1200 tl_ifstart(&sc->tl_if); 1201 break; 1202 case TL_INTR_Stat: 1203 ack++; 1204 #ifdef TLDEBUG 1205 printf("TL_INTR_Stat: ack %d\n", ack); 1206 #endif 1207 tl_read_stats(sc); 1208 break; 1209 case TL_INTR_Adc: 1210 if (int_reg & TL_INTVec_MASK) { 1211 /* adapter check conditions */ 1212 printf("%s: check condition, intvect=0x%x, " 1213 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1214 int_reg & TL_INTVec_MASK, 1215 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1216 tl_reset(sc); 1217 /* shedule reinit of the board */ 1218 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1219 return(1); 1220 } else { 1221 u_int8_t netstat; 1222 /* Network status */ 1223 netstat = 1224 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1225 printf("%s: network status, NetSts=%x\n", 1226 sc->sc_dev.dv_xname, netstat); 1227 /* Ack interrupts */ 1228 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1229 netstat); 1230 ack++; 1231 } 1232 break; 1233 default: 1234 printf("%s: unhandled interrupt code %x!\n", 1235 sc->sc_dev.dv_xname, int_type); 1236 ack++; 1237 } 1238 1239 if (ack) { 1240 /* Ack the interrupt and enable interrupts */ 1241 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1242 HOST_CMD_IntOn); 1243 #if NRND > 0 1244 if (RND_ENABLED(&sc->rnd_source)) 1245 rnd_add_uint32(&sc->rnd_source, int_reg); 1246 #endif 1247 return 1; 1248 } 1249 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1250 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1251 return 0; 1252 } 1253 1254 static int 1255 tl_ifioctl(ifp, cmd, data) 1256 struct ifnet *ifp; 1257 ioctl_cmd_t cmd; 1258 caddr_t data; 1259 { 1260 struct tl_softc *sc = ifp->if_softc; 1261 struct ifreq *ifr = (struct ifreq *)data; 1262 int s, error; 1263 1264 s = splnet(); 1265 switch(cmd) { 1266 case SIOCSIFMEDIA: 1267 case SIOCGIFMEDIA: 1268 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1269 break; 1270 default: 1271 error = ether_ioctl(ifp, cmd, data); 1272 if (error == ENETRESET) { 1273 if (ifp->if_flags & IFF_RUNNING) 1274 tl_addr_filter(sc); 1275 error = 0; 1276 } 1277 } 1278 splx(s); 1279 return error; 1280 } 1281 1282 static void 1283 tl_ifstart(ifp) 1284 struct ifnet *ifp; 1285 { 1286 tl_softc_t *sc = ifp->if_softc; 1287 struct mbuf *mb_head; 1288 struct Tx_list *Tx; 1289 int segment, size; 1290 int again, error; 1291 1292 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1293 return; 1294 txloop: 1295 /* If we don't have more space ... */ 1296 if (sc->Free_Tx == NULL) { 1297 #ifdef TLDEBUG 1298 printf("tl_ifstart: No free TX list\n"); 1299 #endif 1300 sc->tl_if.if_flags |= IFF_OACTIVE; 1301 return; 1302 } 1303 /* Grab a paquet for output */ 1304 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1305 if (mb_head == NULL) { 1306 #ifdef TLDEBUG_TX 1307 printf("tl_ifstart: nothing to send\n"); 1308 #endif 1309 return; 1310 } 1311 Tx = sc->Free_Tx; 1312 sc->Free_Tx = Tx->next; 1313 Tx->next = NULL; 1314 again = 0; 1315 /* 1316 * Go through each of the mbufs in the chain and initialize 1317 * the transmit list descriptors with the physical address 1318 * and size of the mbuf. 1319 */ 1320 tbdinit: 1321 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1322 Tx->m = mb_head; 1323 size = mb_head->m_pkthdr.len; 1324 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1325 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1326 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1327 struct mbuf *mn; 1328 /* 1329 * We ran out of segments, or we will. We have to recopy this 1330 * mbuf chain first. 1331 */ 1332 if (error == 0) 1333 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1334 if (again) { 1335 /* already copyed, can't do much more */ 1336 m_freem(mb_head); 1337 goto bad; 1338 } 1339 again = 1; 1340 #ifdef TLDEBUG_TX 1341 printf("tl_ifstart: need to copy mbuf\n"); 1342 #endif 1343 #ifdef TL_PRIV_STATS 1344 sc->oerr_mcopy++; 1345 #endif 1346 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1347 if (mn == NULL) { 1348 m_freem(mb_head); 1349 goto bad; 1350 } 1351 if (mb_head->m_pkthdr.len > MHLEN) { 1352 MCLGET(mn, M_DONTWAIT); 1353 if ((mn->m_flags & M_EXT) == 0) { 1354 m_freem(mn); 1355 m_freem(mb_head); 1356 goto bad; 1357 } 1358 } 1359 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1360 mtod(mn, caddr_t)); 1361 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1362 m_freem(mb_head); 1363 mb_head = mn; 1364 goto tbdinit; 1365 } 1366 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1367 Tx->hw_list->seg[segment].data_addr = 1368 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1369 Tx->hw_list->seg[segment].data_count = 1370 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1371 } 1372 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1373 Tx->m_dmamap->dm_mapsize, 1374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1375 /* We are at end of mbuf chain. check the size and 1376 * see if it needs to be extended 1377 */ 1378 if (size < ETHER_MIN_TX) { 1379 #ifdef DIAGNOSTIC 1380 if (segment >= TL_NSEG) { 1381 panic("tl_ifstart: to much segmets (%d)", segment); 1382 } 1383 #endif 1384 /* 1385 * add the nullbuf in the seg 1386 */ 1387 Tx->hw_list->seg[segment].data_count = 1388 htole32(ETHER_MIN_TX - size); 1389 Tx->hw_list->seg[segment].data_addr = 1390 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1391 size = ETHER_MIN_TX; 1392 segment++; 1393 } 1394 /* The list is done, finish the list init */ 1395 Tx->hw_list->seg[segment - 1].data_count |= 1396 htole32(TL_LAST_SEG); 1397 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1398 #ifdef TLDEBUG_TX 1399 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1400 le32toh(Tx->hw_list->stat)); 1401 #if 0 1402 for(segment = 0; segment < TL_NSEG; segment++) { 1403 printf(" seg %d addr 0x%x len 0x%x\n", 1404 segment, 1405 le32toh(Tx->hw_list->seg[segment].data_addr), 1406 le32toh(Tx->hw_list->seg[segment].data_count)); 1407 } 1408 #endif 1409 #endif 1410 if (sc->active_Tx == NULL) { 1411 sc->active_Tx = sc->last_Tx = Tx; 1412 #ifdef TLDEBUG_TX 1413 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1414 (int)Tx->hw_listaddr); 1415 #endif 1416 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1417 sizeof(struct tl_Tx_list) * TL_NBUF, 1418 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1419 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1420 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1421 } else { 1422 #ifdef TLDEBUG_TX 1423 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1424 (int)Tx->hw_listaddr); 1425 #endif 1426 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1427 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1428 sizeof(struct tl_Tx_list) * TL_NBUF, 1429 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1430 sc->last_Tx->next = Tx; 1431 sc->last_Tx = Tx; 1432 #ifdef DIAGNOSTIC 1433 if (sc->last_Tx->hw_list->fwd & 0x7) 1434 printf("%s: physical addr 0x%x of list not properly " 1435 "aligned\n", 1436 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1437 #endif 1438 } 1439 #if NBPFILTER > 0 1440 /* Pass packet to bpf if there is a listener */ 1441 if (ifp->if_bpf) 1442 bpf_mtap(ifp->if_bpf, mb_head); 1443 #endif 1444 /* 1445 * Set a 5 second timer just in case we don't hear from the card again. 1446 */ 1447 ifp->if_timer = 5; 1448 goto txloop; 1449 bad: 1450 #ifdef TLDEBUG 1451 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1452 #endif 1453 Tx->next = sc->Free_Tx; 1454 sc->Free_Tx = Tx; 1455 return; 1456 } 1457 1458 static void 1459 tl_ifwatchdog(ifp) 1460 struct ifnet *ifp; 1461 { 1462 tl_softc_t *sc = ifp->if_softc; 1463 1464 if ((ifp->if_flags & IFF_RUNNING) == 0) 1465 return; 1466 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1467 ifp->if_oerrors++; 1468 tl_init(ifp); 1469 } 1470 1471 static int 1472 tl_mediachange(ifp) 1473 struct ifnet *ifp; 1474 { 1475 1476 if (ifp->if_flags & IFF_UP) 1477 tl_init(ifp); 1478 return (0); 1479 } 1480 1481 static void 1482 tl_mediastatus(ifp, ifmr) 1483 struct ifnet *ifp; 1484 struct ifmediareq *ifmr; 1485 { 1486 tl_softc_t *sc = ifp->if_softc; 1487 1488 mii_pollstat(&sc->tl_mii); 1489 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1490 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1491 } 1492 1493 static int tl_add_RxBuff(sc, Rx, oldm) 1494 tl_softc_t *sc; 1495 struct Rx_list *Rx; 1496 struct mbuf *oldm; 1497 { 1498 struct mbuf *m; 1499 int error; 1500 1501 MGETHDR(m, M_DONTWAIT, MT_DATA); 1502 if (m != NULL) { 1503 MCLGET(m, M_DONTWAIT); 1504 if ((m->m_flags & M_EXT) == 0) { 1505 m_freem(m); 1506 if (oldm == NULL) 1507 return 0; 1508 m = oldm; 1509 m->m_data = m->m_ext.ext_buf; 1510 } 1511 } else { 1512 if (oldm == NULL) 1513 return 0; 1514 m = oldm; 1515 m->m_data = m->m_ext.ext_buf; 1516 } 1517 1518 /* (re)init the Rx_list struct */ 1519 1520 Rx->m = m; 1521 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1522 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1523 printf("%s: bus_dmamap_load() failed (error %d) for " 1524 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1525 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1526 m_freem(m); 1527 Rx->m = NULL; 1528 return 0; 1529 } 1530 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1531 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1532 /* 1533 * Move the data pointer up so that the incoming data packet 1534 * will be 32-bit aligned. 1535 */ 1536 m->m_data += 2; 1537 1538 Rx->hw_list->stat = 1539 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1540 Rx->hw_list->seg.data_count = 1541 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1542 Rx->hw_list->seg.data_addr = 1543 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1544 return (m != oldm); 1545 } 1546 1547 static void tl_ticks(v) 1548 void *v; 1549 { 1550 tl_softc_t *sc = v; 1551 1552 tl_read_stats(sc); 1553 1554 /* Tick the MII. */ 1555 mii_tick(&sc->tl_mii); 1556 1557 /* read statistics every seconds */ 1558 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1559 } 1560 1561 static void 1562 tl_read_stats(sc) 1563 tl_softc_t *sc; 1564 { 1565 u_int32_t reg; 1566 int ierr_overr; 1567 int ierr_code; 1568 int ierr_crc; 1569 int oerr_underr; 1570 int oerr_deferred; 1571 int oerr_coll; 1572 int oerr_multicoll; 1573 int oerr_exesscoll; 1574 int oerr_latecoll; 1575 int oerr_carrloss; 1576 struct ifnet *ifp = &sc->tl_if; 1577 1578 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1579 ifp->if_opackets += reg & 0x00ffffff; 1580 oerr_underr = reg >> 24; 1581 1582 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1583 ifp->if_ipackets += reg & 0x00ffffff; 1584 ierr_overr = reg >> 24; 1585 1586 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1587 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1588 ierr_code = (reg & TL_FERR_CODE) >> 24; 1589 oerr_deferred = (reg & TL_FERR_DEF); 1590 1591 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1592 oerr_multicoll = (reg & TL_COL_MULTI); 1593 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1594 1595 reg = tl_intreg_read(sc, TL_INT_LERR); 1596 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1597 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1598 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1599 1600 1601 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1602 oerr_carrloss; 1603 ifp->if_collisions += oerr_coll + oerr_multicoll; 1604 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1605 1606 if (ierr_overr) 1607 printf("%s: receiver ring buffer overrun\n", 1608 sc->sc_dev.dv_xname); 1609 if (oerr_underr) 1610 printf("%s: transmit buffer underrun\n", 1611 sc->sc_dev.dv_xname); 1612 #ifdef TL_PRIV_STATS 1613 sc->ierr_overr += ierr_overr; 1614 sc->ierr_code += ierr_code; 1615 sc->ierr_crc += ierr_crc; 1616 sc->oerr_underr += oerr_underr; 1617 sc->oerr_deferred += oerr_deferred; 1618 sc->oerr_coll += oerr_coll; 1619 sc->oerr_multicoll += oerr_multicoll; 1620 sc->oerr_exesscoll += oerr_exesscoll; 1621 sc->oerr_latecoll += oerr_latecoll; 1622 sc->oerr_carrloss += oerr_carrloss; 1623 #endif 1624 } 1625 1626 static void tl_addr_filter(sc) 1627 tl_softc_t *sc; 1628 { 1629 struct ether_multistep step; 1630 struct ether_multi *enm; 1631 u_int32_t hash[2] = {0, 0}; 1632 int i; 1633 1634 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1635 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1636 while (enm != NULL) { 1637 #ifdef TLDEBUG 1638 printf("tl_addr_filter: addrs %s %s\n", 1639 ether_sprintf(enm->enm_addrlo), 1640 ether_sprintf(enm->enm_addrhi)); 1641 #endif 1642 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1643 i = tl_multicast_hash(enm->enm_addrlo); 1644 hash[i/32] |= 1 << (i%32); 1645 } else { 1646 hash[0] = hash[1] = 0xffffffff; 1647 sc->tl_if.if_flags |= IFF_ALLMULTI; 1648 break; 1649 } 1650 ETHER_NEXT_MULTI(step, enm); 1651 } 1652 #ifdef TLDEBUG 1653 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1654 #endif 1655 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1656 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1657 } 1658 1659 static int tl_multicast_hash(a) 1660 u_int8_t *a; 1661 { 1662 int hash; 1663 1664 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1665 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1666 1667 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1668 DA(a,36), DA(a,42)); 1669 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1670 DA(a,37), DA(a,43)) << 1; 1671 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1672 DA(a,38), DA(a,44)) << 2; 1673 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1674 DA(a,39), DA(a,45)) << 3; 1675 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1676 DA(a,40), DA(a,46)) << 4; 1677 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1678 DA(a,41), DA(a,47)) << 5; 1679 1680 return hash; 1681 } 1682 1683 #if defined(TLDEBUG_RX) 1684 void 1685 ether_printheader(eh) 1686 struct ether_header *eh; 1687 { 1688 u_char *c = (char*)eh; 1689 int i; 1690 for (i=0; i<sizeof(struct ether_header); i++) 1691 printf("%x ", (u_int)c[i]); 1692 printf("\n"); 1693 } 1694 #endif 1695
Indexes created Thu Sep 25 16:09:42 GMT 2025