if_tl.c revision 1.85
1 /* $NetBSD: if_tl.c,v 1.85 2008/01/19 22:10:19 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.85 2008/01/19 22:10:19 dyoung Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #include "rnd.h" 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #endif 87 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match(struct device *, struct cfdata *, void *); 122 static void tl_pci_attach(struct device *, struct device *, void *); 123 static int tl_intr(void *); 124 125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 126 static int tl_mediachange(struct ifnet *); 127 static void tl_ifwatchdog(struct ifnet *); 128 static void tl_shutdown(void*); 129 130 static void tl_ifstart(struct ifnet *); 131 static void tl_reset(tl_softc_t*); 132 static int tl_init(struct ifnet *); 133 static void tl_stop(struct ifnet *, int); 134 static void tl_restart(void *); 135 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 136 static void tl_read_stats(tl_softc_t*); 137 static void tl_ticks(void*); 138 static int tl_multicast_hash(u_int8_t*); 139 static void tl_addr_filter(tl_softc_t*); 140 141 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 142 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 143 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 144 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 145 146 void tl_mii_sync(struct tl_softc *); 147 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader(struct ether_header*); 152 #endif 153 154 int tl_mii_read(struct device *, int, int); 155 void tl_mii_write(struct device *, int, int, int); 156 157 void tl_statchg(struct device *); 158 159 /* I2C glue */ 160 static int tl_i2c_acquire_bus(void *, int); 161 static void tl_i2c_release_bus(void *, int); 162 static int tl_i2c_send_start(void *, int); 163 static int tl_i2c_send_stop(void *, int); 164 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 165 static int tl_i2c_read_byte(void *, uint8_t *, int); 166 static int tl_i2c_write_byte(void *, uint8_t, int); 167 168 /* I2C bit-bang glue */ 169 static void tl_i2cbb_set_bits(void *, uint32_t); 170 static void tl_i2cbb_set_dir(void *, uint32_t); 171 static uint32_t tl_i2cbb_read(void *); 172 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 173 tl_i2cbb_set_bits, 174 tl_i2cbb_set_dir, 175 tl_i2cbb_read, 176 { 177 TL_NETSIO_EDATA, /* SDA */ 178 TL_NETSIO_ECLOCK, /* SCL */ 179 TL_NETSIO_ETXEN, /* SDA is output */ 180 0, /* SDA is input */ 181 } 182 }; 183 184 static inline void netsio_clr(tl_softc_t*, u_int8_t); 185 static inline void netsio_set(tl_softc_t*, u_int8_t); 186 static inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 187 static inline void netsio_clr(sc, bits) 188 tl_softc_t* sc; 189 u_int8_t bits; 190 { 191 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 192 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 193 } 194 static inline void netsio_set(sc, bits) 195 tl_softc_t* sc; 196 u_int8_t bits; 197 { 198 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 199 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 200 } 201 static inline u_int8_t netsio_read(sc, bits) 202 tl_softc_t* sc; 203 u_int8_t bits; 204 { 205 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 206 } 207 208 CFATTACH_DECL(tl, sizeof(tl_softc_t), 209 tl_pci_match, tl_pci_attach, NULL, NULL); 210 211 const struct tl_product_desc tl_compaq_products[] = { 212 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 213 "Compaq Netelligent 10/100 TX" }, 214 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 215 "Integrated Compaq Netelligent 10/100 TX" }, 216 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 217 "Compaq Netelligent 10 T" }, 218 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 219 "Compaq Netelligent 10 T/2 UTP/Coax" }, 220 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 221 "Compaq Integrated NetFlex 3/P" }, 222 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 223 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 224 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 225 "Compaq Dual Port Netelligent 10/100 TX" }, 226 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 227 "Compaq Deskpro 4000 5233MMX" }, 228 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 229 "Compaq NetFlex 3/P w/ BNC" }, 230 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 231 "Compaq NetFlex 3/P" }, 232 { 0, 0, NULL }, 233 }; 234 235 const struct tl_product_desc tl_ti_products[] = { 236 /* 237 * Built-in Ethernet on the TI TravelMate 5000 238 * docking station; better product description? 239 */ 240 { PCI_PRODUCT_TI_TLAN, 0, 241 "Texas Instruments ThunderLAN" }, 242 { 0, 0, NULL }, 243 }; 244 245 struct tl_vendor_desc { 246 u_int32_t tv_vendor; 247 const struct tl_product_desc *tv_products; 248 }; 249 250 const struct tl_vendor_desc tl_vendors[] = { 251 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 252 { PCI_VENDOR_TI, tl_ti_products }, 253 { 0, NULL }, 254 }; 255 256 const struct tl_product_desc *tl_lookup_product(u_int32_t); 257 258 const struct tl_product_desc * 259 tl_lookup_product(id) 260 u_int32_t id; 261 { 262 const struct tl_product_desc *tp; 263 const struct tl_vendor_desc *tv; 264 265 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 266 if (PCI_VENDOR(id) == tv->tv_vendor) 267 break; 268 269 if ((tp = tv->tv_products) == NULL) 270 return (NULL); 271 272 for (; tp->tp_desc != NULL; tp++) 273 if (PCI_PRODUCT(id) == tp->tp_product) 274 break; 275 276 if (tp->tp_desc == NULL) 277 return (NULL); 278 279 return (tp); 280 } 281 282 static int 283 tl_pci_match(struct device *parent, struct cfdata *match, 284 void *aux) 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 287 288 if (tl_lookup_product(pa->pa_id) != NULL) 289 return (1); 290 291 return (0); 292 } 293 294 static void 295 tl_pci_attach(struct device *parent, struct device *self, void *aux) 296 { 297 tl_softc_t *sc = (tl_softc_t *)self; 298 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 299 const struct tl_product_desc *tp; 300 struct ifnet * const ifp = &sc->tl_if; 301 bus_space_tag_t iot, memt; 302 bus_space_handle_t ioh, memh; 303 pci_intr_handle_t intrhandle; 304 const char *intrstr; 305 int ioh_valid, memh_valid; 306 int reg_io, reg_mem; 307 pcireg_t reg10, reg14; 308 pcireg_t csr; 309 310 printf("\n"); 311 312 callout_init(&sc->tl_tick_ch, 0); 313 callout_init(&sc->tl_restart_ch, 0); 314 315 tp = tl_lookup_product(pa->pa_id); 316 if (tp == NULL) 317 panic("tl_pci_attach: impossible"); 318 sc->tl_product = tp; 319 320 /* 321 * Map the card space. First we have to find the I/O and MEM 322 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 323 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 324 * The ThunderLAN manual is not consistent about this either (there 325 * are both cases in code examples). 326 */ 327 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 328 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 329 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 330 reg_io = 0x10; 331 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 332 reg_io = 0x14; 333 else 334 reg_io = 0; 335 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 336 reg_mem = 0x10; 337 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 338 reg_mem = 0x14; 339 else 340 reg_mem = 0; 341 342 if (reg_io != 0) 343 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 344 0, &iot, &ioh, NULL, NULL) == 0); 345 else 346 ioh_valid = 0; 347 if (reg_mem != 0) 348 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 349 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 350 0, &memt, &memh, NULL, NULL) == 0); 351 else 352 memh_valid = 0; 353 354 if (ioh_valid) { 355 sc->tl_bustag = iot; 356 sc->tl_bushandle = ioh; 357 } else if (memh_valid) { 358 sc->tl_bustag = memt; 359 sc->tl_bushandle = memh; 360 } else { 361 printf("%s: unable to map device registers\n", 362 sc->sc_dev.dv_xname); 363 return; 364 } 365 sc->tl_dmatag = pa->pa_dmat; 366 367 /* Enable the device. */ 368 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 369 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 370 csr | PCI_COMMAND_MASTER_ENABLE); 371 372 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 373 374 tl_reset(sc); 375 376 /* fill in the i2c tag */ 377 sc->sc_i2c.ic_cookie = sc; 378 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 379 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 380 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 381 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 382 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 383 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 384 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 385 386 #ifdef TLDEBUG 387 printf("default values of INTreg: 0x%x\n", 388 tl_intreg_read(sc, TL_INT_Defaults)); 389 #endif 390 391 /* read mac addr */ 392 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 393 sc->tl_enaddr, ETHER_ADDR_LEN)) { 394 printf("%s: error reading Ethernet address\n", 395 sc->sc_dev.dv_xname); 396 return; 397 } 398 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 399 ether_sprintf(sc->tl_enaddr)); 400 401 /* Map and establish interrupts */ 402 if (pci_intr_map(pa, &intrhandle)) { 403 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 404 return; 405 } 406 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 407 sc->tl_if.if_softc = sc; 408 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 409 tl_intr, sc); 410 if (sc->tl_ih == NULL) { 411 printf("%s: couldn't establish interrupt", 412 sc->sc_dev.dv_xname); 413 if (intrstr != NULL) 414 printf(" at %s", intrstr); 415 printf("\n"); 416 return; 417 } 418 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 419 420 /* init these pointers, so that tl_shutdown won't try to read them */ 421 sc->Rx_list = NULL; 422 sc->Tx_list = NULL; 423 424 /* allocate DMA-safe memory for control structs */ 425 if (bus_dmamem_alloc(sc->tl_dmatag, 426 PAGE_SIZE, 0, PAGE_SIZE, 427 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 428 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 429 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 430 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 431 printf("%s: can't allocate DMA memory for lists\n", 432 sc->sc_dev.dv_xname); 433 return; 434 } 435 /* 436 * Add shutdown hook so that DMA is disabled prior to reboot. Not 437 * doing 438 * reboot before the driver initializes. 439 */ 440 (void) shutdownhook_establish(tl_shutdown, ifp); 441 442 /* 443 * Initialize our media structures and probe the MII. 444 * 445 * Note that we don't care about the media instance. We 446 * are expecting to have multiple PHYs on the 10/100 cards, 447 * and on those cards we exclude the internal PHY from providing 448 * 10baseT. By ignoring the instance, it allows us to not have 449 * to specify it on the command line when switching media. 450 */ 451 sc->tl_mii.mii_ifp = ifp; 452 sc->tl_mii.mii_readreg = tl_mii_read; 453 sc->tl_mii.mii_writereg = tl_mii_write; 454 sc->tl_mii.mii_statchg = tl_statchg; 455 sc->tl_ec.ec_mii = &sc->tl_mii; 456 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 457 ether_mediastatus); 458 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 459 MII_OFFSET_ANY, 0); 460 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 461 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 462 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 463 } else 464 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 465 466 /* 467 * We can support 802.1Q VLAN-sized frames. 468 */ 469 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 470 471 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 472 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 473 ifp->if_ioctl = tl_ifioctl; 474 ifp->if_start = tl_ifstart; 475 ifp->if_watchdog = tl_ifwatchdog; 476 ifp->if_init = tl_init; 477 ifp->if_stop = tl_stop; 478 ifp->if_timer = 0; 479 IFQ_SET_READY(&ifp->if_snd); 480 if_attach(ifp); 481 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 482 483 #if NRND > 0 484 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 485 RND_TYPE_NET, 0); 486 #endif 487 } 488 489 static void 490 tl_reset(sc) 491 tl_softc_t *sc; 492 { 493 int i; 494 495 /* read stats */ 496 if (sc->tl_if.if_flags & IFF_RUNNING) { 497 callout_stop(&sc->tl_tick_ch); 498 tl_read_stats(sc); 499 } 500 /* Reset adapter */ 501 TL_HR_WRITE(sc, TL_HOST_CMD, 502 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 503 DELAY(100000); 504 /* Disable interrupts */ 505 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 506 /* setup aregs & hash */ 507 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 508 tl_intreg_write(sc, i, 0); 509 #ifdef TLDEBUG_ADDR 510 printf("Areg & hash registers: \n"); 511 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 512 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 513 #endif 514 /* Setup NetConfig */ 515 tl_intreg_write(sc, TL_INT_NetConfig, 516 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 517 /* Bsize: accept default */ 518 /* TX commit in Acommit: accept default */ 519 /* Load Ld_tmr and Ld_thr */ 520 /* Ld_tmr = 3 */ 521 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 522 /* Ld_thr = 0 */ 523 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 524 /* Unreset MII */ 525 netsio_set(sc, TL_NETSIO_NMRST); 526 DELAY(100000); 527 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 528 } 529 530 static void tl_shutdown(v) 531 void *v; 532 { 533 tl_stop(v, 1); 534 } 535 536 static void tl_stop(struct ifnet *ifp, int disable) 537 { 538 tl_softc_t *sc = ifp->if_softc; 539 struct Tx_list *Tx; 540 int i; 541 542 if ((ifp->if_flags & IFF_RUNNING) == 0) 543 return; 544 /* disable interrupts */ 545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 546 /* stop TX and RX channels */ 547 TL_HR_WRITE(sc, TL_HOST_CMD, 548 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 549 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 550 DELAY(100000); 551 552 /* stop statistics reading loop, read stats */ 553 callout_stop(&sc->tl_tick_ch); 554 tl_read_stats(sc); 555 556 /* Down the MII. */ 557 mii_down(&sc->tl_mii); 558 559 /* deallocate memory allocations */ 560 if (sc->Rx_list) { 561 for (i=0; i< TL_NBUF; i++) { 562 if (sc->Rx_list[i].m) { 563 bus_dmamap_unload(sc->tl_dmatag, 564 sc->Rx_list[i].m_dmamap); 565 m_freem(sc->Rx_list[i].m); 566 } 567 bus_dmamap_destroy(sc->tl_dmatag, 568 sc->Rx_list[i].m_dmamap); 569 sc->Rx_list[i].m = NULL; 570 } 571 free(sc->Rx_list, M_DEVBUF); 572 sc->Rx_list = NULL; 573 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 574 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 575 sc->hw_Rx_list = NULL; 576 while ((Tx = sc->active_Tx) != NULL) { 577 Tx->hw_list->stat = 0; 578 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 579 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 580 m_freem(Tx->m); 581 sc->active_Tx = Tx->next; 582 Tx->next = sc->Free_Tx; 583 sc->Free_Tx = Tx; 584 } 585 sc->last_Tx = NULL; 586 free(sc->Tx_list, M_DEVBUF); 587 sc->Tx_list = NULL; 588 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 589 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 590 sc->hw_Tx_list = NULL; 591 } 592 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 593 ifp->if_timer = 0; 594 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 595 } 596 597 static void tl_restart(v) 598 void *v; 599 { 600 tl_init(v); 601 } 602 603 static int tl_init(ifp) 604 struct ifnet *ifp; 605 { 606 tl_softc_t *sc = ifp->if_softc; 607 int i, s, error; 608 bus_size_t boundary; 609 prop_number_t prop_boundary; 610 const char *errstring; 611 char *nullbuf; 612 613 s = splnet(); 614 /* cancel any pending IO */ 615 tl_stop(ifp, 1); 616 tl_reset(sc); 617 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 618 splx(s); 619 return 0; 620 } 621 /* Set various register to reasonable value */ 622 /* setup NetCmd in promisc mode if needed */ 623 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 624 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 625 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 626 /* Max receive size : MCLBYTES */ 627 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 628 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 629 (MCLBYTES >> 8) & 0xff); 630 631 /* init MAC addr */ 632 for (i = 0; i < ETHER_ADDR_LEN; i++) 633 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 634 /* add multicast filters */ 635 tl_addr_filter(sc); 636 #ifdef TLDEBUG_ADDR 637 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 638 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 639 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 640 #endif 641 642 /* Pre-allocate receivers mbuf, make the lists */ 643 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 644 M_NOWAIT|M_ZERO); 645 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 646 M_NOWAIT|M_ZERO); 647 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 648 errstring = "out of memory for lists"; 649 error = ENOMEM; 650 goto bad; 651 } 652 653 /* 654 * Some boards (Set Engineering GFE) do not permit DMA transfers 655 * across page boundaries. 656 */ 657 prop_boundary = prop_dictionary_get(device_properties(&sc->sc_dev), 658 "tl-dma-page-boundary"); 659 if (prop_boundary != NULL) { 660 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 661 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 662 } else { 663 boundary = 0; 664 } 665 666 error = bus_dmamap_create(sc->tl_dmatag, 667 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 668 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 669 &sc->Rx_dmamap); 670 if (error == 0) 671 error = bus_dmamap_create(sc->tl_dmatag, 672 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 673 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 674 BUS_DMA_WAITOK, &sc->Tx_dmamap); 675 if (error == 0) 676 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 677 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 678 &sc->null_dmamap); 679 if (error) { 680 errstring = "can't allocate DMA maps for lists"; 681 goto bad; 682 } 683 memset(sc->ctrl, 0, PAGE_SIZE); 684 sc->hw_Rx_list = (void *)sc->ctrl; 685 sc->hw_Tx_list = 686 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 687 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 688 sizeof(struct tl_Tx_list) * TL_NBUF; 689 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 690 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 691 BUS_DMA_WAITOK); 692 if (error == 0) 693 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 694 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 695 BUS_DMA_WAITOK); 696 if (error == 0) 697 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 698 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 699 if (error) { 700 errstring = "can't DMA map DMA memory for lists"; 701 goto bad; 702 } 703 for (i=0; i< TL_NBUF; i++) { 704 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 705 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 706 &sc->Rx_list[i].m_dmamap); 707 if (error == 0) { 708 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 709 TL_NSEG, MCLBYTES, boundary, 710 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 711 &sc->Tx_list[i].m_dmamap); 712 } 713 if (error) { 714 errstring = "can't allocate DMA maps for mbufs"; 715 goto bad; 716 } 717 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 718 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 719 + sizeof(struct tl_Rx_list) * i; 720 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 721 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 722 + sizeof(struct tl_Tx_list) * i; 723 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 724 errstring = "out of mbuf for receive list"; 725 error = ENOMEM; 726 goto bad; 727 } 728 if (i > 0) { /* chain the list */ 729 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 730 sc->hw_Rx_list[i - 1].fwd = 731 htole32(sc->Rx_list[i].hw_listaddr); 732 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 733 } 734 } 735 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 736 sc->Rx_list[TL_NBUF - 1].next = NULL; 737 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 738 sc->Tx_list[TL_NBUF - 1].next = NULL; 739 740 sc->active_Rx = &sc->Rx_list[0]; 741 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 742 sc->active_Tx = sc->last_Tx = NULL; 743 sc->Free_Tx = &sc->Tx_list[0]; 744 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 745 sizeof(struct tl_Rx_list) * TL_NBUF, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 748 sizeof(struct tl_Tx_list) * TL_NBUF, 749 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 750 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 751 BUS_DMASYNC_PREWRITE); 752 753 /* set media */ 754 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 755 error = 0; 756 else if (error != 0) { 757 errstring = "could not set media"; 758 goto bad; 759 } 760 761 /* start ticks calls */ 762 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 763 /* write address of Rx list and enable interrupts */ 764 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 765 TL_HR_WRITE(sc, TL_HOST_CMD, 766 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 767 sc->tl_if.if_flags |= IFF_RUNNING; 768 sc->tl_if.if_flags &= ~IFF_OACTIVE; 769 return 0; 770 bad: 771 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 772 splx(s); 773 return error; 774 } 775 776 777 static u_int32_t 778 tl_intreg_read(sc, reg) 779 tl_softc_t *sc; 780 u_int32_t reg; 781 { 782 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 783 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 784 } 785 786 static u_int8_t 787 tl_intreg_read_byte(sc, reg) 788 tl_softc_t *sc; 789 u_int32_t reg; 790 { 791 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 792 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 793 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 794 } 795 796 static void 797 tl_intreg_write(sc, reg, val) 798 tl_softc_t *sc; 799 u_int32_t reg; 800 u_int32_t val; 801 { 802 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 803 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 804 } 805 806 static void 807 tl_intreg_write_byte(sc, reg, val) 808 tl_softc_t *sc; 809 u_int32_t reg; 810 u_int8_t val; 811 { 812 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 813 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 814 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 815 } 816 817 void 818 tl_mii_sync(sc) 819 struct tl_softc *sc; 820 { 821 int i; 822 823 netsio_clr(sc, TL_NETSIO_MTXEN); 824 for (i = 0; i < 32; i++) { 825 netsio_clr(sc, TL_NETSIO_MCLK); 826 netsio_set(sc, TL_NETSIO_MCLK); 827 } 828 } 829 830 void 831 tl_mii_sendbits(sc, data, nbits) 832 struct tl_softc *sc; 833 u_int32_t data; 834 int nbits; 835 { 836 int i; 837 838 netsio_set(sc, TL_NETSIO_MTXEN); 839 for (i = 1 << (nbits - 1); i; i = i >> 1) { 840 netsio_clr(sc, TL_NETSIO_MCLK); 841 netsio_read(sc, TL_NETSIO_MCLK); 842 if (data & i) 843 netsio_set(sc, TL_NETSIO_MDATA); 844 else 845 netsio_clr(sc, TL_NETSIO_MDATA); 846 netsio_set(sc, TL_NETSIO_MCLK); 847 netsio_read(sc, TL_NETSIO_MCLK); 848 } 849 } 850 851 int 852 tl_mii_read(self, phy, reg) 853 struct device *self; 854 int phy, reg; 855 { 856 struct tl_softc *sc = (struct tl_softc *)self; 857 int val = 0, i, err; 858 859 /* 860 * Read the PHY register by manually driving the MII control lines. 861 */ 862 863 tl_mii_sync(sc); 864 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 865 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 866 tl_mii_sendbits(sc, phy, 5); 867 tl_mii_sendbits(sc, reg, 5); 868 869 netsio_clr(sc, TL_NETSIO_MTXEN); 870 netsio_clr(sc, TL_NETSIO_MCLK); 871 netsio_set(sc, TL_NETSIO_MCLK); 872 netsio_clr(sc, TL_NETSIO_MCLK); 873 874 err = netsio_read(sc, TL_NETSIO_MDATA); 875 netsio_set(sc, TL_NETSIO_MCLK); 876 877 /* Even if an error occurs, must still clock out the cycle. */ 878 for (i = 0; i < 16; i++) { 879 val <<= 1; 880 netsio_clr(sc, TL_NETSIO_MCLK); 881 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 882 val |= 1; 883 netsio_set(sc, TL_NETSIO_MCLK); 884 } 885 netsio_clr(sc, TL_NETSIO_MCLK); 886 netsio_set(sc, TL_NETSIO_MCLK); 887 888 return (err ? 0 : val); 889 } 890 891 void 892 tl_mii_write(self, phy, reg, val) 893 struct device *self; 894 int phy, reg, val; 895 { 896 struct tl_softc *sc = (struct tl_softc *)self; 897 898 /* 899 * Write the PHY register by manually driving the MII control lines. 900 */ 901 902 tl_mii_sync(sc); 903 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 904 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 905 tl_mii_sendbits(sc, phy, 5); 906 tl_mii_sendbits(sc, reg, 5); 907 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 908 tl_mii_sendbits(sc, val, 16); 909 910 netsio_clr(sc, TL_NETSIO_MCLK); 911 netsio_set(sc, TL_NETSIO_MCLK); 912 } 913 914 void 915 tl_statchg(self) 916 struct device *self; 917 { 918 tl_softc_t *sc = (struct tl_softc *)self; 919 u_int32_t reg; 920 921 #ifdef TLDEBUG 922 printf("tl_statchg, media %x\n", sc->tl_mii.mii_media.ifm_media); 923 #endif 924 925 /* 926 * We must keep the ThunderLAN and the PHY in sync as 927 * to the status of full-duplex! 928 */ 929 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 930 if (sc->tl_mii.mii_media_active & IFM_FDX) 931 reg |= TL_NETCOMMAND_DUPLEX; 932 else 933 reg &= ~TL_NETCOMMAND_DUPLEX; 934 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 935 } 936 937 /********** I2C glue **********/ 938 939 static int 940 tl_i2c_acquire_bus(void *cookie, int flags) 941 { 942 943 /* private bus */ 944 return (0); 945 } 946 947 static void 948 tl_i2c_release_bus(void *cookie, int flags) 949 { 950 951 /* private bus */ 952 } 953 954 static int 955 tl_i2c_send_start(void *cookie, int flags) 956 { 957 958 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 959 } 960 961 static int 962 tl_i2c_send_stop(void *cookie, int flags) 963 { 964 965 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 966 } 967 968 static int 969 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 970 { 971 972 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 973 } 974 975 static int 976 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 977 { 978 979 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 980 } 981 982 static int 983 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 984 { 985 986 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 987 } 988 989 /********** I2C bit-bang glue **********/ 990 991 static void 992 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 993 { 994 struct tl_softc *sc = cookie; 995 uint8_t reg; 996 997 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 998 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 999 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1000 } 1001 1002 static void 1003 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 1004 { 1005 struct tl_softc *sc = cookie; 1006 uint8_t reg; 1007 1008 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 1009 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 1010 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1011 } 1012 1013 static uint32_t 1014 tl_i2cbb_read(void *cookie) 1015 { 1016 1017 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1018 } 1019 1020 /********** End of I2C stuff **********/ 1021 1022 static int 1023 tl_intr(v) 1024 void *v; 1025 { 1026 tl_softc_t *sc = v; 1027 struct ifnet *ifp = &sc->tl_if; 1028 struct Rx_list *Rx; 1029 struct Tx_list *Tx; 1030 struct mbuf *m; 1031 u_int32_t int_type, int_reg; 1032 int ack = 0; 1033 int size; 1034 1035 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1036 int_type = int_reg & TL_INTR_MASK; 1037 if (int_type == 0) 1038 return 0; 1039 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1040 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 1041 int_type, int_reg); 1042 #endif 1043 /* disable interrupts */ 1044 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1045 switch(int_type & TL_INTR_MASK) { 1046 case TL_INTR_RxEOF: 1047 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1048 sizeof(struct tl_Rx_list) * TL_NBUF, 1049 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1050 while(le32toh(sc->active_Rx->hw_list->stat) & 1051 TL_RX_CSTAT_CPLT) { 1052 /* dequeue and requeue at end of list */ 1053 ack++; 1054 Rx = sc->active_Rx; 1055 sc->active_Rx = Rx->next; 1056 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1057 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1058 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1059 m = Rx->m; 1060 size = le32toh(Rx->hw_list->stat) >> 16; 1061 #ifdef TLDEBUG_RX 1062 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1063 Rx, size); 1064 #endif 1065 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1066 /* 1067 * No new mbuf, reuse the same. This means 1068 * that this packet 1069 * is lost 1070 */ 1071 m = NULL; 1072 #ifdef TL_PRIV_STATS 1073 sc->ierr_nomem++; 1074 #endif 1075 #ifdef TLDEBUG 1076 printf("%s: out of mbuf, lost input packet\n", 1077 sc->sc_dev.dv_xname); 1078 #endif 1079 } 1080 Rx->next = NULL; 1081 Rx->hw_list->fwd = 0; 1082 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1083 sc->last_Rx->next = Rx; 1084 sc->last_Rx = Rx; 1085 1086 /* deliver packet */ 1087 if (m) { 1088 if (size < sizeof(struct ether_header)) { 1089 m_freem(m); 1090 continue; 1091 } 1092 m->m_pkthdr.rcvif = ifp; 1093 m->m_pkthdr.len = m->m_len = size; 1094 #ifdef TLDEBUG_RX 1095 { struct ether_header *eh = 1096 mtod(m, struct ether_header *); 1097 printf("tl_intr: Rx packet:\n"); 1098 ether_printheader(eh); } 1099 #endif 1100 #if NBPFILTER > 0 1101 if (ifp->if_bpf) 1102 bpf_mtap(ifp->if_bpf, m); 1103 #endif /* NBPFILTER > 0 */ 1104 (*ifp->if_input)(ifp, m); 1105 } 1106 } 1107 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1108 sizeof(struct tl_Rx_list) * TL_NBUF, 1109 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1110 #ifdef TLDEBUG_RX 1111 printf("TL_INTR_RxEOF: ack %d\n", ack); 1112 #else 1113 if (ack == 0) { 1114 printf("%s: EOF intr without anything to read !\n", 1115 sc->sc_dev.dv_xname); 1116 tl_reset(sc); 1117 /* schedule reinit of the board */ 1118 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1119 return(1); 1120 } 1121 #endif 1122 break; 1123 case TL_INTR_RxEOC: 1124 ack++; 1125 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1126 sizeof(struct tl_Rx_list) * TL_NBUF, 1127 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1128 #ifdef TLDEBUG_RX 1129 printf("TL_INTR_RxEOC: ack %d\n", ack); 1130 #endif 1131 #ifdef DIAGNOSTIC 1132 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1133 printf("%s: Rx EOC interrupt and active Tx list not " 1134 "cleared\n", sc->sc_dev.dv_xname); 1135 return 0; 1136 } else 1137 #endif 1138 { 1139 /* 1140 * write address of Rx list and send Rx GO command, ack 1141 * interrupt and enable interrupts in one command 1142 */ 1143 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1144 TL_HR_WRITE(sc, TL_HOST_CMD, 1145 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1146 HOST_CMD_ACK | HOST_CMD_IntOn); 1147 return 1; 1148 } 1149 case TL_INTR_TxEOF: 1150 case TL_INTR_TxEOC: 1151 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1152 sizeof(struct tl_Tx_list) * TL_NBUF, 1153 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1154 while ((Tx = sc->active_Tx) != NULL) { 1155 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1156 break; 1157 ack++; 1158 #ifdef TLDEBUG_TX 1159 printf("TL_INTR_TxEOC: list 0x%x done\n", 1160 (int)Tx->hw_listaddr); 1161 #endif 1162 Tx->hw_list->stat = 0; 1163 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1164 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1165 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1166 m_freem(Tx->m); 1167 Tx->m = NULL; 1168 sc->active_Tx = Tx->next; 1169 if (sc->active_Tx == NULL) 1170 sc->last_Tx = NULL; 1171 Tx->next = sc->Free_Tx; 1172 sc->Free_Tx = Tx; 1173 } 1174 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1175 sizeof(struct tl_Tx_list) * TL_NBUF, 1176 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1177 /* if this was an EOC, ACK immediatly */ 1178 if (ack) 1179 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1180 if (int_type == TL_INTR_TxEOC) { 1181 #ifdef TLDEBUG_TX 1182 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1183 ack); 1184 #endif 1185 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1186 HOST_CMD_ACK | HOST_CMD_IntOn); 1187 if ( sc->active_Tx != NULL) { 1188 /* needs a Tx go command */ 1189 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1190 sc->active_Tx->hw_listaddr); 1191 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1192 } 1193 sc->tl_if.if_timer = 0; 1194 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1195 tl_ifstart(&sc->tl_if); 1196 return 1; 1197 } 1198 #ifdef TLDEBUG 1199 else { 1200 printf("TL_INTR_TxEOF: ack %d\n", ack); 1201 } 1202 #endif 1203 sc->tl_if.if_timer = 0; 1204 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1205 tl_ifstart(&sc->tl_if); 1206 break; 1207 case TL_INTR_Stat: 1208 ack++; 1209 #ifdef TLDEBUG 1210 printf("TL_INTR_Stat: ack %d\n", ack); 1211 #endif 1212 tl_read_stats(sc); 1213 break; 1214 case TL_INTR_Adc: 1215 if (int_reg & TL_INTVec_MASK) { 1216 /* adapter check conditions */ 1217 printf("%s: check condition, intvect=0x%x, " 1218 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1219 int_reg & TL_INTVec_MASK, 1220 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1221 tl_reset(sc); 1222 /* schedule reinit of the board */ 1223 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1224 return(1); 1225 } else { 1226 u_int8_t netstat; 1227 /* Network status */ 1228 netstat = 1229 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1230 printf("%s: network status, NetSts=%x\n", 1231 sc->sc_dev.dv_xname, netstat); 1232 /* Ack interrupts */ 1233 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1234 netstat); 1235 ack++; 1236 } 1237 break; 1238 default: 1239 printf("%s: unhandled interrupt code %x!\n", 1240 sc->sc_dev.dv_xname, int_type); 1241 ack++; 1242 } 1243 1244 if (ack) { 1245 /* Ack the interrupt and enable interrupts */ 1246 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1247 HOST_CMD_IntOn); 1248 #if NRND > 0 1249 if (RND_ENABLED(&sc->rnd_source)) 1250 rnd_add_uint32(&sc->rnd_source, int_reg); 1251 #endif 1252 return 1; 1253 } 1254 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1255 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1256 return 0; 1257 } 1258 1259 static int 1260 tl_ifioctl(ifp, cmd, data) 1261 struct ifnet *ifp; 1262 ioctl_cmd_t cmd; 1263 void *data; 1264 { 1265 struct tl_softc *sc = ifp->if_softc; 1266 int s, error; 1267 1268 s = splnet(); 1269 error = ether_ioctl(ifp, cmd, data); 1270 if (error == ENETRESET) { 1271 if (ifp->if_flags & IFF_RUNNING) 1272 tl_addr_filter(sc); 1273 error = 0; 1274 } 1275 splx(s); 1276 return error; 1277 } 1278 1279 static void 1280 tl_ifstart(ifp) 1281 struct ifnet *ifp; 1282 { 1283 tl_softc_t *sc = ifp->if_softc; 1284 struct mbuf *mb_head; 1285 struct Tx_list *Tx; 1286 int segment, size; 1287 int again, error; 1288 1289 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1290 return; 1291 txloop: 1292 /* If we don't have more space ... */ 1293 if (sc->Free_Tx == NULL) { 1294 #ifdef TLDEBUG 1295 printf("tl_ifstart: No free TX list\n"); 1296 #endif 1297 sc->tl_if.if_flags |= IFF_OACTIVE; 1298 return; 1299 } 1300 /* Grab a paquet for output */ 1301 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1302 if (mb_head == NULL) { 1303 #ifdef TLDEBUG_TX 1304 printf("tl_ifstart: nothing to send\n"); 1305 #endif 1306 return; 1307 } 1308 Tx = sc->Free_Tx; 1309 sc->Free_Tx = Tx->next; 1310 Tx->next = NULL; 1311 again = 0; 1312 /* 1313 * Go through each of the mbufs in the chain and initialize 1314 * the transmit list descriptors with the physical address 1315 * and size of the mbuf. 1316 */ 1317 tbdinit: 1318 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1319 Tx->m = mb_head; 1320 size = mb_head->m_pkthdr.len; 1321 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1322 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1323 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1324 struct mbuf *mn; 1325 /* 1326 * We ran out of segments, or we will. We have to recopy this 1327 * mbuf chain first. 1328 */ 1329 if (error == 0) 1330 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1331 if (again) { 1332 /* already copyed, can't do much more */ 1333 m_freem(mb_head); 1334 goto bad; 1335 } 1336 again = 1; 1337 #ifdef TLDEBUG_TX 1338 printf("tl_ifstart: need to copy mbuf\n"); 1339 #endif 1340 #ifdef TL_PRIV_STATS 1341 sc->oerr_mcopy++; 1342 #endif 1343 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1344 if (mn == NULL) { 1345 m_freem(mb_head); 1346 goto bad; 1347 } 1348 if (mb_head->m_pkthdr.len > MHLEN) { 1349 MCLGET(mn, M_DONTWAIT); 1350 if ((mn->m_flags & M_EXT) == 0) { 1351 m_freem(mn); 1352 m_freem(mb_head); 1353 goto bad; 1354 } 1355 } 1356 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1357 mtod(mn, void *)); 1358 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1359 m_freem(mb_head); 1360 mb_head = mn; 1361 goto tbdinit; 1362 } 1363 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1364 Tx->hw_list->seg[segment].data_addr = 1365 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1366 Tx->hw_list->seg[segment].data_count = 1367 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1368 } 1369 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1370 Tx->m_dmamap->dm_mapsize, 1371 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1372 /* We are at end of mbuf chain. check the size and 1373 * see if it needs to be extended 1374 */ 1375 if (size < ETHER_MIN_TX) { 1376 #ifdef DIAGNOSTIC 1377 if (segment >= TL_NSEG) { 1378 panic("tl_ifstart: to much segmets (%d)", segment); 1379 } 1380 #endif 1381 /* 1382 * add the nullbuf in the seg 1383 */ 1384 Tx->hw_list->seg[segment].data_count = 1385 htole32(ETHER_MIN_TX - size); 1386 Tx->hw_list->seg[segment].data_addr = 1387 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1388 size = ETHER_MIN_TX; 1389 segment++; 1390 } 1391 /* The list is done, finish the list init */ 1392 Tx->hw_list->seg[segment - 1].data_count |= 1393 htole32(TL_LAST_SEG); 1394 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1395 #ifdef TLDEBUG_TX 1396 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1397 le32toh(Tx->hw_list->stat)); 1398 #if 0 1399 for(segment = 0; segment < TL_NSEG; segment++) { 1400 printf(" seg %d addr 0x%x len 0x%x\n", 1401 segment, 1402 le32toh(Tx->hw_list->seg[segment].data_addr), 1403 le32toh(Tx->hw_list->seg[segment].data_count)); 1404 } 1405 #endif 1406 #endif 1407 if (sc->active_Tx == NULL) { 1408 sc->active_Tx = sc->last_Tx = Tx; 1409 #ifdef TLDEBUG_TX 1410 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1411 (int)Tx->hw_listaddr); 1412 #endif 1413 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1414 sizeof(struct tl_Tx_list) * TL_NBUF, 1415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1416 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1417 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1418 } else { 1419 #ifdef TLDEBUG_TX 1420 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1421 (int)Tx->hw_listaddr); 1422 #endif 1423 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1424 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1425 sizeof(struct tl_Tx_list) * TL_NBUF, 1426 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1427 sc->last_Tx->next = Tx; 1428 sc->last_Tx = Tx; 1429 #ifdef DIAGNOSTIC 1430 if (sc->last_Tx->hw_list->fwd & 0x7) 1431 printf("%s: physical addr 0x%x of list not properly " 1432 "aligned\n", 1433 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1434 #endif 1435 } 1436 #if NBPFILTER > 0 1437 /* Pass packet to bpf if there is a listener */ 1438 if (ifp->if_bpf) 1439 bpf_mtap(ifp->if_bpf, mb_head); 1440 #endif 1441 /* 1442 * Set a 5 second timer just in case we don't hear from the card again. 1443 */ 1444 ifp->if_timer = 5; 1445 goto txloop; 1446 bad: 1447 #ifdef TLDEBUG 1448 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1449 #endif 1450 Tx->next = sc->Free_Tx; 1451 sc->Free_Tx = Tx; 1452 return; 1453 } 1454 1455 static void 1456 tl_ifwatchdog(ifp) 1457 struct ifnet *ifp; 1458 { 1459 tl_softc_t *sc = ifp->if_softc; 1460 1461 if ((ifp->if_flags & IFF_RUNNING) == 0) 1462 return; 1463 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1464 ifp->if_oerrors++; 1465 tl_init(ifp); 1466 } 1467 1468 static int 1469 tl_mediachange(ifp) 1470 struct ifnet *ifp; 1471 { 1472 1473 if (ifp->if_flags & IFF_UP) 1474 tl_init(ifp); 1475 return (0); 1476 } 1477 1478 static int tl_add_RxBuff(sc, Rx, oldm) 1479 tl_softc_t *sc; 1480 struct Rx_list *Rx; 1481 struct mbuf *oldm; 1482 { 1483 struct mbuf *m; 1484 int error; 1485 1486 MGETHDR(m, M_DONTWAIT, MT_DATA); 1487 if (m != NULL) { 1488 MCLGET(m, M_DONTWAIT); 1489 if ((m->m_flags & M_EXT) == 0) { 1490 m_freem(m); 1491 if (oldm == NULL) 1492 return 0; 1493 m = oldm; 1494 m->m_data = m->m_ext.ext_buf; 1495 } 1496 } else { 1497 if (oldm == NULL) 1498 return 0; 1499 m = oldm; 1500 m->m_data = m->m_ext.ext_buf; 1501 } 1502 1503 /* (re)init the Rx_list struct */ 1504 1505 Rx->m = m; 1506 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1507 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1508 printf("%s: bus_dmamap_load() failed (error %d) for " 1509 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1510 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1511 m_freem(m); 1512 Rx->m = NULL; 1513 return 0; 1514 } 1515 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1516 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1517 /* 1518 * Move the data pointer up so that the incoming data packet 1519 * will be 32-bit aligned. 1520 */ 1521 m->m_data += 2; 1522 1523 Rx->hw_list->stat = 1524 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1525 Rx->hw_list->seg.data_count = 1526 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1527 Rx->hw_list->seg.data_addr = 1528 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1529 return (m != oldm); 1530 } 1531 1532 static void tl_ticks(v) 1533 void *v; 1534 { 1535 tl_softc_t *sc = v; 1536 1537 tl_read_stats(sc); 1538 1539 /* Tick the MII. */ 1540 mii_tick(&sc->tl_mii); 1541 1542 /* read statistics every seconds */ 1543 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1544 } 1545 1546 static void 1547 tl_read_stats(sc) 1548 tl_softc_t *sc; 1549 { 1550 u_int32_t reg; 1551 int ierr_overr; 1552 int ierr_code; 1553 int ierr_crc; 1554 int oerr_underr; 1555 int oerr_deferred; 1556 int oerr_coll; 1557 int oerr_multicoll; 1558 int oerr_exesscoll; 1559 int oerr_latecoll; 1560 int oerr_carrloss; 1561 struct ifnet *ifp = &sc->tl_if; 1562 1563 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1564 ifp->if_opackets += reg & 0x00ffffff; 1565 oerr_underr = reg >> 24; 1566 1567 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1568 ifp->if_ipackets += reg & 0x00ffffff; 1569 ierr_overr = reg >> 24; 1570 1571 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1572 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1573 ierr_code = (reg & TL_FERR_CODE) >> 24; 1574 oerr_deferred = (reg & TL_FERR_DEF); 1575 1576 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1577 oerr_multicoll = (reg & TL_COL_MULTI); 1578 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1579 1580 reg = tl_intreg_read(sc, TL_INT_LERR); 1581 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1582 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1583 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1584 1585 1586 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1587 oerr_carrloss; 1588 ifp->if_collisions += oerr_coll + oerr_multicoll; 1589 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1590 1591 if (ierr_overr) 1592 printf("%s: receiver ring buffer overrun\n", 1593 sc->sc_dev.dv_xname); 1594 if (oerr_underr) 1595 printf("%s: transmit buffer underrun\n", 1596 sc->sc_dev.dv_xname); 1597 #ifdef TL_PRIV_STATS 1598 sc->ierr_overr += ierr_overr; 1599 sc->ierr_code += ierr_code; 1600 sc->ierr_crc += ierr_crc; 1601 sc->oerr_underr += oerr_underr; 1602 sc->oerr_deferred += oerr_deferred; 1603 sc->oerr_coll += oerr_coll; 1604 sc->oerr_multicoll += oerr_multicoll; 1605 sc->oerr_exesscoll += oerr_exesscoll; 1606 sc->oerr_latecoll += oerr_latecoll; 1607 sc->oerr_carrloss += oerr_carrloss; 1608 #endif 1609 } 1610 1611 static void tl_addr_filter(sc) 1612 tl_softc_t *sc; 1613 { 1614 struct ether_multistep step; 1615 struct ether_multi *enm; 1616 u_int32_t hash[2] = {0, 0}; 1617 int i; 1618 1619 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1620 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1621 while (enm != NULL) { 1622 #ifdef TLDEBUG 1623 printf("tl_addr_filter: addrs %s %s\n", 1624 ether_sprintf(enm->enm_addrlo), 1625 ether_sprintf(enm->enm_addrhi)); 1626 #endif 1627 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1628 i = tl_multicast_hash(enm->enm_addrlo); 1629 hash[i/32] |= 1 << (i%32); 1630 } else { 1631 hash[0] = hash[1] = 0xffffffff; 1632 sc->tl_if.if_flags |= IFF_ALLMULTI; 1633 break; 1634 } 1635 ETHER_NEXT_MULTI(step, enm); 1636 } 1637 #ifdef TLDEBUG 1638 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1639 #endif 1640 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1641 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1642 } 1643 1644 static int tl_multicast_hash(a) 1645 u_int8_t *a; 1646 { 1647 int hash; 1648 1649 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1650 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1651 1652 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1653 DA(a,36), DA(a,42)); 1654 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1655 DA(a,37), DA(a,43)) << 1; 1656 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1657 DA(a,38), DA(a,44)) << 2; 1658 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1659 DA(a,39), DA(a,45)) << 3; 1660 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1661 DA(a,40), DA(a,46)) << 4; 1662 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1663 DA(a,41), DA(a,47)) << 5; 1664 1665 return hash; 1666 } 1667 1668 #if defined(TLDEBUG_RX) 1669 void 1670 ether_printheader(eh) 1671 struct ether_header *eh; 1672 { 1673 u_char *c = (char*)eh; 1674 int i; 1675 for (i=0; i<sizeof(struct ether_header); i++) 1676 printf("%x ", (u_int)c[i]); 1677 printf("\n"); 1678 } 1679 #endif 1680
Indexes created Thu Sep 25 16:09:42 GMT 2025