if_tl.c revision 1.86.4.2 1 /* $NetBSD: if_tl.c,v 1.86.4.2 2009/09/16 13:37:51 yamt Exp $ */
2
3 /*
4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Texas Instruments ThunderLAN ethernet controller
34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A)
35 * available from www.ti.com
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.86.4.2 2009/09/16 13:37:51 yamt Exp $");
40
41 #undef TLDEBUG
42 #define TL_PRIV_STATS
43 #undef TLDEBUG_RX
44 #undef TLDEBUG_TX
45 #undef TLDEBUG_ADDR
46
47 #include "opt_inet.h"
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/mbuf.h>
52 #include <sys/protosw.h>
53 #include <sys/socket.h>
54 #include <sys/ioctl.h>
55 #include <sys/errno.h>
56 #include <sys/malloc.h>
57 #include <sys/kernel.h>
58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */
59 #include <sys/device.h>
60
61 #include <net/if.h>
62 #if defined(SIOCSIFMEDIA)
63 #include <net/if_media.h>
64 #endif
65 #include <net/if_types.h>
66 #include <net/if_dl.h>
67 #include <net/route.h>
68 #include <net/netisr.h>
69
70 #include "bpfilter.h"
71 #if NBPFILTER > 0
72 #include <net/bpf.h>
73 #include <net/bpfdesc.h>
74 #endif
75
76 #include "rnd.h"
77 #if NRND > 0
78 #include <sys/rnd.h>
79 #endif
80
81 #ifdef INET
82 #include <netinet/in.h>
83 #include <netinet/in_systm.h>
84 #include <netinet/in_var.h>
85 #include <netinet/ip.h>
86 #endif
87
88
89 #if defined(__NetBSD__)
90 #include <net/if_ether.h>
91 #include <uvm/uvm_extern.h>
92 #if defined(INET)
93 #include <netinet/if_inarp.h>
94 #endif
95
96 #include <sys/bus.h>
97 #include <sys/intr.h>
98
99 #include <dev/pci/pcireg.h>
100 #include <dev/pci/pcivar.h>
101 #include <dev/pci/pcidevs.h>
102
103 #include <dev/i2c/i2cvar.h>
104 #include <dev/i2c/i2c_bitbang.h>
105 #include <dev/i2c/at24cxxvar.h>
106
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
109
110 #include <dev/mii/tlphyvar.h>
111
112 #include <dev/pci/if_tlregs.h>
113 #include <dev/pci/if_tlvar.h>
114 #endif /* __NetBSD__ */
115
116 /* number of transmit/receive buffers */
117 #ifndef TL_NBUF
118 #define TL_NBUF 32
119 #endif
120
121 static int tl_pci_match(device_t, cfdata_t, void *);
122 static void tl_pci_attach(device_t, device_t, void *);
123 static int tl_intr(void *);
124
125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
126 static int tl_mediachange(struct ifnet *);
127 static void tl_ifwatchdog(struct ifnet *);
128 static bool tl_shutdown(device_t, int);
129
130 static void tl_ifstart(struct ifnet *);
131 static void tl_reset(tl_softc_t *);
132 static int tl_init(struct ifnet *);
133 static void tl_stop(struct ifnet *, int);
134 static void tl_restart(void *);
135 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *);
136 static void tl_read_stats(tl_softc_t *);
137 static void tl_ticks(void *);
138 static int tl_multicast_hash(uint8_t *);
139 static void tl_addr_filter(tl_softc_t *);
140
141 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t);
142 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t);
143 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t);
144 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t);
145
146 void tl_mii_sync(struct tl_softc *);
147 void tl_mii_sendbits(struct tl_softc *, uint32_t, int);
148
149
150 #if defined(TLDEBUG_RX)
151 static void ether_printheader(struct ether_header *);
152 #endif
153
154 int tl_mii_read(device_t, int, int);
155 void tl_mii_write(device_t, int, int, int);
156
157 void tl_statchg(device_t);
158
159 /* I2C glue */
160 static int tl_i2c_acquire_bus(void *, int);
161 static void tl_i2c_release_bus(void *, int);
162 static int tl_i2c_send_start(void *, int);
163 static int tl_i2c_send_stop(void *, int);
164 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int);
165 static int tl_i2c_read_byte(void *, uint8_t *, int);
166 static int tl_i2c_write_byte(void *, uint8_t, int);
167
168 /* I2C bit-bang glue */
169 static void tl_i2cbb_set_bits(void *, uint32_t);
170 static void tl_i2cbb_set_dir(void *, uint32_t);
171 static uint32_t tl_i2cbb_read(void *);
172 static const struct i2c_bitbang_ops tl_i2cbb_ops = {
173 tl_i2cbb_set_bits,
174 tl_i2cbb_set_dir,
175 tl_i2cbb_read,
176 {
177 TL_NETSIO_EDATA, /* SDA */
178 TL_NETSIO_ECLOCK, /* SCL */
179 TL_NETSIO_ETXEN, /* SDA is output */
180 0, /* SDA is input */
181 }
182 };
183
184 static inline void netsio_clr(tl_softc_t *, uint8_t);
185 static inline void netsio_set(tl_softc_t *, uint8_t);
186 static inline uint8_t netsio_read(tl_softc_t *, uint8_t);
187
188 static inline void
189 netsio_clr(tl_softc_t *sc, uint8_t bits)
190 {
191
192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits));
194 }
195
196 static inline void
197 netsio_set(tl_softc_t *sc, uint8_t bits)
198 {
199
200 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
201 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits);
202 }
203
204 static inline uint8_t
205 netsio_read(tl_softc_t *sc, uint8_t bits)
206 {
207
208 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits;
209 }
210
211 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t),
212 tl_pci_match, tl_pci_attach, NULL, NULL);
213
214 static const struct tl_product_desc tl_compaq_products[] = {
215 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T,
216 "Compaq Netelligent 10/100 TX" },
217 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T,
218 "Integrated Compaq Netelligent 10/100 TX" },
219 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5,
220 "Compaq Netelligent 10 T" },
221 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2,
222 "Compaq Netelligent 10 T/2 UTP/Coax" },
223 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2,
224 "Compaq Integrated NetFlex 3/P" },
225 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T,
226 "Compaq ProLiant Integrated Netelligent 10/100 TX" },
227 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
228 "Compaq Dual Port Netelligent 10/100 TX" },
229 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
230 "Compaq Deskpro 4000 5233MMX" },
231 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2,
232 "Compaq NetFlex 3/P w/ BNC" },
233 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5,
234 "Compaq NetFlex 3/P" },
235 { 0, 0, NULL },
236 };
237
238 static const struct tl_product_desc tl_ti_products[] = {
239 /*
240 * Built-in Ethernet on the TI TravelMate 5000
241 * docking station; better product description?
242 */
243 { PCI_PRODUCT_TI_TLAN, 0,
244 "Texas Instruments ThunderLAN" },
245 { 0, 0, NULL },
246 };
247
248 struct tl_vendor_desc {
249 uint32_t tv_vendor;
250 const struct tl_product_desc *tv_products;
251 };
252
253 const struct tl_vendor_desc tl_vendors[] = {
254 { PCI_VENDOR_COMPAQ, tl_compaq_products },
255 { PCI_VENDOR_TI, tl_ti_products },
256 { 0, NULL },
257 };
258
259 static const struct tl_product_desc *tl_lookup_product(uint32_t);
260
261 static const struct tl_product_desc *
262 tl_lookup_product(uint32_t id)
263 {
264 const struct tl_product_desc *tp;
265 const struct tl_vendor_desc *tv;
266
267 for (tv = tl_vendors; tv->tv_products != NULL; tv++)
268 if (PCI_VENDOR(id) == tv->tv_vendor)
269 break;
270
271 if ((tp = tv->tv_products) == NULL)
272 return NULL;
273
274 for (; tp->tp_desc != NULL; tp++)
275 if (PCI_PRODUCT(id) == tp->tp_product)
276 break;
277
278 if (tp->tp_desc == NULL)
279 return NULL;
280
281 return tp;
282 }
283
284 static int
285 tl_pci_match(device_t parent, cfdata_t cf, void *aux)
286 {
287 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
288
289 if (tl_lookup_product(pa->pa_id) != NULL)
290 return 1;
291
292 return 0;
293 }
294
295 static void
296 tl_pci_attach(device_t parent, device_t self, void *aux)
297 {
298 tl_softc_t *sc = device_private(self);
299 struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
300 const struct tl_product_desc *tp;
301 struct ifnet * const ifp = &sc->tl_if;
302 bus_space_tag_t iot, memt;
303 bus_space_handle_t ioh, memh;
304 pci_intr_handle_t intrhandle;
305 const char *intrstr;
306 int ioh_valid, memh_valid;
307 int reg_io, reg_mem;
308 pcireg_t reg10, reg14;
309 pcireg_t csr;
310
311 sc->sc_dev = self;
312 aprint_normal("\n");
313
314 callout_init(&sc->tl_tick_ch, 0);
315 callout_init(&sc->tl_restart_ch, 0);
316
317 tp = tl_lookup_product(pa->pa_id);
318 if (tp == NULL)
319 panic("%s: impossible", __func__);
320 sc->tl_product = tp;
321
322 /*
323 * Map the card space. First we have to find the I/O and MEM
324 * registers. I/O is supposed to be at 0x10, MEM at 0x14,
325 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed.
326 * The ThunderLAN manual is not consistent about this either (there
327 * are both cases in code examples).
328 */
329 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10);
330 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14);
331 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO)
332 reg_io = 0x10;
333 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO)
334 reg_io = 0x14;
335 else
336 reg_io = 0;
337 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM)
338 reg_mem = 0x10;
339 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM)
340 reg_mem = 0x14;
341 else
342 reg_mem = 0;
343
344 if (reg_io != 0)
345 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO,
346 0, &iot, &ioh, NULL, NULL) == 0);
347 else
348 ioh_valid = 0;
349 if (reg_mem != 0)
350 memh_valid = (pci_mapreg_map(pa, PCI_CBMA,
351 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
352 0, &memt, &memh, NULL, NULL) == 0);
353 else
354 memh_valid = 0;
355
356 if (ioh_valid) {
357 sc->tl_bustag = iot;
358 sc->tl_bushandle = ioh;
359 } else if (memh_valid) {
360 sc->tl_bustag = memt;
361 sc->tl_bushandle = memh;
362 } else {
363 aprint_error_dev(self, "unable to map device registers\n");
364 return;
365 }
366 sc->tl_dmatag = pa->pa_dmat;
367
368 /* Enable the device. */
369 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
370 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
371 csr | PCI_COMMAND_MASTER_ENABLE);
372
373 aprint_normal_dev(self, "%s\n", tp->tp_desc);
374
375 tl_reset(sc);
376
377 /* fill in the i2c tag */
378 sc->sc_i2c.ic_cookie = sc;
379 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus;
380 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus;
381 sc->sc_i2c.ic_send_start = tl_i2c_send_start;
382 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop;
383 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer;
384 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte;
385 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte;
386
387 #ifdef TLDEBUG
388 aprint_debug_dev(self, "default values of INTreg: 0x%x\n",
389 tl_intreg_read(sc, TL_INT_Defaults));
390 #endif
391
392 /* read mac addr */
393 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */,
394 sc->tl_enaddr, ETHER_ADDR_LEN)) {
395 aprint_error_dev(self, "error reading Ethernet address\n");
396 return;
397 }
398 aprint_normal_dev(self, "Ethernet address %s\n",
399 ether_sprintf(sc->tl_enaddr));
400
401 /* Map and establish interrupts */
402 if (pci_intr_map(pa, &intrhandle)) {
403 aprint_error_dev(self, "couldn't map interrupt\n");
404 return;
405 }
406 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
407 sc->tl_if.if_softc = sc;
408 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET,
409 tl_intr, sc);
410 if (sc->tl_ih == NULL) {
411 aprint_error_dev(self, "couldn't establish interrupt");
412 if (intrstr != NULL)
413 aprint_error(" at %s", intrstr);
414 aprint_error("\n");
415 return;
416 }
417 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
418
419 /* init these pointers, so that tl_shutdown won't try to read them */
420 sc->Rx_list = NULL;
421 sc->Tx_list = NULL;
422
423 /* allocate DMA-safe memory for control structs */
424 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
425 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 ||
426 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs,
427 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl,
428 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
429 aprint_error_dev(self, "can't allocate DMA memory for lists\n");
430 return;
431 }
432
433 /*
434 * Initialize our media structures and probe the MII.
435 *
436 * Note that we don't care about the media instance. We
437 * are expecting to have multiple PHYs on the 10/100 cards,
438 * and on those cards we exclude the internal PHY from providing
439 * 10baseT. By ignoring the instance, it allows us to not have
440 * to specify it on the command line when switching media.
441 */
442 sc->tl_mii.mii_ifp = ifp;
443 sc->tl_mii.mii_readreg = tl_mii_read;
444 sc->tl_mii.mii_writereg = tl_mii_write;
445 sc->tl_mii.mii_statchg = tl_statchg;
446 sc->tl_ec.ec_mii = &sc->tl_mii;
447 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange,
448 ether_mediastatus);
449 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY,
450 MII_OFFSET_ANY, 0);
451 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) {
452 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
453 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE);
454 } else
455 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO);
456
457 /*
458 * We can support 802.1Q VLAN-sized frames.
459 */
460 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
461
462 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
463 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
464 ifp->if_ioctl = tl_ifioctl;
465 ifp->if_start = tl_ifstart;
466 ifp->if_watchdog = tl_ifwatchdog;
467 ifp->if_init = tl_init;
468 ifp->if_stop = tl_stop;
469 ifp->if_timer = 0;
470 IFQ_SET_READY(&ifp->if_snd);
471 if_attach(ifp);
472 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr);
473
474 /*
475 * Add shutdown hook so that DMA is disabled prior to reboot.
476 * Not doing reboot before the driver initializes.
477 */
478 if (pmf_device_register1(self, NULL, NULL, tl_shutdown))
479 pmf_class_network_register(self, ifp);
480 else
481 aprint_error_dev(self, "couldn't establish power handler\n");
482
483 #if NRND > 0
484 rnd_attach_source(&sc->rnd_source, device_xname(self),
485 RND_TYPE_NET, 0);
486 #endif
487 }
488
489 static void
490 tl_reset(tl_softc_t *sc)
491 {
492 int i;
493
494 /* read stats */
495 if (sc->tl_if.if_flags & IFF_RUNNING) {
496 callout_stop(&sc->tl_tick_ch);
497 tl_read_stats(sc);
498 }
499 /* Reset adapter */
500 TL_HR_WRITE(sc, TL_HOST_CMD,
501 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst);
502 DELAY(100000);
503 /* Disable interrupts */
504 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
505 /* setup aregs & hash */
506 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
507 tl_intreg_write(sc, i, 0);
508 #ifdef TLDEBUG_ADDR
509 printf("Areg & hash registers: \n");
510 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
511 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
512 #endif
513 /* Setup NetConfig */
514 tl_intreg_write(sc, TL_INT_NetConfig,
515 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN);
516 /* Bsize: accept default */
517 /* TX commit in Acommit: accept default */
518 /* Load Ld_tmr and Ld_thr */
519 /* Ld_tmr = 3 */
520 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr);
521 /* Ld_thr = 0 */
522 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr);
523 /* Unreset MII */
524 netsio_set(sc, TL_NETSIO_NMRST);
525 DELAY(100000);
526 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
527 }
528
529 static bool
530 tl_shutdown(device_t self, int howto)
531 {
532 tl_softc_t *sc = device_private(self);
533 struct ifnet *ifp = &sc->tl_if;
534
535 tl_stop(ifp, 1);
536
537 return true;
538 }
539
540 static void
541 tl_stop(struct ifnet *ifp, int disable)
542 {
543 tl_softc_t *sc = ifp->if_softc;
544 struct Tx_list *Tx;
545 int i;
546
547 if ((ifp->if_flags & IFF_RUNNING) == 0)
548 return;
549 /* disable interrupts */
550 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
551 /* stop TX and RX channels */
552 TL_HR_WRITE(sc, TL_HOST_CMD,
553 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes);
554 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP);
555 DELAY(100000);
556
557 /* stop statistics reading loop, read stats */
558 callout_stop(&sc->tl_tick_ch);
559 tl_read_stats(sc);
560
561 /* Down the MII. */
562 mii_down(&sc->tl_mii);
563
564 /* deallocate memory allocations */
565 if (sc->Rx_list) {
566 for (i = 0; i< TL_NBUF; i++) {
567 if (sc->Rx_list[i].m) {
568 bus_dmamap_unload(sc->tl_dmatag,
569 sc->Rx_list[i].m_dmamap);
570 m_freem(sc->Rx_list[i].m);
571 }
572 bus_dmamap_destroy(sc->tl_dmatag,
573 sc->Rx_list[i].m_dmamap);
574 sc->Rx_list[i].m = NULL;
575 }
576 free(sc->Rx_list, M_DEVBUF);
577 sc->Rx_list = NULL;
578 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap);
579 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap);
580 sc->hw_Rx_list = NULL;
581 while ((Tx = sc->active_Tx) != NULL) {
582 Tx->hw_list->stat = 0;
583 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
584 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap);
585 m_freem(Tx->m);
586 sc->active_Tx = Tx->next;
587 Tx->next = sc->Free_Tx;
588 sc->Free_Tx = Tx;
589 }
590 sc->last_Tx = NULL;
591 free(sc->Tx_list, M_DEVBUF);
592 sc->Tx_list = NULL;
593 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap);
594 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap);
595 sc->hw_Tx_list = NULL;
596 }
597 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
598 ifp->if_timer = 0;
599 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
600 }
601
602 static void
603 tl_restart(void *v)
604 {
605
606 tl_init(v);
607 }
608
609 static int
610 tl_init(struct ifnet *ifp)
611 {
612 tl_softc_t *sc = ifp->if_softc;
613 int i, s, error;
614 bus_size_t boundary;
615 prop_number_t prop_boundary;
616 const char *errstring;
617 char *nullbuf;
618
619 s = splnet();
620 /* cancel any pending IO */
621 tl_stop(ifp, 1);
622 tl_reset(sc);
623 if ((sc->tl_if.if_flags & IFF_UP) == 0) {
624 splx(s);
625 return 0;
626 }
627 /* Set various register to reasonable value */
628 /* setup NetCmd in promisc mode if needed */
629 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0;
630 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd,
631 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i);
632 /* Max receive size : MCLBYTES */
633 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff);
634 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH,
635 (MCLBYTES >> 8) & 0xff);
636
637 /* init MAC addr */
638 for (i = 0; i < ETHER_ADDR_LEN; i++)
639 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]);
640 /* add multicast filters */
641 tl_addr_filter(sc);
642 #ifdef TLDEBUG_ADDR
643 printf("Wrote Mac addr, Areg & hash registers are now: \n");
644 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
645 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
646 #endif
647
648 /* Pre-allocate receivers mbuf, make the lists */
649 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF,
650 M_NOWAIT|M_ZERO);
651 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF,
652 M_NOWAIT|M_ZERO);
653 if (sc->Rx_list == NULL || sc->Tx_list == NULL) {
654 errstring = "out of memory for lists";
655 error = ENOMEM;
656 goto bad;
657 }
658
659 /*
660 * Some boards (Set Engineering GFE) do not permit DMA transfers
661 * across page boundaries.
662 */
663 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev),
664 "tl-dma-page-boundary");
665 if (prop_boundary != NULL) {
666 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER);
667 boundary = (bus_size_t)prop_number_integer_value(prop_boundary);
668 } else {
669 boundary = 0;
670 }
671
672 error = bus_dmamap_create(sc->tl_dmatag,
673 sizeof(struct tl_Rx_list) * TL_NBUF, 1,
674 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK,
675 &sc->Rx_dmamap);
676 if (error == 0)
677 error = bus_dmamap_create(sc->tl_dmatag,
678 sizeof(struct tl_Tx_list) * TL_NBUF, 1,
679 sizeof(struct tl_Tx_list) * TL_NBUF, boundary,
680 BUS_DMA_WAITOK, &sc->Tx_dmamap);
681 if (error == 0)
682 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1,
683 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK,
684 &sc->null_dmamap);
685 if (error) {
686 errstring = "can't allocate DMA maps for lists";
687 goto bad;
688 }
689 memset(sc->ctrl, 0, PAGE_SIZE);
690 sc->hw_Rx_list = (void *)sc->ctrl;
691 sc->hw_Tx_list =
692 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF);
693 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF +
694 sizeof(struct tl_Tx_list) * TL_NBUF;
695 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap,
696 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL,
697 BUS_DMA_WAITOK);
698 if (error == 0)
699 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap,
700 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL,
701 BUS_DMA_WAITOK);
702 if (error == 0)
703 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap,
704 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK);
705 if (error) {
706 errstring = "can't DMA map DMA memory for lists";
707 goto bad;
708 }
709 for (i = 0; i < TL_NBUF; i++) {
710 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
711 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
712 &sc->Rx_list[i].m_dmamap);
713 if (error == 0) {
714 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
715 TL_NSEG, MCLBYTES, boundary,
716 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
717 &sc->Tx_list[i].m_dmamap);
718 }
719 if (error) {
720 errstring = "can't allocate DMA maps for mbufs";
721 goto bad;
722 }
723 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i];
724 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr
725 + sizeof(struct tl_Rx_list) * i;
726 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i];
727 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr
728 + sizeof(struct tl_Tx_list) * i;
729 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) {
730 errstring = "out of mbuf for receive list";
731 error = ENOMEM;
732 goto bad;
733 }
734 if (i > 0) { /* chain the list */
735 sc->Rx_list[i - 1].next = &sc->Rx_list[i];
736 sc->hw_Rx_list[i - 1].fwd =
737 htole32(sc->Rx_list[i].hw_listaddr);
738 sc->Tx_list[i - 1].next = &sc->Tx_list[i];
739 }
740 }
741 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0;
742 sc->Rx_list[TL_NBUF - 1].next = NULL;
743 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0;
744 sc->Tx_list[TL_NBUF - 1].next = NULL;
745
746 sc->active_Rx = &sc->Rx_list[0];
747 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1];
748 sc->active_Tx = sc->last_Tx = NULL;
749 sc->Free_Tx = &sc->Tx_list[0];
750 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
751 sizeof(struct tl_Rx_list) * TL_NBUF,
752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
753 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
754 sizeof(struct tl_Tx_list) * TL_NBUF,
755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
756 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX,
757 BUS_DMASYNC_PREWRITE);
758
759 /* set media */
760 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO)
761 error = 0;
762 else if (error != 0) {
763 errstring = "could not set media";
764 goto bad;
765 }
766
767 /* start ticks calls */
768 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
769 /* write address of Rx list and enable interrupts */
770 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr);
771 TL_HR_WRITE(sc, TL_HOST_CMD,
772 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn);
773 sc->tl_if.if_flags |= IFF_RUNNING;
774 sc->tl_if.if_flags &= ~IFF_OACTIVE;
775 splx(s);
776 return 0;
777 bad:
778 printf("%s: %s\n", device_xname(sc->sc_dev), errstring);
779 splx(s);
780 return error;
781 }
782
783
784 static uint32_t
785 tl_intreg_read(tl_softc_t *sc, uint32_t reg)
786 {
787
788 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
789 return TL_HR_READ(sc, TL_HOST_DIO_DATA);
790 }
791
792 static uint8_t
793 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg)
794 {
795
796 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
797 (reg & (~0x07)) & TL_HOST_DIOADR_MASK);
798 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07));
799 }
800
801 static void
802 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val)
803 {
804
805 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
806 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val);
807 }
808
809 static void
810 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val)
811 {
812
813 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
814 (reg & (~0x03)) & TL_HOST_DIOADR_MASK);
815 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val);
816 }
817
818 void
819 tl_mii_sync(struct tl_softc *sc)
820 {
821 int i;
822
823 netsio_clr(sc, TL_NETSIO_MTXEN);
824 for (i = 0; i < 32; i++) {
825 netsio_clr(sc, TL_NETSIO_MCLK);
826 netsio_set(sc, TL_NETSIO_MCLK);
827 }
828 }
829
830 void
831 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits)
832 {
833 int i;
834
835 netsio_set(sc, TL_NETSIO_MTXEN);
836 for (i = 1 << (nbits - 1); i; i = i >> 1) {
837 netsio_clr(sc, TL_NETSIO_MCLK);
838 netsio_read(sc, TL_NETSIO_MCLK);
839 if (data & i)
840 netsio_set(sc, TL_NETSIO_MDATA);
841 else
842 netsio_clr(sc, TL_NETSIO_MDATA);
843 netsio_set(sc, TL_NETSIO_MCLK);
844 netsio_read(sc, TL_NETSIO_MCLK);
845 }
846 }
847
848 int
849 tl_mii_read(device_t self, int phy, int reg)
850 {
851 struct tl_softc *sc = device_private(self);
852 int val = 0, i, err;
853
854 /*
855 * Read the PHY register by manually driving the MII control lines.
856 */
857
858 tl_mii_sync(sc);
859 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
860 tl_mii_sendbits(sc, MII_COMMAND_READ, 2);
861 tl_mii_sendbits(sc, phy, 5);
862 tl_mii_sendbits(sc, reg, 5);
863
864 netsio_clr(sc, TL_NETSIO_MTXEN);
865 netsio_clr(sc, TL_NETSIO_MCLK);
866 netsio_set(sc, TL_NETSIO_MCLK);
867 netsio_clr(sc, TL_NETSIO_MCLK);
868
869 err = netsio_read(sc, TL_NETSIO_MDATA);
870 netsio_set(sc, TL_NETSIO_MCLK);
871
872 /* Even if an error occurs, must still clock out the cycle. */
873 for (i = 0; i < 16; i++) {
874 val <<= 1;
875 netsio_clr(sc, TL_NETSIO_MCLK);
876 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA))
877 val |= 1;
878 netsio_set(sc, TL_NETSIO_MCLK);
879 }
880 netsio_clr(sc, TL_NETSIO_MCLK);
881 netsio_set(sc, TL_NETSIO_MCLK);
882
883 return err ? 0 : val;
884 }
885
886 void
887 tl_mii_write(device_t self, int phy, int reg, int val)
888 {
889 struct tl_softc *sc = device_private(self);
890
891 /*
892 * Write the PHY register by manually driving the MII control lines.
893 */
894
895 tl_mii_sync(sc);
896 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
897 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
898 tl_mii_sendbits(sc, phy, 5);
899 tl_mii_sendbits(sc, reg, 5);
900 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2);
901 tl_mii_sendbits(sc, val, 16);
902
903 netsio_clr(sc, TL_NETSIO_MCLK);
904 netsio_set(sc, TL_NETSIO_MCLK);
905 }
906
907 void
908 tl_statchg(device_t self)
909 {
910 tl_softc_t *sc = device_private(self);
911 uint32_t reg;
912
913 #ifdef TLDEBUG
914 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media);
915 #endif
916
917 /*
918 * We must keep the ThunderLAN and the PHY in sync as
919 * to the status of full-duplex!
920 */
921 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd);
922 if (sc->tl_mii.mii_media_active & IFM_FDX)
923 reg |= TL_NETCOMMAND_DUPLEX;
924 else
925 reg &= ~TL_NETCOMMAND_DUPLEX;
926 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg);
927 }
928
929 /********** I2C glue **********/
930
931 static int
932 tl_i2c_acquire_bus(void *cookie, int flags)
933 {
934
935 /* private bus */
936 return 0;
937 }
938
939 static void
940 tl_i2c_release_bus(void *cookie, int flags)
941 {
942
943 /* private bus */
944 }
945
946 static int
947 tl_i2c_send_start(void *cookie, int flags)
948 {
949
950 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops);
951 }
952
953 static int
954 tl_i2c_send_stop(void *cookie, int flags)
955 {
956
957 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops);
958 }
959
960 static int
961 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
962 {
963
964 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops);
965 }
966
967 static int
968 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
969 {
970
971 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops);
972 }
973
974 static int
975 tl_i2c_write_byte(void *cookie, uint8_t val, int flags)
976 {
977
978 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops);
979 }
980
981 /********** I2C bit-bang glue **********/
982
983 static void
984 tl_i2cbb_set_bits(void *cookie, uint32_t bits)
985 {
986 struct tl_softc *sc = cookie;
987 uint8_t reg;
988
989 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
990 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits;
991 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
992 }
993
994 static void
995 tl_i2cbb_set_dir(void *cookie, uint32_t bits)
996 {
997 struct tl_softc *sc = cookie;
998 uint8_t reg;
999
1000 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
1001 reg = (reg & ~TL_NETSIO_ETXEN) | bits;
1002 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
1003 }
1004
1005 static uint32_t
1006 tl_i2cbb_read(void *cookie)
1007 {
1008
1009 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio);
1010 }
1011
1012 /********** End of I2C stuff **********/
1013
1014 static int
1015 tl_intr(void *v)
1016 {
1017 tl_softc_t *sc = v;
1018 struct ifnet *ifp = &sc->tl_if;
1019 struct Rx_list *Rx;
1020 struct Tx_list *Tx;
1021 struct mbuf *m;
1022 uint32_t int_type, int_reg;
1023 int ack = 0;
1024 int size;
1025
1026 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR);
1027 int_type = int_reg & TL_INTR_MASK;
1028 if (int_type == 0)
1029 return 0;
1030 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX)
1031 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev),
1032 int_type, int_reg);
1033 #endif
1034 /* disable interrupts */
1035 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
1036 switch(int_type & TL_INTR_MASK) {
1037 case TL_INTR_RxEOF:
1038 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1039 sizeof(struct tl_Rx_list) * TL_NBUF,
1040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1041 while(le32toh(sc->active_Rx->hw_list->stat) &
1042 TL_RX_CSTAT_CPLT) {
1043 /* dequeue and requeue at end of list */
1044 ack++;
1045 Rx = sc->active_Rx;
1046 sc->active_Rx = Rx->next;
1047 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1048 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1049 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap);
1050 m = Rx->m;
1051 size = le32toh(Rx->hw_list->stat) >> 16;
1052 #ifdef TLDEBUG_RX
1053 printf("%s: RX list complete, Rx %p, size=%d\n",
1054 __func__, Rx, size);
1055 #endif
1056 if (tl_add_RxBuff(sc, Rx, m) == 0) {
1057 /*
1058 * No new mbuf, reuse the same. This means
1059 * that this packet
1060 * is lost
1061 */
1062 m = NULL;
1063 #ifdef TL_PRIV_STATS
1064 sc->ierr_nomem++;
1065 #endif
1066 #ifdef TLDEBUG
1067 printf("%s: out of mbuf, lost input packet\n",
1068 device_xname(sc->sc_dev));
1069 #endif
1070 }
1071 Rx->next = NULL;
1072 Rx->hw_list->fwd = 0;
1073 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr);
1074 sc->last_Rx->next = Rx;
1075 sc->last_Rx = Rx;
1076
1077 /* deliver packet */
1078 if (m) {
1079 if (size < sizeof(struct ether_header)) {
1080 m_freem(m);
1081 continue;
1082 }
1083 m->m_pkthdr.rcvif = ifp;
1084 m->m_pkthdr.len = m->m_len = size;
1085 #ifdef TLDEBUG_RX
1086 {
1087 struct ether_header *eh =
1088 mtod(m, struct ether_header *);
1089 printf("%s: Rx packet:\n", __func__);
1090 ether_printheader(eh);
1091 }
1092 #endif
1093 #if NBPFILTER > 0
1094 if (ifp->if_bpf)
1095 bpf_mtap(ifp->if_bpf, m);
1096 #endif /* NBPFILTER > 0 */
1097 (*ifp->if_input)(ifp, m);
1098 }
1099 }
1100 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1101 sizeof(struct tl_Rx_list) * TL_NBUF,
1102 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1103 #ifdef TLDEBUG_RX
1104 printf("TL_INTR_RxEOF: ack %d\n", ack);
1105 #else
1106 if (ack == 0) {
1107 printf("%s: EOF intr without anything to read !\n",
1108 device_xname(sc->sc_dev));
1109 tl_reset(sc);
1110 /* schedule reinit of the board */
1111 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1112 return 1;
1113 }
1114 #endif
1115 break;
1116 case TL_INTR_RxEOC:
1117 ack++;
1118 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1119 sizeof(struct tl_Rx_list) * TL_NBUF,
1120 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1121 #ifdef TLDEBUG_RX
1122 printf("TL_INTR_RxEOC: ack %d\n", ack);
1123 #endif
1124 #ifdef DIAGNOSTIC
1125 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) {
1126 printf("%s: Rx EOC interrupt and active Tx list not "
1127 "cleared\n", device_xname(sc->sc_dev));
1128 return 0;
1129 } else
1130 #endif
1131 {
1132 /*
1133 * write address of Rx list and send Rx GO command, ack
1134 * interrupt and enable interrupts in one command
1135 */
1136 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr);
1137 TL_HR_WRITE(sc, TL_HOST_CMD,
1138 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type |
1139 HOST_CMD_ACK | HOST_CMD_IntOn);
1140 return 1;
1141 }
1142 case TL_INTR_TxEOF:
1143 case TL_INTR_TxEOC:
1144 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1145 sizeof(struct tl_Tx_list) * TL_NBUF,
1146 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1147 while ((Tx = sc->active_Tx) != NULL) {
1148 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0)
1149 break;
1150 ack++;
1151 #ifdef TLDEBUG_TX
1152 printf("TL_INTR_TxEOC: list 0x%x done\n",
1153 (int)Tx->hw_listaddr);
1154 #endif
1155 Tx->hw_list->stat = 0;
1156 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1157 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1158 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1159 m_freem(Tx->m);
1160 Tx->m = NULL;
1161 sc->active_Tx = Tx->next;
1162 if (sc->active_Tx == NULL)
1163 sc->last_Tx = NULL;
1164 Tx->next = sc->Free_Tx;
1165 sc->Free_Tx = Tx;
1166 }
1167 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1168 sizeof(struct tl_Tx_list) * TL_NBUF,
1169 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1170 /* if this was an EOC, ACK immediatly */
1171 if (ack)
1172 sc->tl_if.if_flags &= ~IFF_OACTIVE;
1173 if (int_type == TL_INTR_TxEOC) {
1174 #ifdef TLDEBUG_TX
1175 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n",
1176 ack);
1177 #endif
1178 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type |
1179 HOST_CMD_ACK | HOST_CMD_IntOn);
1180 if (sc->active_Tx != NULL) {
1181 /* needs a Tx go command */
1182 TL_HR_WRITE(sc, TL_HOST_CH_PARM,
1183 sc->active_Tx->hw_listaddr);
1184 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1185 }
1186 sc->tl_if.if_timer = 0;
1187 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1188 tl_ifstart(&sc->tl_if);
1189 return 1;
1190 }
1191 #ifdef TLDEBUG
1192 else {
1193 printf("TL_INTR_TxEOF: ack %d\n", ack);
1194 }
1195 #endif
1196 sc->tl_if.if_timer = 0;
1197 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1198 tl_ifstart(&sc->tl_if);
1199 break;
1200 case TL_INTR_Stat:
1201 ack++;
1202 #ifdef TLDEBUG
1203 printf("TL_INTR_Stat: ack %d\n", ack);
1204 #endif
1205 tl_read_stats(sc);
1206 break;
1207 case TL_INTR_Adc:
1208 if (int_reg & TL_INTVec_MASK) {
1209 /* adapter check conditions */
1210 printf("%s: check condition, intvect=0x%x, "
1211 "ch_param=0x%x\n", device_xname(sc->sc_dev),
1212 int_reg & TL_INTVec_MASK,
1213 TL_HR_READ(sc, TL_HOST_CH_PARM));
1214 tl_reset(sc);
1215 /* schedule reinit of the board */
1216 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1217 return 1;
1218 } else {
1219 uint8_t netstat;
1220 /* Network status */
1221 netstat =
1222 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts);
1223 printf("%s: network status, NetSts=%x\n",
1224 device_xname(sc->sc_dev), netstat);
1225 /* Ack interrupts */
1226 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts,
1227 netstat);
1228 ack++;
1229 }
1230 break;
1231 default:
1232 printf("%s: unhandled interrupt code %x!\n",
1233 device_xname(sc->sc_dev), int_type);
1234 ack++;
1235 }
1236
1237 if (ack) {
1238 /* Ack the interrupt and enable interrupts */
1239 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK |
1240 HOST_CMD_IntOn);
1241 #if NRND > 0
1242 if (RND_ENABLED(&sc->rnd_source))
1243 rnd_add_uint32(&sc->rnd_source, int_reg);
1244 #endif
1245 return 1;
1246 }
1247 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */
1248 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn);
1249 return 0;
1250 }
1251
1252 static int
1253 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1254 {
1255 struct tl_softc *sc = ifp->if_softc;
1256 int s, error;
1257
1258 s = splnet();
1259 error = ether_ioctl(ifp, cmd, data);
1260 if (error == ENETRESET) {
1261 if (ifp->if_flags & IFF_RUNNING)
1262 tl_addr_filter(sc);
1263 error = 0;
1264 }
1265 splx(s);
1266 return error;
1267 }
1268
1269 static void
1270 tl_ifstart(struct ifnet *ifp)
1271 {
1272 tl_softc_t *sc = ifp->if_softc;
1273 struct mbuf *mb_head;
1274 struct Tx_list *Tx;
1275 int segment, size;
1276 int again, error;
1277
1278 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1279 return;
1280 txloop:
1281 /* If we don't have more space ... */
1282 if (sc->Free_Tx == NULL) {
1283 #ifdef TLDEBUG
1284 printf("%s: No free TX list\n", __func__);
1285 #endif
1286 sc->tl_if.if_flags |= IFF_OACTIVE;
1287 return;
1288 }
1289 /* Grab a paquet for output */
1290 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1291 if (mb_head == NULL) {
1292 #ifdef TLDEBUG_TX
1293 printf("%s: nothing to send\n", __func__);
1294 #endif
1295 return;
1296 }
1297 Tx = sc->Free_Tx;
1298 sc->Free_Tx = Tx->next;
1299 Tx->next = NULL;
1300 again = 0;
1301 /*
1302 * Go through each of the mbufs in the chain and initialize
1303 * the transmit list descriptors with the physical address
1304 * and size of the mbuf.
1305 */
1306 tbdinit:
1307 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list));
1308 Tx->m = mb_head;
1309 size = mb_head->m_pkthdr.len;
1310 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head,
1311 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX &&
1312 Tx->m_dmamap->dm_nsegs == TL_NSEG)) {
1313 struct mbuf *mn;
1314 /*
1315 * We ran out of segments, or we will. We have to recopy this
1316 * mbuf chain first.
1317 */
1318 if (error == 0)
1319 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1320 if (again) {
1321 /* already copyed, can't do much more */
1322 m_freem(mb_head);
1323 goto bad;
1324 }
1325 again = 1;
1326 #ifdef TLDEBUG_TX
1327 printf("%s: need to copy mbuf\n", __func__);
1328 #endif
1329 #ifdef TL_PRIV_STATS
1330 sc->oerr_mcopy++;
1331 #endif
1332 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1333 if (mn == NULL) {
1334 m_freem(mb_head);
1335 goto bad;
1336 }
1337 if (mb_head->m_pkthdr.len > MHLEN) {
1338 MCLGET(mn, M_DONTWAIT);
1339 if ((mn->m_flags & M_EXT) == 0) {
1340 m_freem(mn);
1341 m_freem(mb_head);
1342 goto bad;
1343 }
1344 }
1345 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1346 mtod(mn, void *));
1347 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1348 m_freem(mb_head);
1349 mb_head = mn;
1350 goto tbdinit;
1351 }
1352 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) {
1353 Tx->hw_list->seg[segment].data_addr =
1354 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr);
1355 Tx->hw_list->seg[segment].data_count =
1356 htole32(Tx->m_dmamap->dm_segs[segment].ds_len);
1357 }
1358 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1359 Tx->m_dmamap->dm_mapsize,
1360 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1361 /* We are at end of mbuf chain. check the size and
1362 * see if it needs to be extended
1363 */
1364 if (size < ETHER_MIN_TX) {
1365 #ifdef DIAGNOSTIC
1366 if (segment >= TL_NSEG) {
1367 panic("%s: to much segmets (%d)", __func__, segment);
1368 }
1369 #endif
1370 /*
1371 * add the nullbuf in the seg
1372 */
1373 Tx->hw_list->seg[segment].data_count =
1374 htole32(ETHER_MIN_TX - size);
1375 Tx->hw_list->seg[segment].data_addr =
1376 htole32(sc->null_dmamap->dm_segs[0].ds_addr);
1377 size = ETHER_MIN_TX;
1378 segment++;
1379 }
1380 /* The list is done, finish the list init */
1381 Tx->hw_list->seg[segment - 1].data_count |=
1382 htole32(TL_LAST_SEG);
1383 Tx->hw_list->stat = htole32((size << 16) | 0x3000);
1384 #ifdef TLDEBUG_TX
1385 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev),
1386 le32toh(Tx->hw_list->stat));
1387 #if 0
1388 for (segment = 0; segment < TL_NSEG; segment++) {
1389 printf(" seg %d addr 0x%x len 0x%x\n",
1390 segment,
1391 le32toh(Tx->hw_list->seg[segment].data_addr),
1392 le32toh(Tx->hw_list->seg[segment].data_count));
1393 }
1394 #endif
1395 #endif
1396 if (sc->active_Tx == NULL) {
1397 sc->active_Tx = sc->last_Tx = Tx;
1398 #ifdef TLDEBUG_TX
1399 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev),
1400 (int)Tx->hw_listaddr);
1401 #endif
1402 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1403 sizeof(struct tl_Tx_list) * TL_NBUF,
1404 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1405 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr);
1406 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1407 } else {
1408 #ifdef TLDEBUG_TX
1409 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev),
1410 (int)Tx->hw_listaddr);
1411 #endif
1412 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr);
1413 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1414 sizeof(struct tl_Tx_list) * TL_NBUF,
1415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1416 sc->last_Tx->next = Tx;
1417 sc->last_Tx = Tx;
1418 #ifdef DIAGNOSTIC
1419 if (sc->last_Tx->hw_list->fwd & 0x7)
1420 printf("%s: physical addr 0x%x of list not properly "
1421 "aligned\n",
1422 device_xname(sc->sc_dev),
1423 sc->last_Rx->hw_list->fwd);
1424 #endif
1425 }
1426 #if NBPFILTER > 0
1427 /* Pass packet to bpf if there is a listener */
1428 if (ifp->if_bpf)
1429 bpf_mtap(ifp->if_bpf, mb_head);
1430 #endif
1431 /*
1432 * Set a 5 second timer just in case we don't hear from the card again.
1433 */
1434 ifp->if_timer = 5;
1435 goto txloop;
1436 bad:
1437 #ifdef TLDEBUG
1438 printf("%s: Out of mbuf, Tx pkt lost\n", __func__);
1439 #endif
1440 Tx->next = sc->Free_Tx;
1441 sc->Free_Tx = Tx;
1442 }
1443
1444 static void
1445 tl_ifwatchdog(struct ifnet *ifp)
1446 {
1447 tl_softc_t *sc = ifp->if_softc;
1448
1449 if ((ifp->if_flags & IFF_RUNNING) == 0)
1450 return;
1451 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1452 ifp->if_oerrors++;
1453 tl_init(ifp);
1454 }
1455
1456 static int
1457 tl_mediachange(struct ifnet *ifp)
1458 {
1459
1460 if (ifp->if_flags & IFF_UP)
1461 tl_init(ifp);
1462 return 0;
1463 }
1464
1465 static int
1466 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm)
1467 {
1468 struct mbuf *m;
1469 int error;
1470
1471 MGETHDR(m, M_DONTWAIT, MT_DATA);
1472 if (m != NULL) {
1473 MCLGET(m, M_DONTWAIT);
1474 if ((m->m_flags & M_EXT) == 0) {
1475 m_freem(m);
1476 if (oldm == NULL)
1477 return 0;
1478 m = oldm;
1479 m->m_data = m->m_ext.ext_buf;
1480 }
1481 } else {
1482 if (oldm == NULL)
1483 return 0;
1484 m = oldm;
1485 m->m_data = m->m_ext.ext_buf;
1486 }
1487
1488 /* (re)init the Rx_list struct */
1489
1490 Rx->m = m;
1491 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap,
1492 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
1493 printf("%s: bus_dmamap_load() failed (error %d) for "
1494 "tl_add_RxBuff ", device_xname(sc->sc_dev), error);
1495 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES);
1496 m_freem(m);
1497 Rx->m = NULL;
1498 return 0;
1499 }
1500 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1501 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1502 /*
1503 * Move the data pointer up so that the incoming data packet
1504 * will be 32-bit aligned.
1505 */
1506 m->m_data += 2;
1507
1508 Rx->hw_list->stat =
1509 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000);
1510 Rx->hw_list->seg.data_count =
1511 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2);
1512 Rx->hw_list->seg.data_addr =
1513 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2);
1514 return (m != oldm);
1515 }
1516
1517 static void
1518 tl_ticks(void *v)
1519 {
1520 tl_softc_t *sc = v;
1521
1522 tl_read_stats(sc);
1523
1524 /* Tick the MII. */
1525 mii_tick(&sc->tl_mii);
1526
1527 /* read statistics every seconds */
1528 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
1529 }
1530
1531 static void
1532 tl_read_stats(tl_softc_t *sc)
1533 {
1534 uint32_t reg;
1535 int ierr_overr;
1536 int ierr_code;
1537 int ierr_crc;
1538 int oerr_underr;
1539 int oerr_deferred;
1540 int oerr_coll;
1541 int oerr_multicoll;
1542 int oerr_exesscoll;
1543 int oerr_latecoll;
1544 int oerr_carrloss;
1545 struct ifnet *ifp = &sc->tl_if;
1546
1547 reg = tl_intreg_read(sc, TL_INT_STATS_TX);
1548 ifp->if_opackets += reg & 0x00ffffff;
1549 oerr_underr = reg >> 24;
1550
1551 reg = tl_intreg_read(sc, TL_INT_STATS_RX);
1552 ifp->if_ipackets += reg & 0x00ffffff;
1553 ierr_overr = reg >> 24;
1554
1555 reg = tl_intreg_read(sc, TL_INT_STATS_FERR);
1556 ierr_crc = (reg & TL_FERR_CRC) >> 16;
1557 ierr_code = (reg & TL_FERR_CODE) >> 24;
1558 oerr_deferred = (reg & TL_FERR_DEF);
1559
1560 reg = tl_intreg_read(sc, TL_INT_STATS_COLL);
1561 oerr_multicoll = (reg & TL_COL_MULTI);
1562 oerr_coll = (reg & TL_COL_SINGLE) >> 16;
1563
1564 reg = tl_intreg_read(sc, TL_INT_LERR);
1565 oerr_exesscoll = (reg & TL_LERR_ECOLL);
1566 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8;
1567 oerr_carrloss = (reg & TL_LERR_CL) >> 16;
1568
1569
1570 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll +
1571 oerr_carrloss;
1572 ifp->if_collisions += oerr_coll + oerr_multicoll;
1573 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc;
1574
1575 if (ierr_overr)
1576 printf("%s: receiver ring buffer overrun\n",
1577 device_xname(sc->sc_dev));
1578 if (oerr_underr)
1579 printf("%s: transmit buffer underrun\n",
1580 device_xname(sc->sc_dev));
1581 #ifdef TL_PRIV_STATS
1582 sc->ierr_overr += ierr_overr;
1583 sc->ierr_code += ierr_code;
1584 sc->ierr_crc += ierr_crc;
1585 sc->oerr_underr += oerr_underr;
1586 sc->oerr_deferred += oerr_deferred;
1587 sc->oerr_coll += oerr_coll;
1588 sc->oerr_multicoll += oerr_multicoll;
1589 sc->oerr_exesscoll += oerr_exesscoll;
1590 sc->oerr_latecoll += oerr_latecoll;
1591 sc->oerr_carrloss += oerr_carrloss;
1592 #endif
1593 }
1594
1595 static void
1596 tl_addr_filter(tl_softc_t *sc)
1597 {
1598 struct ether_multistep step;
1599 struct ether_multi *enm;
1600 uint32_t hash[2] = {0, 0};
1601 int i;
1602
1603 sc->tl_if.if_flags &= ~IFF_ALLMULTI;
1604 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm);
1605 while (enm != NULL) {
1606 #ifdef TLDEBUG
1607 printf("%s: addrs %s %s\n", __func__,
1608 ether_sprintf(enm->enm_addrlo),
1609 ether_sprintf(enm->enm_addrhi));
1610 #endif
1611 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1612 i = tl_multicast_hash(enm->enm_addrlo);
1613 hash[i / 32] |= 1 << (i%32);
1614 } else {
1615 hash[0] = hash[1] = 0xffffffff;
1616 sc->tl_if.if_flags |= IFF_ALLMULTI;
1617 break;
1618 }
1619 ETHER_NEXT_MULTI(step, enm);
1620 }
1621 #ifdef TLDEBUG
1622 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1623 #endif
1624 tl_intreg_write(sc, TL_INT_HASH1, hash[0]);
1625 tl_intreg_write(sc, TL_INT_HASH2, hash[1]);
1626 }
1627
1628 static int
1629 tl_multicast_hash(uint8_t *a)
1630 {
1631 int hash;
1632
1633 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1634 #define xor8(a,b,c,d,e,f,g,h) \
1635 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \
1636 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1637
1638 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1639 DA(a,36), DA(a,42));
1640 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1641 DA(a,37), DA(a,43)) << 1;
1642 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1643 DA(a,38), DA(a,44)) << 2;
1644 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1645 DA(a,39), DA(a,45)) << 3;
1646 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1647 DA(a,40), DA(a,46)) << 4;
1648 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1649 DA(a,41), DA(a,47)) << 5;
1650
1651 return hash;
1652 }
1653
1654 #if defined(TLDEBUG_RX)
1655 void
1656 ether_printheader(struct ether_header *eh)
1657 {
1658 uint8_t *c = (uint8_t *)eh;
1659 int i;
1660
1661 for (i = 0; i < sizeof(struct ether_header); i++)
1662 printf("%02x ", (u_int)c[i]);
1663 printf("\n");
1664 }
1665 #endif
1666