if_tl.c revision 1.87
1 /* $NetBSD: if_tl.c,v 1.87 2008/05/22 01:23:48 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.87 2008/05/22 01:23:48 dyoung Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #include "rnd.h" 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #endif 87 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match(struct device *, struct cfdata *, void *); 122 static void tl_pci_attach(struct device *, struct device *, void *); 123 static int tl_intr(void *); 124 125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 126 static int tl_mediachange(struct ifnet *); 127 static void tl_ifwatchdog(struct ifnet *); 128 static void tl_shutdown(void*); 129 130 static void tl_ifstart(struct ifnet *); 131 static void tl_reset(tl_softc_t*); 132 static int tl_init(struct ifnet *); 133 static void tl_stop(struct ifnet *, int); 134 static void tl_restart(void *); 135 static int tl_add_RxBuff(tl_softc_t*, struct Rx_list*, struct mbuf*); 136 static void tl_read_stats(tl_softc_t*); 137 static void tl_ticks(void*); 138 static int tl_multicast_hash(u_int8_t*); 139 static void tl_addr_filter(tl_softc_t*); 140 141 static u_int32_t tl_intreg_read(tl_softc_t*, u_int32_t); 142 static void tl_intreg_write(tl_softc_t*, u_int32_t, u_int32_t); 143 static u_int8_t tl_intreg_read_byte(tl_softc_t*, u_int32_t); 144 static void tl_intreg_write_byte(tl_softc_t*, u_int32_t, u_int8_t); 145 146 void tl_mii_sync(struct tl_softc *); 147 void tl_mii_sendbits(struct tl_softc *, u_int32_t, int); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader(struct ether_header*); 152 #endif 153 154 int tl_mii_read(struct device *, int, int); 155 void tl_mii_write(struct device *, int, int, int); 156 157 void tl_statchg(struct device *); 158 159 /* I2C glue */ 160 static int tl_i2c_acquire_bus(void *, int); 161 static void tl_i2c_release_bus(void *, int); 162 static int tl_i2c_send_start(void *, int); 163 static int tl_i2c_send_stop(void *, int); 164 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 165 static int tl_i2c_read_byte(void *, uint8_t *, int); 166 static int tl_i2c_write_byte(void *, uint8_t, int); 167 168 /* I2C bit-bang glue */ 169 static void tl_i2cbb_set_bits(void *, uint32_t); 170 static void tl_i2cbb_set_dir(void *, uint32_t); 171 static uint32_t tl_i2cbb_read(void *); 172 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 173 tl_i2cbb_set_bits, 174 tl_i2cbb_set_dir, 175 tl_i2cbb_read, 176 { 177 TL_NETSIO_EDATA, /* SDA */ 178 TL_NETSIO_ECLOCK, /* SCL */ 179 TL_NETSIO_ETXEN, /* SDA is output */ 180 0, /* SDA is input */ 181 } 182 }; 183 184 static inline void netsio_clr(tl_softc_t*, u_int8_t); 185 static inline void netsio_set(tl_softc_t*, u_int8_t); 186 static inline u_int8_t netsio_read(tl_softc_t*, u_int8_t); 187 static inline void netsio_clr(sc, bits) 188 tl_softc_t* sc; 189 u_int8_t bits; 190 { 191 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 192 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 193 } 194 static inline void netsio_set(sc, bits) 195 tl_softc_t* sc; 196 u_int8_t bits; 197 { 198 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 199 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 200 } 201 static inline u_int8_t netsio_read(sc, bits) 202 tl_softc_t* sc; 203 u_int8_t bits; 204 { 205 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 206 } 207 208 CFATTACH_DECL(tl, sizeof(tl_softc_t), 209 tl_pci_match, tl_pci_attach, NULL, NULL); 210 211 const struct tl_product_desc tl_compaq_products[] = { 212 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 213 "Compaq Netelligent 10/100 TX" }, 214 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 215 "Integrated Compaq Netelligent 10/100 TX" }, 216 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 217 "Compaq Netelligent 10 T" }, 218 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 219 "Compaq Netelligent 10 T/2 UTP/Coax" }, 220 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 221 "Compaq Integrated NetFlex 3/P" }, 222 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 223 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 224 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 225 "Compaq Dual Port Netelligent 10/100 TX" }, 226 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 227 "Compaq Deskpro 4000 5233MMX" }, 228 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 229 "Compaq NetFlex 3/P w/ BNC" }, 230 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 231 "Compaq NetFlex 3/P" }, 232 { 0, 0, NULL }, 233 }; 234 235 const struct tl_product_desc tl_ti_products[] = { 236 /* 237 * Built-in Ethernet on the TI TravelMate 5000 238 * docking station; better product description? 239 */ 240 { PCI_PRODUCT_TI_TLAN, 0, 241 "Texas Instruments ThunderLAN" }, 242 { 0, 0, NULL }, 243 }; 244 245 struct tl_vendor_desc { 246 u_int32_t tv_vendor; 247 const struct tl_product_desc *tv_products; 248 }; 249 250 const struct tl_vendor_desc tl_vendors[] = { 251 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 252 { PCI_VENDOR_TI, tl_ti_products }, 253 { 0, NULL }, 254 }; 255 256 const struct tl_product_desc *tl_lookup_product(u_int32_t); 257 258 const struct tl_product_desc * 259 tl_lookup_product(id) 260 u_int32_t id; 261 { 262 const struct tl_product_desc *tp; 263 const struct tl_vendor_desc *tv; 264 265 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 266 if (PCI_VENDOR(id) == tv->tv_vendor) 267 break; 268 269 if ((tp = tv->tv_products) == NULL) 270 return (NULL); 271 272 for (; tp->tp_desc != NULL; tp++) 273 if (PCI_PRODUCT(id) == tp->tp_product) 274 break; 275 276 if (tp->tp_desc == NULL) 277 return (NULL); 278 279 return (tp); 280 } 281 282 static int 283 tl_pci_match(struct device *parent, struct cfdata *match, 284 void *aux) 285 { 286 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 287 288 if (tl_lookup_product(pa->pa_id) != NULL) 289 return (1); 290 291 return (0); 292 } 293 294 static void 295 tl_pci_attach(struct device *parent, struct device *self, void *aux) 296 { 297 tl_softc_t *sc = (tl_softc_t *)self; 298 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 299 const struct tl_product_desc *tp; 300 struct ifnet * const ifp = &sc->tl_if; 301 bus_space_tag_t iot, memt; 302 bus_space_handle_t ioh, memh; 303 pci_intr_handle_t intrhandle; 304 const char *intrstr; 305 int ioh_valid, memh_valid; 306 int reg_io, reg_mem; 307 pcireg_t reg10, reg14; 308 pcireg_t csr; 309 310 printf("\n"); 311 312 callout_init(&sc->tl_tick_ch, 0); 313 callout_init(&sc->tl_restart_ch, 0); 314 315 tp = tl_lookup_product(pa->pa_id); 316 if (tp == NULL) 317 panic("tl_pci_attach: impossible"); 318 sc->tl_product = tp; 319 320 /* 321 * Map the card space. First we have to find the I/O and MEM 322 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 323 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 324 * The ThunderLAN manual is not consistent about this either (there 325 * are both cases in code examples). 326 */ 327 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 328 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 329 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 330 reg_io = 0x10; 331 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 332 reg_io = 0x14; 333 else 334 reg_io = 0; 335 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 336 reg_mem = 0x10; 337 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 338 reg_mem = 0x14; 339 else 340 reg_mem = 0; 341 342 if (reg_io != 0) 343 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 344 0, &iot, &ioh, NULL, NULL) == 0); 345 else 346 ioh_valid = 0; 347 if (reg_mem != 0) 348 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 349 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 350 0, &memt, &memh, NULL, NULL) == 0); 351 else 352 memh_valid = 0; 353 354 if (ioh_valid) { 355 sc->tl_bustag = iot; 356 sc->tl_bushandle = ioh; 357 } else if (memh_valid) { 358 sc->tl_bustag = memt; 359 sc->tl_bushandle = memh; 360 } else { 361 aprint_error_dev(&sc->sc_dev, "unable to map device registers\n"); 362 return; 363 } 364 sc->tl_dmatag = pa->pa_dmat; 365 366 /* Enable the device. */ 367 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 368 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 369 csr | PCI_COMMAND_MASTER_ENABLE); 370 371 printf("%s: %s\n", device_xname(&sc->sc_dev), tp->tp_desc); 372 373 tl_reset(sc); 374 375 /* fill in the i2c tag */ 376 sc->sc_i2c.ic_cookie = sc; 377 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 378 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 379 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 380 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 381 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 382 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 383 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 384 385 #ifdef TLDEBUG 386 printf("default values of INTreg: 0x%x\n", 387 tl_intreg_read(sc, TL_INT_Defaults)); 388 #endif 389 390 /* read mac addr */ 391 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 512/*?*/, 392 sc->tl_enaddr, ETHER_ADDR_LEN)) { 393 aprint_error_dev(&sc->sc_dev, "error reading Ethernet address\n"); 394 return; 395 } 396 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 397 ether_sprintf(sc->tl_enaddr)); 398 399 /* Map and establish interrupts */ 400 if (pci_intr_map(pa, &intrhandle)) { 401 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 402 return; 403 } 404 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 405 sc->tl_if.if_softc = sc; 406 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 407 tl_intr, sc); 408 if (sc->tl_ih == NULL) { 409 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 410 if (intrstr != NULL) 411 printf(" at %s", intrstr); 412 printf("\n"); 413 return; 414 } 415 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 416 417 /* init these pointers, so that tl_shutdown won't try to read them */ 418 sc->Rx_list = NULL; 419 sc->Tx_list = NULL; 420 421 /* allocate DMA-safe memory for control structs */ 422 if (bus_dmamem_alloc(sc->tl_dmatag, 423 PAGE_SIZE, 0, PAGE_SIZE, 424 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 425 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 426 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 427 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 428 aprint_error_dev(&sc->sc_dev, "can't allocate DMA memory for lists\n"); 429 return; 430 } 431 /* 432 * Add shutdown hook so that DMA is disabled prior to reboot. Not 433 * doing 434 * reboot before the driver initializes. 435 */ 436 (void) shutdownhook_establish(tl_shutdown, ifp); 437 438 /* 439 * Initialize our media structures and probe the MII. 440 * 441 * Note that we don't care about the media instance. We 442 * are expecting to have multiple PHYs on the 10/100 cards, 443 * and on those cards we exclude the internal PHY from providing 444 * 10baseT. By ignoring the instance, it allows us to not have 445 * to specify it on the command line when switching media. 446 */ 447 sc->tl_mii.mii_ifp = ifp; 448 sc->tl_mii.mii_readreg = tl_mii_read; 449 sc->tl_mii.mii_writereg = tl_mii_write; 450 sc->tl_mii.mii_statchg = tl_statchg; 451 sc->tl_ec.ec_mii = &sc->tl_mii; 452 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 453 ether_mediastatus); 454 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 455 MII_OFFSET_ANY, 0); 456 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 457 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 458 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 459 } else 460 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 461 462 /* 463 * We can support 802.1Q VLAN-sized frames. 464 */ 465 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 466 467 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 468 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 469 ifp->if_ioctl = tl_ifioctl; 470 ifp->if_start = tl_ifstart; 471 ifp->if_watchdog = tl_ifwatchdog; 472 ifp->if_init = tl_init; 473 ifp->if_stop = tl_stop; 474 ifp->if_timer = 0; 475 IFQ_SET_READY(&ifp->if_snd); 476 if_attach(ifp); 477 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 478 479 #if NRND > 0 480 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 481 RND_TYPE_NET, 0); 482 #endif 483 } 484 485 static void 486 tl_reset(sc) 487 tl_softc_t *sc; 488 { 489 int i; 490 491 /* read stats */ 492 if (sc->tl_if.if_flags & IFF_RUNNING) { 493 callout_stop(&sc->tl_tick_ch); 494 tl_read_stats(sc); 495 } 496 /* Reset adapter */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, 498 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 499 DELAY(100000); 500 /* Disable interrupts */ 501 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 502 /* setup aregs & hash */ 503 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 504 tl_intreg_write(sc, i, 0); 505 #ifdef TLDEBUG_ADDR 506 printf("Areg & hash registers: \n"); 507 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 508 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 509 #endif 510 /* Setup NetConfig */ 511 tl_intreg_write(sc, TL_INT_NetConfig, 512 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 513 /* Bsize: accept default */ 514 /* TX commit in Acommit: accept default */ 515 /* Load Ld_tmr and Ld_thr */ 516 /* Ld_tmr = 3 */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 518 /* Ld_thr = 0 */ 519 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 520 /* Unreset MII */ 521 netsio_set(sc, TL_NETSIO_NMRST); 522 DELAY(100000); 523 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 524 } 525 526 static void tl_shutdown(v) 527 void *v; 528 { 529 tl_stop(v, 1); 530 } 531 532 static void tl_stop(struct ifnet *ifp, int disable) 533 { 534 tl_softc_t *sc = ifp->if_softc; 535 struct Tx_list *Tx; 536 int i; 537 538 if ((ifp->if_flags & IFF_RUNNING) == 0) 539 return; 540 /* disable interrupts */ 541 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 542 /* stop TX and RX channels */ 543 TL_HR_WRITE(sc, TL_HOST_CMD, 544 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 546 DELAY(100000); 547 548 /* stop statistics reading loop, read stats */ 549 callout_stop(&sc->tl_tick_ch); 550 tl_read_stats(sc); 551 552 /* Down the MII. */ 553 mii_down(&sc->tl_mii); 554 555 /* deallocate memory allocations */ 556 if (sc->Rx_list) { 557 for (i=0; i< TL_NBUF; i++) { 558 if (sc->Rx_list[i].m) { 559 bus_dmamap_unload(sc->tl_dmatag, 560 sc->Rx_list[i].m_dmamap); 561 m_freem(sc->Rx_list[i].m); 562 } 563 bus_dmamap_destroy(sc->tl_dmatag, 564 sc->Rx_list[i].m_dmamap); 565 sc->Rx_list[i].m = NULL; 566 } 567 free(sc->Rx_list, M_DEVBUF); 568 sc->Rx_list = NULL; 569 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 570 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 571 sc->hw_Rx_list = NULL; 572 while ((Tx = sc->active_Tx) != NULL) { 573 Tx->hw_list->stat = 0; 574 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 575 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 576 m_freem(Tx->m); 577 sc->active_Tx = Tx->next; 578 Tx->next = sc->Free_Tx; 579 sc->Free_Tx = Tx; 580 } 581 sc->last_Tx = NULL; 582 free(sc->Tx_list, M_DEVBUF); 583 sc->Tx_list = NULL; 584 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 585 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 586 sc->hw_Tx_list = NULL; 587 } 588 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 589 ifp->if_timer = 0; 590 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 591 } 592 593 static void tl_restart(v) 594 void *v; 595 { 596 tl_init(v); 597 } 598 599 static int tl_init(ifp) 600 struct ifnet *ifp; 601 { 602 tl_softc_t *sc = ifp->if_softc; 603 int i, s, error; 604 bus_size_t boundary; 605 prop_number_t prop_boundary; 606 const char *errstring; 607 char *nullbuf; 608 609 s = splnet(); 610 /* cancel any pending IO */ 611 tl_stop(ifp, 1); 612 tl_reset(sc); 613 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 614 splx(s); 615 return 0; 616 } 617 /* Set various register to reasonable value */ 618 /* setup NetCmd in promisc mode if needed */ 619 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 620 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 621 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 622 /* Max receive size : MCLBYTES */ 623 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 624 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 625 (MCLBYTES >> 8) & 0xff); 626 627 /* init MAC addr */ 628 for (i = 0; i < ETHER_ADDR_LEN; i++) 629 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 630 /* add multicast filters */ 631 tl_addr_filter(sc); 632 #ifdef TLDEBUG_ADDR 633 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 634 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 635 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 636 #endif 637 638 /* Pre-allocate receivers mbuf, make the lists */ 639 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 640 M_NOWAIT|M_ZERO); 641 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 642 M_NOWAIT|M_ZERO); 643 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 644 errstring = "out of memory for lists"; 645 error = ENOMEM; 646 goto bad; 647 } 648 649 /* 650 * Some boards (Set Engineering GFE) do not permit DMA transfers 651 * across page boundaries. 652 */ 653 prop_boundary = prop_dictionary_get(device_properties(&sc->sc_dev), 654 "tl-dma-page-boundary"); 655 if (prop_boundary != NULL) { 656 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 657 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 658 } else { 659 boundary = 0; 660 } 661 662 error = bus_dmamap_create(sc->tl_dmatag, 663 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 664 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 665 &sc->Rx_dmamap); 666 if (error == 0) 667 error = bus_dmamap_create(sc->tl_dmatag, 668 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 669 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 670 BUS_DMA_WAITOK, &sc->Tx_dmamap); 671 if (error == 0) 672 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 673 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 674 &sc->null_dmamap); 675 if (error) { 676 errstring = "can't allocate DMA maps for lists"; 677 goto bad; 678 } 679 memset(sc->ctrl, 0, PAGE_SIZE); 680 sc->hw_Rx_list = (void *)sc->ctrl; 681 sc->hw_Tx_list = 682 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 683 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 684 sizeof(struct tl_Tx_list) * TL_NBUF; 685 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 686 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 687 BUS_DMA_WAITOK); 688 if (error == 0) 689 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 690 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 691 BUS_DMA_WAITOK); 692 if (error == 0) 693 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 694 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 695 if (error) { 696 errstring = "can't DMA map DMA memory for lists"; 697 goto bad; 698 } 699 for (i=0; i< TL_NBUF; i++) { 700 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 701 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 702 &sc->Rx_list[i].m_dmamap); 703 if (error == 0) { 704 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 705 TL_NSEG, MCLBYTES, boundary, 706 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 707 &sc->Tx_list[i].m_dmamap); 708 } 709 if (error) { 710 errstring = "can't allocate DMA maps for mbufs"; 711 goto bad; 712 } 713 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 714 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 715 + sizeof(struct tl_Rx_list) * i; 716 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 717 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 718 + sizeof(struct tl_Tx_list) * i; 719 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 720 errstring = "out of mbuf for receive list"; 721 error = ENOMEM; 722 goto bad; 723 } 724 if (i > 0) { /* chain the list */ 725 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 726 sc->hw_Rx_list[i - 1].fwd = 727 htole32(sc->Rx_list[i].hw_listaddr); 728 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 729 } 730 } 731 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 732 sc->Rx_list[TL_NBUF - 1].next = NULL; 733 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 734 sc->Tx_list[TL_NBUF - 1].next = NULL; 735 736 sc->active_Rx = &sc->Rx_list[0]; 737 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 738 sc->active_Tx = sc->last_Tx = NULL; 739 sc->Free_Tx = &sc->Tx_list[0]; 740 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 741 sizeof(struct tl_Rx_list) * TL_NBUF, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 744 sizeof(struct tl_Tx_list) * TL_NBUF, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 747 BUS_DMASYNC_PREWRITE); 748 749 /* set media */ 750 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 751 error = 0; 752 else if (error != 0) { 753 errstring = "could not set media"; 754 goto bad; 755 } 756 757 /* start ticks calls */ 758 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 759 /* write address of Rx list and enable interrupts */ 760 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 761 TL_HR_WRITE(sc, TL_HOST_CMD, 762 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 763 sc->tl_if.if_flags |= IFF_RUNNING; 764 sc->tl_if.if_flags &= ~IFF_OACTIVE; 765 return 0; 766 bad: 767 printf("%s: %s\n", device_xname(&sc->sc_dev), errstring); 768 splx(s); 769 return error; 770 } 771 772 773 static u_int32_t 774 tl_intreg_read(sc, reg) 775 tl_softc_t *sc; 776 u_int32_t reg; 777 { 778 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 779 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 780 } 781 782 static u_int8_t 783 tl_intreg_read_byte(sc, reg) 784 tl_softc_t *sc; 785 u_int32_t reg; 786 { 787 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 788 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 789 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 790 } 791 792 static void 793 tl_intreg_write(sc, reg, val) 794 tl_softc_t *sc; 795 u_int32_t reg; 796 u_int32_t val; 797 { 798 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 799 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 800 } 801 802 static void 803 tl_intreg_write_byte(sc, reg, val) 804 tl_softc_t *sc; 805 u_int32_t reg; 806 u_int8_t val; 807 { 808 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 809 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 810 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 811 } 812 813 void 814 tl_mii_sync(sc) 815 struct tl_softc *sc; 816 { 817 int i; 818 819 netsio_clr(sc, TL_NETSIO_MTXEN); 820 for (i = 0; i < 32; i++) { 821 netsio_clr(sc, TL_NETSIO_MCLK); 822 netsio_set(sc, TL_NETSIO_MCLK); 823 } 824 } 825 826 void 827 tl_mii_sendbits(sc, data, nbits) 828 struct tl_softc *sc; 829 u_int32_t data; 830 int nbits; 831 { 832 int i; 833 834 netsio_set(sc, TL_NETSIO_MTXEN); 835 for (i = 1 << (nbits - 1); i; i = i >> 1) { 836 netsio_clr(sc, TL_NETSIO_MCLK); 837 netsio_read(sc, TL_NETSIO_MCLK); 838 if (data & i) 839 netsio_set(sc, TL_NETSIO_MDATA); 840 else 841 netsio_clr(sc, TL_NETSIO_MDATA); 842 netsio_set(sc, TL_NETSIO_MCLK); 843 netsio_read(sc, TL_NETSIO_MCLK); 844 } 845 } 846 847 int 848 tl_mii_read(self, phy, reg) 849 struct device *self; 850 int phy, reg; 851 { 852 struct tl_softc *sc = (struct tl_softc *)self; 853 int val = 0, i, err; 854 855 /* 856 * Read the PHY register by manually driving the MII control lines. 857 */ 858 859 tl_mii_sync(sc); 860 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 861 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 862 tl_mii_sendbits(sc, phy, 5); 863 tl_mii_sendbits(sc, reg, 5); 864 865 netsio_clr(sc, TL_NETSIO_MTXEN); 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 netsio_set(sc, TL_NETSIO_MCLK); 868 netsio_clr(sc, TL_NETSIO_MCLK); 869 870 err = netsio_read(sc, TL_NETSIO_MDATA); 871 netsio_set(sc, TL_NETSIO_MCLK); 872 873 /* Even if an error occurs, must still clock out the cycle. */ 874 for (i = 0; i < 16; i++) { 875 val <<= 1; 876 netsio_clr(sc, TL_NETSIO_MCLK); 877 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 878 val |= 1; 879 netsio_set(sc, TL_NETSIO_MCLK); 880 } 881 netsio_clr(sc, TL_NETSIO_MCLK); 882 netsio_set(sc, TL_NETSIO_MCLK); 883 884 return (err ? 0 : val); 885 } 886 887 void 888 tl_mii_write(self, phy, reg, val) 889 struct device *self; 890 int phy, reg, val; 891 { 892 struct tl_softc *sc = (struct tl_softc *)self; 893 894 /* 895 * Write the PHY register by manually driving the MII control lines. 896 */ 897 898 tl_mii_sync(sc); 899 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 900 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 901 tl_mii_sendbits(sc, phy, 5); 902 tl_mii_sendbits(sc, reg, 5); 903 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 904 tl_mii_sendbits(sc, val, 16); 905 906 netsio_clr(sc, TL_NETSIO_MCLK); 907 netsio_set(sc, TL_NETSIO_MCLK); 908 } 909 910 void 911 tl_statchg(self) 912 struct device *self; 913 { 914 tl_softc_t *sc = (struct tl_softc *)self; 915 u_int32_t reg; 916 917 #ifdef TLDEBUG 918 printf("tl_statchg, media %x\n", sc->tl_mii.mii_media.ifm_media); 919 #endif 920 921 /* 922 * We must keep the ThunderLAN and the PHY in sync as 923 * to the status of full-duplex! 924 */ 925 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 926 if (sc->tl_mii.mii_media_active & IFM_FDX) 927 reg |= TL_NETCOMMAND_DUPLEX; 928 else 929 reg &= ~TL_NETCOMMAND_DUPLEX; 930 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 931 } 932 933 /********** I2C glue **********/ 934 935 static int 936 tl_i2c_acquire_bus(void *cookie, int flags) 937 { 938 939 /* private bus */ 940 return (0); 941 } 942 943 static void 944 tl_i2c_release_bus(void *cookie, int flags) 945 { 946 947 /* private bus */ 948 } 949 950 static int 951 tl_i2c_send_start(void *cookie, int flags) 952 { 953 954 return (i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops)); 955 } 956 957 static int 958 tl_i2c_send_stop(void *cookie, int flags) 959 { 960 961 return (i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops)); 962 } 963 964 static int 965 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 966 { 967 968 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops)); 969 } 970 971 static int 972 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 973 { 974 975 return (i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops)); 976 } 977 978 static int 979 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 980 { 981 982 return (i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops)); 983 } 984 985 /********** I2C bit-bang glue **********/ 986 987 static void 988 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 989 { 990 struct tl_softc *sc = cookie; 991 uint8_t reg; 992 993 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 994 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 995 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 996 } 997 998 static void 999 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 1000 { 1001 struct tl_softc *sc = cookie; 1002 uint8_t reg; 1003 1004 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 1005 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 1006 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 1007 } 1008 1009 static uint32_t 1010 tl_i2cbb_read(void *cookie) 1011 { 1012 1013 return (tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio)); 1014 } 1015 1016 /********** End of I2C stuff **********/ 1017 1018 static int 1019 tl_intr(v) 1020 void *v; 1021 { 1022 tl_softc_t *sc = v; 1023 struct ifnet *ifp = &sc->tl_if; 1024 struct Rx_list *Rx; 1025 struct Tx_list *Tx; 1026 struct mbuf *m; 1027 u_int32_t int_type, int_reg; 1028 int ack = 0; 1029 int size; 1030 1031 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1032 int_type = int_reg & TL_INTR_MASK; 1033 if (int_type == 0) 1034 return 0; 1035 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1036 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(&sc->sc_dev), 1037 int_type, int_reg); 1038 #endif 1039 /* disable interrupts */ 1040 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1041 switch(int_type & TL_INTR_MASK) { 1042 case TL_INTR_RxEOF: 1043 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1044 sizeof(struct tl_Rx_list) * TL_NBUF, 1045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1046 while(le32toh(sc->active_Rx->hw_list->stat) & 1047 TL_RX_CSTAT_CPLT) { 1048 /* dequeue and requeue at end of list */ 1049 ack++; 1050 Rx = sc->active_Rx; 1051 sc->active_Rx = Rx->next; 1052 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1053 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1054 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1055 m = Rx->m; 1056 size = le32toh(Rx->hw_list->stat) >> 16; 1057 #ifdef TLDEBUG_RX 1058 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 1059 Rx, size); 1060 #endif 1061 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1062 /* 1063 * No new mbuf, reuse the same. This means 1064 * that this packet 1065 * is lost 1066 */ 1067 m = NULL; 1068 #ifdef TL_PRIV_STATS 1069 sc->ierr_nomem++; 1070 #endif 1071 #ifdef TLDEBUG 1072 printf("%s: out of mbuf, lost input packet\n", 1073 device_xname(&sc->sc_dev)); 1074 #endif 1075 } 1076 Rx->next = NULL; 1077 Rx->hw_list->fwd = 0; 1078 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1079 sc->last_Rx->next = Rx; 1080 sc->last_Rx = Rx; 1081 1082 /* deliver packet */ 1083 if (m) { 1084 if (size < sizeof(struct ether_header)) { 1085 m_freem(m); 1086 continue; 1087 } 1088 m->m_pkthdr.rcvif = ifp; 1089 m->m_pkthdr.len = m->m_len = size; 1090 #ifdef TLDEBUG_RX 1091 { struct ether_header *eh = 1092 mtod(m, struct ether_header *); 1093 printf("tl_intr: Rx packet:\n"); 1094 ether_printheader(eh); } 1095 #endif 1096 #if NBPFILTER > 0 1097 if (ifp->if_bpf) 1098 bpf_mtap(ifp->if_bpf, m); 1099 #endif /* NBPFILTER > 0 */ 1100 (*ifp->if_input)(ifp, m); 1101 } 1102 } 1103 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1104 sizeof(struct tl_Rx_list) * TL_NBUF, 1105 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1106 #ifdef TLDEBUG_RX 1107 printf("TL_INTR_RxEOF: ack %d\n", ack); 1108 #else 1109 if (ack == 0) { 1110 printf("%s: EOF intr without anything to read !\n", 1111 device_xname(&sc->sc_dev)); 1112 tl_reset(sc); 1113 /* schedule reinit of the board */ 1114 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1115 return(1); 1116 } 1117 #endif 1118 break; 1119 case TL_INTR_RxEOC: 1120 ack++; 1121 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1122 sizeof(struct tl_Rx_list) * TL_NBUF, 1123 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1124 #ifdef TLDEBUG_RX 1125 printf("TL_INTR_RxEOC: ack %d\n", ack); 1126 #endif 1127 #ifdef DIAGNOSTIC 1128 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1129 printf("%s: Rx EOC interrupt and active Tx list not " 1130 "cleared\n", device_xname(&sc->sc_dev)); 1131 return 0; 1132 } else 1133 #endif 1134 { 1135 /* 1136 * write address of Rx list and send Rx GO command, ack 1137 * interrupt and enable interrupts in one command 1138 */ 1139 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1140 TL_HR_WRITE(sc, TL_HOST_CMD, 1141 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1142 HOST_CMD_ACK | HOST_CMD_IntOn); 1143 return 1; 1144 } 1145 case TL_INTR_TxEOF: 1146 case TL_INTR_TxEOC: 1147 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1148 sizeof(struct tl_Tx_list) * TL_NBUF, 1149 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1150 while ((Tx = sc->active_Tx) != NULL) { 1151 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1152 break; 1153 ack++; 1154 #ifdef TLDEBUG_TX 1155 printf("TL_INTR_TxEOC: list 0x%x done\n", 1156 (int)Tx->hw_listaddr); 1157 #endif 1158 Tx->hw_list->stat = 0; 1159 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1160 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1161 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1162 m_freem(Tx->m); 1163 Tx->m = NULL; 1164 sc->active_Tx = Tx->next; 1165 if (sc->active_Tx == NULL) 1166 sc->last_Tx = NULL; 1167 Tx->next = sc->Free_Tx; 1168 sc->Free_Tx = Tx; 1169 } 1170 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1171 sizeof(struct tl_Tx_list) * TL_NBUF, 1172 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1173 /* if this was an EOC, ACK immediatly */ 1174 if (ack) 1175 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1176 if (int_type == TL_INTR_TxEOC) { 1177 #ifdef TLDEBUG_TX 1178 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1179 ack); 1180 #endif 1181 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1182 HOST_CMD_ACK | HOST_CMD_IntOn); 1183 if ( sc->active_Tx != NULL) { 1184 /* needs a Tx go command */ 1185 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1186 sc->active_Tx->hw_listaddr); 1187 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1188 } 1189 sc->tl_if.if_timer = 0; 1190 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1191 tl_ifstart(&sc->tl_if); 1192 return 1; 1193 } 1194 #ifdef TLDEBUG 1195 else { 1196 printf("TL_INTR_TxEOF: ack %d\n", ack); 1197 } 1198 #endif 1199 sc->tl_if.if_timer = 0; 1200 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1201 tl_ifstart(&sc->tl_if); 1202 break; 1203 case TL_INTR_Stat: 1204 ack++; 1205 #ifdef TLDEBUG 1206 printf("TL_INTR_Stat: ack %d\n", ack); 1207 #endif 1208 tl_read_stats(sc); 1209 break; 1210 case TL_INTR_Adc: 1211 if (int_reg & TL_INTVec_MASK) { 1212 /* adapter check conditions */ 1213 printf("%s: check condition, intvect=0x%x, " 1214 "ch_param=0x%x\n", device_xname(&sc->sc_dev), 1215 int_reg & TL_INTVec_MASK, 1216 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1217 tl_reset(sc); 1218 /* schedule reinit of the board */ 1219 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1220 return(1); 1221 } else { 1222 u_int8_t netstat; 1223 /* Network status */ 1224 netstat = 1225 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1226 printf("%s: network status, NetSts=%x\n", 1227 device_xname(&sc->sc_dev), netstat); 1228 /* Ack interrupts */ 1229 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1230 netstat); 1231 ack++; 1232 } 1233 break; 1234 default: 1235 printf("%s: unhandled interrupt code %x!\n", 1236 device_xname(&sc->sc_dev), int_type); 1237 ack++; 1238 } 1239 1240 if (ack) { 1241 /* Ack the interrupt and enable interrupts */ 1242 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1243 HOST_CMD_IntOn); 1244 #if NRND > 0 1245 if (RND_ENABLED(&sc->rnd_source)) 1246 rnd_add_uint32(&sc->rnd_source, int_reg); 1247 #endif 1248 return 1; 1249 } 1250 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1251 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1252 return 0; 1253 } 1254 1255 static int 1256 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1257 { 1258 struct tl_softc *sc = ifp->if_softc; 1259 int s, error; 1260 1261 s = splnet(); 1262 error = ether_ioctl(ifp, cmd, data); 1263 if (error == ENETRESET) { 1264 if (ifp->if_flags & IFF_RUNNING) 1265 tl_addr_filter(sc); 1266 error = 0; 1267 } 1268 splx(s); 1269 return error; 1270 } 1271 1272 static void 1273 tl_ifstart(ifp) 1274 struct ifnet *ifp; 1275 { 1276 tl_softc_t *sc = ifp->if_softc; 1277 struct mbuf *mb_head; 1278 struct Tx_list *Tx; 1279 int segment, size; 1280 int again, error; 1281 1282 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1283 return; 1284 txloop: 1285 /* If we don't have more space ... */ 1286 if (sc->Free_Tx == NULL) { 1287 #ifdef TLDEBUG 1288 printf("tl_ifstart: No free TX list\n"); 1289 #endif 1290 sc->tl_if.if_flags |= IFF_OACTIVE; 1291 return; 1292 } 1293 /* Grab a paquet for output */ 1294 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1295 if (mb_head == NULL) { 1296 #ifdef TLDEBUG_TX 1297 printf("tl_ifstart: nothing to send\n"); 1298 #endif 1299 return; 1300 } 1301 Tx = sc->Free_Tx; 1302 sc->Free_Tx = Tx->next; 1303 Tx->next = NULL; 1304 again = 0; 1305 /* 1306 * Go through each of the mbufs in the chain and initialize 1307 * the transmit list descriptors with the physical address 1308 * and size of the mbuf. 1309 */ 1310 tbdinit: 1311 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1312 Tx->m = mb_head; 1313 size = mb_head->m_pkthdr.len; 1314 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1315 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1316 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1317 struct mbuf *mn; 1318 /* 1319 * We ran out of segments, or we will. We have to recopy this 1320 * mbuf chain first. 1321 */ 1322 if (error == 0) 1323 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1324 if (again) { 1325 /* already copyed, can't do much more */ 1326 m_freem(mb_head); 1327 goto bad; 1328 } 1329 again = 1; 1330 #ifdef TLDEBUG_TX 1331 printf("tl_ifstart: need to copy mbuf\n"); 1332 #endif 1333 #ifdef TL_PRIV_STATS 1334 sc->oerr_mcopy++; 1335 #endif 1336 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1337 if (mn == NULL) { 1338 m_freem(mb_head); 1339 goto bad; 1340 } 1341 if (mb_head->m_pkthdr.len > MHLEN) { 1342 MCLGET(mn, M_DONTWAIT); 1343 if ((mn->m_flags & M_EXT) == 0) { 1344 m_freem(mn); 1345 m_freem(mb_head); 1346 goto bad; 1347 } 1348 } 1349 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1350 mtod(mn, void *)); 1351 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1352 m_freem(mb_head); 1353 mb_head = mn; 1354 goto tbdinit; 1355 } 1356 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1357 Tx->hw_list->seg[segment].data_addr = 1358 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1359 Tx->hw_list->seg[segment].data_count = 1360 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1361 } 1362 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1363 Tx->m_dmamap->dm_mapsize, 1364 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1365 /* We are at end of mbuf chain. check the size and 1366 * see if it needs to be extended 1367 */ 1368 if (size < ETHER_MIN_TX) { 1369 #ifdef DIAGNOSTIC 1370 if (segment >= TL_NSEG) { 1371 panic("tl_ifstart: to much segmets (%d)", segment); 1372 } 1373 #endif 1374 /* 1375 * add the nullbuf in the seg 1376 */ 1377 Tx->hw_list->seg[segment].data_count = 1378 htole32(ETHER_MIN_TX - size); 1379 Tx->hw_list->seg[segment].data_addr = 1380 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1381 size = ETHER_MIN_TX; 1382 segment++; 1383 } 1384 /* The list is done, finish the list init */ 1385 Tx->hw_list->seg[segment - 1].data_count |= 1386 htole32(TL_LAST_SEG); 1387 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1388 #ifdef TLDEBUG_TX 1389 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(&sc->sc_dev), 1390 le32toh(Tx->hw_list->stat)); 1391 #if 0 1392 for(segment = 0; segment < TL_NSEG; segment++) { 1393 printf(" seg %d addr 0x%x len 0x%x\n", 1394 segment, 1395 le32toh(Tx->hw_list->seg[segment].data_addr), 1396 le32toh(Tx->hw_list->seg[segment].data_count)); 1397 } 1398 #endif 1399 #endif 1400 if (sc->active_Tx == NULL) { 1401 sc->active_Tx = sc->last_Tx = Tx; 1402 #ifdef TLDEBUG_TX 1403 printf("%s: Tx GO, addr=0x%ux\n", device_xname(&sc->sc_dev), 1404 (int)Tx->hw_listaddr); 1405 #endif 1406 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1407 sizeof(struct tl_Tx_list) * TL_NBUF, 1408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1409 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1410 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1411 } else { 1412 #ifdef TLDEBUG_TX 1413 printf("%s: Tx addr=0x%ux queued\n", device_xname(&sc->sc_dev), 1414 (int)Tx->hw_listaddr); 1415 #endif 1416 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1417 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1418 sizeof(struct tl_Tx_list) * TL_NBUF, 1419 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1420 sc->last_Tx->next = Tx; 1421 sc->last_Tx = Tx; 1422 #ifdef DIAGNOSTIC 1423 if (sc->last_Tx->hw_list->fwd & 0x7) 1424 printf("%s: physical addr 0x%x of list not properly " 1425 "aligned\n", 1426 device_xname(&sc->sc_dev), sc->last_Rx->hw_list->fwd); 1427 #endif 1428 } 1429 #if NBPFILTER > 0 1430 /* Pass packet to bpf if there is a listener */ 1431 if (ifp->if_bpf) 1432 bpf_mtap(ifp->if_bpf, mb_head); 1433 #endif 1434 /* 1435 * Set a 5 second timer just in case we don't hear from the card again. 1436 */ 1437 ifp->if_timer = 5; 1438 goto txloop; 1439 bad: 1440 #ifdef TLDEBUG 1441 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1442 #endif 1443 Tx->next = sc->Free_Tx; 1444 sc->Free_Tx = Tx; 1445 return; 1446 } 1447 1448 static void 1449 tl_ifwatchdog(ifp) 1450 struct ifnet *ifp; 1451 { 1452 tl_softc_t *sc = ifp->if_softc; 1453 1454 if ((ifp->if_flags & IFF_RUNNING) == 0) 1455 return; 1456 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1457 ifp->if_oerrors++; 1458 tl_init(ifp); 1459 } 1460 1461 static int 1462 tl_mediachange(ifp) 1463 struct ifnet *ifp; 1464 { 1465 1466 if (ifp->if_flags & IFF_UP) 1467 tl_init(ifp); 1468 return (0); 1469 } 1470 1471 static int tl_add_RxBuff(sc, Rx, oldm) 1472 tl_softc_t *sc; 1473 struct Rx_list *Rx; 1474 struct mbuf *oldm; 1475 { 1476 struct mbuf *m; 1477 int error; 1478 1479 MGETHDR(m, M_DONTWAIT, MT_DATA); 1480 if (m != NULL) { 1481 MCLGET(m, M_DONTWAIT); 1482 if ((m->m_flags & M_EXT) == 0) { 1483 m_freem(m); 1484 if (oldm == NULL) 1485 return 0; 1486 m = oldm; 1487 m->m_data = m->m_ext.ext_buf; 1488 } 1489 } else { 1490 if (oldm == NULL) 1491 return 0; 1492 m = oldm; 1493 m->m_data = m->m_ext.ext_buf; 1494 } 1495 1496 /* (re)init the Rx_list struct */ 1497 1498 Rx->m = m; 1499 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1500 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1501 aprint_error_dev(&sc->sc_dev, "bus_dmamap_load() failed (error %d) for " 1502 "tl_add_RxBuff\n", error); 1503 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1504 m_freem(m); 1505 Rx->m = NULL; 1506 return 0; 1507 } 1508 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1509 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1510 /* 1511 * Move the data pointer up so that the incoming data packet 1512 * will be 32-bit aligned. 1513 */ 1514 m->m_data += 2; 1515 1516 Rx->hw_list->stat = 1517 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1518 Rx->hw_list->seg.data_count = 1519 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1520 Rx->hw_list->seg.data_addr = 1521 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1522 return (m != oldm); 1523 } 1524 1525 static void tl_ticks(v) 1526 void *v; 1527 { 1528 tl_softc_t *sc = v; 1529 1530 tl_read_stats(sc); 1531 1532 /* Tick the MII. */ 1533 mii_tick(&sc->tl_mii); 1534 1535 /* read statistics every seconds */ 1536 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1537 } 1538 1539 static void 1540 tl_read_stats(sc) 1541 tl_softc_t *sc; 1542 { 1543 u_int32_t reg; 1544 int ierr_overr; 1545 int ierr_code; 1546 int ierr_crc; 1547 int oerr_underr; 1548 int oerr_deferred; 1549 int oerr_coll; 1550 int oerr_multicoll; 1551 int oerr_exesscoll; 1552 int oerr_latecoll; 1553 int oerr_carrloss; 1554 struct ifnet *ifp = &sc->tl_if; 1555 1556 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1557 ifp->if_opackets += reg & 0x00ffffff; 1558 oerr_underr = reg >> 24; 1559 1560 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1561 ifp->if_ipackets += reg & 0x00ffffff; 1562 ierr_overr = reg >> 24; 1563 1564 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1565 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1566 ierr_code = (reg & TL_FERR_CODE) >> 24; 1567 oerr_deferred = (reg & TL_FERR_DEF); 1568 1569 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1570 oerr_multicoll = (reg & TL_COL_MULTI); 1571 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1572 1573 reg = tl_intreg_read(sc, TL_INT_LERR); 1574 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1575 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1576 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1577 1578 1579 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1580 oerr_carrloss; 1581 ifp->if_collisions += oerr_coll + oerr_multicoll; 1582 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1583 1584 if (ierr_overr) 1585 printf("%s: receiver ring buffer overrun\n", 1586 device_xname(&sc->sc_dev)); 1587 if (oerr_underr) 1588 printf("%s: transmit buffer underrun\n", 1589 device_xname(&sc->sc_dev)); 1590 #ifdef TL_PRIV_STATS 1591 sc->ierr_overr += ierr_overr; 1592 sc->ierr_code += ierr_code; 1593 sc->ierr_crc += ierr_crc; 1594 sc->oerr_underr += oerr_underr; 1595 sc->oerr_deferred += oerr_deferred; 1596 sc->oerr_coll += oerr_coll; 1597 sc->oerr_multicoll += oerr_multicoll; 1598 sc->oerr_exesscoll += oerr_exesscoll; 1599 sc->oerr_latecoll += oerr_latecoll; 1600 sc->oerr_carrloss += oerr_carrloss; 1601 #endif 1602 } 1603 1604 static void tl_addr_filter(sc) 1605 tl_softc_t *sc; 1606 { 1607 struct ether_multistep step; 1608 struct ether_multi *enm; 1609 u_int32_t hash[2] = {0, 0}; 1610 int i; 1611 1612 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1613 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1614 while (enm != NULL) { 1615 #ifdef TLDEBUG 1616 printf("tl_addr_filter: addrs %s %s\n", 1617 ether_sprintf(enm->enm_addrlo), 1618 ether_sprintf(enm->enm_addrhi)); 1619 #endif 1620 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1621 i = tl_multicast_hash(enm->enm_addrlo); 1622 hash[i/32] |= 1 << (i%32); 1623 } else { 1624 hash[0] = hash[1] = 0xffffffff; 1625 sc->tl_if.if_flags |= IFF_ALLMULTI; 1626 break; 1627 } 1628 ETHER_NEXT_MULTI(step, enm); 1629 } 1630 #ifdef TLDEBUG 1631 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1632 #endif 1633 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1634 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1635 } 1636 1637 static int tl_multicast_hash(a) 1638 u_int8_t *a; 1639 { 1640 int hash; 1641 1642 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1643 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1644 1645 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1646 DA(a,36), DA(a,42)); 1647 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1648 DA(a,37), DA(a,43)) << 1; 1649 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1650 DA(a,38), DA(a,44)) << 2; 1651 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1652 DA(a,39), DA(a,45)) << 3; 1653 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1654 DA(a,40), DA(a,46)) << 4; 1655 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1656 DA(a,41), DA(a,47)) << 5; 1657 1658 return hash; 1659 } 1660 1661 #if defined(TLDEBUG_RX) 1662 void 1663 ether_printheader(eh) 1664 struct ether_header *eh; 1665 { 1666 u_char *c = (char*)eh; 1667 int i; 1668 for (i=0; i<sizeof(struct ether_header); i++) 1669 printf("%x ", (u_int)c[i]); 1670 printf("\n"); 1671 } 1672 #endif 1673
Indexes created Tue Sep 23 14:10:03 GMT 2025