if_tl.c revision 1.89.4.1
1 /* $NetBSD: if_tl.c,v 1.89.4.1 2008/10/19 22:16:39 haad Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.89.4.1 2008/10/19 22:16:39 haad Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #include "rnd.h" 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #ifdef INET 82 #include <netinet/in.h> 83 #include <netinet/in_systm.h> 84 #include <netinet/in_var.h> 85 #include <netinet/ip.h> 86 #endif 87 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <sys/bus.h> 97 #include <sys/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2cvar.h> 104 #include <dev/i2c/i2c_bitbang.h> 105 #include <dev/i2c/at24cxxvar.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 110 #include <dev/mii/tlphyvar.h> 111 112 #include <dev/pci/if_tlregs.h> 113 #include <dev/pci/if_tlvar.h> 114 #endif /* __NetBSD__ */ 115 116 /* number of transmit/receive buffers */ 117 #ifndef TL_NBUF 118 #define TL_NBUF 32 119 #endif 120 121 static int tl_pci_match(device_t, cfdata_t, void *); 122 static void tl_pci_attach(device_t, device_t, void *); 123 static int tl_intr(void *); 124 125 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 126 static int tl_mediachange(struct ifnet *); 127 static void tl_ifwatchdog(struct ifnet *); 128 static void tl_shutdown(void *); 129 130 static void tl_ifstart(struct ifnet *); 131 static void tl_reset(tl_softc_t *); 132 static int tl_init(struct ifnet *); 133 static void tl_stop(struct ifnet *, int); 134 static void tl_restart(void *); 135 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 136 static void tl_read_stats(tl_softc_t *); 137 static void tl_ticks(void *); 138 static int tl_multicast_hash(uint8_t *); 139 static void tl_addr_filter(tl_softc_t *); 140 141 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 142 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 143 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 144 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 145 146 void tl_mii_sync(struct tl_softc *); 147 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader(struct ether_header *); 152 #endif 153 154 int tl_mii_read(device_t, int, int); 155 void tl_mii_write(device_t, int, int, int); 156 157 void tl_statchg(device_t); 158 159 /* I2C glue */ 160 static int tl_i2c_acquire_bus(void *, int); 161 static void tl_i2c_release_bus(void *, int); 162 static int tl_i2c_send_start(void *, int); 163 static int tl_i2c_send_stop(void *, int); 164 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 165 static int tl_i2c_read_byte(void *, uint8_t *, int); 166 static int tl_i2c_write_byte(void *, uint8_t, int); 167 168 /* I2C bit-bang glue */ 169 static void tl_i2cbb_set_bits(void *, uint32_t); 170 static void tl_i2cbb_set_dir(void *, uint32_t); 171 static uint32_t tl_i2cbb_read(void *); 172 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 173 tl_i2cbb_set_bits, 174 tl_i2cbb_set_dir, 175 tl_i2cbb_read, 176 { 177 TL_NETSIO_EDATA, /* SDA */ 178 TL_NETSIO_ECLOCK, /* SCL */ 179 TL_NETSIO_ETXEN, /* SDA is output */ 180 0, /* SDA is input */ 181 } 182 }; 183 184 static inline void netsio_clr(tl_softc_t *, uint8_t); 185 static inline void netsio_set(tl_softc_t *, uint8_t); 186 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 187 188 static inline void 189 netsio_clr(tl_softc_t *sc, uint8_t bits) 190 { 191 192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 194 } 195 196 static inline void 197 netsio_set(tl_softc_t *sc, uint8_t bits) 198 { 199 200 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 201 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 202 } 203 204 static inline uint8_t 205 netsio_read(tl_softc_t *sc, uint8_t bits) 206 { 207 208 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 209 } 210 211 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 212 tl_pci_match, tl_pci_attach, NULL, NULL); 213 214 static const struct tl_product_desc tl_compaq_products[] = { 215 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 216 "Compaq Netelligent 10/100 TX" }, 217 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 218 "Integrated Compaq Netelligent 10/100 TX" }, 219 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 220 "Compaq Netelligent 10 T" }, 221 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 222 "Compaq Netelligent 10 T/2 UTP/Coax" }, 223 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 224 "Compaq Integrated NetFlex 3/P" }, 225 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 226 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 227 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 228 "Compaq Dual Port Netelligent 10/100 TX" }, 229 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 230 "Compaq Deskpro 4000 5233MMX" }, 231 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 232 "Compaq NetFlex 3/P w/ BNC" }, 233 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 234 "Compaq NetFlex 3/P" }, 235 { 0, 0, NULL }, 236 }; 237 238 static const struct tl_product_desc tl_ti_products[] = { 239 /* 240 * Built-in Ethernet on the TI TravelMate 5000 241 * docking station; better product description? 242 */ 243 { PCI_PRODUCT_TI_TLAN, 0, 244 "Texas Instruments ThunderLAN" }, 245 { 0, 0, NULL }, 246 }; 247 248 struct tl_vendor_desc { 249 uint32_t tv_vendor; 250 const struct tl_product_desc *tv_products; 251 }; 252 253 const struct tl_vendor_desc tl_vendors[] = { 254 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 255 { PCI_VENDOR_TI, tl_ti_products }, 256 { 0, NULL }, 257 }; 258 259 static const struct tl_product_desc *tl_lookup_product(uint32_t); 260 261 static const struct tl_product_desc * 262 tl_lookup_product(uint32_t id) 263 { 264 const struct tl_product_desc *tp; 265 const struct tl_vendor_desc *tv; 266 267 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 268 if (PCI_VENDOR(id) == tv->tv_vendor) 269 break; 270 271 if ((tp = tv->tv_products) == NULL) 272 return NULL; 273 274 for (; tp->tp_desc != NULL; tp++) 275 if (PCI_PRODUCT(id) == tp->tp_product) 276 break; 277 278 if (tp->tp_desc == NULL) 279 return NULL; 280 281 return tp; 282 } 283 284 static int 285 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 286 { 287 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 288 289 if (tl_lookup_product(pa->pa_id) != NULL) 290 return 1; 291 292 return 0; 293 } 294 295 static void 296 tl_pci_attach(device_t parent, device_t self, void *aux) 297 { 298 tl_softc_t *sc = device_private(self); 299 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 300 const struct tl_product_desc *tp; 301 struct ifnet * const ifp = &sc->tl_if; 302 bus_space_tag_t iot, memt; 303 bus_space_handle_t ioh, memh; 304 pci_intr_handle_t intrhandle; 305 const char *intrstr; 306 int ioh_valid, memh_valid; 307 int reg_io, reg_mem; 308 pcireg_t reg10, reg14; 309 pcireg_t csr; 310 311 sc->sc_dev = self; 312 aprint_normal("\n"); 313 314 callout_init(&sc->tl_tick_ch, 0); 315 callout_init(&sc->tl_restart_ch, 0); 316 317 tp = tl_lookup_product(pa->pa_id); 318 if (tp == NULL) 319 panic("%s: impossible", __func__); 320 sc->tl_product = tp; 321 322 /* 323 * Map the card space. First we have to find the I/O and MEM 324 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 325 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 326 * The ThunderLAN manual is not consistent about this either (there 327 * are both cases in code examples). 328 */ 329 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 330 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 331 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 332 reg_io = 0x10; 333 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 334 reg_io = 0x14; 335 else 336 reg_io = 0; 337 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 338 reg_mem = 0x10; 339 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 340 reg_mem = 0x14; 341 else 342 reg_mem = 0; 343 344 if (reg_io != 0) 345 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 346 0, &iot, &ioh, NULL, NULL) == 0); 347 else 348 ioh_valid = 0; 349 if (reg_mem != 0) 350 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 351 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 352 0, &memt, &memh, NULL, NULL) == 0); 353 else 354 memh_valid = 0; 355 356 if (ioh_valid) { 357 sc->tl_bustag = iot; 358 sc->tl_bushandle = ioh; 359 } else if (memh_valid) { 360 sc->tl_bustag = memt; 361 sc->tl_bushandle = memh; 362 } else { 363 aprint_error_dev(self, "unable to map device registers\n"); 364 return; 365 } 366 sc->tl_dmatag = pa->pa_dmat; 367 368 /* Enable the device. */ 369 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 370 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 371 csr | PCI_COMMAND_MASTER_ENABLE); 372 373 aprint_normal_dev(self, "%s\n", tp->tp_desc); 374 375 tl_reset(sc); 376 377 /* fill in the i2c tag */ 378 sc->sc_i2c.ic_cookie = sc; 379 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 380 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 381 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 382 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 383 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 384 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 385 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 386 387 #ifdef TLDEBUG 388 aprint_debug_dev(sefl, "default values of INTreg: 0x%x\n", 389 tl_intreg_read(sc, TL_INT_Defaults)); 390 #endif 391 392 /* read mac addr */ 393 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 394 sc->tl_enaddr, ETHER_ADDR_LEN)) { 395 aprint_error_dev(self, "error reading Ethernet address\n"); 396 return; 397 } 398 aprint_normal_dev(self, "Ethernet address %s\n", 399 ether_sprintf(sc->tl_enaddr)); 400 401 /* Map and establish interrupts */ 402 if (pci_intr_map(pa, &intrhandle)) { 403 aprint_error_dev(self, "couldn't map interrupt\n"); 404 return; 405 } 406 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 407 sc->tl_if.if_softc = sc; 408 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 409 tl_intr, sc); 410 if (sc->tl_ih == NULL) { 411 aprint_error_dev(self, "couldn't establish interrupt"); 412 if (intrstr != NULL) 413 aprint_error(" at %s", intrstr); 414 aprint_error("\n"); 415 return; 416 } 417 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 418 419 /* init these pointers, so that tl_shutdown won't try to read them */ 420 sc->Rx_list = NULL; 421 sc->Tx_list = NULL; 422 423 /* allocate DMA-safe memory for control structs */ 424 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 425 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 426 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 427 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 428 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 429 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 430 return; 431 } 432 /* 433 * Add shutdown hook so that DMA is disabled prior to reboot. Not 434 * doing 435 * reboot before the driver initializes. 436 */ 437 (void)shutdownhook_establish(tl_shutdown, ifp); 438 439 /* 440 * Initialize our media structures and probe the MII. 441 * 442 * Note that we don't care about the media instance. We 443 * are expecting to have multiple PHYs on the 10/100 cards, 444 * and on those cards we exclude the internal PHY from providing 445 * 10baseT. By ignoring the instance, it allows us to not have 446 * to specify it on the command line when switching media. 447 */ 448 sc->tl_mii.mii_ifp = ifp; 449 sc->tl_mii.mii_readreg = tl_mii_read; 450 sc->tl_mii.mii_writereg = tl_mii_write; 451 sc->tl_mii.mii_statchg = tl_statchg; 452 sc->tl_ec.ec_mii = &sc->tl_mii; 453 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 454 ether_mediastatus); 455 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 456 MII_OFFSET_ANY, 0); 457 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 458 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 459 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 460 } else 461 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 462 463 /* 464 * We can support 802.1Q VLAN-sized frames. 465 */ 466 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 467 468 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 469 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 470 ifp->if_ioctl = tl_ifioctl; 471 ifp->if_start = tl_ifstart; 472 ifp->if_watchdog = tl_ifwatchdog; 473 ifp->if_init = tl_init; 474 ifp->if_stop = tl_stop; 475 ifp->if_timer = 0; 476 IFQ_SET_READY(&ifp->if_snd); 477 if_attach(ifp); 478 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 479 480 #if NRND > 0 481 rnd_attach_source(&sc->rnd_source, device_xname(self), 482 RND_TYPE_NET, 0); 483 #endif 484 } 485 486 static void 487 tl_reset(tl_softc_t *sc) 488 { 489 int i; 490 491 /* read stats */ 492 if (sc->tl_if.if_flags & IFF_RUNNING) { 493 callout_stop(&sc->tl_tick_ch); 494 tl_read_stats(sc); 495 } 496 /* Reset adapter */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, 498 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 499 DELAY(100000); 500 /* Disable interrupts */ 501 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 502 /* setup aregs & hash */ 503 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 504 tl_intreg_write(sc, i, 0); 505 #ifdef TLDEBUG_ADDR 506 printf("Areg & hash registers: \n"); 507 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 508 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 509 #endif 510 /* Setup NetConfig */ 511 tl_intreg_write(sc, TL_INT_NetConfig, 512 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 513 /* Bsize: accept default */ 514 /* TX commit in Acommit: accept default */ 515 /* Load Ld_tmr and Ld_thr */ 516 /* Ld_tmr = 3 */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 518 /* Ld_thr = 0 */ 519 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 520 /* Unreset MII */ 521 netsio_set(sc, TL_NETSIO_NMRST); 522 DELAY(100000); 523 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 524 } 525 526 static void 527 tl_shutdown(void *v) 528 { 529 530 tl_stop(v, 1); 531 } 532 533 static void 534 tl_stop(struct ifnet *ifp, int disable) 535 { 536 tl_softc_t *sc = ifp->if_softc; 537 struct Tx_list *Tx; 538 int i; 539 540 if ((ifp->if_flags & IFF_RUNNING) == 0) 541 return; 542 /* disable interrupts */ 543 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 544 /* stop TX and RX channels */ 545 TL_HR_WRITE(sc, TL_HOST_CMD, 546 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 547 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 548 DELAY(100000); 549 550 /* stop statistics reading loop, read stats */ 551 callout_stop(&sc->tl_tick_ch); 552 tl_read_stats(sc); 553 554 /* Down the MII. */ 555 mii_down(&sc->tl_mii); 556 557 /* deallocate memory allocations */ 558 if (sc->Rx_list) { 559 for (i = 0; i< TL_NBUF; i++) { 560 if (sc->Rx_list[i].m) { 561 bus_dmamap_unload(sc->tl_dmatag, 562 sc->Rx_list[i].m_dmamap); 563 m_freem(sc->Rx_list[i].m); 564 } 565 bus_dmamap_destroy(sc->tl_dmatag, 566 sc->Rx_list[i].m_dmamap); 567 sc->Rx_list[i].m = NULL; 568 } 569 free(sc->Rx_list, M_DEVBUF); 570 sc->Rx_list = NULL; 571 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 572 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 573 sc->hw_Rx_list = NULL; 574 while ((Tx = sc->active_Tx) != NULL) { 575 Tx->hw_list->stat = 0; 576 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 577 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 578 m_freem(Tx->m); 579 sc->active_Tx = Tx->next; 580 Tx->next = sc->Free_Tx; 581 sc->Free_Tx = Tx; 582 } 583 sc->last_Tx = NULL; 584 free(sc->Tx_list, M_DEVBUF); 585 sc->Tx_list = NULL; 586 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 587 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 588 sc->hw_Tx_list = NULL; 589 } 590 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 591 ifp->if_timer = 0; 592 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 593 } 594 595 static void 596 tl_restart(void *v) 597 { 598 599 tl_init(v); 600 } 601 602 static int 603 tl_init(struct ifnet *ifp) 604 { 605 tl_softc_t *sc = ifp->if_softc; 606 int i, s, error; 607 bus_size_t boundary; 608 prop_number_t prop_boundary; 609 const char *errstring; 610 char *nullbuf; 611 612 s = splnet(); 613 /* cancel any pending IO */ 614 tl_stop(ifp, 1); 615 tl_reset(sc); 616 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 617 splx(s); 618 return 0; 619 } 620 /* Set various register to reasonable value */ 621 /* setup NetCmd in promisc mode if needed */ 622 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 623 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 624 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 625 /* Max receive size : MCLBYTES */ 626 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 627 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 628 (MCLBYTES >> 8) & 0xff); 629 630 /* init MAC addr */ 631 for (i = 0; i < ETHER_ADDR_LEN; i++) 632 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 633 /* add multicast filters */ 634 tl_addr_filter(sc); 635 #ifdef TLDEBUG_ADDR 636 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 637 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 638 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 639 #endif 640 641 /* Pre-allocate receivers mbuf, make the lists */ 642 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 643 M_NOWAIT|M_ZERO); 644 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 645 M_NOWAIT|M_ZERO); 646 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 647 errstring = "out of memory for lists"; 648 error = ENOMEM; 649 goto bad; 650 } 651 652 /* 653 * Some boards (Set Engineering GFE) do not permit DMA transfers 654 * across page boundaries. 655 */ 656 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 657 "tl-dma-page-boundary"); 658 if (prop_boundary != NULL) { 659 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 660 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 661 } else { 662 boundary = 0; 663 } 664 665 error = bus_dmamap_create(sc->tl_dmatag, 666 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 667 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 668 &sc->Rx_dmamap); 669 if (error == 0) 670 error = bus_dmamap_create(sc->tl_dmatag, 671 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 672 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 673 BUS_DMA_WAITOK, &sc->Tx_dmamap); 674 if (error == 0) 675 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 676 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 677 &sc->null_dmamap); 678 if (error) { 679 errstring = "can't allocate DMA maps for lists"; 680 goto bad; 681 } 682 memset(sc->ctrl, 0, PAGE_SIZE); 683 sc->hw_Rx_list = (void *)sc->ctrl; 684 sc->hw_Tx_list = 685 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 686 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 687 sizeof(struct tl_Tx_list) * TL_NBUF; 688 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 689 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 690 BUS_DMA_WAITOK); 691 if (error == 0) 692 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 693 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 694 BUS_DMA_WAITOK); 695 if (error == 0) 696 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 697 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 698 if (error) { 699 errstring = "can't DMA map DMA memory for lists"; 700 goto bad; 701 } 702 for (i = 0; i < TL_NBUF; i++) { 703 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 704 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 705 &sc->Rx_list[i].m_dmamap); 706 if (error == 0) { 707 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 708 TL_NSEG, MCLBYTES, boundary, 709 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 710 &sc->Tx_list[i].m_dmamap); 711 } 712 if (error) { 713 errstring = "can't allocate DMA maps for mbufs"; 714 goto bad; 715 } 716 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 717 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 718 + sizeof(struct tl_Rx_list) * i; 719 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 720 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 721 + sizeof(struct tl_Tx_list) * i; 722 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 723 errstring = "out of mbuf for receive list"; 724 error = ENOMEM; 725 goto bad; 726 } 727 if (i > 0) { /* chain the list */ 728 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 729 sc->hw_Rx_list[i - 1].fwd = 730 htole32(sc->Rx_list[i].hw_listaddr); 731 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 732 } 733 } 734 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 735 sc->Rx_list[TL_NBUF - 1].next = NULL; 736 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 737 sc->Tx_list[TL_NBUF - 1].next = NULL; 738 739 sc->active_Rx = &sc->Rx_list[0]; 740 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 741 sc->active_Tx = sc->last_Tx = NULL; 742 sc->Free_Tx = &sc->Tx_list[0]; 743 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 744 sizeof(struct tl_Rx_list) * TL_NBUF, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 747 sizeof(struct tl_Tx_list) * TL_NBUF, 748 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 749 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 750 BUS_DMASYNC_PREWRITE); 751 752 /* set media */ 753 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 754 error = 0; 755 else if (error != 0) { 756 errstring = "could not set media"; 757 goto bad; 758 } 759 760 /* start ticks calls */ 761 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 762 /* write address of Rx list and enable interrupts */ 763 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 764 TL_HR_WRITE(sc, TL_HOST_CMD, 765 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 766 sc->tl_if.if_flags |= IFF_RUNNING; 767 sc->tl_if.if_flags &= ~IFF_OACTIVE; 768 splx(s); 769 return 0; 770 bad: 771 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 772 splx(s); 773 return error; 774 } 775 776 777 static uint32_t 778 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 779 { 780 781 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 782 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 783 } 784 785 static uint8_t 786 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 787 { 788 789 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 790 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 791 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 792 } 793 794 static void 795 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 796 { 797 798 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 799 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 800 } 801 802 static void 803 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 804 { 805 806 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 807 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 808 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 809 } 810 811 void 812 tl_mii_sync(struct tl_softc *sc) 813 { 814 int i; 815 816 netsio_clr(sc, TL_NETSIO_MTXEN); 817 for (i = 0; i < 32; i++) { 818 netsio_clr(sc, TL_NETSIO_MCLK); 819 netsio_set(sc, TL_NETSIO_MCLK); 820 } 821 } 822 823 void 824 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 825 { 826 int i; 827 828 netsio_set(sc, TL_NETSIO_MTXEN); 829 for (i = 1 << (nbits - 1); i; i = i >> 1) { 830 netsio_clr(sc, TL_NETSIO_MCLK); 831 netsio_read(sc, TL_NETSIO_MCLK); 832 if (data & i) 833 netsio_set(sc, TL_NETSIO_MDATA); 834 else 835 netsio_clr(sc, TL_NETSIO_MDATA); 836 netsio_set(sc, TL_NETSIO_MCLK); 837 netsio_read(sc, TL_NETSIO_MCLK); 838 } 839 } 840 841 int 842 tl_mii_read(device_t self, int phy, int reg) 843 { 844 struct tl_softc *sc = device_private(self); 845 int val = 0, i, err; 846 847 /* 848 * Read the PHY register by manually driving the MII control lines. 849 */ 850 851 tl_mii_sync(sc); 852 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 853 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 854 tl_mii_sendbits(sc, phy, 5); 855 tl_mii_sendbits(sc, reg, 5); 856 857 netsio_clr(sc, TL_NETSIO_MTXEN); 858 netsio_clr(sc, TL_NETSIO_MCLK); 859 netsio_set(sc, TL_NETSIO_MCLK); 860 netsio_clr(sc, TL_NETSIO_MCLK); 861 862 err = netsio_read(sc, TL_NETSIO_MDATA); 863 netsio_set(sc, TL_NETSIO_MCLK); 864 865 /* Even if an error occurs, must still clock out the cycle. */ 866 for (i = 0; i < 16; i++) { 867 val <<= 1; 868 netsio_clr(sc, TL_NETSIO_MCLK); 869 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 870 val |= 1; 871 netsio_set(sc, TL_NETSIO_MCLK); 872 } 873 netsio_clr(sc, TL_NETSIO_MCLK); 874 netsio_set(sc, TL_NETSIO_MCLK); 875 876 return err ? 0 : val; 877 } 878 879 void 880 tl_mii_write(device_t self, int phy, int reg, int val) 881 { 882 struct tl_softc *sc = device_private(self); 883 884 /* 885 * Write the PHY register by manually driving the MII control lines. 886 */ 887 888 tl_mii_sync(sc); 889 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 890 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 891 tl_mii_sendbits(sc, phy, 5); 892 tl_mii_sendbits(sc, reg, 5); 893 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 894 tl_mii_sendbits(sc, val, 16); 895 896 netsio_clr(sc, TL_NETSIO_MCLK); 897 netsio_set(sc, TL_NETSIO_MCLK); 898 } 899 900 void 901 tl_statchg(device_t self) 902 { 903 tl_softc_t *sc = device_private(self); 904 uint32_t reg; 905 906 #ifdef TLDEBUG 907 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 908 #endif 909 910 /* 911 * We must keep the ThunderLAN and the PHY in sync as 912 * to the status of full-duplex! 913 */ 914 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 915 if (sc->tl_mii.mii_media_active & IFM_FDX) 916 reg |= TL_NETCOMMAND_DUPLEX; 917 else 918 reg &= ~TL_NETCOMMAND_DUPLEX; 919 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 920 } 921 922 /********** I2C glue **********/ 923 924 static int 925 tl_i2c_acquire_bus(void *cookie, int flags) 926 { 927 928 /* private bus */ 929 return 0; 930 } 931 932 static void 933 tl_i2c_release_bus(void *cookie, int flags) 934 { 935 936 /* private bus */ 937 } 938 939 static int 940 tl_i2c_send_start(void *cookie, int flags) 941 { 942 943 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 944 } 945 946 static int 947 tl_i2c_send_stop(void *cookie, int flags) 948 { 949 950 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 951 } 952 953 static int 954 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 955 { 956 957 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 958 } 959 960 static int 961 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 962 { 963 964 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 965 } 966 967 static int 968 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 969 { 970 971 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 972 } 973 974 /********** I2C bit-bang glue **********/ 975 976 static void 977 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 978 { 979 struct tl_softc *sc = cookie; 980 uint8_t reg; 981 982 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 983 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 984 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 985 } 986 987 static void 988 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 989 { 990 struct tl_softc *sc = cookie; 991 uint8_t reg; 992 993 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 994 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 995 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 996 } 997 998 static uint32_t 999 tl_i2cbb_read(void *cookie) 1000 { 1001 1002 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 1003 } 1004 1005 /********** End of I2C stuff **********/ 1006 1007 static int 1008 tl_intr(void *v) 1009 { 1010 tl_softc_t *sc = v; 1011 struct ifnet *ifp = &sc->tl_if; 1012 struct Rx_list *Rx; 1013 struct Tx_list *Tx; 1014 struct mbuf *m; 1015 uint32_t int_type, int_reg; 1016 int ack = 0; 1017 int size; 1018 1019 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1020 int_type = int_reg & TL_INTR_MASK; 1021 if (int_type == 0) 1022 return 0; 1023 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1024 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev), 1025 int_type, int_reg); 1026 #endif 1027 /* disable interrupts */ 1028 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1029 switch(int_type & TL_INTR_MASK) { 1030 case TL_INTR_RxEOF: 1031 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1032 sizeof(struct tl_Rx_list) * TL_NBUF, 1033 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1034 while(le32toh(sc->active_Rx->hw_list->stat) & 1035 TL_RX_CSTAT_CPLT) { 1036 /* dequeue and requeue at end of list */ 1037 ack++; 1038 Rx = sc->active_Rx; 1039 sc->active_Rx = Rx->next; 1040 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1041 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1042 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1043 m = Rx->m; 1044 size = le32toh(Rx->hw_list->stat) >> 16; 1045 #ifdef TLDEBUG_RX 1046 printf("%s: RX list complete, Rx %p, size=%d\n", 1047 __func__, Rx, size); 1048 #endif 1049 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1050 /* 1051 * No new mbuf, reuse the same. This means 1052 * that this packet 1053 * is lost 1054 */ 1055 m = NULL; 1056 #ifdef TL_PRIV_STATS 1057 sc->ierr_nomem++; 1058 #endif 1059 #ifdef TLDEBUG 1060 printf("%s: out of mbuf, lost input packet\n", 1061 device_xname(sc->sc_dev)); 1062 #endif 1063 } 1064 Rx->next = NULL; 1065 Rx->hw_list->fwd = 0; 1066 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1067 sc->last_Rx->next = Rx; 1068 sc->last_Rx = Rx; 1069 1070 /* deliver packet */ 1071 if (m) { 1072 if (size < sizeof(struct ether_header)) { 1073 m_freem(m); 1074 continue; 1075 } 1076 m->m_pkthdr.rcvif = ifp; 1077 m->m_pkthdr.len = m->m_len = size; 1078 #ifdef TLDEBUG_RX 1079 { 1080 struct ether_header *eh = 1081 mtod(m, struct ether_header *); 1082 printf("%s: Rx packet:\n", __func__); 1083 ether_printheader(eh); 1084 } 1085 #endif 1086 #if NBPFILTER > 0 1087 if (ifp->if_bpf) 1088 bpf_mtap(ifp->if_bpf, m); 1089 #endif /* NBPFILTER > 0 */ 1090 (*ifp->if_input)(ifp, m); 1091 } 1092 } 1093 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1094 sizeof(struct tl_Rx_list) * TL_NBUF, 1095 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1096 #ifdef TLDEBUG_RX 1097 printf("TL_INTR_RxEOF: ack %d\n", ack); 1098 #else 1099 if (ack == 0) { 1100 printf("%s: EOF intr without anything to read !\n", 1101 device_xname(sc->sc_dev)); 1102 tl_reset(sc); 1103 /* schedule reinit of the board */ 1104 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1105 return 1; 1106 } 1107 #endif 1108 break; 1109 case TL_INTR_RxEOC: 1110 ack++; 1111 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1112 sizeof(struct tl_Rx_list) * TL_NBUF, 1113 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1114 #ifdef TLDEBUG_RX 1115 printf("TL_INTR_RxEOC: ack %d\n", ack); 1116 #endif 1117 #ifdef DIAGNOSTIC 1118 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1119 printf("%s: Rx EOC interrupt and active Tx list not " 1120 "cleared\n", device_xname(sc->sc_dev)); 1121 return 0; 1122 } else 1123 #endif 1124 { 1125 /* 1126 * write address of Rx list and send Rx GO command, ack 1127 * interrupt and enable interrupts in one command 1128 */ 1129 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1130 TL_HR_WRITE(sc, TL_HOST_CMD, 1131 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1132 HOST_CMD_ACK | HOST_CMD_IntOn); 1133 return 1; 1134 } 1135 case TL_INTR_TxEOF: 1136 case TL_INTR_TxEOC: 1137 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1138 sizeof(struct tl_Tx_list) * TL_NBUF, 1139 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1140 while ((Tx = sc->active_Tx) != NULL) { 1141 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1142 break; 1143 ack++; 1144 #ifdef TLDEBUG_TX 1145 printf("TL_INTR_TxEOC: list 0x%x done\n", 1146 (int)Tx->hw_listaddr); 1147 #endif 1148 Tx->hw_list->stat = 0; 1149 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1150 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1151 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1152 m_freem(Tx->m); 1153 Tx->m = NULL; 1154 sc->active_Tx = Tx->next; 1155 if (sc->active_Tx == NULL) 1156 sc->last_Tx = NULL; 1157 Tx->next = sc->Free_Tx; 1158 sc->Free_Tx = Tx; 1159 } 1160 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1161 sizeof(struct tl_Tx_list) * TL_NBUF, 1162 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1163 /* if this was an EOC, ACK immediatly */ 1164 if (ack) 1165 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1166 if (int_type == TL_INTR_TxEOC) { 1167 #ifdef TLDEBUG_TX 1168 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1169 ack); 1170 #endif 1171 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1172 HOST_CMD_ACK | HOST_CMD_IntOn); 1173 if (sc->active_Tx != NULL) { 1174 /* needs a Tx go command */ 1175 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1176 sc->active_Tx->hw_listaddr); 1177 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1178 } 1179 sc->tl_if.if_timer = 0; 1180 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1181 tl_ifstart(&sc->tl_if); 1182 return 1; 1183 } 1184 #ifdef TLDEBUG 1185 else { 1186 printf("TL_INTR_TxEOF: ack %d\n", ack); 1187 } 1188 #endif 1189 sc->tl_if.if_timer = 0; 1190 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1191 tl_ifstart(&sc->tl_if); 1192 break; 1193 case TL_INTR_Stat: 1194 ack++; 1195 #ifdef TLDEBUG 1196 printf("TL_INTR_Stat: ack %d\n", ack); 1197 #endif 1198 tl_read_stats(sc); 1199 break; 1200 case TL_INTR_Adc: 1201 if (int_reg & TL_INTVec_MASK) { 1202 /* adapter check conditions */ 1203 printf("%s: check condition, intvect=0x%x, " 1204 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1205 int_reg & TL_INTVec_MASK, 1206 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1207 tl_reset(sc); 1208 /* schedule reinit of the board */ 1209 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1210 return 1; 1211 } else { 1212 uint8_t netstat; 1213 /* Network status */ 1214 netstat = 1215 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1216 printf("%s: network status, NetSts=%x\n", 1217 device_xname(sc->sc_dev), netstat); 1218 /* Ack interrupts */ 1219 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1220 netstat); 1221 ack++; 1222 } 1223 break; 1224 default: 1225 printf("%s: unhandled interrupt code %x!\n", 1226 device_xname(sc->sc_dev), int_type); 1227 ack++; 1228 } 1229 1230 if (ack) { 1231 /* Ack the interrupt and enable interrupts */ 1232 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1233 HOST_CMD_IntOn); 1234 #if NRND > 0 1235 if (RND_ENABLED(&sc->rnd_source)) 1236 rnd_add_uint32(&sc->rnd_source, int_reg); 1237 #endif 1238 return 1; 1239 } 1240 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1241 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1242 return 0; 1243 } 1244 1245 static int 1246 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1247 { 1248 struct tl_softc *sc = ifp->if_softc; 1249 int s, error; 1250 1251 s = splnet(); 1252 error = ether_ioctl(ifp, cmd, data); 1253 if (error == ENETRESET) { 1254 if (ifp->if_flags & IFF_RUNNING) 1255 tl_addr_filter(sc); 1256 error = 0; 1257 } 1258 splx(s); 1259 return error; 1260 } 1261 1262 static void 1263 tl_ifstart(struct ifnet *ifp) 1264 { 1265 tl_softc_t *sc = ifp->if_softc; 1266 struct mbuf *mb_head; 1267 struct Tx_list *Tx; 1268 int segment, size; 1269 int again, error; 1270 1271 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1272 return; 1273 txloop: 1274 /* If we don't have more space ... */ 1275 if (sc->Free_Tx == NULL) { 1276 #ifdef TLDEBUG 1277 printf("%s: No free TX list\n", __func__); 1278 #endif 1279 sc->tl_if.if_flags |= IFF_OACTIVE; 1280 return; 1281 } 1282 /* Grab a paquet for output */ 1283 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1284 if (mb_head == NULL) { 1285 #ifdef TLDEBUG_TX 1286 printf("%s: nothing to send\n", __func__); 1287 #endif 1288 return; 1289 } 1290 Tx = sc->Free_Tx; 1291 sc->Free_Tx = Tx->next; 1292 Tx->next = NULL; 1293 again = 0; 1294 /* 1295 * Go through each of the mbufs in the chain and initialize 1296 * the transmit list descriptors with the physical address 1297 * and size of the mbuf. 1298 */ 1299 tbdinit: 1300 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1301 Tx->m = mb_head; 1302 size = mb_head->m_pkthdr.len; 1303 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1304 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1305 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1306 struct mbuf *mn; 1307 /* 1308 * We ran out of segments, or we will. We have to recopy this 1309 * mbuf chain first. 1310 */ 1311 if (error == 0) 1312 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1313 if (again) { 1314 /* already copyed, can't do much more */ 1315 m_freem(mb_head); 1316 goto bad; 1317 } 1318 again = 1; 1319 #ifdef TLDEBUG_TX 1320 printf("%s: need to copy mbuf\n", __func__); 1321 #endif 1322 #ifdef TL_PRIV_STATS 1323 sc->oerr_mcopy++; 1324 #endif 1325 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1326 if (mn == NULL) { 1327 m_freem(mb_head); 1328 goto bad; 1329 } 1330 if (mb_head->m_pkthdr.len > MHLEN) { 1331 MCLGET(mn, M_DONTWAIT); 1332 if ((mn->m_flags & M_EXT) == 0) { 1333 m_freem(mn); 1334 m_freem(mb_head); 1335 goto bad; 1336 } 1337 } 1338 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1339 mtod(mn, void *)); 1340 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1341 m_freem(mb_head); 1342 mb_head = mn; 1343 goto tbdinit; 1344 } 1345 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1346 Tx->hw_list->seg[segment].data_addr = 1347 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1348 Tx->hw_list->seg[segment].data_count = 1349 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1350 } 1351 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1352 Tx->m_dmamap->dm_mapsize, 1353 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1354 /* We are at end of mbuf chain. check the size and 1355 * see if it needs to be extended 1356 */ 1357 if (size < ETHER_MIN_TX) { 1358 #ifdef DIAGNOSTIC 1359 if (segment >= TL_NSEG) { 1360 panic("%s: to much segmets (%d)", __func__, segment); 1361 } 1362 #endif 1363 /* 1364 * add the nullbuf in the seg 1365 */ 1366 Tx->hw_list->seg[segment].data_count = 1367 htole32(ETHER_MIN_TX - size); 1368 Tx->hw_list->seg[segment].data_addr = 1369 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1370 size = ETHER_MIN_TX; 1371 segment++; 1372 } 1373 /* The list is done, finish the list init */ 1374 Tx->hw_list->seg[segment - 1].data_count |= 1375 htole32(TL_LAST_SEG); 1376 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1377 #ifdef TLDEBUG_TX 1378 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1379 le32toh(Tx->hw_list->stat)); 1380 #if 0 1381 for (segment = 0; segment < TL_NSEG; segment++) { 1382 printf(" seg %d addr 0x%x len 0x%x\n", 1383 segment, 1384 le32toh(Tx->hw_list->seg[segment].data_addr), 1385 le32toh(Tx->hw_list->seg[segment].data_count)); 1386 } 1387 #endif 1388 #endif 1389 if (sc->active_Tx == NULL) { 1390 sc->active_Tx = sc->last_Tx = Tx; 1391 #ifdef TLDEBUG_TX 1392 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1393 (int)Tx->hw_listaddr); 1394 #endif 1395 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1396 sizeof(struct tl_Tx_list) * TL_NBUF, 1397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1398 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1399 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1400 } else { 1401 #ifdef TLDEBUG_TX 1402 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1403 (int)Tx->hw_listaddr); 1404 #endif 1405 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1406 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1407 sizeof(struct tl_Tx_list) * TL_NBUF, 1408 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1409 sc->last_Tx->next = Tx; 1410 sc->last_Tx = Tx; 1411 #ifdef DIAGNOSTIC 1412 if (sc->last_Tx->hw_list->fwd & 0x7) 1413 printf("%s: physical addr 0x%x of list not properly " 1414 "aligned\n", 1415 device_xname(sc->sc_dev), 1416 sc->last_Rx->hw_list->fwd); 1417 #endif 1418 } 1419 #if NBPFILTER > 0 1420 /* Pass packet to bpf if there is a listener */ 1421 if (ifp->if_bpf) 1422 bpf_mtap(ifp->if_bpf, mb_head); 1423 #endif 1424 /* 1425 * Set a 5 second timer just in case we don't hear from the card again. 1426 */ 1427 ifp->if_timer = 5; 1428 goto txloop; 1429 bad: 1430 #ifdef TLDEBUG 1431 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1432 #endif 1433 Tx->next = sc->Free_Tx; 1434 sc->Free_Tx = Tx; 1435 } 1436 1437 static void 1438 tl_ifwatchdog(struct ifnet *ifp) 1439 { 1440 tl_softc_t *sc = ifp->if_softc; 1441 1442 if ((ifp->if_flags & IFF_RUNNING) == 0) 1443 return; 1444 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1445 ifp->if_oerrors++; 1446 tl_init(ifp); 1447 } 1448 1449 static int 1450 tl_mediachange(struct ifnet *ifp) 1451 { 1452 1453 if (ifp->if_flags & IFF_UP) 1454 tl_init(ifp); 1455 return 0; 1456 } 1457 1458 static int 1459 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1460 { 1461 struct mbuf *m; 1462 int error; 1463 1464 MGETHDR(m, M_DONTWAIT, MT_DATA); 1465 if (m != NULL) { 1466 MCLGET(m, M_DONTWAIT); 1467 if ((m->m_flags & M_EXT) == 0) { 1468 m_freem(m); 1469 if (oldm == NULL) 1470 return 0; 1471 m = oldm; 1472 m->m_data = m->m_ext.ext_buf; 1473 } 1474 } else { 1475 if (oldm == NULL) 1476 return 0; 1477 m = oldm; 1478 m->m_data = m->m_ext.ext_buf; 1479 } 1480 1481 /* (re)init the Rx_list struct */ 1482 1483 Rx->m = m; 1484 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1485 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1486 printf("%s: bus_dmamap_load() failed (error %d) for " 1487 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1488 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1489 m_freem(m); 1490 Rx->m = NULL; 1491 return 0; 1492 } 1493 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1494 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1495 /* 1496 * Move the data pointer up so that the incoming data packet 1497 * will be 32-bit aligned. 1498 */ 1499 m->m_data += 2; 1500 1501 Rx->hw_list->stat = 1502 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1503 Rx->hw_list->seg.data_count = 1504 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1505 Rx->hw_list->seg.data_addr = 1506 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1507 return (m != oldm); 1508 } 1509 1510 static void 1511 tl_ticks(void *v) 1512 { 1513 tl_softc_t *sc = v; 1514 1515 tl_read_stats(sc); 1516 1517 /* Tick the MII. */ 1518 mii_tick(&sc->tl_mii); 1519 1520 /* read statistics every seconds */ 1521 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1522 } 1523 1524 static void 1525 tl_read_stats(tl_softc_t *sc) 1526 { 1527 uint32_t reg; 1528 int ierr_overr; 1529 int ierr_code; 1530 int ierr_crc; 1531 int oerr_underr; 1532 int oerr_deferred; 1533 int oerr_coll; 1534 int oerr_multicoll; 1535 int oerr_exesscoll; 1536 int oerr_latecoll; 1537 int oerr_carrloss; 1538 struct ifnet *ifp = &sc->tl_if; 1539 1540 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1541 ifp->if_opackets += reg & 0x00ffffff; 1542 oerr_underr = reg >> 24; 1543 1544 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1545 ifp->if_ipackets += reg & 0x00ffffff; 1546 ierr_overr = reg >> 24; 1547 1548 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1549 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1550 ierr_code = (reg & TL_FERR_CODE) >> 24; 1551 oerr_deferred = (reg & TL_FERR_DEF); 1552 1553 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1554 oerr_multicoll = (reg & TL_COL_MULTI); 1555 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1556 1557 reg = tl_intreg_read(sc, TL_INT_LERR); 1558 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1559 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1560 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1561 1562 1563 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1564 oerr_carrloss; 1565 ifp->if_collisions += oerr_coll + oerr_multicoll; 1566 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1567 1568 if (ierr_overr) 1569 printf("%s: receiver ring buffer overrun\n", 1570 device_xname(sc->sc_dev)); 1571 if (oerr_underr) 1572 printf("%s: transmit buffer underrun\n", 1573 device_xname(sc->sc_dev)); 1574 #ifdef TL_PRIV_STATS 1575 sc->ierr_overr += ierr_overr; 1576 sc->ierr_code += ierr_code; 1577 sc->ierr_crc += ierr_crc; 1578 sc->oerr_underr += oerr_underr; 1579 sc->oerr_deferred += oerr_deferred; 1580 sc->oerr_coll += oerr_coll; 1581 sc->oerr_multicoll += oerr_multicoll; 1582 sc->oerr_exesscoll += oerr_exesscoll; 1583 sc->oerr_latecoll += oerr_latecoll; 1584 sc->oerr_carrloss += oerr_carrloss; 1585 #endif 1586 } 1587 1588 static void 1589 tl_addr_filter(tl_softc_t *sc) 1590 { 1591 struct ether_multistep step; 1592 struct ether_multi *enm; 1593 uint32_t hash[2] = {0, 0}; 1594 int i; 1595 1596 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1597 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1598 while (enm != NULL) { 1599 #ifdef TLDEBUG 1600 printf("%s: addrs %s %s\n", __func__, 1601 ether_sprintf(enm->enm_addrlo), 1602 ether_sprintf(enm->enm_addrhi)); 1603 #endif 1604 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1605 i = tl_multicast_hash(enm->enm_addrlo); 1606 hash[i / 32] |= 1 << (i%32); 1607 } else { 1608 hash[0] = hash[1] = 0xffffffff; 1609 sc->tl_if.if_flags |= IFF_ALLMULTI; 1610 break; 1611 } 1612 ETHER_NEXT_MULTI(step, enm); 1613 } 1614 #ifdef TLDEBUG 1615 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1616 #endif 1617 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1618 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1619 } 1620 1621 static int 1622 tl_multicast_hash(uint8_t *a) 1623 { 1624 int hash; 1625 1626 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1627 #define xor8(a,b,c,d,e,f,g,h) \ 1628 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1629 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1630 1631 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1632 DA(a,36), DA(a,42)); 1633 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1634 DA(a,37), DA(a,43)) << 1; 1635 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1636 DA(a,38), DA(a,44)) << 2; 1637 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1638 DA(a,39), DA(a,45)) << 3; 1639 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1640 DA(a,40), DA(a,46)) << 4; 1641 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1642 DA(a,41), DA(a,47)) << 5; 1643 1644 return hash; 1645 } 1646 1647 #if defined(TLDEBUG_RX) 1648 void 1649 ether_printheader(struct ether_header *eh) 1650 { 1651 uint8_t *c = (uint8_t *)eh; 1652 int i; 1653 1654 for (i = 0; i < sizeof(struct ether_header); i++) 1655 printf("%02x ", (u_int)c[i]); 1656 printf("\n"); 1657 } 1658 #endif 1659
Indexes created Sun Oct 19 02:09:48 GMT 2025