if_tl.c revision 1.94 1 /* $NetBSD: if_tl.c,v 1.94 2010/01/19 22:07:02 pooka Exp $ */
2
3 /*
4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * Texas Instruments ThunderLAN ethernet controller
29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A)
30 * available from www.ti.com
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.94 2010/01/19 22:07:02 pooka Exp $");
35
36 #undef TLDEBUG
37 #define TL_PRIV_STATS
38 #undef TLDEBUG_RX
39 #undef TLDEBUG_TX
40 #undef TLDEBUG_ADDR
41
42 #include "opt_inet.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/mbuf.h>
47 #include <sys/protosw.h>
48 #include <sys/socket.h>
49 #include <sys/ioctl.h>
50 #include <sys/errno.h>
51 #include <sys/malloc.h>
52 #include <sys/kernel.h>
53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */
54 #include <sys/device.h>
55
56 #include <net/if.h>
57 #if defined(SIOCSIFMEDIA)
58 #include <net/if_media.h>
59 #endif
60 #include <net/if_types.h>
61 #include <net/if_dl.h>
62 #include <net/route.h>
63 #include <net/netisr.h>
64
65 #include <net/bpf.h>
66 #include <net/bpfdesc.h>
67
68 #include "rnd.h"
69 #if NRND > 0
70 #include <sys/rnd.h>
71 #endif
72
73 #ifdef INET
74 #include <netinet/in.h>
75 #include <netinet/in_systm.h>
76 #include <netinet/in_var.h>
77 #include <netinet/ip.h>
78 #endif
79
80
81 #if defined(__NetBSD__)
82 #include <net/if_ether.h>
83 #include <uvm/uvm_extern.h>
84 #if defined(INET)
85 #include <netinet/if_inarp.h>
86 #endif
87
88 #include <sys/bus.h>
89 #include <sys/intr.h>
90
91 #include <dev/pci/pcireg.h>
92 #include <dev/pci/pcivar.h>
93 #include <dev/pci/pcidevs.h>
94
95 #include <dev/i2c/i2cvar.h>
96 #include <dev/i2c/i2c_bitbang.h>
97 #include <dev/i2c/at24cxxvar.h>
98
99 #include <dev/mii/mii.h>
100 #include <dev/mii/miivar.h>
101
102 #include <dev/mii/tlphyvar.h>
103
104 #include <dev/pci/if_tlregs.h>
105 #include <dev/pci/if_tlvar.h>
106 #endif /* __NetBSD__ */
107
108 /* number of transmit/receive buffers */
109 #ifndef TL_NBUF
110 #define TL_NBUF 32
111 #endif
112
113 static int tl_pci_match(device_t, cfdata_t, void *);
114 static void tl_pci_attach(device_t, device_t, void *);
115 static int tl_intr(void *);
116
117 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *);
118 static int tl_mediachange(struct ifnet *);
119 static void tl_ifwatchdog(struct ifnet *);
120 static bool tl_shutdown(device_t, int);
121
122 static void tl_ifstart(struct ifnet *);
123 static void tl_reset(tl_softc_t *);
124 static int tl_init(struct ifnet *);
125 static void tl_stop(struct ifnet *, int);
126 static void tl_restart(void *);
127 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *);
128 static void tl_read_stats(tl_softc_t *);
129 static void tl_ticks(void *);
130 static int tl_multicast_hash(uint8_t *);
131 static void tl_addr_filter(tl_softc_t *);
132
133 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t);
134 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t);
135 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t);
136 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t);
137
138 void tl_mii_sync(struct tl_softc *);
139 void tl_mii_sendbits(struct tl_softc *, uint32_t, int);
140
141
142 #if defined(TLDEBUG_RX)
143 static void ether_printheader(struct ether_header *);
144 #endif
145
146 int tl_mii_read(device_t, int, int);
147 void tl_mii_write(device_t, int, int, int);
148
149 void tl_statchg(device_t);
150
151 /* I2C glue */
152 static int tl_i2c_acquire_bus(void *, int);
153 static void tl_i2c_release_bus(void *, int);
154 static int tl_i2c_send_start(void *, int);
155 static int tl_i2c_send_stop(void *, int);
156 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int);
157 static int tl_i2c_read_byte(void *, uint8_t *, int);
158 static int tl_i2c_write_byte(void *, uint8_t, int);
159
160 /* I2C bit-bang glue */
161 static void tl_i2cbb_set_bits(void *, uint32_t);
162 static void tl_i2cbb_set_dir(void *, uint32_t);
163 static uint32_t tl_i2cbb_read(void *);
164 static const struct i2c_bitbang_ops tl_i2cbb_ops = {
165 tl_i2cbb_set_bits,
166 tl_i2cbb_set_dir,
167 tl_i2cbb_read,
168 {
169 TL_NETSIO_EDATA, /* SDA */
170 TL_NETSIO_ECLOCK, /* SCL */
171 TL_NETSIO_ETXEN, /* SDA is output */
172 0, /* SDA is input */
173 }
174 };
175
176 static inline void netsio_clr(tl_softc_t *, uint8_t);
177 static inline void netsio_set(tl_softc_t *, uint8_t);
178 static inline uint8_t netsio_read(tl_softc_t *, uint8_t);
179
180 static inline void
181 netsio_clr(tl_softc_t *sc, uint8_t bits)
182 {
183
184 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
185 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits));
186 }
187
188 static inline void
189 netsio_set(tl_softc_t *sc, uint8_t bits)
190 {
191
192 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio,
193 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits);
194 }
195
196 static inline uint8_t
197 netsio_read(tl_softc_t *sc, uint8_t bits)
198 {
199
200 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits;
201 }
202
203 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t),
204 tl_pci_match, tl_pci_attach, NULL, NULL);
205
206 static const struct tl_product_desc tl_compaq_products[] = {
207 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T,
208 "Compaq Netelligent 10/100 TX" },
209 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T,
210 "Integrated Compaq Netelligent 10/100 TX" },
211 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5,
212 "Compaq Netelligent 10 T" },
213 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2,
214 "Compaq Netelligent 10 T/2 UTP/Coax" },
215 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2,
216 "Compaq Integrated NetFlex 3/P" },
217 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T,
218 "Compaq ProLiant Integrated Netelligent 10/100 TX" },
219 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
220 "Compaq Dual Port Netelligent 10/100 TX" },
221 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T,
222 "Compaq Deskpro 4000 5233MMX" },
223 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2,
224 "Compaq NetFlex 3/P w/ BNC" },
225 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5,
226 "Compaq NetFlex 3/P" },
227 { 0, 0, NULL },
228 };
229
230 static const struct tl_product_desc tl_ti_products[] = {
231 /*
232 * Built-in Ethernet on the TI TravelMate 5000
233 * docking station; better product description?
234 */
235 { PCI_PRODUCT_TI_TLAN, 0,
236 "Texas Instruments ThunderLAN" },
237 { 0, 0, NULL },
238 };
239
240 struct tl_vendor_desc {
241 uint32_t tv_vendor;
242 const struct tl_product_desc *tv_products;
243 };
244
245 const struct tl_vendor_desc tl_vendors[] = {
246 { PCI_VENDOR_COMPAQ, tl_compaq_products },
247 { PCI_VENDOR_TI, tl_ti_products },
248 { 0, NULL },
249 };
250
251 static const struct tl_product_desc *tl_lookup_product(uint32_t);
252
253 static const struct tl_product_desc *
254 tl_lookup_product(uint32_t id)
255 {
256 const struct tl_product_desc *tp;
257 const struct tl_vendor_desc *tv;
258
259 for (tv = tl_vendors; tv->tv_products != NULL; tv++)
260 if (PCI_VENDOR(id) == tv->tv_vendor)
261 break;
262
263 if ((tp = tv->tv_products) == NULL)
264 return NULL;
265
266 for (; tp->tp_desc != NULL; tp++)
267 if (PCI_PRODUCT(id) == tp->tp_product)
268 break;
269
270 if (tp->tp_desc == NULL)
271 return NULL;
272
273 return tp;
274 }
275
276 static int
277 tl_pci_match(device_t parent, cfdata_t cf, void *aux)
278 {
279 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
280
281 if (tl_lookup_product(pa->pa_id) != NULL)
282 return 1;
283
284 return 0;
285 }
286
287 static void
288 tl_pci_attach(device_t parent, device_t self, void *aux)
289 {
290 tl_softc_t *sc = device_private(self);
291 struct pci_attach_args * const pa = (struct pci_attach_args *)aux;
292 const struct tl_product_desc *tp;
293 struct ifnet * const ifp = &sc->tl_if;
294 bus_space_tag_t iot, memt;
295 bus_space_handle_t ioh, memh;
296 pci_intr_handle_t intrhandle;
297 const char *intrstr;
298 int ioh_valid, memh_valid;
299 int reg_io, reg_mem;
300 pcireg_t reg10, reg14;
301 pcireg_t csr;
302
303 sc->sc_dev = self;
304 aprint_normal("\n");
305
306 callout_init(&sc->tl_tick_ch, 0);
307 callout_init(&sc->tl_restart_ch, 0);
308
309 tp = tl_lookup_product(pa->pa_id);
310 if (tp == NULL)
311 panic("%s: impossible", __func__);
312 sc->tl_product = tp;
313
314 /*
315 * Map the card space. First we have to find the I/O and MEM
316 * registers. I/O is supposed to be at 0x10, MEM at 0x14,
317 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed.
318 * The ThunderLAN manual is not consistent about this either (there
319 * are both cases in code examples).
320 */
321 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10);
322 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14);
323 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO)
324 reg_io = 0x10;
325 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO)
326 reg_io = 0x14;
327 else
328 reg_io = 0;
329 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM)
330 reg_mem = 0x10;
331 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM)
332 reg_mem = 0x14;
333 else
334 reg_mem = 0;
335
336 if (reg_io != 0)
337 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO,
338 0, &iot, &ioh, NULL, NULL) == 0);
339 else
340 ioh_valid = 0;
341 if (reg_mem != 0)
342 memh_valid = (pci_mapreg_map(pa, PCI_CBMA,
343 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
344 0, &memt, &memh, NULL, NULL) == 0);
345 else
346 memh_valid = 0;
347
348 if (ioh_valid) {
349 sc->tl_bustag = iot;
350 sc->tl_bushandle = ioh;
351 } else if (memh_valid) {
352 sc->tl_bustag = memt;
353 sc->tl_bushandle = memh;
354 } else {
355 aprint_error_dev(self, "unable to map device registers\n");
356 return;
357 }
358 sc->tl_dmatag = pa->pa_dmat;
359
360 /* Enable the device. */
361 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
362 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
363 csr | PCI_COMMAND_MASTER_ENABLE);
364
365 aprint_normal_dev(self, "%s\n", tp->tp_desc);
366
367 tl_reset(sc);
368
369 /* fill in the i2c tag */
370 sc->sc_i2c.ic_cookie = sc;
371 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus;
372 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus;
373 sc->sc_i2c.ic_send_start = tl_i2c_send_start;
374 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop;
375 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer;
376 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte;
377 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte;
378
379 #ifdef TLDEBUG
380 aprint_debug_dev(self, "default values of INTreg: 0x%x\n",
381 tl_intreg_read(sc, TL_INT_Defaults));
382 #endif
383
384 /* read mac addr */
385 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */,
386 sc->tl_enaddr, ETHER_ADDR_LEN)) {
387 aprint_error_dev(self, "error reading Ethernet address\n");
388 return;
389 }
390 aprint_normal_dev(self, "Ethernet address %s\n",
391 ether_sprintf(sc->tl_enaddr));
392
393 /* Map and establish interrupts */
394 if (pci_intr_map(pa, &intrhandle)) {
395 aprint_error_dev(self, "couldn't map interrupt\n");
396 return;
397 }
398 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
399 sc->tl_if.if_softc = sc;
400 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET,
401 tl_intr, sc);
402 if (sc->tl_ih == NULL) {
403 aprint_error_dev(self, "couldn't establish interrupt");
404 if (intrstr != NULL)
405 aprint_error(" at %s", intrstr);
406 aprint_error("\n");
407 return;
408 }
409 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
410
411 /* init these pointers, so that tl_shutdown won't try to read them */
412 sc->Rx_list = NULL;
413 sc->Tx_list = NULL;
414
415 /* allocate DMA-safe memory for control structs */
416 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE,
417 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 ||
418 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs,
419 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl,
420 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
421 aprint_error_dev(self, "can't allocate DMA memory for lists\n");
422 return;
423 }
424
425 /*
426 * Initialize our media structures and probe the MII.
427 *
428 * Note that we don't care about the media instance. We
429 * are expecting to have multiple PHYs on the 10/100 cards,
430 * and on those cards we exclude the internal PHY from providing
431 * 10baseT. By ignoring the instance, it allows us to not have
432 * to specify it on the command line when switching media.
433 */
434 sc->tl_mii.mii_ifp = ifp;
435 sc->tl_mii.mii_readreg = tl_mii_read;
436 sc->tl_mii.mii_writereg = tl_mii_write;
437 sc->tl_mii.mii_statchg = tl_statchg;
438 sc->tl_ec.ec_mii = &sc->tl_mii;
439 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange,
440 ether_mediastatus);
441 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY,
442 MII_OFFSET_ANY, 0);
443 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) {
444 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
445 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE);
446 } else
447 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO);
448
449 /*
450 * We can support 802.1Q VLAN-sized frames.
451 */
452 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
453
454 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
455 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
456 ifp->if_ioctl = tl_ifioctl;
457 ifp->if_start = tl_ifstart;
458 ifp->if_watchdog = tl_ifwatchdog;
459 ifp->if_init = tl_init;
460 ifp->if_stop = tl_stop;
461 ifp->if_timer = 0;
462 IFQ_SET_READY(&ifp->if_snd);
463 if_attach(ifp);
464 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr);
465
466 /*
467 * Add shutdown hook so that DMA is disabled prior to reboot.
468 * Not doing reboot before the driver initializes.
469 */
470 if (pmf_device_register1(self, NULL, NULL, tl_shutdown))
471 pmf_class_network_register(self, ifp);
472 else
473 aprint_error_dev(self, "couldn't establish power handler\n");
474
475 #if NRND > 0
476 rnd_attach_source(&sc->rnd_source, device_xname(self),
477 RND_TYPE_NET, 0);
478 #endif
479 }
480
481 static void
482 tl_reset(tl_softc_t *sc)
483 {
484 int i;
485
486 /* read stats */
487 if (sc->tl_if.if_flags & IFF_RUNNING) {
488 callout_stop(&sc->tl_tick_ch);
489 tl_read_stats(sc);
490 }
491 /* Reset adapter */
492 TL_HR_WRITE(sc, TL_HOST_CMD,
493 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst);
494 DELAY(100000);
495 /* Disable interrupts */
496 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
497 /* setup aregs & hash */
498 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
499 tl_intreg_write(sc, i, 0);
500 #ifdef TLDEBUG_ADDR
501 printf("Areg & hash registers: \n");
502 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
503 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
504 #endif
505 /* Setup NetConfig */
506 tl_intreg_write(sc, TL_INT_NetConfig,
507 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN);
508 /* Bsize: accept default */
509 /* TX commit in Acommit: accept default */
510 /* Load Ld_tmr and Ld_thr */
511 /* Ld_tmr = 3 */
512 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr);
513 /* Ld_thr = 0 */
514 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr);
515 /* Unreset MII */
516 netsio_set(sc, TL_NETSIO_NMRST);
517 DELAY(100000);
518 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
519 }
520
521 static bool
522 tl_shutdown(device_t self, int howto)
523 {
524 tl_softc_t *sc = device_private(self);
525 struct ifnet *ifp = &sc->tl_if;
526
527 tl_stop(ifp, 1);
528
529 return true;
530 }
531
532 static void
533 tl_stop(struct ifnet *ifp, int disable)
534 {
535 tl_softc_t *sc = ifp->if_softc;
536 struct Tx_list *Tx;
537 int i;
538
539 if ((ifp->if_flags & IFF_RUNNING) == 0)
540 return;
541 /* disable interrupts */
542 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
543 /* stop TX and RX channels */
544 TL_HR_WRITE(sc, TL_HOST_CMD,
545 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes);
546 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP);
547 DELAY(100000);
548
549 /* stop statistics reading loop, read stats */
550 callout_stop(&sc->tl_tick_ch);
551 tl_read_stats(sc);
552
553 /* Down the MII. */
554 mii_down(&sc->tl_mii);
555
556 /* deallocate memory allocations */
557 if (sc->Rx_list) {
558 for (i = 0; i< TL_NBUF; i++) {
559 if (sc->Rx_list[i].m) {
560 bus_dmamap_unload(sc->tl_dmatag,
561 sc->Rx_list[i].m_dmamap);
562 m_freem(sc->Rx_list[i].m);
563 }
564 bus_dmamap_destroy(sc->tl_dmatag,
565 sc->Rx_list[i].m_dmamap);
566 sc->Rx_list[i].m = NULL;
567 }
568 free(sc->Rx_list, M_DEVBUF);
569 sc->Rx_list = NULL;
570 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap);
571 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap);
572 sc->hw_Rx_list = NULL;
573 while ((Tx = sc->active_Tx) != NULL) {
574 Tx->hw_list->stat = 0;
575 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
576 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap);
577 m_freem(Tx->m);
578 sc->active_Tx = Tx->next;
579 Tx->next = sc->Free_Tx;
580 sc->Free_Tx = Tx;
581 }
582 sc->last_Tx = NULL;
583 free(sc->Tx_list, M_DEVBUF);
584 sc->Tx_list = NULL;
585 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap);
586 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap);
587 sc->hw_Tx_list = NULL;
588 }
589 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
590 ifp->if_timer = 0;
591 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE;
592 }
593
594 static void
595 tl_restart(void *v)
596 {
597
598 tl_init(v);
599 }
600
601 static int
602 tl_init(struct ifnet *ifp)
603 {
604 tl_softc_t *sc = ifp->if_softc;
605 int i, s, error;
606 bus_size_t boundary;
607 prop_number_t prop_boundary;
608 const char *errstring;
609 char *nullbuf;
610
611 s = splnet();
612 /* cancel any pending IO */
613 tl_stop(ifp, 1);
614 tl_reset(sc);
615 if ((sc->tl_if.if_flags & IFF_UP) == 0) {
616 splx(s);
617 return 0;
618 }
619 /* Set various register to reasonable value */
620 /* setup NetCmd in promisc mode if needed */
621 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0;
622 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd,
623 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i);
624 /* Max receive size : MCLBYTES */
625 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff);
626 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH,
627 (MCLBYTES >> 8) & 0xff);
628
629 /* init MAC addr */
630 for (i = 0; i < ETHER_ADDR_LEN; i++)
631 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]);
632 /* add multicast filters */
633 tl_addr_filter(sc);
634 #ifdef TLDEBUG_ADDR
635 printf("Wrote Mac addr, Areg & hash registers are now: \n");
636 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4)
637 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i));
638 #endif
639
640 /* Pre-allocate receivers mbuf, make the lists */
641 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF,
642 M_NOWAIT|M_ZERO);
643 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF,
644 M_NOWAIT|M_ZERO);
645 if (sc->Rx_list == NULL || sc->Tx_list == NULL) {
646 errstring = "out of memory for lists";
647 error = ENOMEM;
648 goto bad;
649 }
650
651 /*
652 * Some boards (Set Engineering GFE) do not permit DMA transfers
653 * across page boundaries.
654 */
655 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev),
656 "tl-dma-page-boundary");
657 if (prop_boundary != NULL) {
658 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER);
659 boundary = (bus_size_t)prop_number_integer_value(prop_boundary);
660 } else {
661 boundary = 0;
662 }
663
664 error = bus_dmamap_create(sc->tl_dmatag,
665 sizeof(struct tl_Rx_list) * TL_NBUF, 1,
666 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK,
667 &sc->Rx_dmamap);
668 if (error == 0)
669 error = bus_dmamap_create(sc->tl_dmatag,
670 sizeof(struct tl_Tx_list) * TL_NBUF, 1,
671 sizeof(struct tl_Tx_list) * TL_NBUF, boundary,
672 BUS_DMA_WAITOK, &sc->Tx_dmamap);
673 if (error == 0)
674 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1,
675 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK,
676 &sc->null_dmamap);
677 if (error) {
678 errstring = "can't allocate DMA maps for lists";
679 goto bad;
680 }
681 memset(sc->ctrl, 0, PAGE_SIZE);
682 sc->hw_Rx_list = (void *)sc->ctrl;
683 sc->hw_Tx_list =
684 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF);
685 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF +
686 sizeof(struct tl_Tx_list) * TL_NBUF;
687 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap,
688 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL,
689 BUS_DMA_WAITOK);
690 if (error == 0)
691 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap,
692 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL,
693 BUS_DMA_WAITOK);
694 if (error == 0)
695 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap,
696 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK);
697 if (error) {
698 errstring = "can't DMA map DMA memory for lists";
699 goto bad;
700 }
701 for (i = 0; i < TL_NBUF; i++) {
702 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
703 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
704 &sc->Rx_list[i].m_dmamap);
705 if (error == 0) {
706 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES,
707 TL_NSEG, MCLBYTES, boundary,
708 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
709 &sc->Tx_list[i].m_dmamap);
710 }
711 if (error) {
712 errstring = "can't allocate DMA maps for mbufs";
713 goto bad;
714 }
715 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i];
716 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr
717 + sizeof(struct tl_Rx_list) * i;
718 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i];
719 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr
720 + sizeof(struct tl_Tx_list) * i;
721 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) {
722 errstring = "out of mbuf for receive list";
723 error = ENOMEM;
724 goto bad;
725 }
726 if (i > 0) { /* chain the list */
727 sc->Rx_list[i - 1].next = &sc->Rx_list[i];
728 sc->hw_Rx_list[i - 1].fwd =
729 htole32(sc->Rx_list[i].hw_listaddr);
730 sc->Tx_list[i - 1].next = &sc->Tx_list[i];
731 }
732 }
733 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0;
734 sc->Rx_list[TL_NBUF - 1].next = NULL;
735 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0;
736 sc->Tx_list[TL_NBUF - 1].next = NULL;
737
738 sc->active_Rx = &sc->Rx_list[0];
739 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1];
740 sc->active_Tx = sc->last_Tx = NULL;
741 sc->Free_Tx = &sc->Tx_list[0];
742 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
743 sizeof(struct tl_Rx_list) * TL_NBUF,
744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
745 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
746 sizeof(struct tl_Tx_list) * TL_NBUF,
747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
748 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX,
749 BUS_DMASYNC_PREWRITE);
750
751 /* set media */
752 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO)
753 error = 0;
754 else if (error != 0) {
755 errstring = "could not set media";
756 goto bad;
757 }
758
759 /* start ticks calls */
760 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
761 /* write address of Rx list and enable interrupts */
762 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr);
763 TL_HR_WRITE(sc, TL_HOST_CMD,
764 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn);
765 sc->tl_if.if_flags |= IFF_RUNNING;
766 sc->tl_if.if_flags &= ~IFF_OACTIVE;
767 splx(s);
768 return 0;
769 bad:
770 printf("%s: %s\n", device_xname(sc->sc_dev), errstring);
771 splx(s);
772 return error;
773 }
774
775
776 static uint32_t
777 tl_intreg_read(tl_softc_t *sc, uint32_t reg)
778 {
779
780 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
781 return TL_HR_READ(sc, TL_HOST_DIO_DATA);
782 }
783
784 static uint8_t
785 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg)
786 {
787
788 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
789 (reg & (~0x07)) & TL_HOST_DIOADR_MASK);
790 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07));
791 }
792
793 static void
794 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val)
795 {
796
797 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK);
798 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val);
799 }
800
801 static void
802 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val)
803 {
804
805 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR,
806 (reg & (~0x03)) & TL_HOST_DIOADR_MASK);
807 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val);
808 }
809
810 void
811 tl_mii_sync(struct tl_softc *sc)
812 {
813 int i;
814
815 netsio_clr(sc, TL_NETSIO_MTXEN);
816 for (i = 0; i < 32; i++) {
817 netsio_clr(sc, TL_NETSIO_MCLK);
818 netsio_set(sc, TL_NETSIO_MCLK);
819 }
820 }
821
822 void
823 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits)
824 {
825 int i;
826
827 netsio_set(sc, TL_NETSIO_MTXEN);
828 for (i = 1 << (nbits - 1); i; i = i >> 1) {
829 netsio_clr(sc, TL_NETSIO_MCLK);
830 netsio_read(sc, TL_NETSIO_MCLK);
831 if (data & i)
832 netsio_set(sc, TL_NETSIO_MDATA);
833 else
834 netsio_clr(sc, TL_NETSIO_MDATA);
835 netsio_set(sc, TL_NETSIO_MCLK);
836 netsio_read(sc, TL_NETSIO_MCLK);
837 }
838 }
839
840 int
841 tl_mii_read(device_t self, int phy, int reg)
842 {
843 struct tl_softc *sc = device_private(self);
844 int val = 0, i, err;
845
846 /*
847 * Read the PHY register by manually driving the MII control lines.
848 */
849
850 tl_mii_sync(sc);
851 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
852 tl_mii_sendbits(sc, MII_COMMAND_READ, 2);
853 tl_mii_sendbits(sc, phy, 5);
854 tl_mii_sendbits(sc, reg, 5);
855
856 netsio_clr(sc, TL_NETSIO_MTXEN);
857 netsio_clr(sc, TL_NETSIO_MCLK);
858 netsio_set(sc, TL_NETSIO_MCLK);
859 netsio_clr(sc, TL_NETSIO_MCLK);
860
861 err = netsio_read(sc, TL_NETSIO_MDATA);
862 netsio_set(sc, TL_NETSIO_MCLK);
863
864 /* Even if an error occurs, must still clock out the cycle. */
865 for (i = 0; i < 16; i++) {
866 val <<= 1;
867 netsio_clr(sc, TL_NETSIO_MCLK);
868 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA))
869 val |= 1;
870 netsio_set(sc, TL_NETSIO_MCLK);
871 }
872 netsio_clr(sc, TL_NETSIO_MCLK);
873 netsio_set(sc, TL_NETSIO_MCLK);
874
875 return err ? 0 : val;
876 }
877
878 void
879 tl_mii_write(device_t self, int phy, int reg, int val)
880 {
881 struct tl_softc *sc = device_private(self);
882
883 /*
884 * Write the PHY register by manually driving the MII control lines.
885 */
886
887 tl_mii_sync(sc);
888 tl_mii_sendbits(sc, MII_COMMAND_START, 2);
889 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2);
890 tl_mii_sendbits(sc, phy, 5);
891 tl_mii_sendbits(sc, reg, 5);
892 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2);
893 tl_mii_sendbits(sc, val, 16);
894
895 netsio_clr(sc, TL_NETSIO_MCLK);
896 netsio_set(sc, TL_NETSIO_MCLK);
897 }
898
899 void
900 tl_statchg(device_t self)
901 {
902 tl_softc_t *sc = device_private(self);
903 uint32_t reg;
904
905 #ifdef TLDEBUG
906 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media);
907 #endif
908
909 /*
910 * We must keep the ThunderLAN and the PHY in sync as
911 * to the status of full-duplex!
912 */
913 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd);
914 if (sc->tl_mii.mii_media_active & IFM_FDX)
915 reg |= TL_NETCOMMAND_DUPLEX;
916 else
917 reg &= ~TL_NETCOMMAND_DUPLEX;
918 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg);
919 }
920
921 /********** I2C glue **********/
922
923 static int
924 tl_i2c_acquire_bus(void *cookie, int flags)
925 {
926
927 /* private bus */
928 return 0;
929 }
930
931 static void
932 tl_i2c_release_bus(void *cookie, int flags)
933 {
934
935 /* private bus */
936 }
937
938 static int
939 tl_i2c_send_start(void *cookie, int flags)
940 {
941
942 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops);
943 }
944
945 static int
946 tl_i2c_send_stop(void *cookie, int flags)
947 {
948
949 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops);
950 }
951
952 static int
953 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
954 {
955
956 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops);
957 }
958
959 static int
960 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
961 {
962
963 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops);
964 }
965
966 static int
967 tl_i2c_write_byte(void *cookie, uint8_t val, int flags)
968 {
969
970 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops);
971 }
972
973 /********** I2C bit-bang glue **********/
974
975 static void
976 tl_i2cbb_set_bits(void *cookie, uint32_t bits)
977 {
978 struct tl_softc *sc = cookie;
979 uint8_t reg;
980
981 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
982 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits;
983 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
984 }
985
986 static void
987 tl_i2cbb_set_dir(void *cookie, uint32_t bits)
988 {
989 struct tl_softc *sc = cookie;
990 uint8_t reg;
991
992 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio);
993 reg = (reg & ~TL_NETSIO_ETXEN) | bits;
994 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg);
995 }
996
997 static uint32_t
998 tl_i2cbb_read(void *cookie)
999 {
1000
1001 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio);
1002 }
1003
1004 /********** End of I2C stuff **********/
1005
1006 static int
1007 tl_intr(void *v)
1008 {
1009 tl_softc_t *sc = v;
1010 struct ifnet *ifp = &sc->tl_if;
1011 struct Rx_list *Rx;
1012 struct Tx_list *Tx;
1013 struct mbuf *m;
1014 uint32_t int_type, int_reg;
1015 int ack = 0;
1016 int size;
1017
1018 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR);
1019 int_type = int_reg & TL_INTR_MASK;
1020 if (int_type == 0)
1021 return 0;
1022 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX)
1023 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev),
1024 int_type, int_reg);
1025 #endif
1026 /* disable interrupts */
1027 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff);
1028 switch(int_type & TL_INTR_MASK) {
1029 case TL_INTR_RxEOF:
1030 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1031 sizeof(struct tl_Rx_list) * TL_NBUF,
1032 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1033 while(le32toh(sc->active_Rx->hw_list->stat) &
1034 TL_RX_CSTAT_CPLT) {
1035 /* dequeue and requeue at end of list */
1036 ack++;
1037 Rx = sc->active_Rx;
1038 sc->active_Rx = Rx->next;
1039 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1040 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1041 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap);
1042 m = Rx->m;
1043 size = le32toh(Rx->hw_list->stat) >> 16;
1044 #ifdef TLDEBUG_RX
1045 printf("%s: RX list complete, Rx %p, size=%d\n",
1046 __func__, Rx, size);
1047 #endif
1048 if (tl_add_RxBuff(sc, Rx, m) == 0) {
1049 /*
1050 * No new mbuf, reuse the same. This means
1051 * that this packet
1052 * is lost
1053 */
1054 m = NULL;
1055 #ifdef TL_PRIV_STATS
1056 sc->ierr_nomem++;
1057 #endif
1058 #ifdef TLDEBUG
1059 printf("%s: out of mbuf, lost input packet\n",
1060 device_xname(sc->sc_dev));
1061 #endif
1062 }
1063 Rx->next = NULL;
1064 Rx->hw_list->fwd = 0;
1065 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr);
1066 sc->last_Rx->next = Rx;
1067 sc->last_Rx = Rx;
1068
1069 /* deliver packet */
1070 if (m) {
1071 if (size < sizeof(struct ether_header)) {
1072 m_freem(m);
1073 continue;
1074 }
1075 m->m_pkthdr.rcvif = ifp;
1076 m->m_pkthdr.len = m->m_len = size;
1077 #ifdef TLDEBUG_RX
1078 {
1079 struct ether_header *eh =
1080 mtod(m, struct ether_header *);
1081 printf("%s: Rx packet:\n", __func__);
1082 ether_printheader(eh);
1083 }
1084 #endif
1085 if (ifp->if_bpf)
1086 bpf_ops->bpf_mtap(ifp->if_bpf, m);
1087 (*ifp->if_input)(ifp, m);
1088 }
1089 }
1090 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1091 sizeof(struct tl_Rx_list) * TL_NBUF,
1092 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1093 #ifdef TLDEBUG_RX
1094 printf("TL_INTR_RxEOF: ack %d\n", ack);
1095 #else
1096 if (ack == 0) {
1097 printf("%s: EOF intr without anything to read !\n",
1098 device_xname(sc->sc_dev));
1099 tl_reset(sc);
1100 /* schedule reinit of the board */
1101 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1102 return 1;
1103 }
1104 #endif
1105 break;
1106 case TL_INTR_RxEOC:
1107 ack++;
1108 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0,
1109 sizeof(struct tl_Rx_list) * TL_NBUF,
1110 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1111 #ifdef TLDEBUG_RX
1112 printf("TL_INTR_RxEOC: ack %d\n", ack);
1113 #endif
1114 #ifdef DIAGNOSTIC
1115 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) {
1116 printf("%s: Rx EOC interrupt and active Tx list not "
1117 "cleared\n", device_xname(sc->sc_dev));
1118 return 0;
1119 } else
1120 #endif
1121 {
1122 /*
1123 * write address of Rx list and send Rx GO command, ack
1124 * interrupt and enable interrupts in one command
1125 */
1126 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr);
1127 TL_HR_WRITE(sc, TL_HOST_CMD,
1128 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type |
1129 HOST_CMD_ACK | HOST_CMD_IntOn);
1130 return 1;
1131 }
1132 case TL_INTR_TxEOF:
1133 case TL_INTR_TxEOC:
1134 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1135 sizeof(struct tl_Tx_list) * TL_NBUF,
1136 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1137 while ((Tx = sc->active_Tx) != NULL) {
1138 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0)
1139 break;
1140 ack++;
1141 #ifdef TLDEBUG_TX
1142 printf("TL_INTR_TxEOC: list 0x%x done\n",
1143 (int)Tx->hw_listaddr);
1144 #endif
1145 Tx->hw_list->stat = 0;
1146 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1147 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1148 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1149 m_freem(Tx->m);
1150 Tx->m = NULL;
1151 sc->active_Tx = Tx->next;
1152 if (sc->active_Tx == NULL)
1153 sc->last_Tx = NULL;
1154 Tx->next = sc->Free_Tx;
1155 sc->Free_Tx = Tx;
1156 }
1157 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1158 sizeof(struct tl_Tx_list) * TL_NBUF,
1159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1160 /* if this was an EOC, ACK immediatly */
1161 if (ack)
1162 sc->tl_if.if_flags &= ~IFF_OACTIVE;
1163 if (int_type == TL_INTR_TxEOC) {
1164 #ifdef TLDEBUG_TX
1165 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n",
1166 ack);
1167 #endif
1168 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type |
1169 HOST_CMD_ACK | HOST_CMD_IntOn);
1170 if (sc->active_Tx != NULL) {
1171 /* needs a Tx go command */
1172 TL_HR_WRITE(sc, TL_HOST_CH_PARM,
1173 sc->active_Tx->hw_listaddr);
1174 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1175 }
1176 sc->tl_if.if_timer = 0;
1177 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1178 tl_ifstart(&sc->tl_if);
1179 return 1;
1180 }
1181 #ifdef TLDEBUG
1182 else {
1183 printf("TL_INTR_TxEOF: ack %d\n", ack);
1184 }
1185 #endif
1186 sc->tl_if.if_timer = 0;
1187 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0)
1188 tl_ifstart(&sc->tl_if);
1189 break;
1190 case TL_INTR_Stat:
1191 ack++;
1192 #ifdef TLDEBUG
1193 printf("TL_INTR_Stat: ack %d\n", ack);
1194 #endif
1195 tl_read_stats(sc);
1196 break;
1197 case TL_INTR_Adc:
1198 if (int_reg & TL_INTVec_MASK) {
1199 /* adapter check conditions */
1200 printf("%s: check condition, intvect=0x%x, "
1201 "ch_param=0x%x\n", device_xname(sc->sc_dev),
1202 int_reg & TL_INTVec_MASK,
1203 TL_HR_READ(sc, TL_HOST_CH_PARM));
1204 tl_reset(sc);
1205 /* schedule reinit of the board */
1206 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp);
1207 return 1;
1208 } else {
1209 uint8_t netstat;
1210 /* Network status */
1211 netstat =
1212 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts);
1213 printf("%s: network status, NetSts=%x\n",
1214 device_xname(sc->sc_dev), netstat);
1215 /* Ack interrupts */
1216 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts,
1217 netstat);
1218 ack++;
1219 }
1220 break;
1221 default:
1222 printf("%s: unhandled interrupt code %x!\n",
1223 device_xname(sc->sc_dev), int_type);
1224 ack++;
1225 }
1226
1227 if (ack) {
1228 /* Ack the interrupt and enable interrupts */
1229 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK |
1230 HOST_CMD_IntOn);
1231 #if NRND > 0
1232 if (RND_ENABLED(&sc->rnd_source))
1233 rnd_add_uint32(&sc->rnd_source, int_reg);
1234 #endif
1235 return 1;
1236 }
1237 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */
1238 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn);
1239 return 0;
1240 }
1241
1242 static int
1243 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data)
1244 {
1245 struct tl_softc *sc = ifp->if_softc;
1246 int s, error;
1247
1248 s = splnet();
1249 error = ether_ioctl(ifp, cmd, data);
1250 if (error == ENETRESET) {
1251 if (ifp->if_flags & IFF_RUNNING)
1252 tl_addr_filter(sc);
1253 error = 0;
1254 }
1255 splx(s);
1256 return error;
1257 }
1258
1259 static void
1260 tl_ifstart(struct ifnet *ifp)
1261 {
1262 tl_softc_t *sc = ifp->if_softc;
1263 struct mbuf *mb_head;
1264 struct Tx_list *Tx;
1265 int segment, size;
1266 int again, error;
1267
1268 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
1269 return;
1270 txloop:
1271 /* If we don't have more space ... */
1272 if (sc->Free_Tx == NULL) {
1273 #ifdef TLDEBUG
1274 printf("%s: No free TX list\n", __func__);
1275 #endif
1276 sc->tl_if.if_flags |= IFF_OACTIVE;
1277 return;
1278 }
1279 /* Grab a paquet for output */
1280 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1281 if (mb_head == NULL) {
1282 #ifdef TLDEBUG_TX
1283 printf("%s: nothing to send\n", __func__);
1284 #endif
1285 return;
1286 }
1287 Tx = sc->Free_Tx;
1288 sc->Free_Tx = Tx->next;
1289 Tx->next = NULL;
1290 again = 0;
1291 /*
1292 * Go through each of the mbufs in the chain and initialize
1293 * the transmit list descriptors with the physical address
1294 * and size of the mbuf.
1295 */
1296 tbdinit:
1297 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list));
1298 Tx->m = mb_head;
1299 size = mb_head->m_pkthdr.len;
1300 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head,
1301 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX &&
1302 Tx->m_dmamap->dm_nsegs == TL_NSEG)) {
1303 struct mbuf *mn;
1304 /*
1305 * We ran out of segments, or we will. We have to recopy this
1306 * mbuf chain first.
1307 */
1308 if (error == 0)
1309 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap);
1310 if (again) {
1311 /* already copyed, can't do much more */
1312 m_freem(mb_head);
1313 goto bad;
1314 }
1315 again = 1;
1316 #ifdef TLDEBUG_TX
1317 printf("%s: need to copy mbuf\n", __func__);
1318 #endif
1319 #ifdef TL_PRIV_STATS
1320 sc->oerr_mcopy++;
1321 #endif
1322 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1323 if (mn == NULL) {
1324 m_freem(mb_head);
1325 goto bad;
1326 }
1327 if (mb_head->m_pkthdr.len > MHLEN) {
1328 MCLGET(mn, M_DONTWAIT);
1329 if ((mn->m_flags & M_EXT) == 0) {
1330 m_freem(mn);
1331 m_freem(mb_head);
1332 goto bad;
1333 }
1334 }
1335 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1336 mtod(mn, void *));
1337 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1338 m_freem(mb_head);
1339 mb_head = mn;
1340 goto tbdinit;
1341 }
1342 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) {
1343 Tx->hw_list->seg[segment].data_addr =
1344 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr);
1345 Tx->hw_list->seg[segment].data_count =
1346 htole32(Tx->m_dmamap->dm_segs[segment].ds_len);
1347 }
1348 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0,
1349 Tx->m_dmamap->dm_mapsize,
1350 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1351 /* We are at end of mbuf chain. check the size and
1352 * see if it needs to be extended
1353 */
1354 if (size < ETHER_MIN_TX) {
1355 #ifdef DIAGNOSTIC
1356 if (segment >= TL_NSEG) {
1357 panic("%s: to much segmets (%d)", __func__, segment);
1358 }
1359 #endif
1360 /*
1361 * add the nullbuf in the seg
1362 */
1363 Tx->hw_list->seg[segment].data_count =
1364 htole32(ETHER_MIN_TX - size);
1365 Tx->hw_list->seg[segment].data_addr =
1366 htole32(sc->null_dmamap->dm_segs[0].ds_addr);
1367 size = ETHER_MIN_TX;
1368 segment++;
1369 }
1370 /* The list is done, finish the list init */
1371 Tx->hw_list->seg[segment - 1].data_count |=
1372 htole32(TL_LAST_SEG);
1373 Tx->hw_list->stat = htole32((size << 16) | 0x3000);
1374 #ifdef TLDEBUG_TX
1375 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev),
1376 le32toh(Tx->hw_list->stat));
1377 #if 0
1378 for (segment = 0; segment < TL_NSEG; segment++) {
1379 printf(" seg %d addr 0x%x len 0x%x\n",
1380 segment,
1381 le32toh(Tx->hw_list->seg[segment].data_addr),
1382 le32toh(Tx->hw_list->seg[segment].data_count));
1383 }
1384 #endif
1385 #endif
1386 if (sc->active_Tx == NULL) {
1387 sc->active_Tx = sc->last_Tx = Tx;
1388 #ifdef TLDEBUG_TX
1389 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev),
1390 (int)Tx->hw_listaddr);
1391 #endif
1392 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1393 sizeof(struct tl_Tx_list) * TL_NBUF,
1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1395 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr);
1396 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO);
1397 } else {
1398 #ifdef TLDEBUG_TX
1399 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev),
1400 (int)Tx->hw_listaddr);
1401 #endif
1402 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr);
1403 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0,
1404 sizeof(struct tl_Tx_list) * TL_NBUF,
1405 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1406 sc->last_Tx->next = Tx;
1407 sc->last_Tx = Tx;
1408 #ifdef DIAGNOSTIC
1409 if (sc->last_Tx->hw_list->fwd & 0x7)
1410 printf("%s: physical addr 0x%x of list not properly "
1411 "aligned\n",
1412 device_xname(sc->sc_dev),
1413 sc->last_Rx->hw_list->fwd);
1414 #endif
1415 }
1416 /* Pass packet to bpf if there is a listener */
1417 if (ifp->if_bpf)
1418 bpf_ops->bpf_mtap(ifp->if_bpf, mb_head);
1419 /*
1420 * Set a 5 second timer just in case we don't hear from the card again.
1421 */
1422 ifp->if_timer = 5;
1423 goto txloop;
1424 bad:
1425 #ifdef TLDEBUG
1426 printf("%s: Out of mbuf, Tx pkt lost\n", __func__);
1427 #endif
1428 Tx->next = sc->Free_Tx;
1429 sc->Free_Tx = Tx;
1430 }
1431
1432 static void
1433 tl_ifwatchdog(struct ifnet *ifp)
1434 {
1435 tl_softc_t *sc = ifp->if_softc;
1436
1437 if ((ifp->if_flags & IFF_RUNNING) == 0)
1438 return;
1439 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1440 ifp->if_oerrors++;
1441 tl_init(ifp);
1442 }
1443
1444 static int
1445 tl_mediachange(struct ifnet *ifp)
1446 {
1447
1448 if (ifp->if_flags & IFF_UP)
1449 tl_init(ifp);
1450 return 0;
1451 }
1452
1453 static int
1454 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm)
1455 {
1456 struct mbuf *m;
1457 int error;
1458
1459 MGETHDR(m, M_DONTWAIT, MT_DATA);
1460 if (m != NULL) {
1461 MCLGET(m, M_DONTWAIT);
1462 if ((m->m_flags & M_EXT) == 0) {
1463 m_freem(m);
1464 if (oldm == NULL)
1465 return 0;
1466 m = oldm;
1467 m->m_data = m->m_ext.ext_buf;
1468 }
1469 } else {
1470 if (oldm == NULL)
1471 return 0;
1472 m = oldm;
1473 m->m_data = m->m_ext.ext_buf;
1474 }
1475
1476 /* (re)init the Rx_list struct */
1477
1478 Rx->m = m;
1479 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap,
1480 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) {
1481 printf("%s: bus_dmamap_load() failed (error %d) for "
1482 "tl_add_RxBuff ", device_xname(sc->sc_dev), error);
1483 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES);
1484 m_freem(m);
1485 Rx->m = NULL;
1486 return 0;
1487 }
1488 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0,
1489 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1490 /*
1491 * Move the data pointer up so that the incoming data packet
1492 * will be 32-bit aligned.
1493 */
1494 m->m_data += 2;
1495
1496 Rx->hw_list->stat =
1497 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000);
1498 Rx->hw_list->seg.data_count =
1499 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2);
1500 Rx->hw_list->seg.data_addr =
1501 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2);
1502 return (m != oldm);
1503 }
1504
1505 static void
1506 tl_ticks(void *v)
1507 {
1508 tl_softc_t *sc = v;
1509
1510 tl_read_stats(sc);
1511
1512 /* Tick the MII. */
1513 mii_tick(&sc->tl_mii);
1514
1515 /* read statistics every seconds */
1516 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc);
1517 }
1518
1519 static void
1520 tl_read_stats(tl_softc_t *sc)
1521 {
1522 uint32_t reg;
1523 int ierr_overr;
1524 int ierr_code;
1525 int ierr_crc;
1526 int oerr_underr;
1527 int oerr_deferred;
1528 int oerr_coll;
1529 int oerr_multicoll;
1530 int oerr_exesscoll;
1531 int oerr_latecoll;
1532 int oerr_carrloss;
1533 struct ifnet *ifp = &sc->tl_if;
1534
1535 reg = tl_intreg_read(sc, TL_INT_STATS_TX);
1536 ifp->if_opackets += reg & 0x00ffffff;
1537 oerr_underr = reg >> 24;
1538
1539 reg = tl_intreg_read(sc, TL_INT_STATS_RX);
1540 ifp->if_ipackets += reg & 0x00ffffff;
1541 ierr_overr = reg >> 24;
1542
1543 reg = tl_intreg_read(sc, TL_INT_STATS_FERR);
1544 ierr_crc = (reg & TL_FERR_CRC) >> 16;
1545 ierr_code = (reg & TL_FERR_CODE) >> 24;
1546 oerr_deferred = (reg & TL_FERR_DEF);
1547
1548 reg = tl_intreg_read(sc, TL_INT_STATS_COLL);
1549 oerr_multicoll = (reg & TL_COL_MULTI);
1550 oerr_coll = (reg & TL_COL_SINGLE) >> 16;
1551
1552 reg = tl_intreg_read(sc, TL_INT_LERR);
1553 oerr_exesscoll = (reg & TL_LERR_ECOLL);
1554 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8;
1555 oerr_carrloss = (reg & TL_LERR_CL) >> 16;
1556
1557
1558 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll +
1559 oerr_carrloss;
1560 ifp->if_collisions += oerr_coll + oerr_multicoll;
1561 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc;
1562
1563 if (ierr_overr)
1564 printf("%s: receiver ring buffer overrun\n",
1565 device_xname(sc->sc_dev));
1566 if (oerr_underr)
1567 printf("%s: transmit buffer underrun\n",
1568 device_xname(sc->sc_dev));
1569 #ifdef TL_PRIV_STATS
1570 sc->ierr_overr += ierr_overr;
1571 sc->ierr_code += ierr_code;
1572 sc->ierr_crc += ierr_crc;
1573 sc->oerr_underr += oerr_underr;
1574 sc->oerr_deferred += oerr_deferred;
1575 sc->oerr_coll += oerr_coll;
1576 sc->oerr_multicoll += oerr_multicoll;
1577 sc->oerr_exesscoll += oerr_exesscoll;
1578 sc->oerr_latecoll += oerr_latecoll;
1579 sc->oerr_carrloss += oerr_carrloss;
1580 #endif
1581 }
1582
1583 static void
1584 tl_addr_filter(tl_softc_t *sc)
1585 {
1586 struct ether_multistep step;
1587 struct ether_multi *enm;
1588 uint32_t hash[2] = {0, 0};
1589 int i;
1590
1591 sc->tl_if.if_flags &= ~IFF_ALLMULTI;
1592 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm);
1593 while (enm != NULL) {
1594 #ifdef TLDEBUG
1595 printf("%s: addrs %s %s\n", __func__,
1596 ether_sprintf(enm->enm_addrlo),
1597 ether_sprintf(enm->enm_addrhi));
1598 #endif
1599 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) {
1600 i = tl_multicast_hash(enm->enm_addrlo);
1601 hash[i / 32] |= 1 << (i%32);
1602 } else {
1603 hash[0] = hash[1] = 0xffffffff;
1604 sc->tl_if.if_flags |= IFF_ALLMULTI;
1605 break;
1606 }
1607 ETHER_NEXT_MULTI(step, enm);
1608 }
1609 #ifdef TLDEBUG
1610 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]);
1611 #endif
1612 tl_intreg_write(sc, TL_INT_HASH1, hash[0]);
1613 tl_intreg_write(sc, TL_INT_HASH2, hash[1]);
1614 }
1615
1616 static int
1617 tl_multicast_hash(uint8_t *a)
1618 {
1619 int hash;
1620
1621 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8)))
1622 #define xor8(a,b,c,d,e,f,g,h) \
1623 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \
1624 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1)
1625
1626 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30),
1627 DA(a,36), DA(a,42));
1628 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31),
1629 DA(a,37), DA(a,43)) << 1;
1630 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32),
1631 DA(a,38), DA(a,44)) << 2;
1632 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33),
1633 DA(a,39), DA(a,45)) << 3;
1634 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34),
1635 DA(a,40), DA(a,46)) << 4;
1636 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35),
1637 DA(a,41), DA(a,47)) << 5;
1638
1639 return hash;
1640 }
1641
1642 #if defined(TLDEBUG_RX)
1643 void
1644 ether_printheader(struct ether_header *eh)
1645 {
1646 uint8_t *c = (uint8_t *)eh;
1647 int i;
1648
1649 for (i = 0; i < sizeof(struct ether_header); i++)
1650 printf("%02x ", (u_int)c[i]);
1651 printf("\n");
1652 }
1653 #endif
1654