if_tl.c revision 1.96
1 /* $NetBSD: if_tl.c,v 1.96 2010/11/13 13:52:07 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Texas Instruments ThunderLAN ethernet controller 29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 30 * available from www.ti.com 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.96 2010/11/13 13:52:07 uebayasi Exp $"); 35 36 #undef TLDEBUG 37 #define TL_PRIV_STATS 38 #undef TLDEBUG_RX 39 #undef TLDEBUG_TX 40 #undef TLDEBUG_ADDR 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 68 #include "rnd.h" 69 #if NRND > 0 70 #include <sys/rnd.h> 71 #endif 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #endif 79 80 81 #if defined(__NetBSD__) 82 #include <net/if_ether.h> 83 #if defined(INET) 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #include <sys/bus.h> 88 #include <sys/intr.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 #include <dev/pci/pcidevs.h> 93 94 #include <dev/i2c/i2cvar.h> 95 #include <dev/i2c/i2c_bitbang.h> 96 #include <dev/i2c/at24cxxvar.h> 97 98 #include <dev/mii/mii.h> 99 #include <dev/mii/miivar.h> 100 101 #include <dev/mii/tlphyvar.h> 102 103 #include <dev/pci/if_tlregs.h> 104 #include <dev/pci/if_tlvar.h> 105 #endif /* __NetBSD__ */ 106 107 /* number of transmit/receive buffers */ 108 #ifndef TL_NBUF 109 #define TL_NBUF 32 110 #endif 111 112 static int tl_pci_match(device_t, cfdata_t, void *); 113 static void tl_pci_attach(device_t, device_t, void *); 114 static int tl_intr(void *); 115 116 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 117 static int tl_mediachange(struct ifnet *); 118 static void tl_ifwatchdog(struct ifnet *); 119 static bool tl_shutdown(device_t, int); 120 121 static void tl_ifstart(struct ifnet *); 122 static void tl_reset(tl_softc_t *); 123 static int tl_init(struct ifnet *); 124 static void tl_stop(struct ifnet *, int); 125 static void tl_restart(void *); 126 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 127 static void tl_read_stats(tl_softc_t *); 128 static void tl_ticks(void *); 129 static int tl_multicast_hash(uint8_t *); 130 static void tl_addr_filter(tl_softc_t *); 131 132 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 133 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 134 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 135 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 136 137 void tl_mii_sync(struct tl_softc *); 138 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 139 140 141 #if defined(TLDEBUG_RX) 142 static void ether_printheader(struct ether_header *); 143 #endif 144 145 int tl_mii_read(device_t, int, int); 146 void tl_mii_write(device_t, int, int, int); 147 148 void tl_statchg(device_t); 149 150 /* I2C glue */ 151 static int tl_i2c_acquire_bus(void *, int); 152 static void tl_i2c_release_bus(void *, int); 153 static int tl_i2c_send_start(void *, int); 154 static int tl_i2c_send_stop(void *, int); 155 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 156 static int tl_i2c_read_byte(void *, uint8_t *, int); 157 static int tl_i2c_write_byte(void *, uint8_t, int); 158 159 /* I2C bit-bang glue */ 160 static void tl_i2cbb_set_bits(void *, uint32_t); 161 static void tl_i2cbb_set_dir(void *, uint32_t); 162 static uint32_t tl_i2cbb_read(void *); 163 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 164 tl_i2cbb_set_bits, 165 tl_i2cbb_set_dir, 166 tl_i2cbb_read, 167 { 168 TL_NETSIO_EDATA, /* SDA */ 169 TL_NETSIO_ECLOCK, /* SCL */ 170 TL_NETSIO_ETXEN, /* SDA is output */ 171 0, /* SDA is input */ 172 } 173 }; 174 175 static inline void netsio_clr(tl_softc_t *, uint8_t); 176 static inline void netsio_set(tl_softc_t *, uint8_t); 177 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 178 179 static inline void 180 netsio_clr(tl_softc_t *sc, uint8_t bits) 181 { 182 183 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 184 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 185 } 186 187 static inline void 188 netsio_set(tl_softc_t *sc, uint8_t bits) 189 { 190 191 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 192 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 193 } 194 195 static inline uint8_t 196 netsio_read(tl_softc_t *sc, uint8_t bits) 197 { 198 199 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 200 } 201 202 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 203 tl_pci_match, tl_pci_attach, NULL, NULL); 204 205 static const struct tl_product_desc tl_compaq_products[] = { 206 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 207 "Compaq Netelligent 10/100 TX" }, 208 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 209 "Integrated Compaq Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 211 "Compaq Netelligent 10 T" }, 212 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 213 "Compaq Netelligent 10 T/2 UTP/Coax" }, 214 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 215 "Compaq Integrated NetFlex 3/P" }, 216 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 217 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 218 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 219 "Compaq Dual Port Netelligent 10/100 TX" }, 220 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 221 "Compaq Deskpro 4000 5233MMX" }, 222 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 223 "Compaq NetFlex 3/P w/ BNC" }, 224 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 225 "Compaq NetFlex 3/P" }, 226 { 0, 0, NULL }, 227 }; 228 229 static const struct tl_product_desc tl_ti_products[] = { 230 /* 231 * Built-in Ethernet on the TI TravelMate 5000 232 * docking station; better product description? 233 */ 234 { PCI_PRODUCT_TI_TLAN, 0, 235 "Texas Instruments ThunderLAN" }, 236 { 0, 0, NULL }, 237 }; 238 239 struct tl_vendor_desc { 240 uint32_t tv_vendor; 241 const struct tl_product_desc *tv_products; 242 }; 243 244 const struct tl_vendor_desc tl_vendors[] = { 245 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 246 { PCI_VENDOR_TI, tl_ti_products }, 247 { 0, NULL }, 248 }; 249 250 static const struct tl_product_desc *tl_lookup_product(uint32_t); 251 252 static const struct tl_product_desc * 253 tl_lookup_product(uint32_t id) 254 { 255 const struct tl_product_desc *tp; 256 const struct tl_vendor_desc *tv; 257 258 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 259 if (PCI_VENDOR(id) == tv->tv_vendor) 260 break; 261 262 if ((tp = tv->tv_products) == NULL) 263 return NULL; 264 265 for (; tp->tp_desc != NULL; tp++) 266 if (PCI_PRODUCT(id) == tp->tp_product) 267 break; 268 269 if (tp->tp_desc == NULL) 270 return NULL; 271 272 return tp; 273 } 274 275 static int 276 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 277 { 278 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 279 280 if (tl_lookup_product(pa->pa_id) != NULL) 281 return 1; 282 283 return 0; 284 } 285 286 static void 287 tl_pci_attach(device_t parent, device_t self, void *aux) 288 { 289 tl_softc_t *sc = device_private(self); 290 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 291 const struct tl_product_desc *tp; 292 struct ifnet * const ifp = &sc->tl_if; 293 bus_space_tag_t iot, memt; 294 bus_space_handle_t ioh, memh; 295 pci_intr_handle_t intrhandle; 296 const char *intrstr; 297 int ioh_valid, memh_valid; 298 int reg_io, reg_mem; 299 pcireg_t reg10, reg14; 300 pcireg_t csr; 301 302 sc->sc_dev = self; 303 aprint_normal("\n"); 304 305 callout_init(&sc->tl_tick_ch, 0); 306 callout_init(&sc->tl_restart_ch, 0); 307 308 tp = tl_lookup_product(pa->pa_id); 309 if (tp == NULL) 310 panic("%s: impossible", __func__); 311 sc->tl_product = tp; 312 313 /* 314 * Map the card space. First we have to find the I/O and MEM 315 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 316 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 317 * The ThunderLAN manual is not consistent about this either (there 318 * are both cases in code examples). 319 */ 320 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 321 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 322 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 323 reg_io = 0x10; 324 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 325 reg_io = 0x14; 326 else 327 reg_io = 0; 328 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 329 reg_mem = 0x10; 330 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 331 reg_mem = 0x14; 332 else 333 reg_mem = 0; 334 335 if (reg_io != 0) 336 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 337 0, &iot, &ioh, NULL, NULL) == 0); 338 else 339 ioh_valid = 0; 340 if (reg_mem != 0) 341 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 342 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 343 0, &memt, &memh, NULL, NULL) == 0); 344 else 345 memh_valid = 0; 346 347 if (ioh_valid) { 348 sc->tl_bustag = iot; 349 sc->tl_bushandle = ioh; 350 } else if (memh_valid) { 351 sc->tl_bustag = memt; 352 sc->tl_bushandle = memh; 353 } else { 354 aprint_error_dev(self, "unable to map device registers\n"); 355 return; 356 } 357 sc->tl_dmatag = pa->pa_dmat; 358 359 /* Enable the device. */ 360 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 361 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 362 csr | PCI_COMMAND_MASTER_ENABLE); 363 364 aprint_normal_dev(self, "%s\n", tp->tp_desc); 365 366 tl_reset(sc); 367 368 /* fill in the i2c tag */ 369 sc->sc_i2c.ic_cookie = sc; 370 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 371 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 372 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 373 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 374 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 375 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 376 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 377 378 #ifdef TLDEBUG 379 aprint_debug_dev(self, "default values of INTreg: 0x%x\n", 380 tl_intreg_read(sc, TL_INT_Defaults)); 381 #endif 382 383 /* read mac addr */ 384 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 385 sc->tl_enaddr, ETHER_ADDR_LEN)) { 386 aprint_error_dev(self, "error reading Ethernet address\n"); 387 return; 388 } 389 aprint_normal_dev(self, "Ethernet address %s\n", 390 ether_sprintf(sc->tl_enaddr)); 391 392 /* Map and establish interrupts */ 393 if (pci_intr_map(pa, &intrhandle)) { 394 aprint_error_dev(self, "couldn't map interrupt\n"); 395 return; 396 } 397 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 398 sc->tl_if.if_softc = sc; 399 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 400 tl_intr, sc); 401 if (sc->tl_ih == NULL) { 402 aprint_error_dev(self, "couldn't establish interrupt"); 403 if (intrstr != NULL) 404 aprint_error(" at %s", intrstr); 405 aprint_error("\n"); 406 return; 407 } 408 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 409 410 /* init these pointers, so that tl_shutdown won't try to read them */ 411 sc->Rx_list = NULL; 412 sc->Tx_list = NULL; 413 414 /* allocate DMA-safe memory for control structs */ 415 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 416 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 417 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 418 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 419 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 420 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 421 return; 422 } 423 424 /* 425 * Initialize our media structures and probe the MII. 426 * 427 * Note that we don't care about the media instance. We 428 * are expecting to have multiple PHYs on the 10/100 cards, 429 * and on those cards we exclude the internal PHY from providing 430 * 10baseT. By ignoring the instance, it allows us to not have 431 * to specify it on the command line when switching media. 432 */ 433 sc->tl_mii.mii_ifp = ifp; 434 sc->tl_mii.mii_readreg = tl_mii_read; 435 sc->tl_mii.mii_writereg = tl_mii_write; 436 sc->tl_mii.mii_statchg = tl_statchg; 437 sc->tl_ec.ec_mii = &sc->tl_mii; 438 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 439 ether_mediastatus); 440 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 441 MII_OFFSET_ANY, 0); 442 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 443 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 444 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 445 } else 446 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 447 448 /* 449 * We can support 802.1Q VLAN-sized frames. 450 */ 451 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 452 453 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 454 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 455 ifp->if_ioctl = tl_ifioctl; 456 ifp->if_start = tl_ifstart; 457 ifp->if_watchdog = tl_ifwatchdog; 458 ifp->if_init = tl_init; 459 ifp->if_stop = tl_stop; 460 ifp->if_timer = 0; 461 IFQ_SET_READY(&ifp->if_snd); 462 if_attach(ifp); 463 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 464 465 /* 466 * Add shutdown hook so that DMA is disabled prior to reboot. 467 * Not doing reboot before the driver initializes. 468 */ 469 if (pmf_device_register1(self, NULL, NULL, tl_shutdown)) 470 pmf_class_network_register(self, ifp); 471 else 472 aprint_error_dev(self, "couldn't establish power handler\n"); 473 474 #if NRND > 0 475 rnd_attach_source(&sc->rnd_source, device_xname(self), 476 RND_TYPE_NET, 0); 477 #endif 478 } 479 480 static void 481 tl_reset(tl_softc_t *sc) 482 { 483 int i; 484 485 /* read stats */ 486 if (sc->tl_if.if_flags & IFF_RUNNING) { 487 callout_stop(&sc->tl_tick_ch); 488 tl_read_stats(sc); 489 } 490 /* Reset adapter */ 491 TL_HR_WRITE(sc, TL_HOST_CMD, 492 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 493 DELAY(100000); 494 /* Disable interrupts */ 495 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 496 /* setup aregs & hash */ 497 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 498 tl_intreg_write(sc, i, 0); 499 #ifdef TLDEBUG_ADDR 500 printf("Areg & hash registers: \n"); 501 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 502 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 503 #endif 504 /* Setup NetConfig */ 505 tl_intreg_write(sc, TL_INT_NetConfig, 506 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 507 /* Bsize: accept default */ 508 /* TX commit in Acommit: accept default */ 509 /* Load Ld_tmr and Ld_thr */ 510 /* Ld_tmr = 3 */ 511 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 512 /* Ld_thr = 0 */ 513 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 514 /* Unreset MII */ 515 netsio_set(sc, TL_NETSIO_NMRST); 516 DELAY(100000); 517 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 518 } 519 520 static bool 521 tl_shutdown(device_t self, int howto) 522 { 523 tl_softc_t *sc = device_private(self); 524 struct ifnet *ifp = &sc->tl_if; 525 526 tl_stop(ifp, 1); 527 528 return true; 529 } 530 531 static void 532 tl_stop(struct ifnet *ifp, int disable) 533 { 534 tl_softc_t *sc = ifp->if_softc; 535 struct Tx_list *Tx; 536 int i; 537 538 if ((ifp->if_flags & IFF_RUNNING) == 0) 539 return; 540 /* disable interrupts */ 541 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 542 /* stop TX and RX channels */ 543 TL_HR_WRITE(sc, TL_HOST_CMD, 544 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 545 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 546 DELAY(100000); 547 548 /* stop statistics reading loop, read stats */ 549 callout_stop(&sc->tl_tick_ch); 550 tl_read_stats(sc); 551 552 /* Down the MII. */ 553 mii_down(&sc->tl_mii); 554 555 /* deallocate memory allocations */ 556 if (sc->Rx_list) { 557 for (i = 0; i< TL_NBUF; i++) { 558 if (sc->Rx_list[i].m) { 559 bus_dmamap_unload(sc->tl_dmatag, 560 sc->Rx_list[i].m_dmamap); 561 m_freem(sc->Rx_list[i].m); 562 } 563 bus_dmamap_destroy(sc->tl_dmatag, 564 sc->Rx_list[i].m_dmamap); 565 sc->Rx_list[i].m = NULL; 566 } 567 free(sc->Rx_list, M_DEVBUF); 568 sc->Rx_list = NULL; 569 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 570 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 571 sc->hw_Rx_list = NULL; 572 while ((Tx = sc->active_Tx) != NULL) { 573 Tx->hw_list->stat = 0; 574 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 575 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 576 m_freem(Tx->m); 577 sc->active_Tx = Tx->next; 578 Tx->next = sc->Free_Tx; 579 sc->Free_Tx = Tx; 580 } 581 sc->last_Tx = NULL; 582 free(sc->Tx_list, M_DEVBUF); 583 sc->Tx_list = NULL; 584 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 585 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 586 sc->hw_Tx_list = NULL; 587 } 588 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 589 ifp->if_timer = 0; 590 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 591 } 592 593 static void 594 tl_restart(void *v) 595 { 596 597 tl_init(v); 598 } 599 600 static int 601 tl_init(struct ifnet *ifp) 602 { 603 tl_softc_t *sc = ifp->if_softc; 604 int i, s, error; 605 bus_size_t boundary; 606 prop_number_t prop_boundary; 607 const char *errstring; 608 char *nullbuf; 609 610 s = splnet(); 611 /* cancel any pending IO */ 612 tl_stop(ifp, 1); 613 tl_reset(sc); 614 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 615 splx(s); 616 return 0; 617 } 618 /* Set various register to reasonable value */ 619 /* setup NetCmd in promisc mode if needed */ 620 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 621 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 622 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 623 /* Max receive size : MCLBYTES */ 624 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 625 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 626 (MCLBYTES >> 8) & 0xff); 627 628 /* init MAC addr */ 629 for (i = 0; i < ETHER_ADDR_LEN; i++) 630 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 631 /* add multicast filters */ 632 tl_addr_filter(sc); 633 #ifdef TLDEBUG_ADDR 634 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 635 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 636 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 637 #endif 638 639 /* Pre-allocate receivers mbuf, make the lists */ 640 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 641 M_NOWAIT|M_ZERO); 642 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 643 M_NOWAIT|M_ZERO); 644 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 645 errstring = "out of memory for lists"; 646 error = ENOMEM; 647 goto bad; 648 } 649 650 /* 651 * Some boards (Set Engineering GFE) do not permit DMA transfers 652 * across page boundaries. 653 */ 654 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 655 "tl-dma-page-boundary"); 656 if (prop_boundary != NULL) { 657 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 658 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 659 } else { 660 boundary = 0; 661 } 662 663 error = bus_dmamap_create(sc->tl_dmatag, 664 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 665 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 666 &sc->Rx_dmamap); 667 if (error == 0) 668 error = bus_dmamap_create(sc->tl_dmatag, 669 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 670 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 671 BUS_DMA_WAITOK, &sc->Tx_dmamap); 672 if (error == 0) 673 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 674 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 675 &sc->null_dmamap); 676 if (error) { 677 errstring = "can't allocate DMA maps for lists"; 678 goto bad; 679 } 680 memset(sc->ctrl, 0, PAGE_SIZE); 681 sc->hw_Rx_list = (void *)sc->ctrl; 682 sc->hw_Tx_list = 683 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 684 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 685 sizeof(struct tl_Tx_list) * TL_NBUF; 686 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 687 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 688 BUS_DMA_WAITOK); 689 if (error == 0) 690 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 691 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 692 BUS_DMA_WAITOK); 693 if (error == 0) 694 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 695 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 696 if (error) { 697 errstring = "can't DMA map DMA memory for lists"; 698 goto bad; 699 } 700 for (i = 0; i < TL_NBUF; i++) { 701 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 702 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 703 &sc->Rx_list[i].m_dmamap); 704 if (error == 0) { 705 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 706 TL_NSEG, MCLBYTES, boundary, 707 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 708 &sc->Tx_list[i].m_dmamap); 709 } 710 if (error) { 711 errstring = "can't allocate DMA maps for mbufs"; 712 goto bad; 713 } 714 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 715 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 716 + sizeof(struct tl_Rx_list) * i; 717 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 718 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 719 + sizeof(struct tl_Tx_list) * i; 720 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 721 errstring = "out of mbuf for receive list"; 722 error = ENOMEM; 723 goto bad; 724 } 725 if (i > 0) { /* chain the list */ 726 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 727 sc->hw_Rx_list[i - 1].fwd = 728 htole32(sc->Rx_list[i].hw_listaddr); 729 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 730 } 731 } 732 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 733 sc->Rx_list[TL_NBUF - 1].next = NULL; 734 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 735 sc->Tx_list[TL_NBUF - 1].next = NULL; 736 737 sc->active_Rx = &sc->Rx_list[0]; 738 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 739 sc->active_Tx = sc->last_Tx = NULL; 740 sc->Free_Tx = &sc->Tx_list[0]; 741 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 742 sizeof(struct tl_Rx_list) * TL_NBUF, 743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 745 sizeof(struct tl_Tx_list) * TL_NBUF, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 748 BUS_DMASYNC_PREWRITE); 749 750 /* set media */ 751 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 752 error = 0; 753 else if (error != 0) { 754 errstring = "could not set media"; 755 goto bad; 756 } 757 758 /* start ticks calls */ 759 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 760 /* write address of Rx list and enable interrupts */ 761 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 762 TL_HR_WRITE(sc, TL_HOST_CMD, 763 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 764 sc->tl_if.if_flags |= IFF_RUNNING; 765 sc->tl_if.if_flags &= ~IFF_OACTIVE; 766 splx(s); 767 return 0; 768 bad: 769 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 770 splx(s); 771 return error; 772 } 773 774 775 static uint32_t 776 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 777 { 778 779 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 780 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 781 } 782 783 static uint8_t 784 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 785 { 786 787 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 788 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 789 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 790 } 791 792 static void 793 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 794 { 795 796 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 797 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 798 } 799 800 static void 801 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 802 { 803 804 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 805 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 806 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 807 } 808 809 void 810 tl_mii_sync(struct tl_softc *sc) 811 { 812 int i; 813 814 netsio_clr(sc, TL_NETSIO_MTXEN); 815 for (i = 0; i < 32; i++) { 816 netsio_clr(sc, TL_NETSIO_MCLK); 817 netsio_set(sc, TL_NETSIO_MCLK); 818 } 819 } 820 821 void 822 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 823 { 824 int i; 825 826 netsio_set(sc, TL_NETSIO_MTXEN); 827 for (i = 1 << (nbits - 1); i; i = i >> 1) { 828 netsio_clr(sc, TL_NETSIO_MCLK); 829 netsio_read(sc, TL_NETSIO_MCLK); 830 if (data & i) 831 netsio_set(sc, TL_NETSIO_MDATA); 832 else 833 netsio_clr(sc, TL_NETSIO_MDATA); 834 netsio_set(sc, TL_NETSIO_MCLK); 835 netsio_read(sc, TL_NETSIO_MCLK); 836 } 837 } 838 839 int 840 tl_mii_read(device_t self, int phy, int reg) 841 { 842 struct tl_softc *sc = device_private(self); 843 int val = 0, i, err; 844 845 /* 846 * Read the PHY register by manually driving the MII control lines. 847 */ 848 849 tl_mii_sync(sc); 850 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 851 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 852 tl_mii_sendbits(sc, phy, 5); 853 tl_mii_sendbits(sc, reg, 5); 854 855 netsio_clr(sc, TL_NETSIO_MTXEN); 856 netsio_clr(sc, TL_NETSIO_MCLK); 857 netsio_set(sc, TL_NETSIO_MCLK); 858 netsio_clr(sc, TL_NETSIO_MCLK); 859 860 err = netsio_read(sc, TL_NETSIO_MDATA); 861 netsio_set(sc, TL_NETSIO_MCLK); 862 863 /* Even if an error occurs, must still clock out the cycle. */ 864 for (i = 0; i < 16; i++) { 865 val <<= 1; 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 868 val |= 1; 869 netsio_set(sc, TL_NETSIO_MCLK); 870 } 871 netsio_clr(sc, TL_NETSIO_MCLK); 872 netsio_set(sc, TL_NETSIO_MCLK); 873 874 return err ? 0 : val; 875 } 876 877 void 878 tl_mii_write(device_t self, int phy, int reg, int val) 879 { 880 struct tl_softc *sc = device_private(self); 881 882 /* 883 * Write the PHY register by manually driving the MII control lines. 884 */ 885 886 tl_mii_sync(sc); 887 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 888 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 889 tl_mii_sendbits(sc, phy, 5); 890 tl_mii_sendbits(sc, reg, 5); 891 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 892 tl_mii_sendbits(sc, val, 16); 893 894 netsio_clr(sc, TL_NETSIO_MCLK); 895 netsio_set(sc, TL_NETSIO_MCLK); 896 } 897 898 void 899 tl_statchg(device_t self) 900 { 901 tl_softc_t *sc = device_private(self); 902 uint32_t reg; 903 904 #ifdef TLDEBUG 905 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 906 #endif 907 908 /* 909 * We must keep the ThunderLAN and the PHY in sync as 910 * to the status of full-duplex! 911 */ 912 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 913 if (sc->tl_mii.mii_media_active & IFM_FDX) 914 reg |= TL_NETCOMMAND_DUPLEX; 915 else 916 reg &= ~TL_NETCOMMAND_DUPLEX; 917 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 918 } 919 920 /********** I2C glue **********/ 921 922 static int 923 tl_i2c_acquire_bus(void *cookie, int flags) 924 { 925 926 /* private bus */ 927 return 0; 928 } 929 930 static void 931 tl_i2c_release_bus(void *cookie, int flags) 932 { 933 934 /* private bus */ 935 } 936 937 static int 938 tl_i2c_send_start(void *cookie, int flags) 939 { 940 941 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 942 } 943 944 static int 945 tl_i2c_send_stop(void *cookie, int flags) 946 { 947 948 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 949 } 950 951 static int 952 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 953 { 954 955 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 956 } 957 958 static int 959 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 960 { 961 962 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 963 } 964 965 static int 966 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 967 { 968 969 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 970 } 971 972 /********** I2C bit-bang glue **********/ 973 974 static void 975 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 976 { 977 struct tl_softc *sc = cookie; 978 uint8_t reg; 979 980 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 981 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 982 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 983 } 984 985 static void 986 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 987 { 988 struct tl_softc *sc = cookie; 989 uint8_t reg; 990 991 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 992 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 993 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 994 } 995 996 static uint32_t 997 tl_i2cbb_read(void *cookie) 998 { 999 1000 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 1001 } 1002 1003 /********** End of I2C stuff **********/ 1004 1005 static int 1006 tl_intr(void *v) 1007 { 1008 tl_softc_t *sc = v; 1009 struct ifnet *ifp = &sc->tl_if; 1010 struct Rx_list *Rx; 1011 struct Tx_list *Tx; 1012 struct mbuf *m; 1013 uint32_t int_type, int_reg; 1014 int ack = 0; 1015 int size; 1016 1017 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1018 int_type = int_reg & TL_INTR_MASK; 1019 if (int_type == 0) 1020 return 0; 1021 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1022 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev), 1023 int_type, int_reg); 1024 #endif 1025 /* disable interrupts */ 1026 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1027 switch(int_type & TL_INTR_MASK) { 1028 case TL_INTR_RxEOF: 1029 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1030 sizeof(struct tl_Rx_list) * TL_NBUF, 1031 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1032 while(le32toh(sc->active_Rx->hw_list->stat) & 1033 TL_RX_CSTAT_CPLT) { 1034 /* dequeue and requeue at end of list */ 1035 ack++; 1036 Rx = sc->active_Rx; 1037 sc->active_Rx = Rx->next; 1038 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1039 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1040 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1041 m = Rx->m; 1042 size = le32toh(Rx->hw_list->stat) >> 16; 1043 #ifdef TLDEBUG_RX 1044 printf("%s: RX list complete, Rx %p, size=%d\n", 1045 __func__, Rx, size); 1046 #endif 1047 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1048 /* 1049 * No new mbuf, reuse the same. This means 1050 * that this packet 1051 * is lost 1052 */ 1053 m = NULL; 1054 #ifdef TL_PRIV_STATS 1055 sc->ierr_nomem++; 1056 #endif 1057 #ifdef TLDEBUG 1058 printf("%s: out of mbuf, lost input packet\n", 1059 device_xname(sc->sc_dev)); 1060 #endif 1061 } 1062 Rx->next = NULL; 1063 Rx->hw_list->fwd = 0; 1064 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1065 sc->last_Rx->next = Rx; 1066 sc->last_Rx = Rx; 1067 1068 /* deliver packet */ 1069 if (m) { 1070 if (size < sizeof(struct ether_header)) { 1071 m_freem(m); 1072 continue; 1073 } 1074 m->m_pkthdr.rcvif = ifp; 1075 m->m_pkthdr.len = m->m_len = size; 1076 #ifdef TLDEBUG_RX 1077 { 1078 struct ether_header *eh = 1079 mtod(m, struct ether_header *); 1080 printf("%s: Rx packet:\n", __func__); 1081 ether_printheader(eh); 1082 } 1083 #endif 1084 bpf_mtap(ifp, m); 1085 (*ifp->if_input)(ifp, m); 1086 } 1087 } 1088 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1089 sizeof(struct tl_Rx_list) * TL_NBUF, 1090 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1091 #ifdef TLDEBUG_RX 1092 printf("TL_INTR_RxEOF: ack %d\n", ack); 1093 #else 1094 if (ack == 0) { 1095 printf("%s: EOF intr without anything to read !\n", 1096 device_xname(sc->sc_dev)); 1097 tl_reset(sc); 1098 /* schedule reinit of the board */ 1099 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1100 return 1; 1101 } 1102 #endif 1103 break; 1104 case TL_INTR_RxEOC: 1105 ack++; 1106 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1107 sizeof(struct tl_Rx_list) * TL_NBUF, 1108 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1109 #ifdef TLDEBUG_RX 1110 printf("TL_INTR_RxEOC: ack %d\n", ack); 1111 #endif 1112 #ifdef DIAGNOSTIC 1113 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1114 printf("%s: Rx EOC interrupt and active Tx list not " 1115 "cleared\n", device_xname(sc->sc_dev)); 1116 return 0; 1117 } else 1118 #endif 1119 { 1120 /* 1121 * write address of Rx list and send Rx GO command, ack 1122 * interrupt and enable interrupts in one command 1123 */ 1124 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1125 TL_HR_WRITE(sc, TL_HOST_CMD, 1126 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1127 HOST_CMD_ACK | HOST_CMD_IntOn); 1128 return 1; 1129 } 1130 case TL_INTR_TxEOF: 1131 case TL_INTR_TxEOC: 1132 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1133 sizeof(struct tl_Tx_list) * TL_NBUF, 1134 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1135 while ((Tx = sc->active_Tx) != NULL) { 1136 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1137 break; 1138 ack++; 1139 #ifdef TLDEBUG_TX 1140 printf("TL_INTR_TxEOC: list 0x%x done\n", 1141 (int)Tx->hw_listaddr); 1142 #endif 1143 Tx->hw_list->stat = 0; 1144 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1145 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1146 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1147 m_freem(Tx->m); 1148 Tx->m = NULL; 1149 sc->active_Tx = Tx->next; 1150 if (sc->active_Tx == NULL) 1151 sc->last_Tx = NULL; 1152 Tx->next = sc->Free_Tx; 1153 sc->Free_Tx = Tx; 1154 } 1155 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1156 sizeof(struct tl_Tx_list) * TL_NBUF, 1157 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1158 /* if this was an EOC, ACK immediatly */ 1159 if (ack) 1160 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1161 if (int_type == TL_INTR_TxEOC) { 1162 #ifdef TLDEBUG_TX 1163 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1164 ack); 1165 #endif 1166 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1167 HOST_CMD_ACK | HOST_CMD_IntOn); 1168 if (sc->active_Tx != NULL) { 1169 /* needs a Tx go command */ 1170 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1171 sc->active_Tx->hw_listaddr); 1172 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1173 } 1174 sc->tl_if.if_timer = 0; 1175 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1176 tl_ifstart(&sc->tl_if); 1177 return 1; 1178 } 1179 #ifdef TLDEBUG 1180 else { 1181 printf("TL_INTR_TxEOF: ack %d\n", ack); 1182 } 1183 #endif 1184 sc->tl_if.if_timer = 0; 1185 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1186 tl_ifstart(&sc->tl_if); 1187 break; 1188 case TL_INTR_Stat: 1189 ack++; 1190 #ifdef TLDEBUG 1191 printf("TL_INTR_Stat: ack %d\n", ack); 1192 #endif 1193 tl_read_stats(sc); 1194 break; 1195 case TL_INTR_Adc: 1196 if (int_reg & TL_INTVec_MASK) { 1197 /* adapter check conditions */ 1198 printf("%s: check condition, intvect=0x%x, " 1199 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1200 int_reg & TL_INTVec_MASK, 1201 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1202 tl_reset(sc); 1203 /* schedule reinit of the board */ 1204 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1205 return 1; 1206 } else { 1207 uint8_t netstat; 1208 /* Network status */ 1209 netstat = 1210 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1211 printf("%s: network status, NetSts=%x\n", 1212 device_xname(sc->sc_dev), netstat); 1213 /* Ack interrupts */ 1214 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1215 netstat); 1216 ack++; 1217 } 1218 break; 1219 default: 1220 printf("%s: unhandled interrupt code %x!\n", 1221 device_xname(sc->sc_dev), int_type); 1222 ack++; 1223 } 1224 1225 if (ack) { 1226 /* Ack the interrupt and enable interrupts */ 1227 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1228 HOST_CMD_IntOn); 1229 #if NRND > 0 1230 if (RND_ENABLED(&sc->rnd_source)) 1231 rnd_add_uint32(&sc->rnd_source, int_reg); 1232 #endif 1233 return 1; 1234 } 1235 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1236 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1237 return 0; 1238 } 1239 1240 static int 1241 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1242 { 1243 struct tl_softc *sc = ifp->if_softc; 1244 int s, error; 1245 1246 s = splnet(); 1247 error = ether_ioctl(ifp, cmd, data); 1248 if (error == ENETRESET) { 1249 if (ifp->if_flags & IFF_RUNNING) 1250 tl_addr_filter(sc); 1251 error = 0; 1252 } 1253 splx(s); 1254 return error; 1255 } 1256 1257 static void 1258 tl_ifstart(struct ifnet *ifp) 1259 { 1260 tl_softc_t *sc = ifp->if_softc; 1261 struct mbuf *mb_head; 1262 struct Tx_list *Tx; 1263 int segment, size; 1264 int again, error; 1265 1266 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1267 return; 1268 txloop: 1269 /* If we don't have more space ... */ 1270 if (sc->Free_Tx == NULL) { 1271 #ifdef TLDEBUG 1272 printf("%s: No free TX list\n", __func__); 1273 #endif 1274 sc->tl_if.if_flags |= IFF_OACTIVE; 1275 return; 1276 } 1277 /* Grab a paquet for output */ 1278 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1279 if (mb_head == NULL) { 1280 #ifdef TLDEBUG_TX 1281 printf("%s: nothing to send\n", __func__); 1282 #endif 1283 return; 1284 } 1285 Tx = sc->Free_Tx; 1286 sc->Free_Tx = Tx->next; 1287 Tx->next = NULL; 1288 again = 0; 1289 /* 1290 * Go through each of the mbufs in the chain and initialize 1291 * the transmit list descriptors with the physical address 1292 * and size of the mbuf. 1293 */ 1294 tbdinit: 1295 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1296 Tx->m = mb_head; 1297 size = mb_head->m_pkthdr.len; 1298 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1299 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1300 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1301 struct mbuf *mn; 1302 /* 1303 * We ran out of segments, or we will. We have to recopy this 1304 * mbuf chain first. 1305 */ 1306 if (error == 0) 1307 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1308 if (again) { 1309 /* already copyed, can't do much more */ 1310 m_freem(mb_head); 1311 goto bad; 1312 } 1313 again = 1; 1314 #ifdef TLDEBUG_TX 1315 printf("%s: need to copy mbuf\n", __func__); 1316 #endif 1317 #ifdef TL_PRIV_STATS 1318 sc->oerr_mcopy++; 1319 #endif 1320 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1321 if (mn == NULL) { 1322 m_freem(mb_head); 1323 goto bad; 1324 } 1325 if (mb_head->m_pkthdr.len > MHLEN) { 1326 MCLGET(mn, M_DONTWAIT); 1327 if ((mn->m_flags & M_EXT) == 0) { 1328 m_freem(mn); 1329 m_freem(mb_head); 1330 goto bad; 1331 } 1332 } 1333 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1334 mtod(mn, void *)); 1335 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1336 m_freem(mb_head); 1337 mb_head = mn; 1338 goto tbdinit; 1339 } 1340 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1341 Tx->hw_list->seg[segment].data_addr = 1342 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1343 Tx->hw_list->seg[segment].data_count = 1344 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1345 } 1346 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1347 Tx->m_dmamap->dm_mapsize, 1348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1349 /* We are at end of mbuf chain. check the size and 1350 * see if it needs to be extended 1351 */ 1352 if (size < ETHER_MIN_TX) { 1353 #ifdef DIAGNOSTIC 1354 if (segment >= TL_NSEG) { 1355 panic("%s: to much segmets (%d)", __func__, segment); 1356 } 1357 #endif 1358 /* 1359 * add the nullbuf in the seg 1360 */ 1361 Tx->hw_list->seg[segment].data_count = 1362 htole32(ETHER_MIN_TX - size); 1363 Tx->hw_list->seg[segment].data_addr = 1364 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1365 size = ETHER_MIN_TX; 1366 segment++; 1367 } 1368 /* The list is done, finish the list init */ 1369 Tx->hw_list->seg[segment - 1].data_count |= 1370 htole32(TL_LAST_SEG); 1371 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1372 #ifdef TLDEBUG_TX 1373 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1374 le32toh(Tx->hw_list->stat)); 1375 #if 0 1376 for (segment = 0; segment < TL_NSEG; segment++) { 1377 printf(" seg %d addr 0x%x len 0x%x\n", 1378 segment, 1379 le32toh(Tx->hw_list->seg[segment].data_addr), 1380 le32toh(Tx->hw_list->seg[segment].data_count)); 1381 } 1382 #endif 1383 #endif 1384 if (sc->active_Tx == NULL) { 1385 sc->active_Tx = sc->last_Tx = Tx; 1386 #ifdef TLDEBUG_TX 1387 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1388 (int)Tx->hw_listaddr); 1389 #endif 1390 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1391 sizeof(struct tl_Tx_list) * TL_NBUF, 1392 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1393 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1394 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1395 } else { 1396 #ifdef TLDEBUG_TX 1397 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1398 (int)Tx->hw_listaddr); 1399 #endif 1400 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1401 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1402 sizeof(struct tl_Tx_list) * TL_NBUF, 1403 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1404 sc->last_Tx->next = Tx; 1405 sc->last_Tx = Tx; 1406 #ifdef DIAGNOSTIC 1407 if (sc->last_Tx->hw_list->fwd & 0x7) 1408 printf("%s: physical addr 0x%x of list not properly " 1409 "aligned\n", 1410 device_xname(sc->sc_dev), 1411 sc->last_Rx->hw_list->fwd); 1412 #endif 1413 } 1414 /* Pass packet to bpf if there is a listener */ 1415 bpf_mtap(ifp, mb_head); 1416 /* 1417 * Set a 5 second timer just in case we don't hear from the card again. 1418 */ 1419 ifp->if_timer = 5; 1420 goto txloop; 1421 bad: 1422 #ifdef TLDEBUG 1423 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1424 #endif 1425 Tx->next = sc->Free_Tx; 1426 sc->Free_Tx = Tx; 1427 } 1428 1429 static void 1430 tl_ifwatchdog(struct ifnet *ifp) 1431 { 1432 tl_softc_t *sc = ifp->if_softc; 1433 1434 if ((ifp->if_flags & IFF_RUNNING) == 0) 1435 return; 1436 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1437 ifp->if_oerrors++; 1438 tl_init(ifp); 1439 } 1440 1441 static int 1442 tl_mediachange(struct ifnet *ifp) 1443 { 1444 1445 if (ifp->if_flags & IFF_UP) 1446 tl_init(ifp); 1447 return 0; 1448 } 1449 1450 static int 1451 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1452 { 1453 struct mbuf *m; 1454 int error; 1455 1456 MGETHDR(m, M_DONTWAIT, MT_DATA); 1457 if (m != NULL) { 1458 MCLGET(m, M_DONTWAIT); 1459 if ((m->m_flags & M_EXT) == 0) { 1460 m_freem(m); 1461 if (oldm == NULL) 1462 return 0; 1463 m = oldm; 1464 m->m_data = m->m_ext.ext_buf; 1465 } 1466 } else { 1467 if (oldm == NULL) 1468 return 0; 1469 m = oldm; 1470 m->m_data = m->m_ext.ext_buf; 1471 } 1472 1473 /* (re)init the Rx_list struct */ 1474 1475 Rx->m = m; 1476 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1477 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1478 printf("%s: bus_dmamap_load() failed (error %d) for " 1479 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1480 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1481 m_freem(m); 1482 Rx->m = NULL; 1483 return 0; 1484 } 1485 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1486 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1487 /* 1488 * Move the data pointer up so that the incoming data packet 1489 * will be 32-bit aligned. 1490 */ 1491 m->m_data += 2; 1492 1493 Rx->hw_list->stat = 1494 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1495 Rx->hw_list->seg.data_count = 1496 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1497 Rx->hw_list->seg.data_addr = 1498 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1499 return (m != oldm); 1500 } 1501 1502 static void 1503 tl_ticks(void *v) 1504 { 1505 tl_softc_t *sc = v; 1506 1507 tl_read_stats(sc); 1508 1509 /* Tick the MII. */ 1510 mii_tick(&sc->tl_mii); 1511 1512 /* read statistics every seconds */ 1513 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1514 } 1515 1516 static void 1517 tl_read_stats(tl_softc_t *sc) 1518 { 1519 uint32_t reg; 1520 int ierr_overr; 1521 int ierr_code; 1522 int ierr_crc; 1523 int oerr_underr; 1524 int oerr_deferred; 1525 int oerr_coll; 1526 int oerr_multicoll; 1527 int oerr_exesscoll; 1528 int oerr_latecoll; 1529 int oerr_carrloss; 1530 struct ifnet *ifp = &sc->tl_if; 1531 1532 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1533 ifp->if_opackets += reg & 0x00ffffff; 1534 oerr_underr = reg >> 24; 1535 1536 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1537 ifp->if_ipackets += reg & 0x00ffffff; 1538 ierr_overr = reg >> 24; 1539 1540 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1541 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1542 ierr_code = (reg & TL_FERR_CODE) >> 24; 1543 oerr_deferred = (reg & TL_FERR_DEF); 1544 1545 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1546 oerr_multicoll = (reg & TL_COL_MULTI); 1547 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1548 1549 reg = tl_intreg_read(sc, TL_INT_LERR); 1550 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1551 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1552 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1553 1554 1555 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1556 oerr_carrloss; 1557 ifp->if_collisions += oerr_coll + oerr_multicoll; 1558 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1559 1560 if (ierr_overr) 1561 printf("%s: receiver ring buffer overrun\n", 1562 device_xname(sc->sc_dev)); 1563 if (oerr_underr) 1564 printf("%s: transmit buffer underrun\n", 1565 device_xname(sc->sc_dev)); 1566 #ifdef TL_PRIV_STATS 1567 sc->ierr_overr += ierr_overr; 1568 sc->ierr_code += ierr_code; 1569 sc->ierr_crc += ierr_crc; 1570 sc->oerr_underr += oerr_underr; 1571 sc->oerr_deferred += oerr_deferred; 1572 sc->oerr_coll += oerr_coll; 1573 sc->oerr_multicoll += oerr_multicoll; 1574 sc->oerr_exesscoll += oerr_exesscoll; 1575 sc->oerr_latecoll += oerr_latecoll; 1576 sc->oerr_carrloss += oerr_carrloss; 1577 #endif 1578 } 1579 1580 static void 1581 tl_addr_filter(tl_softc_t *sc) 1582 { 1583 struct ether_multistep step; 1584 struct ether_multi *enm; 1585 uint32_t hash[2] = {0, 0}; 1586 int i; 1587 1588 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1589 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1590 while (enm != NULL) { 1591 #ifdef TLDEBUG 1592 printf("%s: addrs %s %s\n", __func__, 1593 ether_sprintf(enm->enm_addrlo), 1594 ether_sprintf(enm->enm_addrhi)); 1595 #endif 1596 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1597 i = tl_multicast_hash(enm->enm_addrlo); 1598 hash[i / 32] |= 1 << (i%32); 1599 } else { 1600 hash[0] = hash[1] = 0xffffffff; 1601 sc->tl_if.if_flags |= IFF_ALLMULTI; 1602 break; 1603 } 1604 ETHER_NEXT_MULTI(step, enm); 1605 } 1606 #ifdef TLDEBUG 1607 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1608 #endif 1609 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1610 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1611 } 1612 1613 static int 1614 tl_multicast_hash(uint8_t *a) 1615 { 1616 int hash; 1617 1618 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1619 #define xor8(a,b,c,d,e,f,g,h) \ 1620 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1621 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1622 1623 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1624 DA(a,36), DA(a,42)); 1625 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1626 DA(a,37), DA(a,43)) << 1; 1627 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1628 DA(a,38), DA(a,44)) << 2; 1629 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1630 DA(a,39), DA(a,45)) << 3; 1631 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1632 DA(a,40), DA(a,46)) << 4; 1633 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1634 DA(a,41), DA(a,47)) << 5; 1635 1636 return hash; 1637 } 1638 1639 #if defined(TLDEBUG_RX) 1640 void 1641 ether_printheader(struct ether_header *eh) 1642 { 1643 uint8_t *c = (uint8_t *)eh; 1644 int i; 1645 1646 for (i = 0; i < sizeof(struct ether_header); i++) 1647 printf("%02x ", (u_int)c[i]); 1648 printf("\n"); 1649 } 1650 #endif 1651
Indexes created Thu Oct 23 22:10:10 GMT 2025