if_tl.c revision 1.98
1 /* $NetBSD: if_tl.c,v 1.98 2012/07/22 14:33:04 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Texas Instruments ThunderLAN ethernet controller 29 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 30 * available from www.ti.com 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.98 2012/07/22 14:33:04 matt Exp $"); 35 36 #undef TLDEBUG 37 #define TL_PRIV_STATS 38 #undef TLDEBUG_RX 39 #undef TLDEBUG_TX 40 #undef TLDEBUG_ADDR 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/mbuf.h> 47 #include <sys/protosw.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/malloc.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 54 #include <sys/device.h> 55 56 #include <net/if.h> 57 #if defined(SIOCSIFMEDIA) 58 #include <net/if_media.h> 59 #endif 60 #include <net/if_types.h> 61 #include <net/if_dl.h> 62 #include <net/route.h> 63 #include <net/netisr.h> 64 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 68 #include <sys/rnd.h> 69 70 #ifdef INET 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/in_var.h> 74 #include <netinet/ip.h> 75 #endif 76 77 78 #if defined(__NetBSD__) 79 #include <net/if_ether.h> 80 #if defined(INET) 81 #include <netinet/if_inarp.h> 82 #endif 83 84 #include <sys/bus.h> 85 #include <sys/intr.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #include <dev/i2c/i2cvar.h> 92 #include <dev/i2c/i2c_bitbang.h> 93 #include <dev/i2c/at24cxxvar.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/mii/tlphyvar.h> 99 100 #include <dev/pci/if_tlregs.h> 101 #include <dev/pci/if_tlvar.h> 102 #endif /* __NetBSD__ */ 103 104 /* number of transmit/receive buffers */ 105 #ifndef TL_NBUF 106 #define TL_NBUF 32 107 #endif 108 109 static int tl_pci_match(device_t, cfdata_t, void *); 110 static void tl_pci_attach(device_t, device_t, void *); 111 static int tl_intr(void *); 112 113 static int tl_ifioctl(struct ifnet *, ioctl_cmd_t, void *); 114 static int tl_mediachange(struct ifnet *); 115 static void tl_ifwatchdog(struct ifnet *); 116 static bool tl_shutdown(device_t, int); 117 118 static void tl_ifstart(struct ifnet *); 119 static void tl_reset(tl_softc_t *); 120 static int tl_init(struct ifnet *); 121 static void tl_stop(struct ifnet *, int); 122 static void tl_restart(void *); 123 static int tl_add_RxBuff(tl_softc_t *, struct Rx_list *, struct mbuf *); 124 static void tl_read_stats(tl_softc_t *); 125 static void tl_ticks(void *); 126 static int tl_multicast_hash(uint8_t *); 127 static void tl_addr_filter(tl_softc_t *); 128 129 static uint32_t tl_intreg_read(tl_softc_t *, uint32_t); 130 static void tl_intreg_write(tl_softc_t *, uint32_t, uint32_t); 131 static uint8_t tl_intreg_read_byte(tl_softc_t *, uint32_t); 132 static void tl_intreg_write_byte(tl_softc_t *, uint32_t, uint8_t); 133 134 void tl_mii_sync(struct tl_softc *); 135 void tl_mii_sendbits(struct tl_softc *, uint32_t, int); 136 137 138 #if defined(TLDEBUG_RX) 139 static void ether_printheader(struct ether_header *); 140 #endif 141 142 int tl_mii_read(device_t, int, int); 143 void tl_mii_write(device_t, int, int, int); 144 145 void tl_statchg(struct ifnet *); 146 147 /* I2C glue */ 148 static int tl_i2c_acquire_bus(void *, int); 149 static void tl_i2c_release_bus(void *, int); 150 static int tl_i2c_send_start(void *, int); 151 static int tl_i2c_send_stop(void *, int); 152 static int tl_i2c_initiate_xfer(void *, i2c_addr_t, int); 153 static int tl_i2c_read_byte(void *, uint8_t *, int); 154 static int tl_i2c_write_byte(void *, uint8_t, int); 155 156 /* I2C bit-bang glue */ 157 static void tl_i2cbb_set_bits(void *, uint32_t); 158 static void tl_i2cbb_set_dir(void *, uint32_t); 159 static uint32_t tl_i2cbb_read(void *); 160 static const struct i2c_bitbang_ops tl_i2cbb_ops = { 161 tl_i2cbb_set_bits, 162 tl_i2cbb_set_dir, 163 tl_i2cbb_read, 164 { 165 TL_NETSIO_EDATA, /* SDA */ 166 TL_NETSIO_ECLOCK, /* SCL */ 167 TL_NETSIO_ETXEN, /* SDA is output */ 168 0, /* SDA is input */ 169 } 170 }; 171 172 static inline void netsio_clr(tl_softc_t *, uint8_t); 173 static inline void netsio_set(tl_softc_t *, uint8_t); 174 static inline uint8_t netsio_read(tl_softc_t *, uint8_t); 175 176 static inline void 177 netsio_clr(tl_softc_t *sc, uint8_t bits) 178 { 179 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 184 static inline void 185 netsio_set(tl_softc_t *sc, uint8_t bits) 186 { 187 188 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 189 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 190 } 191 192 static inline uint8_t 193 netsio_read(tl_softc_t *sc, uint8_t bits) 194 { 195 196 return tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits; 197 } 198 199 CFATTACH_DECL_NEW(tl, sizeof(tl_softc_t), 200 tl_pci_match, tl_pci_attach, NULL, NULL); 201 202 static const struct tl_product_desc tl_compaq_products[] = { 203 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 204 "Compaq Netelligent 10/100 TX" }, 205 { PCI_PRODUCT_COMPAQ_INT100TX, TLPHY_MEDIA_NO_10_T, 206 "Integrated Compaq Netelligent 10/100 TX" }, 207 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 208 "Compaq Netelligent 10 T" }, 209 { PCI_PRODUCT_COMPAQ_N10T2, TLPHY_MEDIA_10_2, 210 "Compaq Netelligent 10 T/2 UTP/Coax" }, 211 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 212 "Compaq Integrated NetFlex 3/P" }, 213 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 214 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 215 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 216 "Compaq Dual Port Netelligent 10/100 TX" }, 217 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 218 "Compaq Deskpro 4000 5233MMX" }, 219 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 220 "Compaq NetFlex 3/P w/ BNC" }, 221 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 222 "Compaq NetFlex 3/P" }, 223 { 0, 0, NULL }, 224 }; 225 226 static const struct tl_product_desc tl_ti_products[] = { 227 /* 228 * Built-in Ethernet on the TI TravelMate 5000 229 * docking station; better product description? 230 */ 231 { PCI_PRODUCT_TI_TLAN, 0, 232 "Texas Instruments ThunderLAN" }, 233 { 0, 0, NULL }, 234 }; 235 236 struct tl_vendor_desc { 237 uint32_t tv_vendor; 238 const struct tl_product_desc *tv_products; 239 }; 240 241 const struct tl_vendor_desc tl_vendors[] = { 242 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 243 { PCI_VENDOR_TI, tl_ti_products }, 244 { 0, NULL }, 245 }; 246 247 static const struct tl_product_desc *tl_lookup_product(uint32_t); 248 249 static const struct tl_product_desc * 250 tl_lookup_product(uint32_t id) 251 { 252 const struct tl_product_desc *tp; 253 const struct tl_vendor_desc *tv; 254 255 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 256 if (PCI_VENDOR(id) == tv->tv_vendor) 257 break; 258 259 if ((tp = tv->tv_products) == NULL) 260 return NULL; 261 262 for (; tp->tp_desc != NULL; tp++) 263 if (PCI_PRODUCT(id) == tp->tp_product) 264 break; 265 266 if (tp->tp_desc == NULL) 267 return NULL; 268 269 return tp; 270 } 271 272 static int 273 tl_pci_match(device_t parent, cfdata_t cf, void *aux) 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 276 277 if (tl_lookup_product(pa->pa_id) != NULL) 278 return 1; 279 280 return 0; 281 } 282 283 static void 284 tl_pci_attach(device_t parent, device_t self, void *aux) 285 { 286 tl_softc_t *sc = device_private(self); 287 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 288 const struct tl_product_desc *tp; 289 struct ifnet * const ifp = &sc->tl_if; 290 bus_space_tag_t iot, memt; 291 bus_space_handle_t ioh, memh; 292 pci_intr_handle_t intrhandle; 293 const char *intrstr; 294 int ioh_valid, memh_valid; 295 int reg_io, reg_mem; 296 pcireg_t reg10, reg14; 297 pcireg_t csr; 298 299 sc->sc_dev = self; 300 aprint_normal("\n"); 301 302 callout_init(&sc->tl_tick_ch, 0); 303 callout_init(&sc->tl_restart_ch, 0); 304 305 tp = tl_lookup_product(pa->pa_id); 306 if (tp == NULL) 307 panic("%s: impossible", __func__); 308 sc->tl_product = tp; 309 310 /* 311 * Map the card space. First we have to find the I/O and MEM 312 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 313 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 314 * The ThunderLAN manual is not consistent about this either (there 315 * are both cases in code examples). 316 */ 317 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 318 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 319 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 320 reg_io = 0x10; 321 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 322 reg_io = 0x14; 323 else 324 reg_io = 0; 325 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 326 reg_mem = 0x10; 327 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 328 reg_mem = 0x14; 329 else 330 reg_mem = 0; 331 332 if (reg_io != 0) 333 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 334 0, &iot, &ioh, NULL, NULL) == 0); 335 else 336 ioh_valid = 0; 337 if (reg_mem != 0) 338 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 339 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 340 0, &memt, &memh, NULL, NULL) == 0); 341 else 342 memh_valid = 0; 343 344 if (ioh_valid) { 345 sc->tl_bustag = iot; 346 sc->tl_bushandle = ioh; 347 } else if (memh_valid) { 348 sc->tl_bustag = memt; 349 sc->tl_bushandle = memh; 350 } else { 351 aprint_error_dev(self, "unable to map device registers\n"); 352 return; 353 } 354 sc->tl_dmatag = pa->pa_dmat; 355 356 /* Enable the device. */ 357 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 358 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 359 csr | PCI_COMMAND_MASTER_ENABLE); 360 361 aprint_normal_dev(self, "%s\n", tp->tp_desc); 362 363 tl_reset(sc); 364 365 /* fill in the i2c tag */ 366 sc->sc_i2c.ic_cookie = sc; 367 sc->sc_i2c.ic_acquire_bus = tl_i2c_acquire_bus; 368 sc->sc_i2c.ic_release_bus = tl_i2c_release_bus; 369 sc->sc_i2c.ic_send_start = tl_i2c_send_start; 370 sc->sc_i2c.ic_send_stop = tl_i2c_send_stop; 371 sc->sc_i2c.ic_initiate_xfer = tl_i2c_initiate_xfer; 372 sc->sc_i2c.ic_read_byte = tl_i2c_read_byte; 373 sc->sc_i2c.ic_write_byte = tl_i2c_write_byte; 374 375 #ifdef TLDEBUG 376 aprint_debug_dev(self, "default values of INTreg: 0x%x\n", 377 tl_intreg_read(sc, TL_INT_Defaults)); 378 #endif 379 380 /* read mac addr */ 381 if (seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0x83, 256 /* 2kbit */, 382 sc->tl_enaddr, ETHER_ADDR_LEN)) { 383 aprint_error_dev(self, "error reading Ethernet address\n"); 384 return; 385 } 386 aprint_normal_dev(self, "Ethernet address %s\n", 387 ether_sprintf(sc->tl_enaddr)); 388 389 /* Map and establish interrupts */ 390 if (pci_intr_map(pa, &intrhandle)) { 391 aprint_error_dev(self, "couldn't map interrupt\n"); 392 return; 393 } 394 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 395 sc->tl_if.if_softc = sc; 396 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 397 tl_intr, sc); 398 if (sc->tl_ih == NULL) { 399 aprint_error_dev(self, "couldn't establish interrupt"); 400 if (intrstr != NULL) 401 aprint_error(" at %s", intrstr); 402 aprint_error("\n"); 403 return; 404 } 405 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 406 407 /* init these pointers, so that tl_shutdown won't try to read them */ 408 sc->Rx_list = NULL; 409 sc->Tx_list = NULL; 410 411 /* allocate DMA-safe memory for control structs */ 412 if (bus_dmamem_alloc(sc->tl_dmatag, PAGE_SIZE, 0, PAGE_SIZE, 413 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 414 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 415 sc->ctrl_nsegs, PAGE_SIZE, (void **)&sc->ctrl, 416 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 417 aprint_error_dev(self, "can't allocate DMA memory for lists\n"); 418 return; 419 } 420 421 /* 422 * Initialize our media structures and probe the MII. 423 * 424 * Note that we don't care about the media instance. We 425 * are expecting to have multiple PHYs on the 10/100 cards, 426 * and on those cards we exclude the internal PHY from providing 427 * 10baseT. By ignoring the instance, it allows us to not have 428 * to specify it on the command line when switching media. 429 */ 430 sc->tl_mii.mii_ifp = ifp; 431 sc->tl_mii.mii_readreg = tl_mii_read; 432 sc->tl_mii.mii_writereg = tl_mii_write; 433 sc->tl_mii.mii_statchg = tl_statchg; 434 sc->tl_ec.ec_mii = &sc->tl_mii; 435 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 436 ether_mediastatus); 437 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 438 MII_OFFSET_ANY, 0); 439 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 440 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 441 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 442 } else 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = tl_ifioctl; 453 ifp->if_start = tl_ifstart; 454 ifp->if_watchdog = tl_ifwatchdog; 455 ifp->if_init = tl_init; 456 ifp->if_stop = tl_stop; 457 ifp->if_timer = 0; 458 IFQ_SET_READY(&ifp->if_snd); 459 if_attach(ifp); 460 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 461 462 /* 463 * Add shutdown hook so that DMA is disabled prior to reboot. 464 * Not doing reboot before the driver initializes. 465 */ 466 if (pmf_device_register1(self, NULL, NULL, tl_shutdown)) 467 pmf_class_network_register(self, ifp); 468 else 469 aprint_error_dev(self, "couldn't establish power handler\n"); 470 471 rnd_attach_source(&sc->rnd_source, device_xname(self), 472 RND_TYPE_NET, 0); 473 } 474 475 static void 476 tl_reset(tl_softc_t *sc) 477 { 478 int i; 479 480 /* read stats */ 481 if (sc->tl_if.if_flags & IFF_RUNNING) { 482 callout_stop(&sc->tl_tick_ch); 483 tl_read_stats(sc); 484 } 485 /* Reset adapter */ 486 TL_HR_WRITE(sc, TL_HOST_CMD, 487 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 488 DELAY(100000); 489 /* Disable interrupts */ 490 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 491 /* setup aregs & hash */ 492 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 493 tl_intreg_write(sc, i, 0); 494 #ifdef TLDEBUG_ADDR 495 printf("Areg & hash registers: \n"); 496 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 497 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 498 #endif 499 /* Setup NetConfig */ 500 tl_intreg_write(sc, TL_INT_NetConfig, 501 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 502 /* Bsize: accept default */ 503 /* TX commit in Acommit: accept default */ 504 /* Load Ld_tmr and Ld_thr */ 505 /* Ld_tmr = 3 */ 506 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 507 /* Ld_thr = 0 */ 508 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 509 /* Unreset MII */ 510 netsio_set(sc, TL_NETSIO_NMRST); 511 DELAY(100000); 512 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 513 } 514 515 static bool 516 tl_shutdown(device_t self, int howto) 517 { 518 tl_softc_t *sc = device_private(self); 519 struct ifnet *ifp = &sc->tl_if; 520 521 tl_stop(ifp, 1); 522 523 return true; 524 } 525 526 static void 527 tl_stop(struct ifnet *ifp, int disable) 528 { 529 tl_softc_t *sc = ifp->if_softc; 530 struct Tx_list *Tx; 531 int i; 532 533 if ((ifp->if_flags & IFF_RUNNING) == 0) 534 return; 535 /* disable interrupts */ 536 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 537 /* stop TX and RX channels */ 538 TL_HR_WRITE(sc, TL_HOST_CMD, 539 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 540 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 541 DELAY(100000); 542 543 /* stop statistics reading loop, read stats */ 544 callout_stop(&sc->tl_tick_ch); 545 tl_read_stats(sc); 546 547 /* Down the MII. */ 548 mii_down(&sc->tl_mii); 549 550 /* deallocate memory allocations */ 551 if (sc->Rx_list) { 552 for (i = 0; i< TL_NBUF; i++) { 553 if (sc->Rx_list[i].m) { 554 bus_dmamap_unload(sc->tl_dmatag, 555 sc->Rx_list[i].m_dmamap); 556 m_freem(sc->Rx_list[i].m); 557 } 558 bus_dmamap_destroy(sc->tl_dmatag, 559 sc->Rx_list[i].m_dmamap); 560 sc->Rx_list[i].m = NULL; 561 } 562 free(sc->Rx_list, M_DEVBUF); 563 sc->Rx_list = NULL; 564 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 565 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 566 sc->hw_Rx_list = NULL; 567 while ((Tx = sc->active_Tx) != NULL) { 568 Tx->hw_list->stat = 0; 569 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 570 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 571 m_freem(Tx->m); 572 sc->active_Tx = Tx->next; 573 Tx->next = sc->Free_Tx; 574 sc->Free_Tx = Tx; 575 } 576 sc->last_Tx = NULL; 577 free(sc->Tx_list, M_DEVBUF); 578 sc->Tx_list = NULL; 579 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 580 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 581 sc->hw_Tx_list = NULL; 582 } 583 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 584 ifp->if_timer = 0; 585 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 586 } 587 588 static void 589 tl_restart(void *v) 590 { 591 592 tl_init(v); 593 } 594 595 static int 596 tl_init(struct ifnet *ifp) 597 { 598 tl_softc_t *sc = ifp->if_softc; 599 int i, s, error; 600 bus_size_t boundary; 601 prop_number_t prop_boundary; 602 const char *errstring; 603 char *nullbuf; 604 605 s = splnet(); 606 /* cancel any pending IO */ 607 tl_stop(ifp, 1); 608 tl_reset(sc); 609 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 610 splx(s); 611 return 0; 612 } 613 /* Set various register to reasonable value */ 614 /* setup NetCmd in promisc mode if needed */ 615 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 616 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 617 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 618 /* Max receive size : MCLBYTES */ 619 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 620 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 621 (MCLBYTES >> 8) & 0xff); 622 623 /* init MAC addr */ 624 for (i = 0; i < ETHER_ADDR_LEN; i++) 625 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 626 /* add multicast filters */ 627 tl_addr_filter(sc); 628 #ifdef TLDEBUG_ADDR 629 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 630 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 631 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 632 #endif 633 634 /* Pre-allocate receivers mbuf, make the lists */ 635 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 636 M_NOWAIT|M_ZERO); 637 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 638 M_NOWAIT|M_ZERO); 639 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 640 errstring = "out of memory for lists"; 641 error = ENOMEM; 642 goto bad; 643 } 644 645 /* 646 * Some boards (Set Engineering GFE) do not permit DMA transfers 647 * across page boundaries. 648 */ 649 prop_boundary = prop_dictionary_get(device_properties(sc->sc_dev), 650 "tl-dma-page-boundary"); 651 if (prop_boundary != NULL) { 652 KASSERT(prop_object_type(prop_boundary) == PROP_TYPE_NUMBER); 653 boundary = (bus_size_t)prop_number_integer_value(prop_boundary); 654 } else { 655 boundary = 0; 656 } 657 658 error = bus_dmamap_create(sc->tl_dmatag, 659 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 660 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 661 &sc->Rx_dmamap); 662 if (error == 0) 663 error = bus_dmamap_create(sc->tl_dmatag, 664 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 665 sizeof(struct tl_Tx_list) * TL_NBUF, boundary, 666 BUS_DMA_WAITOK, &sc->Tx_dmamap); 667 if (error == 0) 668 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 669 ETHER_MIN_TX, boundary, BUS_DMA_WAITOK, 670 &sc->null_dmamap); 671 if (error) { 672 errstring = "can't allocate DMA maps for lists"; 673 goto bad; 674 } 675 memset(sc->ctrl, 0, PAGE_SIZE); 676 sc->hw_Rx_list = (void *)sc->ctrl; 677 sc->hw_Tx_list = 678 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 679 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 680 sizeof(struct tl_Tx_list) * TL_NBUF; 681 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 682 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 683 BUS_DMA_WAITOK); 684 if (error == 0) 685 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 686 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 687 BUS_DMA_WAITOK); 688 if (error == 0) 689 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 690 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 691 if (error) { 692 errstring = "can't DMA map DMA memory for lists"; 693 goto bad; 694 } 695 for (i = 0; i < TL_NBUF; i++) { 696 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 697 1, MCLBYTES, boundary, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 698 &sc->Rx_list[i].m_dmamap); 699 if (error == 0) { 700 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 701 TL_NSEG, MCLBYTES, boundary, 702 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 703 &sc->Tx_list[i].m_dmamap); 704 } 705 if (error) { 706 errstring = "can't allocate DMA maps for mbufs"; 707 goto bad; 708 } 709 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 710 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 711 + sizeof(struct tl_Rx_list) * i; 712 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 713 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 714 + sizeof(struct tl_Tx_list) * i; 715 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 716 errstring = "out of mbuf for receive list"; 717 error = ENOMEM; 718 goto bad; 719 } 720 if (i > 0) { /* chain the list */ 721 sc->Rx_list[i - 1].next = &sc->Rx_list[i]; 722 sc->hw_Rx_list[i - 1].fwd = 723 htole32(sc->Rx_list[i].hw_listaddr); 724 sc->Tx_list[i - 1].next = &sc->Tx_list[i]; 725 } 726 } 727 sc->hw_Rx_list[TL_NBUF - 1].fwd = 0; 728 sc->Rx_list[TL_NBUF - 1].next = NULL; 729 sc->hw_Tx_list[TL_NBUF - 1].fwd = 0; 730 sc->Tx_list[TL_NBUF - 1].next = NULL; 731 732 sc->active_Rx = &sc->Rx_list[0]; 733 sc->last_Rx = &sc->Rx_list[TL_NBUF - 1]; 734 sc->active_Tx = sc->last_Tx = NULL; 735 sc->Free_Tx = &sc->Tx_list[0]; 736 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 737 sizeof(struct tl_Rx_list) * TL_NBUF, 738 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 739 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 740 sizeof(struct tl_Tx_list) * TL_NBUF, 741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 742 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 743 BUS_DMASYNC_PREWRITE); 744 745 /* set media */ 746 if ((error = mii_mediachg(&sc->tl_mii)) == ENXIO) 747 error = 0; 748 else if (error != 0) { 749 errstring = "could not set media"; 750 goto bad; 751 } 752 753 /* start ticks calls */ 754 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 755 /* write address of Rx list and enable interrupts */ 756 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 757 TL_HR_WRITE(sc, TL_HOST_CMD, 758 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 759 sc->tl_if.if_flags |= IFF_RUNNING; 760 sc->tl_if.if_flags &= ~IFF_OACTIVE; 761 splx(s); 762 return 0; 763 bad: 764 printf("%s: %s\n", device_xname(sc->sc_dev), errstring); 765 splx(s); 766 return error; 767 } 768 769 770 static uint32_t 771 tl_intreg_read(tl_softc_t *sc, uint32_t reg) 772 { 773 774 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 775 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 776 } 777 778 static uint8_t 779 tl_intreg_read_byte(tl_softc_t *sc, uint32_t reg) 780 { 781 782 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 783 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 784 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 785 } 786 787 static void 788 tl_intreg_write(tl_softc_t *sc, uint32_t reg, uint32_t val) 789 { 790 791 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 792 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 793 } 794 795 static void 796 tl_intreg_write_byte(tl_softc_t *sc, uint32_t reg, uint8_t val) 797 { 798 799 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 800 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 801 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 802 } 803 804 void 805 tl_mii_sync(struct tl_softc *sc) 806 { 807 int i; 808 809 netsio_clr(sc, TL_NETSIO_MTXEN); 810 for (i = 0; i < 32; i++) { 811 netsio_clr(sc, TL_NETSIO_MCLK); 812 netsio_set(sc, TL_NETSIO_MCLK); 813 } 814 } 815 816 void 817 tl_mii_sendbits(struct tl_softc *sc, uint32_t data, int nbits) 818 { 819 int i; 820 821 netsio_set(sc, TL_NETSIO_MTXEN); 822 for (i = 1 << (nbits - 1); i; i = i >> 1) { 823 netsio_clr(sc, TL_NETSIO_MCLK); 824 netsio_read(sc, TL_NETSIO_MCLK); 825 if (data & i) 826 netsio_set(sc, TL_NETSIO_MDATA); 827 else 828 netsio_clr(sc, TL_NETSIO_MDATA); 829 netsio_set(sc, TL_NETSIO_MCLK); 830 netsio_read(sc, TL_NETSIO_MCLK); 831 } 832 } 833 834 int 835 tl_mii_read(device_t self, int phy, int reg) 836 { 837 struct tl_softc *sc = device_private(self); 838 int val = 0, i, err; 839 840 /* 841 * Read the PHY register by manually driving the MII control lines. 842 */ 843 844 tl_mii_sync(sc); 845 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 846 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 847 tl_mii_sendbits(sc, phy, 5); 848 tl_mii_sendbits(sc, reg, 5); 849 850 netsio_clr(sc, TL_NETSIO_MTXEN); 851 netsio_clr(sc, TL_NETSIO_MCLK); 852 netsio_set(sc, TL_NETSIO_MCLK); 853 netsio_clr(sc, TL_NETSIO_MCLK); 854 855 err = netsio_read(sc, TL_NETSIO_MDATA); 856 netsio_set(sc, TL_NETSIO_MCLK); 857 858 /* Even if an error occurs, must still clock out the cycle. */ 859 for (i = 0; i < 16; i++) { 860 val <<= 1; 861 netsio_clr(sc, TL_NETSIO_MCLK); 862 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 863 val |= 1; 864 netsio_set(sc, TL_NETSIO_MCLK); 865 } 866 netsio_clr(sc, TL_NETSIO_MCLK); 867 netsio_set(sc, TL_NETSIO_MCLK); 868 869 return err ? 0 : val; 870 } 871 872 void 873 tl_mii_write(device_t self, int phy, int reg, int val) 874 { 875 struct tl_softc *sc = device_private(self); 876 877 /* 878 * Write the PHY register by manually driving the MII control lines. 879 */ 880 881 tl_mii_sync(sc); 882 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 883 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 884 tl_mii_sendbits(sc, phy, 5); 885 tl_mii_sendbits(sc, reg, 5); 886 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 887 tl_mii_sendbits(sc, val, 16); 888 889 netsio_clr(sc, TL_NETSIO_MCLK); 890 netsio_set(sc, TL_NETSIO_MCLK); 891 } 892 893 void 894 tl_statchg(struct ifnet *ifp) 895 { 896 tl_softc_t *sc = ifp->if_softc; 897 uint32_t reg; 898 899 #ifdef TLDEBUG 900 printf("%s: media %x\n", __func__, sc->tl_mii.mii_media.ifm_media); 901 #endif 902 903 /* 904 * We must keep the ThunderLAN and the PHY in sync as 905 * to the status of full-duplex! 906 */ 907 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 908 if (sc->tl_mii.mii_media_active & IFM_FDX) 909 reg |= TL_NETCOMMAND_DUPLEX; 910 else 911 reg &= ~TL_NETCOMMAND_DUPLEX; 912 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 913 } 914 915 /********** I2C glue **********/ 916 917 static int 918 tl_i2c_acquire_bus(void *cookie, int flags) 919 { 920 921 /* private bus */ 922 return 0; 923 } 924 925 static void 926 tl_i2c_release_bus(void *cookie, int flags) 927 { 928 929 /* private bus */ 930 } 931 932 static int 933 tl_i2c_send_start(void *cookie, int flags) 934 { 935 936 return i2c_bitbang_send_start(cookie, flags, &tl_i2cbb_ops); 937 } 938 939 static int 940 tl_i2c_send_stop(void *cookie, int flags) 941 { 942 943 return i2c_bitbang_send_stop(cookie, flags, &tl_i2cbb_ops); 944 } 945 946 static int 947 tl_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 948 { 949 950 return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tl_i2cbb_ops); 951 } 952 953 static int 954 tl_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 955 { 956 957 return i2c_bitbang_read_byte(cookie, valp, flags, &tl_i2cbb_ops); 958 } 959 960 static int 961 tl_i2c_write_byte(void *cookie, uint8_t val, int flags) 962 { 963 964 return i2c_bitbang_write_byte(cookie, val, flags, &tl_i2cbb_ops); 965 } 966 967 /********** I2C bit-bang glue **********/ 968 969 static void 970 tl_i2cbb_set_bits(void *cookie, uint32_t bits) 971 { 972 struct tl_softc *sc = cookie; 973 uint8_t reg; 974 975 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 976 reg = (reg & ~(TL_NETSIO_EDATA|TL_NETSIO_ECLOCK)) | bits; 977 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 978 } 979 980 static void 981 tl_i2cbb_set_dir(void *cookie, uint32_t bits) 982 { 983 struct tl_softc *sc = cookie; 984 uint8_t reg; 985 986 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio); 987 reg = (reg & ~TL_NETSIO_ETXEN) | bits; 988 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, reg); 989 } 990 991 static uint32_t 992 tl_i2cbb_read(void *cookie) 993 { 994 995 return tl_intreg_read_byte(cookie, TL_INT_NET + TL_INT_NetSio); 996 } 997 998 /********** End of I2C stuff **********/ 999 1000 static int 1001 tl_intr(void *v) 1002 { 1003 tl_softc_t *sc = v; 1004 struct ifnet *ifp = &sc->tl_if; 1005 struct Rx_list *Rx; 1006 struct Tx_list *Tx; 1007 struct mbuf *m; 1008 uint32_t int_type, int_reg; 1009 int ack = 0; 1010 int size; 1011 1012 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 1013 int_type = int_reg & TL_INTR_MASK; 1014 if (int_type == 0) 1015 return 0; 1016 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 1017 printf("%s: interrupt type %x, intr_reg %x\n", device_xname(sc->sc_dev), 1018 int_type, int_reg); 1019 #endif 1020 /* disable interrupts */ 1021 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 1022 switch(int_type & TL_INTR_MASK) { 1023 case TL_INTR_RxEOF: 1024 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1025 sizeof(struct tl_Rx_list) * TL_NBUF, 1026 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1027 while(le32toh(sc->active_Rx->hw_list->stat) & 1028 TL_RX_CSTAT_CPLT) { 1029 /* dequeue and requeue at end of list */ 1030 ack++; 1031 Rx = sc->active_Rx; 1032 sc->active_Rx = Rx->next; 1033 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1034 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1035 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 1036 m = Rx->m; 1037 size = le32toh(Rx->hw_list->stat) >> 16; 1038 #ifdef TLDEBUG_RX 1039 printf("%s: RX list complete, Rx %p, size=%d\n", 1040 __func__, Rx, size); 1041 #endif 1042 if (tl_add_RxBuff(sc, Rx, m) == 0) { 1043 /* 1044 * No new mbuf, reuse the same. This means 1045 * that this packet 1046 * is lost 1047 */ 1048 m = NULL; 1049 #ifdef TL_PRIV_STATS 1050 sc->ierr_nomem++; 1051 #endif 1052 #ifdef TLDEBUG 1053 printf("%s: out of mbuf, lost input packet\n", 1054 device_xname(sc->sc_dev)); 1055 #endif 1056 } 1057 Rx->next = NULL; 1058 Rx->hw_list->fwd = 0; 1059 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1060 sc->last_Rx->next = Rx; 1061 sc->last_Rx = Rx; 1062 1063 /* deliver packet */ 1064 if (m) { 1065 if (size < sizeof(struct ether_header)) { 1066 m_freem(m); 1067 continue; 1068 } 1069 m->m_pkthdr.rcvif = ifp; 1070 m->m_pkthdr.len = m->m_len = size; 1071 #ifdef TLDEBUG_RX 1072 { 1073 struct ether_header *eh = 1074 mtod(m, struct ether_header *); 1075 printf("%s: Rx packet:\n", __func__); 1076 ether_printheader(eh); 1077 } 1078 #endif 1079 bpf_mtap(ifp, m); 1080 (*ifp->if_input)(ifp, m); 1081 } 1082 } 1083 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1084 sizeof(struct tl_Rx_list) * TL_NBUF, 1085 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1086 #ifdef TLDEBUG_RX 1087 printf("TL_INTR_RxEOF: ack %d\n", ack); 1088 #else 1089 if (ack == 0) { 1090 printf("%s: EOF intr without anything to read !\n", 1091 device_xname(sc->sc_dev)); 1092 tl_reset(sc); 1093 /* schedule reinit of the board */ 1094 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1095 return 1; 1096 } 1097 #endif 1098 break; 1099 case TL_INTR_RxEOC: 1100 ack++; 1101 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1102 sizeof(struct tl_Rx_list) * TL_NBUF, 1103 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1104 #ifdef TLDEBUG_RX 1105 printf("TL_INTR_RxEOC: ack %d\n", ack); 1106 #endif 1107 #ifdef DIAGNOSTIC 1108 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1109 printf("%s: Rx EOC interrupt and active Tx list not " 1110 "cleared\n", device_xname(sc->sc_dev)); 1111 return 0; 1112 } else 1113 #endif 1114 { 1115 /* 1116 * write address of Rx list and send Rx GO command, ack 1117 * interrupt and enable interrupts in one command 1118 */ 1119 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1120 TL_HR_WRITE(sc, TL_HOST_CMD, 1121 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1122 HOST_CMD_ACK | HOST_CMD_IntOn); 1123 return 1; 1124 } 1125 case TL_INTR_TxEOF: 1126 case TL_INTR_TxEOC: 1127 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1128 sizeof(struct tl_Tx_list) * TL_NBUF, 1129 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1130 while ((Tx = sc->active_Tx) != NULL) { 1131 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1132 break; 1133 ack++; 1134 #ifdef TLDEBUG_TX 1135 printf("TL_INTR_TxEOC: list 0x%x done\n", 1136 (int)Tx->hw_listaddr); 1137 #endif 1138 Tx->hw_list->stat = 0; 1139 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1140 Tx->m_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1142 m_freem(Tx->m); 1143 Tx->m = NULL; 1144 sc->active_Tx = Tx->next; 1145 if (sc->active_Tx == NULL) 1146 sc->last_Tx = NULL; 1147 Tx->next = sc->Free_Tx; 1148 sc->Free_Tx = Tx; 1149 } 1150 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1151 sizeof(struct tl_Tx_list) * TL_NBUF, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 /* if this was an EOC, ACK immediatly */ 1154 if (ack) 1155 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1156 if (int_type == TL_INTR_TxEOC) { 1157 #ifdef TLDEBUG_TX 1158 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1159 ack); 1160 #endif 1161 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1162 HOST_CMD_ACK | HOST_CMD_IntOn); 1163 if (sc->active_Tx != NULL) { 1164 /* needs a Tx go command */ 1165 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1166 sc->active_Tx->hw_listaddr); 1167 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1168 } 1169 sc->tl_if.if_timer = 0; 1170 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1171 tl_ifstart(&sc->tl_if); 1172 return 1; 1173 } 1174 #ifdef TLDEBUG 1175 else { 1176 printf("TL_INTR_TxEOF: ack %d\n", ack); 1177 } 1178 #endif 1179 sc->tl_if.if_timer = 0; 1180 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1181 tl_ifstart(&sc->tl_if); 1182 break; 1183 case TL_INTR_Stat: 1184 ack++; 1185 #ifdef TLDEBUG 1186 printf("TL_INTR_Stat: ack %d\n", ack); 1187 #endif 1188 tl_read_stats(sc); 1189 break; 1190 case TL_INTR_Adc: 1191 if (int_reg & TL_INTVec_MASK) { 1192 /* adapter check conditions */ 1193 printf("%s: check condition, intvect=0x%x, " 1194 "ch_param=0x%x\n", device_xname(sc->sc_dev), 1195 int_reg & TL_INTVec_MASK, 1196 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1197 tl_reset(sc); 1198 /* schedule reinit of the board */ 1199 callout_reset(&sc->tl_restart_ch, 1, tl_restart, ifp); 1200 return 1; 1201 } else { 1202 uint8_t netstat; 1203 /* Network status */ 1204 netstat = 1205 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1206 printf("%s: network status, NetSts=%x\n", 1207 device_xname(sc->sc_dev), netstat); 1208 /* Ack interrupts */ 1209 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1210 netstat); 1211 ack++; 1212 } 1213 break; 1214 default: 1215 printf("%s: unhandled interrupt code %x!\n", 1216 device_xname(sc->sc_dev), int_type); 1217 ack++; 1218 } 1219 1220 if (ack) { 1221 /* Ack the interrupt and enable interrupts */ 1222 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1223 HOST_CMD_IntOn); 1224 rnd_add_uint32(&sc->rnd_source, int_reg); 1225 return 1; 1226 } 1227 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1228 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1229 return 0; 1230 } 1231 1232 static int 1233 tl_ifioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1234 { 1235 struct tl_softc *sc = ifp->if_softc; 1236 int s, error; 1237 1238 s = splnet(); 1239 error = ether_ioctl(ifp, cmd, data); 1240 if (error == ENETRESET) { 1241 if (ifp->if_flags & IFF_RUNNING) 1242 tl_addr_filter(sc); 1243 error = 0; 1244 } 1245 splx(s); 1246 return error; 1247 } 1248 1249 static void 1250 tl_ifstart(struct ifnet *ifp) 1251 { 1252 tl_softc_t *sc = ifp->if_softc; 1253 struct mbuf *mb_head; 1254 struct Tx_list *Tx; 1255 int segment, size; 1256 int again, error; 1257 1258 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1259 return; 1260 txloop: 1261 /* If we don't have more space ... */ 1262 if (sc->Free_Tx == NULL) { 1263 #ifdef TLDEBUG 1264 printf("%s: No free TX list\n", __func__); 1265 #endif 1266 sc->tl_if.if_flags |= IFF_OACTIVE; 1267 return; 1268 } 1269 /* Grab a paquet for output */ 1270 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1271 if (mb_head == NULL) { 1272 #ifdef TLDEBUG_TX 1273 printf("%s: nothing to send\n", __func__); 1274 #endif 1275 return; 1276 } 1277 Tx = sc->Free_Tx; 1278 sc->Free_Tx = Tx->next; 1279 Tx->next = NULL; 1280 again = 0; 1281 /* 1282 * Go through each of the mbufs in the chain and initialize 1283 * the transmit list descriptors with the physical address 1284 * and size of the mbuf. 1285 */ 1286 tbdinit: 1287 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1288 Tx->m = mb_head; 1289 size = mb_head->m_pkthdr.len; 1290 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1291 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1292 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1293 struct mbuf *mn; 1294 /* 1295 * We ran out of segments, or we will. We have to recopy this 1296 * mbuf chain first. 1297 */ 1298 if (error == 0) 1299 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1300 if (again) { 1301 /* already copyed, can't do much more */ 1302 m_freem(mb_head); 1303 goto bad; 1304 } 1305 again = 1; 1306 #ifdef TLDEBUG_TX 1307 printf("%s: need to copy mbuf\n", __func__); 1308 #endif 1309 #ifdef TL_PRIV_STATS 1310 sc->oerr_mcopy++; 1311 #endif 1312 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1313 if (mn == NULL) { 1314 m_freem(mb_head); 1315 goto bad; 1316 } 1317 if (mb_head->m_pkthdr.len > MHLEN) { 1318 MCLGET(mn, M_DONTWAIT); 1319 if ((mn->m_flags & M_EXT) == 0) { 1320 m_freem(mn); 1321 m_freem(mb_head); 1322 goto bad; 1323 } 1324 } 1325 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1326 mtod(mn, void *)); 1327 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1328 m_freem(mb_head); 1329 mb_head = mn; 1330 goto tbdinit; 1331 } 1332 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1333 Tx->hw_list->seg[segment].data_addr = 1334 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1335 Tx->hw_list->seg[segment].data_count = 1336 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1337 } 1338 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1339 Tx->m_dmamap->dm_mapsize, 1340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1341 /* We are at end of mbuf chain. check the size and 1342 * see if it needs to be extended 1343 */ 1344 if (size < ETHER_MIN_TX) { 1345 #ifdef DIAGNOSTIC 1346 if (segment >= TL_NSEG) { 1347 panic("%s: to much segmets (%d)", __func__, segment); 1348 } 1349 #endif 1350 /* 1351 * add the nullbuf in the seg 1352 */ 1353 Tx->hw_list->seg[segment].data_count = 1354 htole32(ETHER_MIN_TX - size); 1355 Tx->hw_list->seg[segment].data_addr = 1356 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1357 size = ETHER_MIN_TX; 1358 segment++; 1359 } 1360 /* The list is done, finish the list init */ 1361 Tx->hw_list->seg[segment - 1].data_count |= 1362 htole32(TL_LAST_SEG); 1363 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1364 #ifdef TLDEBUG_TX 1365 printf("%s: sending, Tx : stat = 0x%x\n", device_xname(sc->sc_dev), 1366 le32toh(Tx->hw_list->stat)); 1367 #if 0 1368 for (segment = 0; segment < TL_NSEG; segment++) { 1369 printf(" seg %d addr 0x%x len 0x%x\n", 1370 segment, 1371 le32toh(Tx->hw_list->seg[segment].data_addr), 1372 le32toh(Tx->hw_list->seg[segment].data_count)); 1373 } 1374 #endif 1375 #endif 1376 if (sc->active_Tx == NULL) { 1377 sc->active_Tx = sc->last_Tx = Tx; 1378 #ifdef TLDEBUG_TX 1379 printf("%s: Tx GO, addr=0x%ux\n", device_xname(sc->sc_dev), 1380 (int)Tx->hw_listaddr); 1381 #endif 1382 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1383 sizeof(struct tl_Tx_list) * TL_NBUF, 1384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1385 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1386 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1387 } else { 1388 #ifdef TLDEBUG_TX 1389 printf("%s: Tx addr=0x%ux queued\n", device_xname(sc->sc_dev), 1390 (int)Tx->hw_listaddr); 1391 #endif 1392 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1393 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1394 sizeof(struct tl_Tx_list) * TL_NBUF, 1395 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1396 sc->last_Tx->next = Tx; 1397 sc->last_Tx = Tx; 1398 #ifdef DIAGNOSTIC 1399 if (sc->last_Tx->hw_list->fwd & 0x7) 1400 printf("%s: physical addr 0x%x of list not properly " 1401 "aligned\n", 1402 device_xname(sc->sc_dev), 1403 sc->last_Rx->hw_list->fwd); 1404 #endif 1405 } 1406 /* Pass packet to bpf if there is a listener */ 1407 bpf_mtap(ifp, mb_head); 1408 /* 1409 * Set a 5 second timer just in case we don't hear from the card again. 1410 */ 1411 ifp->if_timer = 5; 1412 goto txloop; 1413 bad: 1414 #ifdef TLDEBUG 1415 printf("%s: Out of mbuf, Tx pkt lost\n", __func__); 1416 #endif 1417 Tx->next = sc->Free_Tx; 1418 sc->Free_Tx = Tx; 1419 } 1420 1421 static void 1422 tl_ifwatchdog(struct ifnet *ifp) 1423 { 1424 tl_softc_t *sc = ifp->if_softc; 1425 1426 if ((ifp->if_flags & IFF_RUNNING) == 0) 1427 return; 1428 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1429 ifp->if_oerrors++; 1430 tl_init(ifp); 1431 } 1432 1433 static int 1434 tl_mediachange(struct ifnet *ifp) 1435 { 1436 1437 if (ifp->if_flags & IFF_UP) 1438 tl_init(ifp); 1439 return 0; 1440 } 1441 1442 static int 1443 tl_add_RxBuff(tl_softc_t *sc, struct Rx_list *Rx, struct mbuf *oldm) 1444 { 1445 struct mbuf *m; 1446 int error; 1447 1448 MGETHDR(m, M_DONTWAIT, MT_DATA); 1449 if (m != NULL) { 1450 MCLGET(m, M_DONTWAIT); 1451 if ((m->m_flags & M_EXT) == 0) { 1452 m_freem(m); 1453 if (oldm == NULL) 1454 return 0; 1455 m = oldm; 1456 m->m_data = m->m_ext.ext_buf; 1457 } 1458 } else { 1459 if (oldm == NULL) 1460 return 0; 1461 m = oldm; 1462 m->m_data = m->m_ext.ext_buf; 1463 } 1464 1465 /* (re)init the Rx_list struct */ 1466 1467 Rx->m = m; 1468 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1469 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1470 printf("%s: bus_dmamap_load() failed (error %d) for " 1471 "tl_add_RxBuff ", device_xname(sc->sc_dev), error); 1472 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1473 m_freem(m); 1474 Rx->m = NULL; 1475 return 0; 1476 } 1477 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1478 Rx->m_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1479 /* 1480 * Move the data pointer up so that the incoming data packet 1481 * will be 32-bit aligned. 1482 */ 1483 m->m_data += 2; 1484 1485 Rx->hw_list->stat = 1486 htole32(((Rx->m_dmamap->dm_segs[0].ds_len - 2) << 16) | 0x3000); 1487 Rx->hw_list->seg.data_count = 1488 htole32(Rx->m_dmamap->dm_segs[0].ds_len - 2); 1489 Rx->hw_list->seg.data_addr = 1490 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1491 return (m != oldm); 1492 } 1493 1494 static void 1495 tl_ticks(void *v) 1496 { 1497 tl_softc_t *sc = v; 1498 1499 tl_read_stats(sc); 1500 1501 /* Tick the MII. */ 1502 mii_tick(&sc->tl_mii); 1503 1504 /* read statistics every seconds */ 1505 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1506 } 1507 1508 static void 1509 tl_read_stats(tl_softc_t *sc) 1510 { 1511 uint32_t reg; 1512 int ierr_overr; 1513 int ierr_code; 1514 int ierr_crc; 1515 int oerr_underr; 1516 int oerr_deferred; 1517 int oerr_coll; 1518 int oerr_multicoll; 1519 int oerr_exesscoll; 1520 int oerr_latecoll; 1521 int oerr_carrloss; 1522 struct ifnet *ifp = &sc->tl_if; 1523 1524 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1525 ifp->if_opackets += reg & 0x00ffffff; 1526 oerr_underr = reg >> 24; 1527 1528 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1529 ifp->if_ipackets += reg & 0x00ffffff; 1530 ierr_overr = reg >> 24; 1531 1532 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1533 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1534 ierr_code = (reg & TL_FERR_CODE) >> 24; 1535 oerr_deferred = (reg & TL_FERR_DEF); 1536 1537 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1538 oerr_multicoll = (reg & TL_COL_MULTI); 1539 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1540 1541 reg = tl_intreg_read(sc, TL_INT_LERR); 1542 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1543 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1544 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1545 1546 1547 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1548 oerr_carrloss; 1549 ifp->if_collisions += oerr_coll + oerr_multicoll; 1550 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1551 1552 if (ierr_overr) 1553 printf("%s: receiver ring buffer overrun\n", 1554 device_xname(sc->sc_dev)); 1555 if (oerr_underr) 1556 printf("%s: transmit buffer underrun\n", 1557 device_xname(sc->sc_dev)); 1558 #ifdef TL_PRIV_STATS 1559 sc->ierr_overr += ierr_overr; 1560 sc->ierr_code += ierr_code; 1561 sc->ierr_crc += ierr_crc; 1562 sc->oerr_underr += oerr_underr; 1563 sc->oerr_deferred += oerr_deferred; 1564 sc->oerr_coll += oerr_coll; 1565 sc->oerr_multicoll += oerr_multicoll; 1566 sc->oerr_exesscoll += oerr_exesscoll; 1567 sc->oerr_latecoll += oerr_latecoll; 1568 sc->oerr_carrloss += oerr_carrloss; 1569 #endif 1570 } 1571 1572 static void 1573 tl_addr_filter(tl_softc_t *sc) 1574 { 1575 struct ether_multistep step; 1576 struct ether_multi *enm; 1577 uint32_t hash[2] = {0, 0}; 1578 int i; 1579 1580 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1581 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1582 while (enm != NULL) { 1583 #ifdef TLDEBUG 1584 printf("%s: addrs %s %s\n", __func__, 1585 ether_sprintf(enm->enm_addrlo), 1586 ether_sprintf(enm->enm_addrhi)); 1587 #endif 1588 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1589 i = tl_multicast_hash(enm->enm_addrlo); 1590 hash[i / 32] |= 1 << (i%32); 1591 } else { 1592 hash[0] = hash[1] = 0xffffffff; 1593 sc->tl_if.if_flags |= IFF_ALLMULTI; 1594 break; 1595 } 1596 ETHER_NEXT_MULTI(step, enm); 1597 } 1598 #ifdef TLDEBUG 1599 printf("%s: hash1 %x has2 %x\n", __func__, hash[0], hash[1]); 1600 #endif 1601 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1602 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1603 } 1604 1605 static int 1606 tl_multicast_hash(uint8_t *a) 1607 { 1608 int hash; 1609 1610 #define DA(addr,bit) (addr[5 - (bit / 8)] & (1 << (bit % 8))) 1611 #define xor8(a,b,c,d,e,f,g,h) \ 1612 (((a != 0) + (b != 0) + (c != 0) + (d != 0) + \ 1613 (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1614 1615 hash = xor8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1616 DA(a,36), DA(a,42)); 1617 hash |= xor8(DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1618 DA(a,37), DA(a,43)) << 1; 1619 hash |= xor8(DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1620 DA(a,38), DA(a,44)) << 2; 1621 hash |= xor8(DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1622 DA(a,39), DA(a,45)) << 3; 1623 hash |= xor8(DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1624 DA(a,40), DA(a,46)) << 4; 1625 hash |= xor8(DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1626 DA(a,41), DA(a,47)) << 5; 1627 1628 return hash; 1629 } 1630 1631 #if defined(TLDEBUG_RX) 1632 void 1633 ether_printheader(struct ether_header *eh) 1634 { 1635 uint8_t *c = (uint8_t *)eh; 1636 int i; 1637 1638 for (i = 0; i < sizeof(struct ether_header); i++) 1639 printf("%02x ", (u_int)c[i]); 1640 printf("\n"); 1641 } 1642 #endif 1643
Indexes created Wed Sep 24 05:09:52 GMT 2025