if_tlp_pci.c revision 1.130
1 /* $NetBSD: if_tlp_pci.c,v 1.130 2021/05/08 00:27:02 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; and Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI bus front-end for the Digital Semiconductor ``Tulip'' (21x4x) 35 * Ethernet controller family driver. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tlp_pci.c,v 1.130 2021/05/08 00:27:02 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_ether.h> 57 58 #include <sys/bus.h> 59 #include <sys/intr.h> 60 61 #include <dev/mii/miivar.h> 62 #include <dev/mii/mii_bitbang.h> 63 64 #include <dev/ic/tulipreg.h> 65 #include <dev/ic/tulipvar.h> 66 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcidevs.h> 70 71 /* 72 * PCI configuration space registers used by the Tulip. 73 */ 74 #define TULIP_PCI_IOBA PCI_BAR(0) /* i/o mapped base */ 75 #define TULIP_PCI_MMBA PCI_BAR(1) /* memory mapped base */ 76 #define TULIP_PCI_CFDA 0x40 /* configuration driver area */ 77 78 #define CFDA_SLEEP 0x80000000 /* sleep mode */ 79 #define CFDA_SNOOZE 0x40000000 /* snooze mode */ 80 81 struct tulip_pci_softc { 82 struct tulip_softc sc_tulip; /* real Tulip softc */ 83 84 /* PCI-specific goo. */ 85 void *sc_ih; /* interrupt handle */ 86 bus_size_t sc_mapsize; 87 88 pci_chipset_tag_t sc_pc; /* our PCI chipset */ 89 pcitag_t sc_pcitag; /* our PCI tag */ 90 91 int sc_flags; /* flags; see below */ 92 93 LIST_HEAD(, tulip_pci_softc) sc_intrslaves; 94 LIST_ENTRY(tulip_pci_softc) sc_intrq; 95 96 /* Our {ROM,interrupt} master. */ 97 struct tulip_pci_softc *sc_master; 98 }; 99 100 /* sc_flags */ 101 #define TULIP_PCI_SHAREDINTR 0x01 /* interrupt is shared */ 102 #define TULIP_PCI_SLAVEINTR 0x02 /* interrupt is slave */ 103 #define TULIP_PCI_SHAREDROM 0x04 /* ROM is shared */ 104 #define TULIP_PCI_SLAVEROM 0x08 /* slave of shared ROM */ 105 106 static int tlp_pci_match(device_t, cfdata_t, void *); 107 static void tlp_pci_attach(device_t, device_t, void *); 108 static int tlp_pci_detach(device_t, int); 109 110 CFATTACH_DECL3_NEW(tlp_pci, sizeof(struct tulip_pci_softc), 111 tlp_pci_match, tlp_pci_attach, tlp_pci_detach, NULL, NULL, NULL, 112 DVF_DETACH_SHUTDOWN); 113 114 static const struct device_compatible_entry compat_data[] = { 115 { .id = PCI_ID_CODE(PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21040), 116 .value = TULIP_CHIP_21040 }, 117 118 { .id = PCI_ID_CODE(PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21041), 119 .value = TULIP_CHIP_21041 }, 120 121 { .id = PCI_ID_CODE(PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21140), 122 .value = TULIP_CHIP_21140 }, 123 124 { .id = PCI_ID_CODE(PCI_VENDOR_DEC, PCI_PRODUCT_DEC_21142), 125 .value = TULIP_CHIP_21142 }, 126 127 128 129 { .id = PCI_ID_CODE(PCI_VENDOR_LITEON, PCI_PRODUCT_LITEON_82C168), 130 .value = TULIP_CHIP_82C168 }, 131 132 /* 133 * Note: This is like a MX98725 with Wake-On-LAN and a 134 * 128-bit multicast hash table. 135 */ 136 { .id = PCI_ID_CODE(PCI_VENDOR_LITEON, PCI_PRODUCT_LITEON_82C115), 137 .value = TULIP_CHIP_82C115 }, 138 139 140 141 { .id = PCI_ID_CODE(PCI_VENDOR_MACRONIX, PCI_PRODUCT_MACRONIX_MX98713), 142 .value = TULIP_CHIP_MX98713 }, 143 144 { .id = PCI_ID_CODE(PCI_VENDOR_MACRONIX, PCI_PRODUCT_MACRONIX_MX987x5), 145 .value = TULIP_CHIP_MX98715 }, 146 147 { .id = PCI_ID_CODE(PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100TX), 148 .value = TULIP_CHIP_MX98713 }, 149 150 151 152 { .id = PCI_ID_CODE(PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F), 153 .value = TULIP_CHIP_WB89C840F }, 154 155 { .id = PCI_ID_CODE(PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX), 156 .value = TULIP_CHIP_WB89C840F }, 157 158 159 160 { .id = PCI_ID_CODE(PCI_VENDOR_DAVICOM, PCI_PRODUCT_DAVICOM_DM9102), 161 .value = TULIP_CHIP_DM9102 }, 162 163 164 165 { .id = PCI_ID_CODE(PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_AL981), 166 .value = TULIP_CHIP_AL981 }, 167 168 { .id = PCI_ID_CODE(PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_AN983), 169 .value = TULIP_CHIP_AN985 }, 170 171 { .id = PCI_ID_CODE(PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM9511), 172 .value = TULIP_CHIP_AN985 }, 173 174 { .id = PCI_ID_CODE(PCI_VENDOR_ADMTEK, PCI_PRODUCT_ADMTEK_ADM9513), 175 .value = TULIP_CHIP_AN985 }, 176 177 { .id = PCI_ID_CODE(PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_EN2242), 178 .value = TULIP_CHIP_AN985 }, 179 180 { .id = PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C910SOHOB), 181 .value = TULIP_CHIP_AN985 }, 182 183 184 185 { .id = PCI_ID_CODE(PCI_VENDOR_ASIX, PCI_PRODUCT_ASIX_AX88140A), 186 .value = TULIP_CHIP_AX88140 }, 187 188 189 190 { .id = PCI_ID_CODE(PCI_VENDOR_CONEXANT, 191 PCI_PRODUCT_CONEXANT_LANFINITY), 192 .value = TULIP_CHIP_RS7112 }, 193 194 195 196 PCI_COMPAT_EOL 197 }; 198 199 struct tlp_pci_quirks { 200 void (*tpq_func)(struct tulip_pci_softc *, 201 const uint8_t *); 202 uint8_t tpq_oui[3]; 203 }; 204 205 static void tlp_pci_dec_quirks(struct tulip_pci_softc *, 206 const uint8_t *); 207 208 static void tlp_pci_znyx_21040_quirks(struct tulip_pci_softc *, 209 const uint8_t *); 210 static void tlp_pci_smc_21040_quirks(struct tulip_pci_softc *, 211 const uint8_t *); 212 static void tlp_pci_cogent_21040_quirks(struct tulip_pci_softc *, 213 const uint8_t *); 214 static void tlp_pci_accton_21040_quirks(struct tulip_pci_softc *, 215 const uint8_t *); 216 217 static void tlp_pci_cobalt_21142_quirks(struct tulip_pci_softc *, 218 const uint8_t *); 219 static void tlp_pci_algor_21142_quirks(struct tulip_pci_softc *, 220 const uint8_t *); 221 static void tlp_pci_netwinder_21142_quirks(struct tulip_pci_softc *, 222 const uint8_t *); 223 static void tlp_pci_phobos_21142_quirks(struct tulip_pci_softc *, 224 const uint8_t *); 225 static void tlp_pci_znyx_21142_quirks(struct tulip_pci_softc *, 226 const uint8_t *); 227 228 static void tlp_pci_adaptec_quirks(struct tulip_pci_softc *, 229 const uint8_t *); 230 231 static const struct tlp_pci_quirks tlp_pci_21040_quirks[] = { 232 { tlp_pci_znyx_21040_quirks, { 0x00, 0xc0, 0x95 } }, 233 { tlp_pci_smc_21040_quirks, { 0x00, 0x00, 0xc0 } }, 234 { tlp_pci_cogent_21040_quirks, { 0x00, 0x00, 0x92 } }, 235 { tlp_pci_accton_21040_quirks, { 0x00, 0x00, 0xe8 } }, 236 { NULL, { 0, 0, 0 } } 237 }; 238 239 static const struct tlp_pci_quirks tlp_pci_21041_quirks[] = { 240 { tlp_pci_dec_quirks, { 0x08, 0x00, 0x2b } }, 241 { tlp_pci_dec_quirks, { 0x00, 0x00, 0xf8 } }, 242 { NULL, { 0, 0, 0 } } 243 }; 244 245 static void tlp_pci_asante_21140_quirks(struct tulip_pci_softc *, 246 const uint8_t *); 247 static void tlp_pci_e100_quirks(struct tulip_pci_softc *, 248 const uint8_t *); 249 static void tlp_pci_phobos_21140_quirks(struct tulip_pci_softc *, 250 const uint8_t *); 251 static void tlp_pci_smc_21140_quirks(struct tulip_pci_softc *, 252 const uint8_t *); 253 static void tlp_pci_vpc_21140_quirks(struct tulip_pci_softc *, 254 const uint8_t *); 255 256 static const struct tlp_pci_quirks tlp_pci_21140_quirks[] = { 257 { tlp_pci_dec_quirks, { 0x08, 0x00, 0x2b } }, 258 { tlp_pci_dec_quirks, { 0x00, 0x00, 0xf8 } }, 259 { tlp_pci_e100_quirks, { 0x00, 0xa0, 0x59 } }, 260 { tlp_pci_asante_21140_quirks, { 0x00, 0x00, 0x94 } }, 261 { tlp_pci_adaptec_quirks, { 0x00, 0x00, 0x92 } }, 262 { tlp_pci_adaptec_quirks, { 0x00, 0x00, 0xd1 } }, 263 { tlp_pci_phobos_21140_quirks, { 0x00, 0x60, 0xf5 } }, 264 { tlp_pci_smc_21140_quirks, { 0x00, 0x00, 0xc0 } }, 265 { tlp_pci_vpc_21140_quirks, { 0x00, 0x03, 0xff } }, 266 { NULL, { 0, 0, 0 } } 267 }; 268 269 static const struct tlp_pci_quirks tlp_pci_21142_quirks[] = { 270 { tlp_pci_dec_quirks, { 0x08, 0x00, 0x2b } }, 271 { tlp_pci_dec_quirks, { 0x00, 0x00, 0xf8 } }, 272 { tlp_pci_cobalt_21142_quirks, { 0x00, 0x10, 0xe0 } }, 273 { tlp_pci_algor_21142_quirks, { 0x00, 0x40, 0xbc } }, 274 { tlp_pci_adaptec_quirks, { 0x00, 0x00, 0xd1 } }, 275 { tlp_pci_netwinder_21142_quirks,{ 0x00, 0x10, 0x57 } }, 276 { tlp_pci_phobos_21142_quirks, { 0x00, 0x60, 0xf5 } }, 277 { tlp_pci_znyx_21142_quirks, { 0x00, 0xc0, 0x95 } }, 278 { NULL, { 0, 0, 0 } } 279 }; 280 281 static int tlp_pci_shared_intr(void *); 282 283 static void 284 tlp_pci_get_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr, 285 const struct tlp_pci_quirks *tpq) 286 { 287 288 for (; tpq->tpq_func != NULL; tpq++) { 289 if (tpq->tpq_oui[0] == enaddr[0] && 290 tpq->tpq_oui[1] == enaddr[1] && 291 tpq->tpq_oui[2] == enaddr[2]) { 292 (*tpq->tpq_func)(psc, enaddr); 293 return; 294 } 295 } 296 } 297 298 static void 299 tlp_pci_check_slaved(struct tulip_pci_softc *psc, int shared, int slaved) 300 { 301 extern struct cfdriver tlp_cd; 302 struct tulip_pci_softc *cur, *best = NULL; 303 struct tulip_softc *sc = &psc->sc_tulip; 304 int i; 305 306 /* 307 * First of all, find the lowest pcidev numbered device on our 308 * bus marked as shared. That should be our master. 309 */ 310 for (i = 0; i < tlp_cd.cd_ndevs; i++) { 311 if ((cur = device_lookup_private(&tlp_cd, i)) == NULL) 312 continue; 313 if (device_parent(cur->sc_tulip.sc_dev) != 314 device_parent(sc->sc_dev)) 315 continue; 316 if ((cur->sc_flags & shared) == 0) 317 continue; 318 if (cur == psc) 319 continue; 320 if (best == NULL || 321 best->sc_tulip.sc_devno > cur->sc_tulip.sc_devno) 322 best = cur; 323 } 324 325 if (best != NULL) { 326 psc->sc_master = best; 327 psc->sc_flags |= (shared | slaved); 328 } 329 } 330 331 static int 332 tlp_pci_match(device_t parent, cfdata_t match, void *aux) 333 { 334 struct pci_attach_args *pa = aux; 335 336 if (pci_compatible_match(pa, compat_data)) { 337 /* Don't match lmc cards */ 338 const pcireg_t subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, 339 PCI_SUBSYS_ID_REG); 340 if (PCI_VENDOR(subsys) == PCI_VENDOR_LMC) { 341 return 0; 342 } 343 return 10; /* beat if_de.c */ 344 } 345 return 0; 346 } 347 348 static void 349 tlp_pci_attach(device_t parent, device_t self, void *aux) 350 { 351 struct tulip_pci_softc *psc = device_private(self); 352 struct tulip_softc *sc = &psc->sc_tulip; 353 struct pci_attach_args *pa = aux; 354 pci_chipset_tag_t pc = pa->pa_pc; 355 pci_intr_handle_t ih; 356 const char *intrstr = NULL; 357 bus_space_tag_t iot, memt; 358 bus_space_handle_t ioh, memh; 359 int ioh_valid, memh_valid, i, j; 360 const struct device_compatible_entry *dce; 361 prop_data_t ea; 362 uint8_t enaddr[ETHER_ADDR_LEN]; 363 uint32_t val = 0; 364 pcireg_t reg; 365 int error; 366 bus_size_t iosize = 0, memsize = 0; 367 char intrbuf[PCI_INTRSTR_LEN]; 368 369 sc->sc_dev = self; 370 sc->sc_devno = pa->pa_device; 371 psc->sc_pc = pa->pa_pc; 372 psc->sc_pcitag = pa->pa_tag; 373 374 LIST_INIT(&psc->sc_intrslaves); 375 376 dce = pci_compatible_lookup(pa, compat_data); 377 KASSERT(dce != NULL); 378 sc->sc_chip = (tulip_chip_t)dce->value; 379 380 /* 381 * By default, Tulip registers are 8 bytes long (4 bytes 382 * followed by a 4 byte pad). 383 */ 384 sc->sc_regshift = 3; 385 386 /* 387 * No power management hooks. 388 * XXX Maybe we should add some! 389 */ 390 sc->sc_flags |= TULIPF_ENABLED; 391 392 /* 393 * Get revision info, and set some chip-specific variables. 394 */ 395 sc->sc_rev = PCI_REVISION(pa->pa_class); 396 switch (sc->sc_chip) { 397 case TULIP_CHIP_21140: 398 if (sc->sc_rev >= 0x20) 399 sc->sc_chip = TULIP_CHIP_21140A; 400 break; 401 402 case TULIP_CHIP_21142: 403 if (sc->sc_rev >= 0x20) 404 sc->sc_chip = TULIP_CHIP_21143; 405 break; 406 407 case TULIP_CHIP_82C168: 408 if (sc->sc_rev >= 0x20) 409 sc->sc_chip = TULIP_CHIP_82C169; 410 break; 411 412 case TULIP_CHIP_MX98713: 413 if (sc->sc_rev >= 0x10) 414 sc->sc_chip = TULIP_CHIP_MX98713A; 415 break; 416 417 case TULIP_CHIP_MX98715: 418 if (sc->sc_rev >= 0x20) 419 sc->sc_chip = TULIP_CHIP_MX98715A; 420 if (sc->sc_rev >= 0x25) 421 sc->sc_chip = TULIP_CHIP_MX98715AEC_X; 422 if (sc->sc_rev >= 0x30) 423 sc->sc_chip = TULIP_CHIP_MX98725; 424 break; 425 426 case TULIP_CHIP_WB89C840F: 427 sc->sc_regshift = 2; 428 break; 429 430 case TULIP_CHIP_AN985: 431 /* 432 * The AN983 and AN985 are very similar, and are 433 * differentiated by a "signature" register that 434 * is like, but not identical, to a PCI ID register. 435 */ 436 reg = pci_conf_read(pc, pa->pa_tag, 0x80); 437 switch (reg) { 438 case 0x09811317: 439 sc->sc_chip = TULIP_CHIP_AN985; 440 break; 441 442 case 0x09851317: 443 sc->sc_chip = TULIP_CHIP_AN983; 444 break; 445 446 default: 447 /* Unknown -- use default. */ 448 break; 449 } 450 break; 451 452 case TULIP_CHIP_AX88140: 453 if (sc->sc_rev >= 0x10) 454 sc->sc_chip = TULIP_CHIP_AX88141; 455 break; 456 457 case TULIP_CHIP_DM9102: 458 if (sc->sc_rev >= 0x30) 459 sc->sc_chip = TULIP_CHIP_DM9102A; 460 break; 461 462 default: 463 /* Nothing. */ 464 break; 465 } 466 467 aprint_normal(": %s Ethernet, pass %d.%d\n", 468 tlp_chip_name(sc->sc_chip), 469 (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf); 470 471 switch (sc->sc_chip) { 472 case TULIP_CHIP_21040: 473 if (sc->sc_rev < 0x20) { 474 aprint_normal_dev(self, 475 "21040 must be at least pass 2.0\n"); 476 return; 477 } 478 break; 479 480 case TULIP_CHIP_21140: 481 if (sc->sc_rev < 0x11) { 482 aprint_normal_dev(self, 483 "21140 must be at least pass 1.1\n"); 484 return; 485 } 486 break; 487 488 default: 489 /* Nothing. */ 490 break; 491 } 492 493 /* 494 * Check to see if the device is in power-save mode, and 495 * being it out if necessary. 496 */ 497 switch (sc->sc_chip) { 498 case TULIP_CHIP_21140: 499 case TULIP_CHIP_21140A: 500 case TULIP_CHIP_21142: 501 case TULIP_CHIP_21143: 502 case TULIP_CHIP_MX98713A: 503 case TULIP_CHIP_MX98715: 504 case TULIP_CHIP_MX98715A: 505 case TULIP_CHIP_MX98715AEC_X: 506 case TULIP_CHIP_MX98725: 507 case TULIP_CHIP_DM9102: 508 case TULIP_CHIP_DM9102A: 509 case TULIP_CHIP_AX88140: 510 case TULIP_CHIP_AX88141: 511 case TULIP_CHIP_RS7112: 512 /* 513 * Clear the "sleep mode" bit in the CFDA register. 514 */ 515 reg = pci_conf_read(pc, pa->pa_tag, TULIP_PCI_CFDA); 516 if (reg & (CFDA_SLEEP | CFDA_SNOOZE)) 517 pci_conf_write(pc, pa->pa_tag, TULIP_PCI_CFDA, 518 reg & ~(CFDA_SLEEP | CFDA_SNOOZE)); 519 break; 520 521 default: 522 /* Nothing. */ 523 break; 524 } 525 526 /* power up chip */ 527 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 528 NULL)) && error != EOPNOTSUPP) { 529 aprint_error_dev(self, "cannot activate %d\n", error); 530 return; 531 } 532 533 /* 534 * Map the device. 535 */ 536 537 ioh_valid = (pci_mapreg_map(pa, TULIP_PCI_IOBA, 538 PCI_MAPREG_TYPE_IO, 0, 539 &iot, &ioh, NULL, &iosize) == 0); 540 memh_valid = (pci_mapreg_map(pa, TULIP_PCI_MMBA, 541 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 542 &memt, &memh, NULL, &memsize) == 0); 543 if (memh_valid) { 544 sc->sc_st = memt; 545 sc->sc_sh = memh; 546 psc->sc_mapsize = memsize; 547 if (ioh_valid) { 548 bus_space_unmap(iot, ioh, iosize); 549 ioh_valid = 0; 550 } 551 } else if (ioh_valid) { 552 sc->sc_st = iot; 553 sc->sc_sh = ioh; 554 psc->sc_mapsize = iosize; 555 if (memh_valid) { 556 bus_space_unmap(memt, memh, memsize); 557 memh_valid = 0; 558 } 559 } else { 560 aprint_error_dev(self, "unable to map device registers\n"); 561 goto fail; 562 } 563 564 sc->sc_dmat = pa->pa_dmat; 565 566 /* 567 * Make sure bus mastering is enabled. 568 */ 569 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 570 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 571 PCI_COMMAND_MASTER_ENABLE); 572 573 /* 574 * Get the cacheline size. 575 */ 576 sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag, 577 PCI_BHLC_REG)); 578 579 /* 580 * Get PCI data moving command info. 581 */ 582 if (pa->pa_flags & PCI_FLAGS_MRL_OKAY) 583 sc->sc_flags |= TULIPF_MRL; 584 if (pa->pa_flags & PCI_FLAGS_MRM_OKAY) 585 sc->sc_flags |= TULIPF_MRM; 586 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 587 sc->sc_flags |= TULIPF_MWI; 588 589 /* 590 * Read the contents of the Ethernet Address ROM/SROM. 591 */ 592 switch (sc->sc_chip) { 593 case TULIP_CHIP_21040: 594 sc->sc_srom_addrbits = 6; 595 sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF, M_WAITOK); 596 TULIP_WRITE(sc, CSR_MIIROM, MIIROM_SROMCS); 597 for (i = 0; i < TULIP_ROM_SIZE(6); i++) { 598 for (j = 0; j < 10000; j++) { 599 val = TULIP_READ(sc, CSR_MIIROM); 600 if ((val & MIIROM_DN) == 0) 601 break; 602 } 603 sc->sc_srom[i] = val & MIIROM_DATA; 604 } 605 break; 606 607 case TULIP_CHIP_82C168: 608 case TULIP_CHIP_82C169: 609 { 610 sc->sc_srom_addrbits = 2; 611 sc->sc_srom = malloc(TULIP_ROM_SIZE(2), M_DEVBUF, M_WAITOK); 612 613 /* 614 * The Lite-On PNIC stores the Ethernet address in 615 * the first 3 words of the EEPROM. EEPROM access 616 * is not like the other Tulip chips. 617 */ 618 for (i = 0; i < 6; i += 2) { 619 TULIP_WRITE(sc, CSR_PNIC_SROMCTL, 620 PNIC_SROMCTL_READ | (i >> 1)); 621 for (j = 0; j < 500; j++) { 622 delay(2); 623 val = TULIP_READ(sc, CSR_MIIROM); 624 if ((val & PNIC_MIIROM_BUSY) == 0) 625 break; 626 } 627 if (val & PNIC_MIIROM_BUSY) { 628 aprint_error_dev(self, "EEPROM timed out\n"); 629 goto fail; 630 } 631 val &= PNIC_MIIROM_DATA; 632 sc->sc_srom[i] = val >> 8; 633 sc->sc_srom[i + 1] = val & 0xff; 634 } 635 break; 636 } 637 638 default: 639 /* 640 * XXX This isn't quite the right way to do this; we should 641 * XXX be attempting to fetch the mac-addr property in the 642 * XXX bus-agnostic part of the driver independently. But 643 * XXX that requires a larger change in the SROM handling 644 * XXX logic, and for now we can at least remove a machine- 645 * XXX dependent wart from the PCI front-end. 646 */ 647 ea = prop_dictionary_get(device_properties(self), 648 "mac-address"); 649 if (ea != NULL) { 650 extern int tlp_srom_debug; 651 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 652 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 653 654 memcpy(enaddr, prop_data_value(ea), 655 ETHER_ADDR_LEN); 656 657 sc->sc_srom_addrbits = 6; 658 sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF, 659 M_WAITOK | M_ZERO); 660 memcpy(sc->sc_srom, enaddr, sizeof(enaddr)); 661 if (tlp_srom_debug) { 662 aprint_normal("SROM CONTENTS:"); 663 for (i = 0; i < TULIP_ROM_SIZE(6); i++) { 664 if ((i % 8) == 0) 665 aprint_normal("\n\t"); 666 aprint_normal("0x%02x ", 667 sc->sc_srom[i]); 668 } 669 aprint_normal("\n"); 670 } 671 break; 672 } 673 674 /* Check for a slaved ROM on a multi-port board. */ 675 tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDROM, 676 TULIP_PCI_SLAVEROM); 677 if (psc->sc_flags & TULIP_PCI_SLAVEROM) { 678 sc->sc_srom_addrbits = 679 psc->sc_master->sc_tulip.sc_srom_addrbits; 680 sc->sc_srom = psc->sc_master->sc_tulip.sc_srom; 681 enaddr[5] += 682 sc->sc_devno - psc->sc_master->sc_tulip.sc_devno; 683 } 684 else if (tlp_read_srom(sc) == 0) 685 goto cant_cope; 686 break; 687 } 688 689 /* 690 * Deal with chip/board quirks. This includes setting up 691 * the mediasw, and extracting the Ethernet address from 692 * the rombuf. 693 */ 694 switch (sc->sc_chip) { 695 case TULIP_CHIP_21040: 696 /* 697 * Parse the Ethernet Address ROM. 698 */ 699 if (tlp_parse_old_srom(sc, enaddr) == 0) 700 goto cant_cope; 701 702 703 /* 704 * All 21040 boards start out with the same 705 * media switch. 706 */ 707 sc->sc_mediasw = &tlp_21040_mediasw; 708 709 /* 710 * Deal with any quirks this board might have. 711 */ 712 tlp_pci_get_quirks(psc, enaddr, tlp_pci_21040_quirks); 713 break; 714 715 case TULIP_CHIP_21041: 716 /* Check for new format SROM. */ 717 if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { 718 /* 719 * Not an ISV SROM; try the old DEC Ethernet Address 720 * ROM format. 721 */ 722 if (tlp_parse_old_srom(sc, enaddr) == 0) 723 goto cant_cope; 724 } 725 726 /* 727 * All 21041 boards use the same media switch; they all 728 * work basically the same! Yippee! 729 */ 730 sc->sc_mediasw = &tlp_21041_mediasw; 731 732 /* 733 * Deal with any quirks this board might have. 734 */ 735 tlp_pci_get_quirks(psc, enaddr, tlp_pci_21041_quirks); 736 break; 737 738 case TULIP_CHIP_21140: 739 case TULIP_CHIP_21140A: 740 /* Check for new format SROM. */ 741 if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { 742 /* 743 * Not an ISV SROM; try the old DEC Ethernet Address 744 * ROM format. 745 */ 746 if (tlp_parse_old_srom(sc, enaddr) == 0) 747 goto cant_cope; 748 } else { 749 /* 750 * We start out with the 2114x ISV media switch. 751 * When we search for quirks, we may change to 752 * a different switch. 753 */ 754 sc->sc_mediasw = &tlp_2114x_isv_mediasw; 755 } 756 757 /* 758 * Deal with any quirks this board might have. 759 */ 760 tlp_pci_get_quirks(psc, enaddr, tlp_pci_21140_quirks); 761 762 /* 763 * Bail out now if we can't deal with this board. 764 */ 765 if (sc->sc_mediasw == NULL) 766 goto cant_cope; 767 break; 768 769 case TULIP_CHIP_21142: 770 case TULIP_CHIP_21143: 771 /* Check for new format SROM. */ 772 if (tlp_isv_srom_enaddr(sc, enaddr) == 0) { 773 /* 774 * Not an ISV SROM; try the old DEC Ethernet Address 775 * ROM format. 776 */ 777 if (tlp_parse_old_srom(sc, enaddr) == 0) { 778 /* 779 * One last try: just copy the address 780 * from offset 20 and try to look 781 * up quirks. 782 */ 783 memcpy(enaddr, &sc->sc_srom[20], 784 ETHER_ADDR_LEN); 785 } 786 } else { 787 /* 788 * We start out with the 2114x ISV media switch. 789 * When we search for quirks, we may change to 790 * a different switch. 791 */ 792 sc->sc_mediasw = &tlp_2114x_isv_mediasw; 793 } 794 795 /* 796 * Deal with any quirks this board might have. 797 */ 798 tlp_pci_get_quirks(psc, enaddr, tlp_pci_21142_quirks); 799 800 /* 801 * Bail out now if we can't deal with this board. 802 */ 803 if (sc->sc_mediasw == NULL) 804 goto cant_cope; 805 break; 806 807 case TULIP_CHIP_82C168: 808 case TULIP_CHIP_82C169: 809 /* 810 * Lite-On PNIC's Ethernet address is the first 6 811 * bytes of its EEPROM. 812 */ 813 memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN); 814 815 /* 816 * Lite-On PNICs always use the same mediasw; we 817 * select MII vs. internal NWAY automatically. 818 */ 819 sc->sc_mediasw = &tlp_pnic_mediasw; 820 break; 821 822 case TULIP_CHIP_MX98713: 823 /* 824 * The Macronix MX98713 has an MII and GPIO, but no 825 * internal Nway block. This chip is basically a 826 * perfect 21140A clone, with the exception of the 827 * a magic register frobbing in order to make the 828 * interface function. 829 */ 830 if (tlp_isv_srom_enaddr(sc, enaddr)) { 831 sc->sc_mediasw = &tlp_2114x_isv_mediasw; 832 break; 833 } 834 /* FALLTHROUGH */ 835 836 case TULIP_CHIP_82C115: 837 /* 838 * Yippee! The Lite-On 82C115 is a clone of 839 * the MX98725 (the data sheet even says `MXIC' 840 * on it)! Imagine that, a clone of a clone. 841 * 842 * The differences are really minimal: 843 * 844 * - Wake-On-LAN support 845 * - 128-bit multicast hash table, rather than 846 * the standard 512-bit hash table 847 */ 848 /* FALLTHROUGH */ 849 850 case TULIP_CHIP_MX98713A: 851 case TULIP_CHIP_MX98715A: 852 case TULIP_CHIP_MX98715AEC_X: 853 case TULIP_CHIP_MX98725: 854 /* 855 * The MX98713A has an MII as well as an internal Nway block, 856 * but no GPIO. The MX98715 and MX98725 have an internal 857 * Nway block only. 858 * 859 * The internal Nway block, unlike the Lite-On PNIC's, does 860 * just that - performs Nway. Once autonegotiation completes, 861 * we must program the GPR media information into the chip. 862 * 863 * The byte offset of the Ethernet address is stored at 864 * offset 0x70. 865 */ 866 memcpy(enaddr, &sc->sc_srom[sc->sc_srom[0x70]], ETHER_ADDR_LEN); 867 sc->sc_mediasw = &tlp_pmac_mediasw; 868 break; 869 870 case TULIP_CHIP_WB89C840F: 871 /* 872 * Winbond 89C840F's Ethernet address is the first 873 * 6 bytes of its EEPROM. 874 */ 875 memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN); 876 877 /* 878 * Winbond 89C840F has an MII attached to the SIO. 879 */ 880 sc->sc_mediasw = &tlp_sio_mii_mediasw; 881 break; 882 883 case TULIP_CHIP_AL981: 884 /* 885 * The ADMtek AL981's Ethernet address is located 886 * at offset 8 of its EEPROM. 887 */ 888 memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN); 889 890 /* 891 * ADMtek AL981 has a built-in PHY accessed through 892 * special registers. 893 */ 894 sc->sc_mediasw = &tlp_al981_mediasw; 895 break; 896 897 case TULIP_CHIP_AN983: 898 case TULIP_CHIP_AN985: 899 /* 900 * The ADMtek AN985's Ethernet address is located 901 * at offset 8 of its EEPROM. 902 */ 903 memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN); 904 905 /* 906 * The ADMtek AN985 can be configured in Single-Chip 907 * mode or MAC-only mode. Single-Chip uses the built-in 908 * PHY, MAC-only has an external PHY (usually HomePNA). 909 * The selection is based on an EEPROM setting, and both 910 * PHYs are accessed via MII attached to SIO. 911 * 912 * The AN985 "ghosts" the internal PHY onto all 913 * MII addresses, so we have to use a media init 914 * routine that limits the search. 915 * XXX How does this work with MAC-only mode? 916 */ 917 sc->sc_mediasw = &tlp_an985_mediasw; 918 break; 919 920 case TULIP_CHIP_DM9102: 921 case TULIP_CHIP_DM9102A: 922 /* 923 * Some boards with the Davicom chip have an ISV 924 * SROM (mostly DM9102A boards -- trying to describe 925 * the HomePNA PHY, probably) although the data in 926 * them is generally wrong. Check for ISV format 927 * and grab the Ethernet address that way, and if 928 * that fails, fall back on grabbing it from an 929 * observed offset of 20 (which is where it would 930 * be in an ISV SROM anyhow, tho ISV can cope with 931 * multi-port boards). 932 */ 933 if (!tlp_isv_srom_enaddr(sc, enaddr)) { 934 935 prop_data_t eaddrprop; 936 937 eaddrprop = prop_dictionary_get( 938 device_properties(self), "mac-address"); 939 940 if (eaddrprop != NULL 941 && prop_data_size(eaddrprop) == ETHER_ADDR_LEN) 942 memcpy(enaddr, 943 prop_data_value(eaddrprop), 944 ETHER_ADDR_LEN); 945 else 946 memcpy(enaddr, &sc->sc_srom[20], 947 ETHER_ADDR_LEN); 948 } 949 950 /* 951 * Davicom chips all have an internal MII interface 952 * and a built-in PHY. DM9102A also has a an external 953 * MII interface, usually with a HomePNA PHY attached 954 * to it. 955 */ 956 sc->sc_mediasw = &tlp_dm9102_mediasw; 957 break; 958 959 case TULIP_CHIP_AX88140: 960 case TULIP_CHIP_AX88141: 961 /* 962 * ASIX AX88140/AX88141 Ethernet Address is located at offset 963 * 20 of the SROM. 964 */ 965 memcpy(enaddr, &sc->sc_srom[20], ETHER_ADDR_LEN); 966 967 /* 968 * ASIX AX88140A/AX88141 chip can have a built-in PHY or 969 * an external MII interface. 970 */ 971 sc->sc_mediasw = &tlp_asix_mediasw; 972 break; 973 974 case TULIP_CHIP_RS7112: 975 /* 976 * RS7112 Ethernet Address is located of offset 0x19a 977 * of the SROM 978 */ 979 memcpy(enaddr, &sc->sc_srom[0x19a], ETHER_ADDR_LEN); 980 981 /* RS7112 chip has a PHY at MII address 1 */ 982 sc->sc_mediasw = &tlp_rs7112_mediasw; 983 break; 984 985 default: 986 cant_cope: 987 aprint_error_dev(self, "sorry, unable to handle your board\n"); 988 goto fail; 989 } 990 991 /* 992 * Handle shared interrupts. 993 */ 994 if (psc->sc_flags & TULIP_PCI_SHAREDINTR) { 995 if (psc->sc_master) 996 psc->sc_flags |= TULIP_PCI_SLAVEINTR; 997 else { 998 tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDINTR, 999 TULIP_PCI_SLAVEINTR); 1000 if (psc->sc_master == NULL) 1001 psc->sc_master = psc; 1002 } 1003 LIST_INSERT_HEAD(&psc->sc_master->sc_intrslaves, 1004 psc, sc_intrq); 1005 } 1006 1007 if (psc->sc_flags & TULIP_PCI_SLAVEINTR) { 1008 aprint_normal_dev(self, "sharing interrupt with %s\n", 1009 device_xname(psc->sc_master->sc_tulip.sc_dev)); 1010 } else { 1011 /* 1012 * Map and establish our interrupt. 1013 */ 1014 if (pci_intr_map(pa, &ih)) { 1015 aprint_error_dev(self, "unable to map interrupt\n"); 1016 goto fail; 1017 } 1018 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1019 psc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, 1020 (psc->sc_flags & TULIP_PCI_SHAREDINTR) ? 1021 tlp_pci_shared_intr : tlp_intr, sc, device_xname(self)); 1022 if (psc->sc_ih == NULL) { 1023 aprint_error_dev(self, "unable to establish interrupt"); 1024 if (intrstr != NULL) 1025 aprint_error(" at %s", intrstr); 1026 aprint_error("\n"); 1027 goto fail; 1028 } 1029 aprint_normal_dev(self, "interrupting at %s\n", 1030 intrstr); 1031 } 1032 1033 /* 1034 * Finish off the attach. 1035 */ 1036 error = tlp_attach(sc, enaddr); 1037 if (error) 1038 goto fail; 1039 return; 1040 1041 fail: 1042 if (psc->sc_ih != NULL) { 1043 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 1044 psc->sc_ih = NULL; 1045 } 1046 1047 if (ioh_valid) 1048 bus_space_unmap(iot, ioh, iosize); 1049 if (memh_valid) 1050 bus_space_unmap(memt, memh, memsize); 1051 psc->sc_mapsize = 0; 1052 return; 1053 } 1054 1055 static int 1056 tlp_pci_detach(device_t self, int flags) 1057 { 1058 struct tulip_pci_softc *psc = device_private(self); 1059 struct tulip_softc *sc = &psc->sc_tulip; 1060 int rv; 1061 1062 rv = tlp_detach(sc); 1063 if (rv) 1064 return rv; 1065 1066 if (psc->sc_ih != NULL) { 1067 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 1068 psc->sc_ih = NULL; 1069 } 1070 1071 if (psc->sc_mapsize) { 1072 bus_space_unmap(sc->sc_st, sc->sc_sh, psc->sc_mapsize); 1073 psc->sc_mapsize = 0; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int 1080 tlp_pci_shared_intr(void *arg) 1081 { 1082 struct tulip_pci_softc *master = arg, *slave; 1083 int rv = 0; 1084 1085 for (slave = LIST_FIRST(&master->sc_intrslaves); 1086 slave != NULL; 1087 slave = LIST_NEXT(slave, sc_intrq)) 1088 rv |= tlp_intr(&slave->sc_tulip); 1089 1090 return rv; 1091 } 1092 1093 static void 1094 tlp_pci_dec_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1095 { 1096 struct tulip_softc *sc = &psc->sc_tulip; 1097 1098 /* 1099 * This isn't really a quirk-gathering device, really. We 1100 * just want to get the spiffy DEC board name from the SROM. 1101 */ 1102 strcpy(sc->sc_name, "DEC "); 1103 1104 if (memcmp(&sc->sc_srom[29], "DE500", 5) == 0 || 1105 memcmp(&sc->sc_srom[29], "DE450", 5) == 0) 1106 memcpy(&sc->sc_name[4], &sc->sc_srom[29], 8); 1107 else 1108 sc->sc_name[3] = '\0'; 1109 } 1110 1111 static void 1112 tlp_pci_znyx_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1113 { 1114 struct tulip_softc *sc = &psc->sc_tulip; 1115 uint16_t id = 0; 1116 1117 /* 1118 * If we have a slaved ROM, just copy the bits from the master. 1119 * This is in case we fail the ROM ID check (older boards) and 1120 * need to fall back on Ethernet address model checking; that 1121 * will fail for slave chips. 1122 */ 1123 if (psc->sc_flags & TULIP_PCI_SLAVEROM) { 1124 strcpy(sc->sc_name, psc->sc_master->sc_tulip.sc_name); 1125 sc->sc_mediasw = psc->sc_master->sc_tulip.sc_mediasw; 1126 psc->sc_flags |= 1127 psc->sc_master->sc_flags & TULIP_PCI_SHAREDINTR; 1128 return; 1129 } 1130 1131 if (sc->sc_srom[32] == 0x4a && sc->sc_srom[33] == 0x52) { 1132 id = sc->sc_srom[37] | (sc->sc_srom[36] << 8); 1133 switch (id) { 1134 zx312: 1135 case 0x0602: /* ZX312 */ 1136 strcpy(sc->sc_name, "ZNYX ZX312"); 1137 return; 1138 1139 case 0x0622: /* ZX312T */ 1140 strcpy(sc->sc_name, "ZNYX ZX312T"); 1141 sc->sc_mediasw = &tlp_21040_tp_mediasw; 1142 return; 1143 1144 zx314_inta: 1145 case 0x0701: /* ZX314 INTA */ 1146 psc->sc_flags |= TULIP_PCI_SHAREDINTR; 1147 /* FALLTHROUGH */ 1148 case 0x0711: /* ZX314 */ 1149 strcpy(sc->sc_name, "ZNYX ZX314"); 1150 psc->sc_flags |= TULIP_PCI_SHAREDROM; 1151 sc->sc_mediasw = &tlp_21040_tp_mediasw; 1152 return; 1153 1154 zx315_inta: 1155 case 0x0801: /* ZX315 INTA */ 1156 psc->sc_flags |= TULIP_PCI_SHAREDINTR; 1157 /* FALLTHROUGH */ 1158 case 0x0811: /* ZX315 */ 1159 strcpy(sc->sc_name, "ZNYX ZX315"); 1160 psc->sc_flags |= TULIP_PCI_SHAREDROM; 1161 return; 1162 1163 default: 1164 id = 0; 1165 break; 1166 } 1167 } 1168 1169 /* 1170 * Deal with boards that have broken ROMs. 1171 */ 1172 if (id == 0) { 1173 if ((enaddr[3] & ~3) == 0xf0 && (enaddr[5] & 3) == 0x00) 1174 goto zx314_inta; 1175 if ((enaddr[3] & ~3) == 0xf4 && (enaddr[5] & 1) == 0x00) 1176 goto zx315_inta; 1177 if ((enaddr[3] & ~3) == 0xec) 1178 goto zx312; 1179 } 1180 1181 strcpy(sc->sc_name, "ZNYX ZX31x"); 1182 } 1183 1184 static void tlp_pci_znyx_21142_qs6611_reset(struct tulip_softc *); 1185 1186 static void 1187 tlp_pci_znyx_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1188 { 1189 struct tulip_softc *sc = &psc->sc_tulip; 1190 pcireg_t subid; 1191 1192 subid = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_SUBSYS_ID_REG); 1193 1194 if (PCI_VENDOR(subid) != PCI_VENDOR_ZNYX) 1195 return; /* ? */ 1196 1197 switch (PCI_PRODUCT(subid) & 0xff) { 1198 /* 1199 * ZNYX 21143 boards with QS6611 PHY 1200 */ 1201 case 0x12: /* ZX345Q */ 1202 case 0x13: /* ZX346Q */ 1203 case 0x14: /* ZX348Q */ 1204 case 0x18: /* ZX414 */ 1205 case 0x19: /* ZX412 */ 1206 case 0x1a: /* ZX444 */ 1207 case 0x1b: /* ZX442 */ 1208 case 0x23: /* ZX212 */ 1209 case 0x24: /* ZX214 */ 1210 case 0x29: /* ZX374 */ 1211 case 0x2d: /* ZX372 */ 1212 case 0x2b: /* ZX244 */ 1213 case 0x2c: /* ZX424 */ 1214 case 0x2e: /* ZX422 */ 1215 aprint_normal_dev(sc->sc_dev, "QS6611 PHY\n"); 1216 sc->sc_reset = tlp_pci_znyx_21142_qs6611_reset; 1217 break; 1218 } 1219 } 1220 1221 static void 1222 tlp_pci_znyx_21142_qs6611_reset(struct tulip_softc *sc) 1223 { 1224 1225 /* 1226 * Reset QS6611 PHY. 1227 */ 1228 TULIP_WRITE(sc, CSR_SIAGEN, 1229 SIAGEN_CWE | SIAGEN_LGS1 | SIAGEN_ABM | (0xf << 16)); 1230 delay(200); 1231 TULIP_WRITE(sc, CSR_SIAGEN, (0x4 << 16)); 1232 delay(10000); 1233 } 1234 1235 static void 1236 tlp_pci_smc_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1237 { 1238 struct tulip_softc *sc = &psc->sc_tulip; 1239 uint16_t id1, id2, ei; 1240 int auibnc = 0, utp = 0; 1241 char *cp; 1242 1243 id1 = sc->sc_srom[0x60] | (sc->sc_srom[0x61] << 8); 1244 id2 = sc->sc_srom[0x62] | (sc->sc_srom[0x63] << 8); 1245 ei = sc->sc_srom[0x66] | (sc->sc_srom[0x67] << 8); 1246 1247 strcpy(sc->sc_name, "SMC 8432"); 1248 cp = &sc->sc_name[8]; 1249 1250 if ((id1 & 1) == 0) { 1251 *cp++ = 'B'; 1252 auibnc = 1; 1253 } 1254 if ((id1 & 0xff) > 0x32) { 1255 *cp++ = 'T'; 1256 utp = 1; 1257 } 1258 if ((id1 & 0x4000) == 0) { 1259 *cp++ = 'A'; 1260 auibnc = 1; 1261 } 1262 if (id2 == 0x15) { 1263 sc->sc_name[7] = '4'; 1264 *cp++ = '-'; 1265 *cp++ = 'C'; 1266 *cp++ = 'H'; 1267 *cp++ = ei ? '2' : '1'; 1268 } 1269 *cp = '\0'; 1270 1271 if (utp != 0 && auibnc == 0) 1272 sc->sc_mediasw = &tlp_21040_tp_mediasw; 1273 else if (utp == 0 && auibnc != 0) 1274 sc->sc_mediasw = &tlp_21040_auibnc_mediasw; 1275 } 1276 1277 static void 1278 tlp_pci_cogent_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1279 { 1280 1281 strcpy(psc->sc_tulip.sc_name, "Cogent multi-port"); 1282 psc->sc_flags |= TULIP_PCI_SHAREDINTR | TULIP_PCI_SHAREDROM; 1283 } 1284 1285 static void 1286 tlp_pci_accton_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1287 { 1288 1289 strcpy(psc->sc_tulip.sc_name, "ACCTON EN1203"); 1290 } 1291 1292 static void tlp_pci_asante_21140_reset(struct tulip_softc *); 1293 1294 static void 1295 tlp_pci_asante_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1296 { 1297 struct tulip_softc *sc = &psc->sc_tulip; 1298 1299 /* 1300 * Some Asante boards don't use the ISV SROM format. For 1301 * those that don't, we initialize the GPIO direction bits, 1302 * and provide our own reset hook, which resets the MII. 1303 * 1304 * All of these boards use SIO-attached-MII media. 1305 */ 1306 if (sc->sc_mediasw == &tlp_2114x_isv_mediasw) 1307 return; 1308 1309 strcpy(sc->sc_name, "Asante"); 1310 1311 sc->sc_gp_dir = 0xbf; 1312 sc->sc_reset = tlp_pci_asante_21140_reset; 1313 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1314 } 1315 1316 static void 1317 tlp_pci_e100_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1318 { 1319 struct tulip_softc *sc = &psc->sc_tulip; 1320 1321 if (sc->sc_mediasw == &tlp_2114x_isv_mediasw) 1322 return; 1323 1324 strcpy(sc->sc_name, "UMAX E100"); 1325 1326 sc->sc_gp_dir = 0xbf; 1327 sc->sc_reset = tlp_pci_asante_21140_reset; 1328 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1329 } 1330 1331 static void 1332 tlp_pci_asante_21140_reset(struct tulip_softc *sc) 1333 { 1334 1335 TULIP_WRITE(sc, CSR_GPP, GPP_GPC | sc->sc_gp_dir); 1336 TULIP_WRITE(sc, CSR_GPP, 0x8); 1337 delay(100); 1338 TULIP_WRITE(sc, CSR_GPP, 0); 1339 } 1340 1341 static void tlp_pci_phobos_21140_reset(struct tulip_softc *); 1342 1343 static void 1344 tlp_pci_phobos_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1345 { 1346 struct tulip_softc *sc = &psc->sc_tulip; 1347 1348 /* 1349 * Phobos boards just use MII-on-SIO. 1350 */ 1351 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1352 sc->sc_reset = tlp_pci_phobos_21140_reset; 1353 1354 /* 1355 * These boards appear solely on sgimips machines behind a special 1356 * GIO<->PCI ASIC and require the DBO and BLE bits to be set in CSR0. 1357 */ 1358 sc->sc_flags |= (TULIPF_BLE | TULIPF_DBO); 1359 } 1360 1361 static void 1362 tlp_pci_phobos_21140_reset(struct tulip_softc *sc) 1363 { 1364 1365 TULIP_WRITE(sc, CSR_GPP, GPP_GPC | 0xfd); 1366 delay(10); 1367 TULIP_WRITE(sc, CSR_GPP, 0xfd); 1368 delay(10); 1369 TULIP_WRITE(sc, CSR_GPP, 0); 1370 } 1371 1372 /* 1373 * SMC 9332DST media switch. 1374 */ 1375 static void tlp_smc9332dst_tmsw_init(struct tulip_softc *); 1376 1377 static const struct tulip_mediasw tlp_smc9332dst_mediasw = { 1378 tlp_smc9332dst_tmsw_init, 1379 tlp_21140_gpio_get, 1380 tlp_21140_gpio_set 1381 }; 1382 1383 static void 1384 tlp_pci_smc_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1385 { 1386 struct tulip_softc *sc = &psc->sc_tulip; 1387 1388 strcpy(psc->sc_tulip.sc_name, "SMC 9332DST"); 1389 sc->sc_mediasw = &tlp_smc9332dst_mediasw; 1390 } 1391 1392 static void 1393 tlp_smc9332dst_tmsw_init(struct tulip_softc *sc) 1394 { 1395 struct tulip_21x4x_media *tm; 1396 struct mii_data *mii = &sc->sc_mii; 1397 const char *sep = ""; 1398 uint32_t reg; 1399 int i, cnt; 1400 1401 sc->sc_gp_dir = GPP_SMC9332DST_PINS; 1402 sc->sc_opmode = OPMODE_MBO | OPMODE_PS; 1403 TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode); 1404 1405 ifmedia_init(&mii->mii_media, 0, tlp_mediachange, tlp_mediastatus); 1406 aprint_normal_dev(sc->sc_dev, ""); 1407 1408 #define ADD(m, c) \ 1409 tm = malloc(sizeof(*tm), M_DEVBUF, M_WAITOK | M_ZERO); \ 1410 tm->tm_opmode = (c); \ 1411 tm->tm_gpdata = GPP_SMC9332DST_INIT; \ 1412 ifmedia_add(&mii->mii_media, (m), 0, tm) 1413 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 1414 1415 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, 0), OPMODE_TTM); 1416 PRINT("10baseT"); 1417 1418 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, 0), 1419 OPMODE_TTM | OPMODE_FD); 1420 PRINT("10baseT-FDX"); 1421 1422 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, 0), 1423 OPMODE_PS | OPMODE_PCS | OPMODE_SCR); 1424 PRINT("100baseTX"); 1425 1426 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, 0), 1427 OPMODE_PS | OPMODE_PCS | OPMODE_SCR | OPMODE_FD); 1428 PRINT("100baseTX-FDX"); 1429 1430 #undef ADD 1431 #undef PRINT 1432 1433 aprint_normal("\n"); 1434 1435 tlp_reset(sc); 1436 TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode | OPMODE_PCS | OPMODE_SCR); 1437 TULIP_WRITE(sc, CSR_GPP, GPP_GPC | sc->sc_gp_dir); 1438 delay(10); 1439 TULIP_WRITE(sc, CSR_GPP, GPP_SMC9332DST_INIT); 1440 delay(200000); 1441 cnt = 0; 1442 for (i = 1000; i > 0; i--) { 1443 reg = TULIP_READ(sc, CSR_GPP); 1444 if ((~reg & (GPP_SMC9332DST_OK10 | 1445 GPP_SMC9332DST_OK100)) == 0) { 1446 if (cnt++ > 100) { 1447 break; 1448 } 1449 } else if ((reg & GPP_SMC9332DST_OK10) == 0) { 1450 break; 1451 } else { 1452 cnt = 0; 1453 } 1454 delay(1000); 1455 } 1456 if (cnt > 100) 1457 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_100_TX); 1458 else 1459 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_10_T); 1460 } 1461 1462 static void 1463 tlp_pci_vpc_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1464 { 1465 struct tulip_softc *sc = &psc->sc_tulip; 1466 char *p1 = (char *)&sc->sc_srom[32]; 1467 char *p2 = &sc->sc_name[0]; 1468 1469 do { 1470 if ((unsigned char) *p1 & 0x80) 1471 *p2++ = ' '; 1472 else 1473 *p2++ = *p1; 1474 } while (*p1++); 1475 } 1476 1477 static void tlp_pci_cobalt_21142_reset(struct tulip_softc *); 1478 1479 static void 1480 tlp_pci_cobalt_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1481 { 1482 struct tulip_softc *sc = &psc->sc_tulip; 1483 1484 /* 1485 * Cobalt Networks interfaces are just MII-on-SIO. 1486 */ 1487 sc->sc_reset = tlp_pci_cobalt_21142_reset; 1488 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1489 1490 /* 1491 * The Cobalt systems tend to fall back to store-and-forward 1492 * pretty quickly, so we select that from the beginning to 1493 * avoid initial timeouts. 1494 */ 1495 sc->sc_txthresh = TXTH_SF; 1496 } 1497 1498 static void 1499 tlp_pci_cobalt_21142_reset(struct tulip_softc *sc) 1500 { 1501 1502 /* 1503 * Reset PHY. 1504 */ 1505 TULIP_WRITE(sc, CSR_SIAGEN, SIAGEN_CWE | (1 << 16)); 1506 delay(10); 1507 TULIP_WRITE(sc, CSR_SIAGEN, SIAGEN_CWE); 1508 delay(10); 1509 } 1510 1511 static void 1512 tlp_pci_algor_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1513 { 1514 struct tulip_softc *sc = &psc->sc_tulip; 1515 1516 /* 1517 * Algorithmics boards just have MII-on-SIO. 1518 * 1519 * XXX They also have AUI on the serial interface. 1520 * XXX Deal with this. 1521 */ 1522 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1523 } 1524 1525 /* 1526 * Cogent EM1x0 (aka. Adaptec ANA-6910) media switch. 1527 */ 1528 static void tlp_cogent_em1x0_tmsw_init(struct tulip_softc *); 1529 1530 static const struct tulip_mediasw tlp_cogent_em1x0_mediasw = { 1531 tlp_cogent_em1x0_tmsw_init, 1532 tlp_21140_gpio_get, 1533 tlp_21140_gpio_set 1534 }; 1535 1536 static void 1537 tlp_pci_adaptec_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1538 { 1539 struct tulip_softc *sc = &psc->sc_tulip; 1540 uint8_t *srom = sc->sc_srom, id0; 1541 uint16_t id1, id2; 1542 1543 if (sc->sc_mediasw == NULL) { 1544 id0 = srom[32]; 1545 switch (id0) { 1546 case 0x12: 1547 strcpy(psc->sc_tulip.sc_name, "Cogent EM100TX"); 1548 sc->sc_mediasw = &tlp_cogent_em1x0_mediasw; 1549 break; 1550 1551 case 0x13: 1552 strcpy(psc->sc_tulip.sc_name, "Cogent ???"); 1553 sc->sc_mediasw = &tlp_cogent_em1x0_mediasw; 1554 psc->sc_flags |= TULIP_PCI_SHAREDINTR | 1555 TULIP_PCI_SHAREDROM; 1556 break; 1557 1558 case 0x15: 1559 strcpy(psc->sc_tulip.sc_name, "Cogent EM100FX"); 1560 sc->sc_mediasw = &tlp_cogent_em1x0_mediasw; 1561 break; 1562 1563 #if 0 1564 case XXX: 1565 strcpy(psc->sc_tulip.sc_name, "Cogent EM110TX"); 1566 sc->sc_mediasw = &tlp_cogent_em1x0_mediasw; 1567 break; 1568 #endif 1569 1570 default: 1571 printf("%s: unknown Cogent board ID 0x%02x\n", 1572 device_xname(sc->sc_dev), id0); 1573 } 1574 return; 1575 } 1576 1577 id1 = TULIP_ROM_GETW(srom, 0); 1578 id2 = TULIP_ROM_GETW(srom, 2); 1579 if (id1 != 0x1109) { 1580 goto unknown; 1581 } 1582 1583 switch (id2) { 1584 case 0x1900: 1585 strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6911"); 1586 break; 1587 1588 case 0x2400: 1589 strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6944A"); 1590 psc->sc_flags |= TULIP_PCI_SHAREDINTR | TULIP_PCI_SHAREDROM; 1591 break; 1592 1593 case 0x2b00: 1594 strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6911A"); 1595 break; 1596 1597 case 0x3000: 1598 strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6922"); 1599 psc->sc_flags |= TULIP_PCI_SHAREDINTR | TULIP_PCI_SHAREDROM; 1600 break; 1601 1602 default: 1603 unknown: 1604 printf("%s: unknown Adaptec/Cogent board ID 0x%04x/0x%04x\n", 1605 device_xname(sc->sc_dev), id1, id2); 1606 } 1607 } 1608 1609 static void 1610 tlp_cogent_em1x0_tmsw_init(struct tulip_softc *sc) 1611 { 1612 struct tulip_21x4x_media *tm; 1613 struct mii_data *mii = &sc->sc_mii; 1614 const char *sep = ""; 1615 1616 sc->sc_gp_dir = GPP_COGENT_EM1x0_PINS; 1617 sc->sc_opmode = OPMODE_MBO | OPMODE_PS; 1618 TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode); 1619 1620 ifmedia_init(&mii->mii_media, 0, tlp_mediachange, tlp_mediastatus); 1621 aprint_normal_dev(sc->sc_dev, ""); 1622 1623 #define ADD(m, c) \ 1624 tm = malloc(sizeof(*tm), M_DEVBUF, M_WAITOK | M_ZERO); \ 1625 tm->tm_opmode = (c); \ 1626 tm->tm_gpdata = GPP_COGENT_EM1x0_INIT; \ 1627 ifmedia_add(&mii->mii_media, (m), 0, tm) 1628 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 1629 1630 if (sc->sc_srom[32] == 0x15) { 1631 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, 0, 0), 1632 OPMODE_PS | OPMODE_PCS); 1633 PRINT("100baseFX"); 1634 1635 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, IFM_FDX, 0), 1636 OPMODE_PS | OPMODE_PCS | OPMODE_FD); 1637 PRINT("100baseFX-FDX"); 1638 aprint_normal("\n"); 1639 1640 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_100_FX); 1641 } else { 1642 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, 0), 1643 OPMODE_PS | OPMODE_PCS | OPMODE_SCR); 1644 PRINT("100baseTX"); 1645 1646 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, IFM_FDX, 0), 1647 OPMODE_PS | OPMODE_PCS | OPMODE_SCR | OPMODE_FD); 1648 PRINT("100baseTX-FDX"); 1649 aprint_normal("\n"); 1650 1651 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_100_TX); 1652 } 1653 1654 #undef ADD 1655 #undef PRINT 1656 } 1657 1658 static void tlp_pci_netwinder_21142_reset(struct tulip_softc *); 1659 1660 static void 1661 tlp_pci_netwinder_21142_quirks(struct tulip_pci_softc *psc, 1662 const uint8_t *enaddr) 1663 { 1664 struct tulip_softc *sc = &psc->sc_tulip; 1665 1666 /* 1667 * Netwinders just use MII-on-SIO. 1668 */ 1669 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1670 sc->sc_reset = tlp_pci_netwinder_21142_reset; 1671 } 1672 1673 void 1674 tlp_pci_netwinder_21142_reset(struct tulip_softc *sc) 1675 { 1676 1677 /* 1678 * Reset the PHY. 1679 */ 1680 TULIP_WRITE(sc, CSR_SIAGEN, 0x0821 << 16); 1681 delay(10); 1682 TULIP_WRITE(sc, CSR_SIAGEN, 0x0000 << 16); 1683 delay(10); 1684 TULIP_WRITE(sc, CSR_SIAGEN, 0x0001 << 16); 1685 delay(10); 1686 } 1687 1688 static void tlp_pci_phobos_21142_reset(struct tulip_softc *); 1689 1690 static void 1691 tlp_pci_phobos_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr) 1692 { 1693 struct tulip_softc *sc = &psc->sc_tulip; 1694 1695 /* 1696 * Phobos boards just use MII-on-SIO. 1697 */ 1698 sc->sc_mediasw = &tlp_sio_mii_mediasw; 1699 sc->sc_reset = tlp_pci_phobos_21142_reset; 1700 1701 /* 1702 * These boards appear solely on sgimips machines behind a special 1703 * GIO<->PCI ASIC and require the DBO and BLE bits to be set in CSR0. 1704 */ 1705 sc->sc_flags |= (TULIPF_BLE | TULIPF_DBO); 1706 } 1707 1708 static void 1709 tlp_pci_phobos_21142_reset(struct tulip_softc *sc) 1710 { 1711 /* 1712 * Reset PHY. 1713 */ 1714 TULIP_WRITE(sc, CSR_SIAGEN, (0x880f << 16)); 1715 delay(10); 1716 TULIP_WRITE(sc, CSR_SIAGEN, (0x800f << 16)); 1717 delay(10); 1718 } 1719
Indexes created Wed Oct 01 13:09:50 GMT 2025