if_tlregs.h revision 1.3
1 /* $NetBSD: if_tlregs.h,v 1.3 1998/08/15 16:49:33 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #if !defined(_DEV_PCI_IF_TLREGS_H_) 33 #define _DEV_PCI_IF_TLREGS_H_ 34 35 #define PCI_CFID 0x00 /* Configuration ID */ 36 #define PCI_CFCS 0x04 /* Configurtion Command/Status */ 37 #define PCI_CFRV 0x08 /* Configuration Revision */ 38 #define PCI_CFLT 0x0c /* Configuration Latency Timer */ 39 #define PCI_CBIO 0x10 /* Configuration Base IO Address */ 40 #define PCI_CBMA 0x14 /* Configuration Base Memory Address */ 41 #define PCI_CFIT 0x3c /* Configuration Interrupt */ 42 #define PCI_CFDA 0x40 /* Configuration Driver Area */ 43 44 /* Host registers */ 45 #define TL_HOST_CMD 0x00 46 #define TL_HOST_CH_PARM 0x04 47 #define TL_HOST_INTR_DIOADR 0x08 48 # define TL_HOST_INTR_MASK 0xffff0000 49 # define TL_HOST_DIOADR_MASK 0x0000ffff 50 #define TL_HOST_DIO_DATA 0x0c 51 52 #define TL_INTR_MASK 0x001c0000 53 #define TL_INTR_TxEOF 0x00040000 54 #define TL_INTR_Stat 0x00080000 55 #define TL_INTR_RxEOF 0x000c0000 56 #define TL_INTR_Dumm 0x00100000 57 #define TL_INTR_TxEOC 0x00140000 58 #define TL_INTR_Adc 0x00180000 59 #define TL_INTR_RxEOC 0x001c0000 60 #define TL_INTVec_MASK 0x1fe00000 61 62 /* HOST_CMD bits */ 63 #define HOST_CMD_GO 0x80000000 64 #define HOST_CMD_STOP 0x40000000 65 #define HOST_CMD_ACK 0x20000000 66 #define HOST_CMD_CHSEL_mask 0x1fe00000 67 #define HOST_CMD_EOC 0x00100000 68 #define HOST_CMD_RT 0x00080000 69 #define HOST_CMD_Nes 0x00040000 70 #define HOST_CMD_Ad_Rst 0x00008000 71 #define HOST_CMD_LdTmr 0x00004000 72 #define HOST_CMD_LdThr 0x00002000 73 #define HOST_CMD_ReqInt 0x00001000 74 #define HOST_CMD_IntOff 0x00000800 75 #define HOST_CMD_IntOn 0x00000400 76 #define HOST_CMD_AckCnt_mask 0x000000ff 77 78 79 /* Internal registers */ 80 #define TL_INT_NET 0x00 81 # define TL_INT_NetCmd 0x00 /* offsets from TL_INT_NET */ 82 # define TL_INT_NetSio 0x01 83 # define TL_INT_NetSts 0x02 84 # define TL_INT_NetMask 0x03 85 #define TL_INT_NetConfig 0x04 86 #define TL_INT_Defaults 0x08 87 #define TL_INT_Areg0 0x10 88 #define TL_INT_HASH1 0x28 89 #define TL_INT_HASH2 0x2c 90 #define TL_INT_STATS_TX 0x30 91 #define TL_INT_STATS_RX 0x34 92 #define TL_INT_STATS_FERR 0x38 93 # define TL_FERR_DEF 0x0000ffff 94 # define TL_FERR_CRC 0x00ff0000 95 # define TL_FERR_CODE 0xff000000 96 #define TL_INT_STATS_COLL 0x3c 97 # define TL_COL_MULTI 0x0000ffff 98 # define TL_COL_SINGLE 0xffff0000 99 #define TL_INT_LERR 0x40 100 # define TL_LERR_ECOLL 0x000000ff 101 # define TL_LERR_LCOLL 0x0000ff00 102 # define TL_LERR_CL 0x00ff0000 103 # define TL_LERR_AC 0xff000000 104 #define TL_INT_MISC 0x44 105 # define TL_MISC_LED 0x1 106 # define TL_MISC_BSIZE 0x2 107 # define TL_MISC_MaxRxL 0x3 108 # define TL_MISC_MaxRxH 0x4 109 110 /* LEDs for the Integrated Netelligent 10/100 TX */ 111 #define TL_LED_LINK 0x01 112 #define TL_LED_ACT 0x10 113 114 /* NETCOMMAND bits */ 115 #define TL_NETCOMMAND_NRESET 0x80 116 #define TL_NETCOMMAND_NWRAP 0x40 117 #define TL_NETCOMMAND_CSF 0x20 118 #define TL_NETCOMMAND_CAF 0x10 119 #define TL_NETCOMMAND_NOBRX 0x08 120 #define TL_NETCOMMAND_DUPLEX 0x04 121 #define TL_NETCOMMAND_TRFRAM 0x02 122 #define TL_NETCOMMAND_TXPACE 0x01 123 124 /* NETCONFIG bits */ 125 #define TL_NETCONFIG_Trclk 0x8000 126 #define TL_NETCONFIG_Ttclk 0x4000 127 #define TL_NETCONFIG_Brate 0x2000 128 #define TL_NETCONFIG_RxCRC 0x1000 129 #define TL_NETCONFIG_PEF 0x0800 130 #define TL_NETCONFIG_1F 0x0400 131 #define TL_NETCONFIG_1chn 0x0200 132 #define TL_NETCONFIG_Mtest 0x0100 133 #define TL_NETCONFIG_PHY_EN 0x0080 134 #define TL_NETCONFIG_MAC_MASK 0x007f 135 136 /* NetSio bits definition */ 137 #define TL_NETSIO_MDATA 0x01 138 #define TL_NETSIO_MTXEN 0x02 139 #define TL_NETSIO_MCLK 0x04 140 #define TL_NETSIO_NMRST 0x08 141 #define TL_NETSIO_EDATA 0x10 142 #define TL_NETSIO_ETXEN 0x20 143 #define TL_NETSIO_ECLOCK 0x40 144 #define TL_NETSIO_MINTEN 0x80 145 146 /* NetSts buts definition */ 147 #define TL_NETSTS_MIRQ 0x80 148 #define TL_NETSTS_HBEAT 0x40 149 #define TL_NETSTS_TXSTOP 0x20 150 #define TL_NETSTS_RXSTOP 0x10 151 152 /* Linked lists for receive/transmit of datagrams */ 153 154 struct tl_data_seg { 155 u_int32_t data_count; 156 u_int32_t data_addr; 157 }; 158 159 /* Receive list (one_frag = 1) */ 160 struct tl_Rx_list { 161 u_int32_t fwd; 162 u_int32_t stat; 163 struct tl_data_seg seg; 164 }; 165 166 #define TL_RX_CSTAT_CPLT 0x4000 /* Frame complete */ 167 #define TL_RX_CSTAT_EOC 0x0800 /* Rx EOC */ 168 #define TL_RX_CSTAT_Err 0x0400 /* Error frame */ 169 170 /* transmit list */ 171 #define TL_NSEG 10 172 #define TL_LAST_SEG 0x80000000 173 struct tl_Tx_list { 174 u_int32_t fwd; 175 u_int32_t stat; 176 struct tl_data_seg seg[TL_NSEG]; 177 }; 178 179 #define TL_TX_CSTAT_CPL 0x4000 /* Frame complete */ 180 #define TL_TX_CSTAT_EOC 0x0800 /* Tx EOC */ 181 182 /* 183 * Structs used by the host used for lists management. Note that the adapter's 184 * lists must start on an 8 bytes boundary. 185 */ 186 187 struct Tx_list { 188 struct mbuf *m; /* mbuf associated with this list */ 189 struct Tx_list* next; 190 struct tl_Tx_list hw_list; 191 }; 192 193 struct Rx_list { 194 struct mbuf *m; /* mbuf associated with this list */ 195 struct Rx_list *next; 196 struct tl_Rx_list hw_list; 197 }; 198 199 #endif /* ! _DEV_PCI_IF_TLREGS_H_ */ 200
Indexes created Fri Sep 26 20:09:58 GMT 2025