if_txp.c revision 1.1
1 /* $NetBSD: if_txp.c,v 1.1 2003/07/01 20:08:51 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 /* #include "vlan.h" XXX notyet */ 36 #include "opt_inet.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/if_ether.h> 52 #include <net/if_arp.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 #endif 61 62 #include <net/if_media.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #if NVLAN > 0 69 #include <net/if_vlanvar.h> 70 #endif 71 72 #include <uvm/uvm_extern.h> /* for vtophys */ 73 #include <machine/bus.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/if_txpreg.h> 82 83 #include <dev/microcode/typhoon/3c990img.h> 84 85 /* 86 * These currently break the 3c990 firmware, hopefully will be resolved 87 * at some point. 88 */ 89 #undef TRY_TX_UDP_CSUM 90 #undef TRY_TX_TCP_CSUM 91 92 int txp_probe(struct device *, struct cfdata *, void *); 93 void txp_attach(struct device *, struct device *, void *); 94 int txp_intr(void *); 95 void txp_tick(void *); 96 void txp_shutdown(void *); 97 int txp_ioctl(struct ifnet *, u_long, caddr_t); 98 void txp_start(struct ifnet *); 99 void txp_stop(struct txp_softc *); 100 void txp_init(struct txp_softc *); 101 void txp_watchdog(struct ifnet *); 102 103 int txp_chip_init(struct txp_softc *); 104 int txp_reset_adapter(struct txp_softc *); 105 int txp_download_fw(struct txp_softc *); 106 int txp_download_fw_wait(struct txp_softc *); 107 int txp_download_fw_section(struct txp_softc *, 108 struct txp_fw_section_header *, int); 109 int txp_alloc_rings(struct txp_softc *); 110 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 111 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 112 void txp_set_filter(struct txp_softc *); 113 114 int txp_cmd_desc_numfree(struct txp_softc *); 115 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 116 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 117 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 118 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 119 struct txp_rsp_desc **, int); 120 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 121 struct txp_rsp_desc **); 122 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 123 struct txp_rsp_desc *); 124 void txp_capabilities(struct txp_softc *); 125 126 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 127 int txp_ifmedia_upd(struct ifnet *); 128 void txp_show_descriptor(void *); 129 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 130 struct txp_dma_alloc *); 131 void txp_rxbuf_reclaim(struct txp_softc *); 132 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 133 struct txp_dma_alloc *); 134 135 struct cfattach txp_ca = { 136 "txp", {0}, sizeof(struct txp_softc), txp_probe, txp_attach, 137 }; 138 139 const struct pci_matchid { 140 int vid, did; 141 } txp_devices[] = { 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97 }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95 }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97 }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B }, 148 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR }, 149 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX }, 150 }; 151 152 int 153 txp_probe(parent, match, aux) 154 struct device *parent; 155 struct cfdata *match; 156 void *aux; 157 { 158 struct pci_attach_args *pa = aux; 159 int i; 160 161 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 162 if ((PCI_VENDOR(pa->pa_id) == txp_devices[i].vid) && 163 (PCI_PRODUCT(pa->pa_id) == txp_devices[i].did)) 164 return (1); 165 return (0); 166 } 167 168 void 169 txp_attach(parent, self, aux) 170 struct device *parent, *self; 171 void *aux; 172 { 173 struct txp_softc *sc = (struct txp_softc *)self; 174 struct pci_attach_args *pa = aux; 175 pci_chipset_tag_t pc = pa->pa_pc; 176 pci_intr_handle_t ih; 177 const char *intrstr = NULL; 178 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 179 u_int32_t command; 180 u_int16_t p1; 181 u_int32_t p2; 182 u_char enaddr[6]; 183 184 sc->sc_cold = 1; 185 186 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 187 188 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 189 printf(": failed to enable bus mastering\n"); 190 return; 191 } 192 193 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 194 printf(": failed to enable memory mapping\n"); 195 return; 196 } 197 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 198 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 199 printf(": can't map mem space %d\n", 0); 200 return; 201 } 202 203 sc->sc_dmat = pa->pa_dmat; 204 205 /* 206 * Allocate our interrupt. 207 */ 208 if (pci_intr_map(pa, &ih)) { 209 printf(": couldn't map interrupt\n"); 210 return; 211 } 212 213 intrstr = pci_intr_string(pc, ih); 214 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 215 if (sc->sc_ih == NULL) { 216 printf(": couldn't establish interrupt"); 217 if (intrstr != NULL) 218 printf(" at %s", intrstr); 219 printf("\n"); 220 return; 221 } 222 printf(": %s", intrstr); 223 224 if (txp_chip_init(sc)) 225 return; 226 227 if (txp_download_fw(sc)) 228 return; 229 230 if (txp_alloc_rings(sc)) 231 return; 232 233 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 234 NULL, NULL, NULL, 1)) 235 return; 236 237 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 238 &p1, &p2, NULL, 1)) 239 return; 240 241 txp_set_filter(sc); 242 243 p1 = htole16(p1); 244 enaddr[0] = ((u_int8_t *)&p1)[1]; 245 enaddr[1] = ((u_int8_t *)&p1)[0]; 246 p2 = htole32(p2); 247 enaddr[2] = ((u_int8_t *)&p2)[3]; 248 enaddr[3] = ((u_int8_t *)&p2)[2]; 249 enaddr[4] = ((u_int8_t *)&p2)[1]; 250 enaddr[5] = ((u_int8_t *)&p2)[0]; 251 252 printf(" address %s\n", ether_sprintf(enaddr)); 253 sc->sc_cold = 0; 254 255 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 256 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 257 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 258 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 259 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 260 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 261 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 262 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 263 264 sc->sc_xcvr = TXP_XCVR_AUTO; 265 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 266 NULL, NULL, NULL, 0); 267 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 268 269 ifp->if_softc = sc; 270 ifp->if_mtu = ETHERMTU; 271 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 272 ifp->if_ioctl = txp_ioctl; 273 ifp->if_start = txp_start; 274 ifp->if_watchdog = txp_watchdog; 275 ifp->if_baudrate = 10000000; 276 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 277 IFQ_SET_READY(&ifp->if_snd); 278 ifp->if_capabilities = 0; 279 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 280 281 txp_capabilities(sc); 282 283 callout_setfunc(&sc->sc_tick, txp_tick, sc); 284 285 /* 286 * Attach us everywhere 287 */ 288 if_attach(ifp); 289 ether_ifattach(ifp, enaddr); 290 291 shutdownhook_establish(txp_shutdown, sc); 292 } 293 294 int 295 txp_chip_init(sc) 296 struct txp_softc *sc; 297 { 298 /* disable interrupts */ 299 WRITE_REG(sc, TXP_IER, 0); 300 WRITE_REG(sc, TXP_IMR, 301 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 302 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 303 TXP_INT_LATCH); 304 305 /* ack all interrupts */ 306 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 307 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 308 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 309 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 310 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 311 312 if (txp_reset_adapter(sc)) 313 return (-1); 314 315 /* disable interrupts */ 316 WRITE_REG(sc, TXP_IER, 0); 317 WRITE_REG(sc, TXP_IMR, 318 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 319 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 320 TXP_INT_LATCH); 321 322 /* ack all interrupts */ 323 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 324 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 325 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 326 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 327 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 328 329 return (0); 330 } 331 332 int 333 txp_reset_adapter(sc) 334 struct txp_softc *sc; 335 { 336 u_int32_t r; 337 int i; 338 339 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 340 DELAY(1000); 341 WRITE_REG(sc, TXP_SRR, 0); 342 343 /* Should wait max 6 seconds */ 344 for (i = 0; i < 6000; i++) { 345 r = READ_REG(sc, TXP_A2H_0); 346 if (r == STAT_WAITING_FOR_HOST_REQUEST) 347 break; 348 DELAY(1000); 349 } 350 351 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 352 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 353 return (-1); 354 } 355 356 return (0); 357 } 358 359 int 360 txp_download_fw(sc) 361 struct txp_softc *sc; 362 { 363 struct txp_fw_file_header *fileheader; 364 struct txp_fw_section_header *secthead; 365 int sect; 366 u_int32_t r, i, ier, imr; 367 368 ier = READ_REG(sc, TXP_IER); 369 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 370 371 imr = READ_REG(sc, TXP_IMR); 372 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 373 374 for (i = 0; i < 10000; i++) { 375 r = READ_REG(sc, TXP_A2H_0); 376 if (r == STAT_WAITING_FOR_HOST_REQUEST) 377 break; 378 DELAY(50); 379 } 380 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 381 printf(": not waiting for host request\n"); 382 return (-1); 383 } 384 385 /* Ack the status */ 386 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 387 388 fileheader = (struct txp_fw_file_header *)tc990image; 389 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 390 printf(": fw invalid magic\n"); 391 return (-1); 392 } 393 394 /* Tell boot firmware to get ready for image */ 395 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 396 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 397 398 if (txp_download_fw_wait(sc)) { 399 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 400 return (-1); 401 } 402 403 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 404 sizeof(struct txp_fw_file_header)); 405 406 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 407 if (txp_download_fw_section(sc, secthead, sect)) 408 return (-1); 409 secthead = (struct txp_fw_section_header *) 410 (((u_int8_t *)secthead) + le32toh(secthead->nbytes) + 411 sizeof(*secthead)); 412 } 413 414 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 415 416 for (i = 0; i < 10000; i++) { 417 r = READ_REG(sc, TXP_A2H_0); 418 if (r == STAT_WAITING_FOR_BOOT) 419 break; 420 DELAY(50); 421 } 422 if (r != STAT_WAITING_FOR_BOOT) { 423 printf(": not waiting for boot\n"); 424 return (-1); 425 } 426 427 WRITE_REG(sc, TXP_IER, ier); 428 WRITE_REG(sc, TXP_IMR, imr); 429 430 return (0); 431 } 432 433 int 434 txp_download_fw_wait(sc) 435 struct txp_softc *sc; 436 { 437 u_int32_t i, r; 438 439 for (i = 0; i < 10000; i++) { 440 r = READ_REG(sc, TXP_ISR); 441 if (r & TXP_INT_A2H_0) 442 break; 443 DELAY(50); 444 } 445 446 if (!(r & TXP_INT_A2H_0)) { 447 printf(": fw wait failed comm0\n"); 448 return (-1); 449 } 450 451 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 452 453 r = READ_REG(sc, TXP_A2H_0); 454 if (r != STAT_WAITING_FOR_SEGMENT) { 455 printf(": fw not waiting for segment\n"); 456 return (-1); 457 } 458 return (0); 459 } 460 461 int 462 txp_download_fw_section(sc, sect, sectnum) 463 struct txp_softc *sc; 464 struct txp_fw_section_header *sect; 465 int sectnum; 466 { 467 struct txp_dma_alloc dma; 468 int rseg, err = 0; 469 struct mbuf m; 470 u_int16_t csum; 471 472 /* Skip zero length sections */ 473 if (sect->nbytes == 0) 474 return (0); 475 476 /* Make sure we aren't past the end of the image */ 477 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 478 if (rseg >= sizeof(tc990image)) { 479 printf(": fw invalid section address, section %d\n", sectnum); 480 return (-1); 481 } 482 483 /* Make sure this section doesn't go past the end */ 484 rseg += le32toh(sect->nbytes); 485 if (rseg >= sizeof(tc990image)) { 486 printf(": fw truncated section %d\n", sectnum); 487 return (-1); 488 } 489 490 /* map a buffer, copy segment to it, get physaddr */ 491 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 492 printf(": fw dma malloc failed, section %d\n", sectnum); 493 return (-1); 494 } 495 496 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 497 le32toh(sect->nbytes)); 498 499 /* 500 * dummy up mbuf and verify section checksum 501 */ 502 m.m_type = MT_DATA; 503 m.m_next = m.m_nextpkt = NULL; 504 m.m_len = le32toh(sect->nbytes); 505 m.m_data = dma.dma_vaddr; 506 m.m_flags = 0; 507 csum = in_cksum(&m, le32toh(sect->nbytes)); 508 if (csum != sect->cksum) { 509 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 510 sectnum, sect->cksum, csum); 511 err = -1; 512 goto bail; 513 } 514 515 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 516 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 517 518 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 519 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 520 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 521 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 522 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 523 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 524 525 if (txp_download_fw_wait(sc)) { 526 printf("%s: fw wait failed, section %d\n", 527 sc->sc_dev.dv_xname, sectnum); 528 err = -1; 529 } 530 531 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 532 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 533 534 bail: 535 txp_dma_free(sc, &dma); 536 537 return (err); 538 } 539 540 int 541 txp_intr(vsc) 542 void *vsc; 543 { 544 struct txp_softc *sc = vsc; 545 struct txp_hostvar *hv = sc->sc_hostvar; 546 u_int32_t isr; 547 int claimed = 0; 548 549 /* mask all interrupts */ 550 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 551 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 552 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 553 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 554 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 555 556 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 557 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 558 559 isr = READ_REG(sc, TXP_ISR); 560 while (isr) { 561 claimed = 1; 562 WRITE_REG(sc, TXP_ISR, isr); 563 564 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 565 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 566 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 567 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 568 569 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 570 txp_rxbuf_reclaim(sc); 571 572 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 573 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 574 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 575 576 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 577 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 578 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 579 580 isr = READ_REG(sc, TXP_ISR); 581 } 582 583 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 584 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 585 586 /* unmask all interrupts */ 587 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 588 589 txp_start(&sc->sc_arpcom.ec_if); 590 591 return (claimed); 592 } 593 594 void 595 txp_rx_reclaim(sc, r, dma) 596 struct txp_softc *sc; 597 struct txp_rx_ring *r; 598 struct txp_dma_alloc *dma; 599 { 600 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 601 struct txp_rx_desc *rxd; 602 struct mbuf *m; 603 struct txp_swdesc *sd; 604 u_int32_t roff, woff; 605 #if 0 606 int sumflags = 0; 607 #endif 608 int idx; 609 610 roff = le32toh(*r->r_roff); 611 woff = le32toh(*r->r_woff); 612 idx = roff / sizeof(struct txp_rx_desc); 613 rxd = r->r_desc + idx; 614 615 while (roff != woff) { 616 617 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 618 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 619 BUS_DMASYNC_POSTREAD); 620 621 if (rxd->rx_flags & RX_FLAGS_ERROR) { 622 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 623 le32toh(rxd->rx_stat)); 624 ifp->if_ierrors++; 625 goto next; 626 } 627 628 /* retrieve stashed pointer */ 629 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 630 631 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 632 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 633 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 634 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 635 m = sd->sd_mbuf; 636 free(sd, M_DEVBUF); 637 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 638 639 #ifdef __STRICT_ALIGNMENT 640 { 641 /* 642 * XXX Nice chip, except it won't accept "off by 2" 643 * buffers, so we're force to copy. Supposedly 644 * this will be fixed in a newer firmware rev 645 * and this will be temporary. 646 */ 647 struct mbuf *mnew; 648 649 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 650 if (mnew == NULL) { 651 m_freem(m); 652 goto next; 653 } 654 if (m->m_len > (MHLEN - 2)) { 655 MCLGET(mnew, M_DONTWAIT); 656 if (!(mnew->m_flags & M_EXT)) { 657 m_freem(mnew); 658 m_freem(m); 659 goto next; 660 } 661 } 662 mnew->m_pkthdr.rcvif = ifp; 663 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 664 mnew->m_data += 2; 665 bcopy(m->m_data, mnew->m_data, m->m_len); 666 m_freem(m); 667 m = mnew; 668 } 669 #endif 670 671 #if NBPFILTER > 0 672 /* 673 * Handle BPF listeners. Let the BPF user see the packet. 674 */ 675 if (ifp->if_bpf) 676 bpf_mtap(ifp->if_bpf, m); 677 #endif 678 679 #if 0 680 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 681 sumflags |= M_IPV4_CSUM_IN_BAD; 682 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 683 sumflags |= M_IPV4_CSUM_IN_OK; 684 685 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 686 sumflags |= M_TCP_CSUM_IN_BAD; 687 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 688 sumflags |= M_TCP_CSUM_IN_OK; 689 690 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 691 sumflags |= M_UDP_CSUM_IN_BAD; 692 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 693 sumflags |= M_UDP_CSUM_IN_OK; 694 695 m->m_pkthdr.csum = sumflags; 696 #endif 697 698 #if NVLAN > 0 699 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 700 if (vlan_input_tag(m, htons(rxd->rx_vlan >> 16)) < 0) 701 ifp->if_noproto++; 702 goto next; 703 } 704 #endif 705 706 (*ifp->if_input)(ifp, m); 707 708 next: 709 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 710 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 711 BUS_DMASYNC_PREREAD); 712 713 roff += sizeof(struct txp_rx_desc); 714 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 715 idx = 0; 716 roff = 0; 717 rxd = r->r_desc; 718 } else { 719 idx++; 720 rxd++; 721 } 722 woff = le32toh(*r->r_woff); 723 } 724 725 *r->r_roff = htole32(woff); 726 } 727 728 void 729 txp_rxbuf_reclaim(sc) 730 struct txp_softc *sc; 731 { 732 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 733 struct txp_hostvar *hv = sc->sc_hostvar; 734 struct txp_rxbuf_desc *rbd; 735 struct txp_swdesc *sd; 736 u_int32_t i, end; 737 738 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 739 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 740 741 if (++i == RXBUF_ENTRIES) 742 i = 0; 743 744 rbd = sc->sc_rxbufs + i; 745 746 while (i != end) { 747 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 748 M_DEVBUF, M_NOWAIT); 749 if (sd == NULL) 750 break; 751 752 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 753 if (sd->sd_mbuf == NULL) 754 goto err_sd; 755 756 MCLGET(sd->sd_mbuf, M_DONTWAIT); 757 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 758 goto err_mbuf; 759 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 760 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 761 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 762 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 763 goto err_mbuf; 764 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 765 BUS_DMA_NOWAIT)) { 766 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 767 goto err_mbuf; 768 } 769 770 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 771 i * sizeof(struct txp_rxbuf_desc), 772 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 773 774 /* stash away pointer */ 775 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 776 777 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 778 & 0xffffffff; 779 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 780 >> 32; 781 782 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 783 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 784 785 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 786 i * sizeof(struct txp_rxbuf_desc), 787 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 788 789 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 790 791 if (++i == RXBUF_ENTRIES) { 792 i = 0; 793 rbd = sc->sc_rxbufs; 794 } else 795 rbd++; 796 } 797 return; 798 799 err_mbuf: 800 m_freem(sd->sd_mbuf); 801 err_sd: 802 free(sd, M_DEVBUF); 803 } 804 805 /* 806 * Reclaim mbufs and entries from a transmit ring. 807 */ 808 void 809 txp_tx_reclaim(sc, r, dma) 810 struct txp_softc *sc; 811 struct txp_tx_ring *r; 812 struct txp_dma_alloc *dma; 813 { 814 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 815 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 816 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 817 struct txp_tx_desc *txd = r->r_desc + cons; 818 struct txp_swdesc *sd = sc->sc_txd + cons; 819 struct mbuf *m; 820 821 while (cons != idx) { 822 if (cnt == 0) 823 break; 824 825 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 826 cons * sizeof(struct txp_tx_desc), 827 sizeof(struct txp_tx_desc), 828 BUS_DMASYNC_POSTWRITE); 829 830 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 831 TX_FLAGS_TYPE_DATA) { 832 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 833 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 834 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 835 m = sd->sd_mbuf; 836 if (m != NULL) { 837 m_freem(m); 838 txd->tx_addrlo = 0; 839 txd->tx_addrhi = 0; 840 ifp->if_opackets++; 841 } 842 } 843 ifp->if_flags &= ~IFF_OACTIVE; 844 845 if (++cons == TX_ENTRIES) { 846 txd = r->r_desc; 847 cons = 0; 848 sd = sc->sc_txd; 849 } else { 850 txd++; 851 sd++; 852 } 853 854 cnt--; 855 } 856 857 r->r_cons = cons; 858 r->r_cnt = cnt; 859 if (cnt == 0) 860 ifp->if_timer = 0; 861 } 862 863 void 864 txp_shutdown(vsc) 865 void *vsc; 866 { 867 struct txp_softc *sc = (struct txp_softc *)vsc; 868 869 /* mask all interrupts */ 870 WRITE_REG(sc, TXP_IMR, 871 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 872 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 873 TXP_INT_LATCH); 874 875 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 876 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 877 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 878 } 879 880 int 881 txp_alloc_rings(sc) 882 struct txp_softc *sc; 883 { 884 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 885 struct txp_boot_record *boot; 886 struct txp_swdesc *sd; 887 u_int32_t r; 888 int i, j; 889 890 /* boot record */ 891 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 892 BUS_DMA_COHERENT)) { 893 printf(": can't allocate boot record\n"); 894 return (-1); 895 } 896 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 897 bzero(boot, sizeof(*boot)); 898 sc->sc_boot = boot; 899 900 /* host variables */ 901 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 902 BUS_DMA_COHERENT)) { 903 printf(": can't allocate host ring\n"); 904 goto bail_boot; 905 } 906 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 907 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 908 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 909 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 910 911 /* high priority tx ring */ 912 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 913 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 914 printf(": can't allocate high tx ring\n"); 915 goto bail_host; 916 } 917 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 918 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 919 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 920 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 921 sc->sc_txhir.r_reg = TXP_H2A_1; 922 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 923 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 924 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 925 for (i = 0; i < TX_ENTRIES; i++) { 926 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 927 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 928 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 929 for (j = 0; j < i; j++) { 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txd[j].sd_map); 932 sc->sc_txd[j].sd_map = NULL; 933 } 934 goto bail_txhiring; 935 } 936 } 937 938 /* low priority tx ring */ 939 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 940 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 941 printf(": can't allocate low tx ring\n"); 942 goto bail_txhiring; 943 } 944 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 945 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 946 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 947 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 948 sc->sc_txlor.r_reg = TXP_H2A_3; 949 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 950 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 951 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 952 953 /* high priority rx ring */ 954 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 955 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 956 printf(": can't allocate high rx ring\n"); 957 goto bail_txloring; 958 } 959 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 960 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 961 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 962 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 963 sc->sc_rxhir.r_desc = 964 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 965 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 966 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 967 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 968 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 969 970 /* low priority ring */ 971 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 972 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 973 printf(": can't allocate low rx ring\n"); 974 goto bail_rxhiring; 975 } 976 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 977 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 978 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 979 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 980 sc->sc_rxlor.r_desc = 981 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 982 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 983 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 984 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 985 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 986 987 /* command ring */ 988 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 989 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 990 printf(": can't allocate command ring\n"); 991 goto bail_rxloring; 992 } 993 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 994 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 995 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 996 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 997 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 998 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 999 sc->sc_cmdring.lastwrite = 0; 1000 1001 /* response ring */ 1002 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1003 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1004 printf(": can't allocate response ring\n"); 1005 goto bail_cmdring; 1006 } 1007 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1008 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1009 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1010 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1011 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1012 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1013 sc->sc_rspring.lastwrite = 0; 1014 1015 /* receive buffer ring */ 1016 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1017 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1018 printf(": can't allocate rx buffer ring\n"); 1019 goto bail_rspring; 1020 } 1021 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1022 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1023 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1024 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1025 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1026 for (i = 0; i < RXBUF_ENTRIES; i++) { 1027 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1028 M_DEVBUF, M_NOWAIT); 1029 if (sd == NULL) 1030 break; 1031 1032 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1033 if (sd->sd_mbuf == NULL) { 1034 goto bail_rxbufring; 1035 } 1036 1037 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1038 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1039 goto bail_rxbufring; 1040 } 1041 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1042 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1043 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1044 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1045 goto bail_rxbufring; 1046 } 1047 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1048 BUS_DMA_NOWAIT)) { 1049 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1050 goto bail_rxbufring; 1051 } 1052 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1053 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1054 1055 /* stash away pointer */ 1056 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1057 1058 sc->sc_rxbufs[i].rb_paddrlo = 1059 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1060 sc->sc_rxbufs[i].rb_paddrhi = 1061 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1062 } 1063 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1064 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1065 BUS_DMASYNC_PREWRITE); 1066 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1067 sizeof(struct txp_rxbuf_desc)); 1068 1069 /* zero dma */ 1070 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1071 BUS_DMA_COHERENT)) { 1072 printf(": can't allocate response ring\n"); 1073 goto bail_rxbufring; 1074 } 1075 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1076 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1077 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1078 1079 /* See if it's waiting for boot, and try to boot it */ 1080 for (i = 0; i < 10000; i++) { 1081 r = READ_REG(sc, TXP_A2H_0); 1082 if (r == STAT_WAITING_FOR_BOOT) 1083 break; 1084 DELAY(50); 1085 } 1086 if (r != STAT_WAITING_FOR_BOOT) { 1087 printf(": not waiting for boot\n"); 1088 goto bail; 1089 } 1090 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1091 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1092 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1093 1094 /* See if it booted */ 1095 for (i = 0; i < 10000; i++) { 1096 r = READ_REG(sc, TXP_A2H_0); 1097 if (r == STAT_RUNNING) 1098 break; 1099 DELAY(50); 1100 } 1101 if (r != STAT_RUNNING) { 1102 printf(": fw not running\n"); 1103 goto bail; 1104 } 1105 1106 /* Clear TX and CMD ring write registers */ 1107 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1108 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1109 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1110 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1111 1112 return (0); 1113 1114 bail: 1115 txp_dma_free(sc, &sc->sc_zero_dma); 1116 bail_rxbufring: 1117 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1118 bail_rspring: 1119 txp_dma_free(sc, &sc->sc_rspring_dma); 1120 bail_cmdring: 1121 txp_dma_free(sc, &sc->sc_cmdring_dma); 1122 bail_rxloring: 1123 txp_dma_free(sc, &sc->sc_rxloring_dma); 1124 bail_rxhiring: 1125 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1126 bail_txloring: 1127 txp_dma_free(sc, &sc->sc_txloring_dma); 1128 bail_txhiring: 1129 txp_dma_free(sc, &sc->sc_txhiring_dma); 1130 bail_host: 1131 txp_dma_free(sc, &sc->sc_host_dma); 1132 bail_boot: 1133 txp_dma_free(sc, &sc->sc_boot_dma); 1134 return (-1); 1135 } 1136 1137 int 1138 txp_dma_malloc(sc, size, dma, mapflags) 1139 struct txp_softc *sc; 1140 bus_size_t size; 1141 struct txp_dma_alloc *dma; 1142 int mapflags; 1143 { 1144 int r; 1145 1146 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1147 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1148 goto fail_0; 1149 1150 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1151 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1152 goto fail_1; 1153 1154 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1155 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1156 goto fail_2; 1157 1158 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1159 size, NULL, BUS_DMA_NOWAIT)) != 0) 1160 goto fail_3; 1161 1162 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1163 return (0); 1164 1165 fail_3: 1166 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1167 fail_2: 1168 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1169 fail_1: 1170 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1171 fail_0: 1172 return (r); 1173 } 1174 1175 void 1176 txp_dma_free(sc, dma) 1177 struct txp_softc *sc; 1178 struct txp_dma_alloc *dma; 1179 { 1180 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1181 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1182 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1183 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1184 } 1185 1186 int 1187 txp_ioctl(ifp, command, data) 1188 struct ifnet *ifp; 1189 u_long command; 1190 caddr_t data; 1191 { 1192 struct txp_softc *sc = ifp->if_softc; 1193 struct ifreq *ifr = (struct ifreq *)data; 1194 struct ifaddr *ifa = (struct ifaddr *)data; 1195 int s, error = 0; 1196 1197 s = splnet(); 1198 1199 #if 0 1200 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1201 splx(s); 1202 return error; 1203 } 1204 #endif 1205 1206 switch(command) { 1207 case SIOCSIFADDR: 1208 ifp->if_flags |= IFF_UP; 1209 switch (ifa->ifa_addr->sa_family) { 1210 #ifdef INET 1211 case AF_INET: 1212 txp_init(sc); 1213 arp_ifinit(ifp, ifa); 1214 break; 1215 #endif /* INET */ 1216 default: 1217 txp_init(sc); 1218 break; 1219 } 1220 break; 1221 case SIOCSIFFLAGS: 1222 if (ifp->if_flags & IFF_UP) { 1223 txp_init(sc); 1224 } else { 1225 if (ifp->if_flags & IFF_RUNNING) 1226 txp_stop(sc); 1227 } 1228 break; 1229 case SIOCADDMULTI: 1230 case SIOCDELMULTI: 1231 error = (command == SIOCADDMULTI) ? 1232 ether_addmulti(ifr, &sc->sc_arpcom) : 1233 ether_delmulti(ifr, &sc->sc_arpcom); 1234 1235 if (error == ENETRESET) { 1236 /* 1237 * Multicast list has changed; set the hardware 1238 * filter accordingly. 1239 */ 1240 txp_set_filter(sc); 1241 error = 0; 1242 } 1243 break; 1244 case SIOCGIFMEDIA: 1245 case SIOCSIFMEDIA: 1246 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1247 break; 1248 default: 1249 error = EINVAL; 1250 break; 1251 } 1252 1253 splx(s); 1254 1255 return(error); 1256 } 1257 1258 void 1259 txp_init(sc) 1260 struct txp_softc *sc; 1261 { 1262 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1263 int s; 1264 1265 txp_stop(sc); 1266 1267 s = splnet(); 1268 1269 txp_set_filter(sc); 1270 1271 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1272 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1273 1274 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1275 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1276 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1277 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1278 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1279 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1280 1281 ifp->if_flags |= IFF_RUNNING; 1282 ifp->if_flags &= ~IFF_OACTIVE; 1283 ifp->if_timer = 0; 1284 1285 if (!callout_pending(&sc->sc_tick)) 1286 callout_schedule(&sc->sc_tick, hz); 1287 1288 splx(s); 1289 } 1290 1291 void 1292 txp_tick(vsc) 1293 void *vsc; 1294 { 1295 struct txp_softc *sc = vsc; 1296 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1297 struct txp_rsp_desc *rsp = NULL; 1298 struct txp_ext_desc *ext; 1299 int s; 1300 1301 s = splnet(); 1302 txp_rxbuf_reclaim(sc); 1303 1304 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1305 &rsp, 1)) 1306 goto out; 1307 if (rsp->rsp_numdesc != 6) 1308 goto out; 1309 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1310 NULL, NULL, NULL, 1)) 1311 goto out; 1312 ext = (struct txp_ext_desc *)(rsp + 1); 1313 1314 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1315 ext[4].ext_1 + ext[4].ext_4; 1316 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1317 ext[2].ext_1; 1318 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1319 ext[1].ext_3; 1320 ifp->if_opackets += rsp->rsp_par2; 1321 ifp->if_ipackets += ext[2].ext_3; 1322 1323 out: 1324 if (rsp != NULL) 1325 free(rsp, M_DEVBUF); 1326 1327 splx(s); 1328 callout_schedule(&sc->sc_tick, hz); 1329 } 1330 1331 void 1332 txp_start(ifp) 1333 struct ifnet *ifp; 1334 { 1335 struct txp_softc *sc = ifp->if_softc; 1336 struct txp_tx_ring *r = &sc->sc_txhir; 1337 struct txp_tx_desc *txd; 1338 int txdidx; 1339 struct txp_frag_desc *fxd; 1340 struct mbuf *m, *mnew; 1341 struct txp_swdesc *sd; 1342 u_int32_t firstprod, firstcnt, prod, cnt, i; 1343 #if NVLAN > 0 1344 struct ifvlan *ifv; 1345 #endif 1346 1347 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1348 return; 1349 1350 prod = r->r_prod; 1351 cnt = r->r_cnt; 1352 1353 while (1) { 1354 IFQ_POLL(&ifp->if_snd, m); 1355 if (m == NULL) 1356 break; 1357 mnew = NULL; 1358 1359 firstprod = prod; 1360 firstcnt = cnt; 1361 1362 sd = sc->sc_txd + prod; 1363 sd->sd_mbuf = m; 1364 1365 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1366 BUS_DMA_NOWAIT)) { 1367 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1368 if (mnew == NULL) 1369 goto oactive1; 1370 if (m->m_pkthdr.len > MHLEN) { 1371 MCLGET(mnew, M_DONTWAIT); 1372 if ((mnew->m_flags & M_EXT) == 0) { 1373 m_freem(mnew); 1374 goto oactive1; 1375 } 1376 } 1377 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1378 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1379 IFQ_DEQUEUE(&ifp->if_snd, m); 1380 m_freem(m); 1381 m = mnew; 1382 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1383 BUS_DMA_NOWAIT)) 1384 goto oactive1; 1385 } 1386 1387 if ((TX_ENTRIES - cnt) < 4) 1388 goto oactive; 1389 1390 txd = r->r_desc + prod; 1391 txdidx = prod; 1392 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1393 txd->tx_numdesc = 0; 1394 txd->tx_addrlo = 0; 1395 txd->tx_addrhi = 0; 1396 txd->tx_totlen = m->m_pkthdr.len; 1397 txd->tx_pflags = 0; 1398 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1399 1400 if (++prod == TX_ENTRIES) 1401 prod = 0; 1402 1403 if (++cnt >= (TX_ENTRIES - 4)) 1404 goto oactive; 1405 1406 #if NVLAN > 0 1407 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1408 m->m_pkthdr.rcvif != NULL) { 1409 ifv = m->m_pkthdr.rcvif->if_softc; 1410 txd->tx_pflags = TX_PFLAGS_VLAN | 1411 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1412 } 1413 #endif 1414 1415 #if 0 1416 if (m->m_pkthdr.csum & M_IPV4_CSUM_OUT) 1417 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1418 #ifdef TRY_TX_TCP_CSUM 1419 if (m->m_pkthdr.csum & M_TCPV4_CSUM_OUT) 1420 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1421 #endif 1422 #ifdef TRY_TX_UDP_CSUM 1423 if (m->m_pkthdr.csum & M_UDPV4_CSUM_OUT) 1424 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1425 #endif 1426 #endif 1427 1428 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1429 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1430 1431 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1432 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1433 if (++cnt >= (TX_ENTRIES - 4)) { 1434 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1435 0, sd->sd_map->dm_mapsize, 1436 BUS_DMASYNC_POSTWRITE); 1437 goto oactive; 1438 } 1439 1440 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1441 FRAG_FLAGS_VALID; 1442 fxd->frag_rsvd1 = 0; 1443 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1444 fxd->frag_addrlo = 1445 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1446 0xffffffff; 1447 fxd->frag_addrhi = 1448 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1449 32; 1450 fxd->frag_rsvd2 = 0; 1451 1452 bus_dmamap_sync(sc->sc_dmat, 1453 sc->sc_txhiring_dma.dma_map, 1454 prod * sizeof(struct txp_frag_desc), 1455 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1456 1457 if (++prod == TX_ENTRIES) { 1458 fxd = (struct txp_frag_desc *)r->r_desc; 1459 prod = 0; 1460 } else 1461 fxd++; 1462 1463 } 1464 1465 /* 1466 * if mnew isn't NULL, we already dequeued and copied 1467 * the packet. 1468 */ 1469 if (mnew == NULL) 1470 IFQ_DEQUEUE(&ifp->if_snd, m); 1471 1472 ifp->if_timer = 5; 1473 1474 #if NBPFILTER > 0 1475 if (ifp->if_bpf) 1476 bpf_mtap(ifp->if_bpf, m); 1477 #endif 1478 1479 txd->tx_flags |= TX_FLAGS_VALID; 1480 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1481 txdidx * sizeof(struct txp_tx_desc), 1482 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1483 1484 #if 0 1485 { 1486 struct mbuf *mx; 1487 int i; 1488 1489 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1490 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1491 txd->tx_pflags); 1492 for (mx = m; mx != NULL; mx = mx->m_next) { 1493 for (i = 0; i < mx->m_len; i++) { 1494 printf(":%02x", 1495 (u_int8_t)m->m_data[i]); 1496 } 1497 } 1498 printf("\n"); 1499 } 1500 #endif 1501 1502 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1503 } 1504 1505 r->r_prod = prod; 1506 r->r_cnt = cnt; 1507 return; 1508 1509 oactive: 1510 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1511 oactive1: 1512 ifp->if_flags |= IFF_OACTIVE; 1513 r->r_prod = firstprod; 1514 r->r_cnt = firstcnt; 1515 } 1516 1517 /* 1518 * Handle simple commands sent to the typhoon 1519 */ 1520 int 1521 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1522 struct txp_softc *sc; 1523 u_int16_t id, in1, *out1; 1524 u_int32_t in2, in3, *out2, *out3; 1525 int wait; 1526 { 1527 struct txp_rsp_desc *rsp = NULL; 1528 1529 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1530 return (-1); 1531 1532 if (!wait) 1533 return (0); 1534 1535 if (out1 != NULL) 1536 *out1 = le16toh(rsp->rsp_par1); 1537 if (out2 != NULL) 1538 *out2 = le32toh(rsp->rsp_par2); 1539 if (out3 != NULL) 1540 *out3 = le32toh(rsp->rsp_par3); 1541 free(rsp, M_DEVBUF); 1542 return (0); 1543 } 1544 1545 int 1546 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1547 struct txp_softc *sc; 1548 u_int16_t id, in1; 1549 u_int32_t in2, in3; 1550 struct txp_ext_desc *in_extp; 1551 u_int8_t in_extn; 1552 struct txp_rsp_desc **rspp; 1553 int wait; 1554 { 1555 struct txp_hostvar *hv = sc->sc_hostvar; 1556 struct txp_cmd_desc *cmd; 1557 struct txp_ext_desc *ext; 1558 u_int32_t idx, i; 1559 u_int16_t seq; 1560 1561 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1562 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1563 return (-1); 1564 } 1565 1566 idx = sc->sc_cmdring.lastwrite; 1567 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1568 bzero(cmd, sizeof(*cmd)); 1569 1570 cmd->cmd_numdesc = in_extn; 1571 seq = sc->sc_seq++; 1572 cmd->cmd_seq = htole16(seq); 1573 cmd->cmd_id = htole16(id); 1574 cmd->cmd_par1 = htole16(in1); 1575 cmd->cmd_par2 = htole32(in2); 1576 cmd->cmd_par3 = htole32(in3); 1577 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1578 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1579 1580 idx += sizeof(struct txp_cmd_desc); 1581 if (idx == sc->sc_cmdring.size) 1582 idx = 0; 1583 1584 for (i = 0; i < in_extn; i++) { 1585 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1586 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1587 in_extp++; 1588 idx += sizeof(struct txp_cmd_desc); 1589 if (idx == sc->sc_cmdring.size) 1590 idx = 0; 1591 } 1592 1593 sc->sc_cmdring.lastwrite = idx; 1594 1595 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1596 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1597 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1598 1599 if (!wait) 1600 return (0); 1601 1602 for (i = 0; i < 10000; i++) { 1603 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1604 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1605 idx = le32toh(hv->hv_resp_read_idx); 1606 if (idx != le32toh(hv->hv_resp_write_idx)) { 1607 *rspp = NULL; 1608 if (txp_response(sc, idx, id, seq, rspp)) 1609 return (-1); 1610 if (*rspp != NULL) 1611 break; 1612 } 1613 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1614 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1615 DELAY(50); 1616 } 1617 if (i == 1000 || (*rspp) == NULL) { 1618 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1619 return (-1); 1620 } 1621 1622 return (0); 1623 } 1624 1625 int 1626 txp_response(sc, ridx, id, seq, rspp) 1627 struct txp_softc *sc; 1628 u_int32_t ridx; 1629 u_int16_t id; 1630 u_int16_t seq; 1631 struct txp_rsp_desc **rspp; 1632 { 1633 struct txp_hostvar *hv = sc->sc_hostvar; 1634 struct txp_rsp_desc *rsp; 1635 1636 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1637 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1638 1639 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1640 *rspp = (struct txp_rsp_desc *)malloc( 1641 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1642 M_DEVBUF, M_NOWAIT); 1643 if ((*rspp) == NULL) 1644 return (-1); 1645 txp_rsp_fixup(sc, rsp, *rspp); 1646 return (0); 1647 } 1648 1649 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1650 printf("%s: response error: id 0x%x\n", 1651 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1652 txp_rsp_fixup(sc, rsp, NULL); 1653 ridx = le32toh(hv->hv_resp_read_idx); 1654 continue; 1655 } 1656 1657 switch (le16toh(rsp->rsp_id)) { 1658 case TXP_CMD_CYCLE_STATISTICS: 1659 case TXP_CMD_MEDIA_STATUS_READ: 1660 break; 1661 case TXP_CMD_HELLO_RESPONSE: 1662 printf("%s: hello\n", TXP_DEVNAME(sc)); 1663 break; 1664 default: 1665 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1666 le16toh(rsp->rsp_id)); 1667 } 1668 1669 txp_rsp_fixup(sc, rsp, NULL); 1670 ridx = le32toh(hv->hv_resp_read_idx); 1671 hv->hv_resp_read_idx = le32toh(ridx); 1672 } 1673 1674 return (0); 1675 } 1676 1677 void 1678 txp_rsp_fixup(sc, rsp, dst) 1679 struct txp_softc *sc; 1680 struct txp_rsp_desc *rsp, *dst; 1681 { 1682 struct txp_rsp_desc *src = rsp; 1683 struct txp_hostvar *hv = sc->sc_hostvar; 1684 u_int32_t i, ridx; 1685 1686 ridx = le32toh(hv->hv_resp_read_idx); 1687 1688 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1689 if (dst != NULL) 1690 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1691 ridx += sizeof(struct txp_rsp_desc); 1692 if (ridx == sc->sc_rspring.size) { 1693 src = sc->sc_rspring.base; 1694 ridx = 0; 1695 } else 1696 src++; 1697 sc->sc_rspring.lastwrite = ridx; 1698 hv->hv_resp_read_idx = htole32(ridx); 1699 } 1700 1701 hv->hv_resp_read_idx = htole32(ridx); 1702 } 1703 1704 int 1705 txp_cmd_desc_numfree(sc) 1706 struct txp_softc *sc; 1707 { 1708 struct txp_hostvar *hv = sc->sc_hostvar; 1709 struct txp_boot_record *br = sc->sc_boot; 1710 u_int32_t widx, ridx, nfree; 1711 1712 widx = sc->sc_cmdring.lastwrite; 1713 ridx = le32toh(hv->hv_cmd_read_idx); 1714 1715 if (widx == ridx) { 1716 /* Ring is completely free */ 1717 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1718 } else { 1719 if (widx > ridx) 1720 nfree = le32toh(br->br_cmd_siz) - 1721 (widx - ridx + sizeof(struct txp_cmd_desc)); 1722 else 1723 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1724 } 1725 1726 return (nfree / sizeof(struct txp_cmd_desc)); 1727 } 1728 1729 void 1730 txp_stop(sc) 1731 struct txp_softc *sc; 1732 { 1733 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1734 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1735 1736 if (callout_pending(&sc->sc_tick)) 1737 callout_stop(&sc->sc_tick); 1738 } 1739 1740 void 1741 txp_watchdog(ifp) 1742 struct ifnet *ifp; 1743 { 1744 } 1745 1746 int 1747 txp_ifmedia_upd(ifp) 1748 struct ifnet *ifp; 1749 { 1750 struct txp_softc *sc = ifp->if_softc; 1751 struct ifmedia *ifm = &sc->sc_ifmedia; 1752 u_int16_t new_xcvr; 1753 1754 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1755 return (EINVAL); 1756 1757 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1758 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1759 new_xcvr = TXP_XCVR_10_FDX; 1760 else 1761 new_xcvr = TXP_XCVR_10_HDX; 1762 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1763 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1764 new_xcvr = TXP_XCVR_100_FDX; 1765 else 1766 new_xcvr = TXP_XCVR_100_HDX; 1767 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1768 new_xcvr = TXP_XCVR_AUTO; 1769 } else 1770 return (EINVAL); 1771 1772 /* nothing to do */ 1773 if (sc->sc_xcvr == new_xcvr) 1774 return (0); 1775 1776 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1777 NULL, NULL, NULL, 0); 1778 sc->sc_xcvr = new_xcvr; 1779 1780 return (0); 1781 } 1782 1783 void 1784 txp_ifmedia_sts(ifp, ifmr) 1785 struct ifnet *ifp; 1786 struct ifmediareq *ifmr; 1787 { 1788 struct txp_softc *sc = ifp->if_softc; 1789 struct ifmedia *ifm = &sc->sc_ifmedia; 1790 u_int16_t bmsr, bmcr, anlpar; 1791 1792 ifmr->ifm_status = IFM_AVALID; 1793 ifmr->ifm_active = IFM_ETHER; 1794 1795 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1796 &bmsr, NULL, NULL, 1)) 1797 goto bail; 1798 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1799 &bmsr, NULL, NULL, 1)) 1800 goto bail; 1801 1802 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1803 &bmcr, NULL, NULL, 1)) 1804 goto bail; 1805 1806 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1807 &anlpar, NULL, NULL, 1)) 1808 goto bail; 1809 1810 if (bmsr & BMSR_LINK) 1811 ifmr->ifm_status |= IFM_ACTIVE; 1812 1813 if (bmcr & BMCR_ISO) { 1814 ifmr->ifm_active |= IFM_NONE; 1815 ifmr->ifm_status = 0; 1816 return; 1817 } 1818 1819 if (bmcr & BMCR_LOOP) 1820 ifmr->ifm_active |= IFM_LOOP; 1821 1822 if (bmcr & BMCR_AUTOEN) { 1823 if ((bmsr & BMSR_ACOMP) == 0) { 1824 ifmr->ifm_active |= IFM_NONE; 1825 return; 1826 } 1827 1828 if (anlpar & ANLPAR_T4) 1829 ifmr->ifm_active |= IFM_100_T4; 1830 else if (anlpar & ANLPAR_TX_FD) 1831 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1832 else if (anlpar & ANLPAR_TX) 1833 ifmr->ifm_active |= IFM_100_TX; 1834 else if (anlpar & ANLPAR_10_FD) 1835 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1836 else if (anlpar & ANLPAR_10) 1837 ifmr->ifm_active |= IFM_10_T; 1838 else 1839 ifmr->ifm_active |= IFM_NONE; 1840 } else 1841 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1842 return; 1843 1844 bail: 1845 ifmr->ifm_active |= IFM_NONE; 1846 ifmr->ifm_status &= ~IFM_AVALID; 1847 } 1848 1849 void 1850 txp_show_descriptor(d) 1851 void *d; 1852 { 1853 struct txp_cmd_desc *cmd = d; 1854 struct txp_rsp_desc *rsp = d; 1855 struct txp_tx_desc *txd = d; 1856 struct txp_frag_desc *frgd = d; 1857 1858 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1859 case CMD_FLAGS_TYPE_CMD: 1860 /* command descriptor */ 1861 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1862 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1863 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1864 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1865 break; 1866 case CMD_FLAGS_TYPE_RESP: 1867 /* response descriptor */ 1868 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1869 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1870 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1871 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1872 break; 1873 case CMD_FLAGS_TYPE_DATA: 1874 /* data header (assuming tx for now) */ 1875 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1876 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1877 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1878 break; 1879 case CMD_FLAGS_TYPE_FRAG: 1880 /* fragment descriptor */ 1881 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1882 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1883 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1884 break; 1885 default: 1886 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1887 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1888 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1889 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1890 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1891 break; 1892 } 1893 } 1894 1895 void 1896 txp_set_filter(sc) 1897 struct txp_softc *sc; 1898 { 1899 struct ethercom *ac = &sc->sc_arpcom; 1900 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1901 u_int32_t crc, carry, hashbit, hash[2]; 1902 u_int16_t filter; 1903 u_int8_t octet; 1904 int i, j, mcnt = 0; 1905 struct ether_multi *enm; 1906 struct ether_multistep step; 1907 1908 if (ifp->if_flags & IFF_PROMISC) { 1909 filter = TXP_RXFILT_PROMISC; 1910 goto setit; 1911 } 1912 1913 again: 1914 filter = TXP_RXFILT_DIRECT; 1915 1916 if (ifp->if_flags & IFF_BROADCAST) 1917 filter |= TXP_RXFILT_BROADCAST; 1918 1919 if (ifp->if_flags & IFF_ALLMULTI) 1920 filter |= TXP_RXFILT_ALLMULTI; 1921 else { 1922 hash[0] = hash[1] = 0; 1923 1924 ETHER_FIRST_MULTI(step, ac, enm); 1925 while (enm != NULL) { 1926 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1927 /* 1928 * We must listen to a range of multicast 1929 * addresses. For now, just accept all 1930 * multicasts, rather than trying to set only 1931 * those filter bits needed to match the range. 1932 * (At this time, the only use of address 1933 * ranges is for IP multicast routing, for 1934 * which the range is big enough to require 1935 * all bits set.) 1936 */ 1937 ifp->if_flags |= IFF_ALLMULTI; 1938 goto again; 1939 } 1940 1941 mcnt++; 1942 crc = 0xffffffff; 1943 1944 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1945 octet = enm->enm_addrlo[i]; 1946 for (j = 0; j < 8; j++) { 1947 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1948 (octet & 1); 1949 crc <<= 1; 1950 octet >>= 1; 1951 if (carry) 1952 crc = (crc ^ TXP_POLYNOMIAL) | 1953 carry; 1954 } 1955 } 1956 hashbit = (u_int16_t)(crc & (64 - 1)); 1957 hash[hashbit / 32] |= (1 << hashbit % 32); 1958 ETHER_NEXT_MULTI(step, enm); 1959 } 1960 1961 if (mcnt > 0) { 1962 filter |= TXP_RXFILT_HASHMULTI; 1963 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1964 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1965 } 1966 } 1967 1968 setit: 1969 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1970 NULL, NULL, NULL, 1); 1971 } 1972 1973 void 1974 txp_capabilities(sc) 1975 struct txp_softc *sc; 1976 { 1977 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1978 struct txp_rsp_desc *rsp = NULL; 1979 struct txp_ext_desc *ext; 1980 1981 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1982 goto out; 1983 1984 if (rsp->rsp_numdesc != 1) 1985 goto out; 1986 ext = (struct txp_ext_desc *)(rsp + 1); 1987 1988 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1989 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1990 1991 #if NVLAN > 0 1992 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1993 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1994 sc->sc_tx_capability |= OFFLOAD_VLAN; 1995 sc->sc_rx_capability |= OFFLOAD_VLAN; 1996 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1997 } 1998 #endif 1999 2000 #if 0 2001 /* not ready yet */ 2002 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2003 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2004 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2005 ifp->if_capabilities |= IFCAP_IPSEC; 2006 } 2007 #endif 2008 2009 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2010 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2011 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2012 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 2013 } 2014 2015 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2016 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2017 #ifdef TRY_TX_TCP_CSUM 2018 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2019 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 2020 #endif 2021 } 2022 2023 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2024 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2025 #ifdef TRY_TX_UDP_CSUM 2026 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2027 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 2028 #endif 2029 } 2030 2031 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2032 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2033 goto out; 2034 2035 out: 2036 if (rsp != NULL) 2037 free(rsp, M_DEVBUF); 2038 } 2039
Indexes created Tue Sep 30 20:09:53 GMT 2025