if_txp.c revision 1.12
1 /* $NetBSD: if_txp.c,v 1.12 2005/06/18 16:10:44 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.12 2005/06/18 16:10:44 chs Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for vtophys */ 71 #include <machine/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(struct device *, struct cfdata *, void *); 91 void txp_attach(struct device *, struct device *, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, caddr_t); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 const struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(id) 167 pcireg_t id; 168 { 169 int i; 170 171 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 172 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 173 (PCI_PRODUCT(id) == txp_devices[i].did)) 174 return (&txp_devices[i]); 175 return (0); 176 } 177 178 int 179 txp_probe(parent, match, aux) 180 struct device *parent; 181 struct cfdata *match; 182 void *aux; 183 { 184 struct pci_attach_args *pa = aux; 185 186 if (txp_pcilookup(pa->pa_id)) 187 return (1); 188 return (0); 189 } 190 191 void 192 txp_attach(parent, self, aux) 193 struct device *parent, *self; 194 void *aux; 195 { 196 struct txp_softc *sc = (struct txp_softc *)self; 197 struct pci_attach_args *pa = aux; 198 pci_chipset_tag_t pc = pa->pa_pc; 199 pci_intr_handle_t ih; 200 const char *intrstr = NULL; 201 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 202 u_int32_t command; 203 u_int16_t p1; 204 u_int32_t p2; 205 u_char enaddr[6]; 206 const struct txp_pci_match *pcimatch; 207 u_int16_t subsys; 208 int i, flags; 209 char devinfo[256]; 210 211 sc->sc_cold = 1; 212 213 pcimatch = txp_pcilookup(pa->pa_id); 214 flags = pcimatch->flags; 215 if (pcimatch->flags & TXP_USESUBSYSTEM) { 216 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 217 PCI_SUBSYS_ID_REG)); 218 for (i = 0; 219 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 220 i++) 221 if ((subsys & txp_subsysinfo[i].mask) == 222 txp_subsysinfo[i].value) 223 flags |= txp_subsysinfo[i].flags; 224 } 225 sc->sc_flags = flags; 226 227 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 228 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 229 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 230 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 231 232 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 234 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 235 printf(": failed to enable bus mastering\n"); 236 return; 237 } 238 239 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 240 printf(": failed to enable memory mapping\n"); 241 return; 242 } 243 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 244 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 245 printf(": can't map mem space %d\n", 0); 246 return; 247 } 248 249 sc->sc_dmat = pa->pa_dmat; 250 251 /* 252 * Allocate our interrupt. 253 */ 254 if (pci_intr_map(pa, &ih)) { 255 printf(": couldn't map interrupt\n"); 256 return; 257 } 258 259 intrstr = pci_intr_string(pc, ih); 260 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 261 if (sc->sc_ih == NULL) { 262 printf(": couldn't establish interrupt"); 263 if (intrstr != NULL) 264 printf(" at %s", intrstr); 265 printf("\n"); 266 return; 267 } 268 printf(": interrupting at %s\n", intrstr); 269 270 if (txp_chip_init(sc)) 271 goto cleanupintr; 272 273 if (txp_download_fw(sc)) 274 goto cleanupintr; 275 276 if (txp_alloc_rings(sc)) 277 goto cleanupintr; 278 279 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 280 NULL, NULL, NULL, 1)) 281 goto cleanupintr; 282 283 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 284 &p1, &p2, NULL, 1)) 285 goto cleanupintr; 286 287 txp_set_filter(sc); 288 289 p1 = htole16(p1); 290 enaddr[0] = ((u_int8_t *)&p1)[1]; 291 enaddr[1] = ((u_int8_t *)&p1)[0]; 292 p2 = htole32(p2); 293 enaddr[2] = ((u_int8_t *)&p2)[3]; 294 enaddr[3] = ((u_int8_t *)&p2)[2]; 295 enaddr[4] = ((u_int8_t *)&p2)[1]; 296 enaddr[5] = ((u_int8_t *)&p2)[0]; 297 298 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 299 ether_sprintf(enaddr)); 300 sc->sc_cold = 0; 301 302 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 303 if (flags & TXP_FIBER) { 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 305 0, NULL); 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 309 0, NULL); 310 } else { 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 318 0, NULL); 319 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 320 0, NULL); 321 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 322 0, NULL); 323 } 324 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 325 326 sc->sc_xcvr = TXP_XCVR_AUTO; 327 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 328 NULL, NULL, NULL, 0); 329 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 330 331 ifp->if_softc = sc; 332 ifp->if_mtu = ETHERMTU; 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 334 ifp->if_ioctl = txp_ioctl; 335 ifp->if_start = txp_start; 336 ifp->if_watchdog = txp_watchdog; 337 ifp->if_baudrate = 10000000; 338 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 339 IFQ_SET_READY(&ifp->if_snd); 340 ifp->if_capabilities = 0; 341 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 342 343 txp_capabilities(sc); 344 345 callout_init(&sc->sc_tick); 346 callout_setfunc(&sc->sc_tick, txp_tick, sc); 347 348 /* 349 * Attach us everywhere 350 */ 351 if_attach(ifp); 352 ether_ifattach(ifp, enaddr); 353 354 shutdownhook_establish(txp_shutdown, sc); 355 356 357 return; 358 359 cleanupintr: 360 pci_intr_disestablish(pc,sc->sc_ih); 361 362 return; 363 364 } 365 366 int 367 txp_chip_init(sc) 368 struct txp_softc *sc; 369 { 370 /* disable interrupts */ 371 WRITE_REG(sc, TXP_IER, 0); 372 WRITE_REG(sc, TXP_IMR, 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_LATCH); 376 377 /* ack all interrupts */ 378 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 379 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 380 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 381 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 382 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 383 384 if (txp_reset_adapter(sc)) 385 return (-1); 386 387 /* disable interrupts */ 388 WRITE_REG(sc, TXP_IER, 0); 389 WRITE_REG(sc, TXP_IMR, 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_LATCH); 393 394 /* ack all interrupts */ 395 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 396 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 397 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 398 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 399 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 400 401 return (0); 402 } 403 404 int 405 txp_reset_adapter(sc) 406 struct txp_softc *sc; 407 { 408 u_int32_t r; 409 int i; 410 411 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 412 DELAY(1000); 413 WRITE_REG(sc, TXP_SRR, 0); 414 415 /* Should wait max 6 seconds */ 416 for (i = 0; i < 6000; i++) { 417 r = READ_REG(sc, TXP_A2H_0); 418 if (r == STAT_WAITING_FOR_HOST_REQUEST) 419 break; 420 DELAY(1000); 421 } 422 423 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 424 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 425 return (-1); 426 } 427 428 return (0); 429 } 430 431 int 432 txp_download_fw(sc) 433 struct txp_softc *sc; 434 { 435 const struct txp_fw_file_header *fileheader; 436 const struct txp_fw_section_header *secthead; 437 int sect; 438 u_int32_t r, i, ier, imr; 439 440 ier = READ_REG(sc, TXP_IER); 441 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 442 443 imr = READ_REG(sc, TXP_IMR); 444 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 445 446 for (i = 0; i < 10000; i++) { 447 r = READ_REG(sc, TXP_A2H_0); 448 if (r == STAT_WAITING_FOR_HOST_REQUEST) 449 break; 450 DELAY(50); 451 } 452 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 453 printf(": not waiting for host request\n"); 454 return (-1); 455 } 456 457 /* Ack the status */ 458 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 459 460 fileheader = (const struct txp_fw_file_header *)tc990image; 461 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 462 printf(": fw invalid magic\n"); 463 return (-1); 464 } 465 466 /* Tell boot firmware to get ready for image */ 467 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 468 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 469 470 if (txp_download_fw_wait(sc)) { 471 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 472 return (-1); 473 } 474 475 secthead = (const struct txp_fw_section_header *) 476 (((const u_int8_t *)tc990image) + 477 sizeof(struct txp_fw_file_header)); 478 479 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 480 if (txp_download_fw_section(sc, secthead, sect)) 481 return (-1); 482 secthead = (const struct txp_fw_section_header *) 483 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 484 sizeof(*secthead)); 485 } 486 487 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 488 489 for (i = 0; i < 10000; i++) { 490 r = READ_REG(sc, TXP_A2H_0); 491 if (r == STAT_WAITING_FOR_BOOT) 492 break; 493 DELAY(50); 494 } 495 if (r != STAT_WAITING_FOR_BOOT) { 496 printf(": not waiting for boot\n"); 497 return (-1); 498 } 499 500 WRITE_REG(sc, TXP_IER, ier); 501 WRITE_REG(sc, TXP_IMR, imr); 502 503 return (0); 504 } 505 506 int 507 txp_download_fw_wait(sc) 508 struct txp_softc *sc; 509 { 510 u_int32_t i, r; 511 512 for (i = 0; i < 10000; i++) { 513 r = READ_REG(sc, TXP_ISR); 514 if (r & TXP_INT_A2H_0) 515 break; 516 DELAY(50); 517 } 518 519 if (!(r & TXP_INT_A2H_0)) { 520 printf(": fw wait failed comm0\n"); 521 return (-1); 522 } 523 524 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 525 526 r = READ_REG(sc, TXP_A2H_0); 527 if (r != STAT_WAITING_FOR_SEGMENT) { 528 printf(": fw not waiting for segment\n"); 529 return (-1); 530 } 531 return (0); 532 } 533 534 int 535 txp_download_fw_section(sc, sect, sectnum) 536 struct txp_softc *sc; 537 const struct txp_fw_section_header *sect; 538 int sectnum; 539 { 540 struct txp_dma_alloc dma; 541 int rseg, err = 0; 542 struct mbuf m; 543 u_int16_t csum; 544 545 /* Skip zero length sections */ 546 if (sect->nbytes == 0) 547 return (0); 548 549 /* Make sure we aren't past the end of the image */ 550 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 551 if (rseg >= sizeof(tc990image)) { 552 printf(": fw invalid section address, section %d\n", sectnum); 553 return (-1); 554 } 555 556 /* Make sure this section doesn't go past the end */ 557 rseg += le32toh(sect->nbytes); 558 if (rseg >= sizeof(tc990image)) { 559 printf(": fw truncated section %d\n", sectnum); 560 return (-1); 561 } 562 563 /* map a buffer, copy segment to it, get physaddr */ 564 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 565 printf(": fw dma malloc failed, section %d\n", sectnum); 566 return (-1); 567 } 568 569 bcopy(((const u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 570 le32toh(sect->nbytes)); 571 572 /* 573 * dummy up mbuf and verify section checksum 574 */ 575 m.m_type = MT_DATA; 576 m.m_next = m.m_nextpkt = NULL; 577 m.m_len = le32toh(sect->nbytes); 578 m.m_data = dma.dma_vaddr; 579 m.m_flags = 0; 580 csum = in_cksum(&m, le32toh(sect->nbytes)); 581 if (csum != sect->cksum) { 582 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 583 sectnum, sect->cksum, csum); 584 err = -1; 585 goto bail; 586 } 587 588 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 589 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 590 591 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 592 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 593 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 594 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 595 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 596 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 597 598 if (txp_download_fw_wait(sc)) { 599 printf("%s: fw wait failed, section %d\n", 600 sc->sc_dev.dv_xname, sectnum); 601 err = -1; 602 } 603 604 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 605 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 606 607 bail: 608 txp_dma_free(sc, &dma); 609 610 return (err); 611 } 612 613 int 614 txp_intr(vsc) 615 void *vsc; 616 { 617 struct txp_softc *sc = vsc; 618 struct txp_hostvar *hv = sc->sc_hostvar; 619 u_int32_t isr; 620 int claimed = 0; 621 622 /* mask all interrupts */ 623 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 624 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 625 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 626 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 627 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 628 629 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 630 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 631 632 isr = READ_REG(sc, TXP_ISR); 633 while (isr) { 634 claimed = 1; 635 WRITE_REG(sc, TXP_ISR, isr); 636 637 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 638 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 639 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 640 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 641 642 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 643 txp_rxbuf_reclaim(sc); 644 645 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 646 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 647 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 648 649 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 650 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 651 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 652 653 isr = READ_REG(sc, TXP_ISR); 654 } 655 656 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 657 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 658 659 /* unmask all interrupts */ 660 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 661 662 txp_start(&sc->sc_arpcom.ec_if); 663 664 return (claimed); 665 } 666 667 void 668 txp_rx_reclaim(sc, r, dma) 669 struct txp_softc *sc; 670 struct txp_rx_ring *r; 671 struct txp_dma_alloc *dma; 672 { 673 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 674 struct txp_rx_desc *rxd; 675 struct mbuf *m; 676 struct txp_swdesc *sd; 677 u_int32_t roff, woff; 678 int sumflags = 0; 679 int idx; 680 681 roff = le32toh(*r->r_roff); 682 woff = le32toh(*r->r_woff); 683 idx = roff / sizeof(struct txp_rx_desc); 684 rxd = r->r_desc + idx; 685 686 while (roff != woff) { 687 688 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 689 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 690 BUS_DMASYNC_POSTREAD); 691 692 if (rxd->rx_flags & RX_FLAGS_ERROR) { 693 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 694 le32toh(rxd->rx_stat)); 695 ifp->if_ierrors++; 696 goto next; 697 } 698 699 /* retrieve stashed pointer */ 700 bcopy(__UNVOLATILE(&rxd->rx_vaddrlo), &sd, sizeof(sd)); 701 702 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 703 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 704 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 705 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 706 m = sd->sd_mbuf; 707 free(sd, M_DEVBUF); 708 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 709 710 #ifdef __STRICT_ALIGNMENT 711 { 712 /* 713 * XXX Nice chip, except it won't accept "off by 2" 714 * buffers, so we're force to copy. Supposedly 715 * this will be fixed in a newer firmware rev 716 * and this will be temporary. 717 */ 718 struct mbuf *mnew; 719 720 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 721 if (mnew == NULL) { 722 m_freem(m); 723 goto next; 724 } 725 if (m->m_len > (MHLEN - 2)) { 726 MCLGET(mnew, M_DONTWAIT); 727 if (!(mnew->m_flags & M_EXT)) { 728 m_freem(mnew); 729 m_freem(m); 730 goto next; 731 } 732 } 733 mnew->m_pkthdr.rcvif = ifp; 734 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 735 mnew->m_data += 2; 736 bcopy(m->m_data, mnew->m_data, m->m_len); 737 m_freem(m); 738 m = mnew; 739 } 740 #endif 741 742 #if NBPFILTER > 0 743 /* 744 * Handle BPF listeners. Let the BPF user see the packet. 745 */ 746 if (ifp->if_bpf) 747 bpf_mtap(ifp->if_bpf, m); 748 #endif 749 750 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 751 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 752 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 753 sumflags |= M_CSUM_IPv4; 754 755 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 756 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 757 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 758 sumflags |= M_CSUM_TCPv4; 759 760 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 761 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 762 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 763 sumflags |= M_CSUM_UDPv4; 764 765 m->m_pkthdr.csum_flags = sumflags; 766 767 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 768 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 769 continue); 770 } 771 772 (*ifp->if_input)(ifp, m); 773 774 next: 775 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 776 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 777 BUS_DMASYNC_PREREAD); 778 779 roff += sizeof(struct txp_rx_desc); 780 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 781 idx = 0; 782 roff = 0; 783 rxd = r->r_desc; 784 } else { 785 idx++; 786 rxd++; 787 } 788 woff = le32toh(*r->r_woff); 789 } 790 791 *r->r_roff = htole32(woff); 792 } 793 794 void 795 txp_rxbuf_reclaim(sc) 796 struct txp_softc *sc; 797 { 798 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 799 struct txp_hostvar *hv = sc->sc_hostvar; 800 struct txp_rxbuf_desc *rbd; 801 struct txp_swdesc *sd; 802 u_int32_t i, end; 803 804 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 805 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 806 807 if (++i == RXBUF_ENTRIES) 808 i = 0; 809 810 rbd = sc->sc_rxbufs + i; 811 812 while (i != end) { 813 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 814 M_DEVBUF, M_NOWAIT); 815 if (sd == NULL) 816 break; 817 818 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 819 if (sd->sd_mbuf == NULL) 820 goto err_sd; 821 822 MCLGET(sd->sd_mbuf, M_DONTWAIT); 823 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 824 goto err_mbuf; 825 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 826 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 827 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 828 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 829 goto err_mbuf; 830 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 831 BUS_DMA_NOWAIT)) { 832 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 833 goto err_mbuf; 834 } 835 836 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 837 i * sizeof(struct txp_rxbuf_desc), 838 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 839 840 /* stash away pointer */ 841 bcopy(&sd, __UNVOLATILE(&rbd->rb_vaddrlo), sizeof(sd)); 842 843 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 844 & 0xffffffff; 845 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 846 >> 32; 847 848 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 849 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 850 851 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 852 i * sizeof(struct txp_rxbuf_desc), 853 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 854 855 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 856 857 if (++i == RXBUF_ENTRIES) { 858 i = 0; 859 rbd = sc->sc_rxbufs; 860 } else 861 rbd++; 862 } 863 return; 864 865 err_mbuf: 866 m_freem(sd->sd_mbuf); 867 err_sd: 868 free(sd, M_DEVBUF); 869 } 870 871 /* 872 * Reclaim mbufs and entries from a transmit ring. 873 */ 874 void 875 txp_tx_reclaim(sc, r, dma) 876 struct txp_softc *sc; 877 struct txp_tx_ring *r; 878 struct txp_dma_alloc *dma; 879 { 880 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 881 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 882 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 883 struct txp_tx_desc *txd = r->r_desc + cons; 884 struct txp_swdesc *sd = sc->sc_txd + cons; 885 struct mbuf *m; 886 887 while (cons != idx) { 888 if (cnt == 0) 889 break; 890 891 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 892 cons * sizeof(struct txp_tx_desc), 893 sizeof(struct txp_tx_desc), 894 BUS_DMASYNC_POSTWRITE); 895 896 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 897 TX_FLAGS_TYPE_DATA) { 898 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 899 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 900 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 901 m = sd->sd_mbuf; 902 if (m != NULL) { 903 m_freem(m); 904 txd->tx_addrlo = 0; 905 txd->tx_addrhi = 0; 906 ifp->if_opackets++; 907 } 908 } 909 ifp->if_flags &= ~IFF_OACTIVE; 910 911 if (++cons == TX_ENTRIES) { 912 txd = r->r_desc; 913 cons = 0; 914 sd = sc->sc_txd; 915 } else { 916 txd++; 917 sd++; 918 } 919 920 cnt--; 921 } 922 923 r->r_cons = cons; 924 r->r_cnt = cnt; 925 if (cnt == 0) 926 ifp->if_timer = 0; 927 } 928 929 void 930 txp_shutdown(vsc) 931 void *vsc; 932 { 933 struct txp_softc *sc = (struct txp_softc *)vsc; 934 935 /* mask all interrupts */ 936 WRITE_REG(sc, TXP_IMR, 937 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 938 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 939 TXP_INT_LATCH); 940 941 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 942 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 943 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 944 } 945 946 int 947 txp_alloc_rings(sc) 948 struct txp_softc *sc; 949 { 950 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 951 struct txp_boot_record *boot; 952 struct txp_swdesc *sd; 953 u_int32_t r; 954 int i, j; 955 956 /* boot record */ 957 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 958 BUS_DMA_COHERENT)) { 959 printf(": can't allocate boot record\n"); 960 return (-1); 961 } 962 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 963 bzero(boot, sizeof(*boot)); 964 sc->sc_boot = boot; 965 966 /* host variables */ 967 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 968 BUS_DMA_COHERENT)) { 969 printf(": can't allocate host ring\n"); 970 goto bail_boot; 971 } 972 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 973 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 974 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 975 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 976 977 /* high priority tx ring */ 978 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 979 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 980 printf(": can't allocate high tx ring\n"); 981 goto bail_host; 982 } 983 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 984 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 985 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 986 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 987 sc->sc_txhir.r_reg = TXP_H2A_1; 988 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 989 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 990 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 991 for (i = 0; i < TX_ENTRIES; i++) { 992 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 993 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 994 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 995 for (j = 0; j < i; j++) { 996 bus_dmamap_destroy(sc->sc_dmat, 997 sc->sc_txd[j].sd_map); 998 sc->sc_txd[j].sd_map = NULL; 999 } 1000 goto bail_txhiring; 1001 } 1002 } 1003 1004 /* low priority tx ring */ 1005 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1006 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1007 printf(": can't allocate low tx ring\n"); 1008 goto bail_txhiring; 1009 } 1010 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1011 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1012 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1013 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1014 sc->sc_txlor.r_reg = TXP_H2A_3; 1015 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1016 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1017 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1018 1019 /* high priority rx ring */ 1020 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1021 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1022 printf(": can't allocate high rx ring\n"); 1023 goto bail_txloring; 1024 } 1025 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1026 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1027 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1028 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1029 sc->sc_rxhir.r_desc = 1030 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1031 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1032 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1033 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1034 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1035 1036 /* low priority ring */ 1037 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1038 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1039 printf(": can't allocate low rx ring\n"); 1040 goto bail_rxhiring; 1041 } 1042 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1043 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1044 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1045 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1046 sc->sc_rxlor.r_desc = 1047 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1048 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1049 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1050 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1051 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1052 1053 /* command ring */ 1054 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1055 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1056 printf(": can't allocate command ring\n"); 1057 goto bail_rxloring; 1058 } 1059 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1060 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1061 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1062 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1063 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1064 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1065 sc->sc_cmdring.lastwrite = 0; 1066 1067 /* response ring */ 1068 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1069 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1070 printf(": can't allocate response ring\n"); 1071 goto bail_cmdring; 1072 } 1073 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1074 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1075 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1076 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1077 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1078 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1079 sc->sc_rspring.lastwrite = 0; 1080 1081 /* receive buffer ring */ 1082 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1083 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1084 printf(": can't allocate rx buffer ring\n"); 1085 goto bail_rspring; 1086 } 1087 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1088 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1089 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1090 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1091 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1092 for (i = 0; i < RXBUF_ENTRIES; i++) { 1093 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1094 M_DEVBUF, M_NOWAIT); 1095 if (sd == NULL) 1096 break; 1097 1098 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1099 if (sd->sd_mbuf == NULL) { 1100 goto bail_rxbufring; 1101 } 1102 1103 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1104 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1105 goto bail_rxbufring; 1106 } 1107 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1108 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1109 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1110 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1111 goto bail_rxbufring; 1112 } 1113 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1114 BUS_DMA_NOWAIT)) { 1115 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1116 goto bail_rxbufring; 1117 } 1118 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1119 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1120 1121 /* stash away pointer */ 1122 bcopy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), sizeof(sd)); 1123 1124 sc->sc_rxbufs[i].rb_paddrlo = 1125 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1126 sc->sc_rxbufs[i].rb_paddrhi = 1127 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1128 } 1129 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1130 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1131 BUS_DMASYNC_PREWRITE); 1132 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1133 sizeof(struct txp_rxbuf_desc)); 1134 1135 /* zero dma */ 1136 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1137 BUS_DMA_COHERENT)) { 1138 printf(": can't allocate response ring\n"); 1139 goto bail_rxbufring; 1140 } 1141 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1142 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1143 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1144 1145 /* See if it's waiting for boot, and try to boot it */ 1146 for (i = 0; i < 10000; i++) { 1147 r = READ_REG(sc, TXP_A2H_0); 1148 if (r == STAT_WAITING_FOR_BOOT) 1149 break; 1150 DELAY(50); 1151 } 1152 if (r != STAT_WAITING_FOR_BOOT) { 1153 printf(": not waiting for boot\n"); 1154 goto bail; 1155 } 1156 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1157 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1158 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1159 1160 /* See if it booted */ 1161 for (i = 0; i < 10000; i++) { 1162 r = READ_REG(sc, TXP_A2H_0); 1163 if (r == STAT_RUNNING) 1164 break; 1165 DELAY(50); 1166 } 1167 if (r != STAT_RUNNING) { 1168 printf(": fw not running\n"); 1169 goto bail; 1170 } 1171 1172 /* Clear TX and CMD ring write registers */ 1173 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1174 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1175 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1176 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1177 1178 return (0); 1179 1180 bail: 1181 txp_dma_free(sc, &sc->sc_zero_dma); 1182 bail_rxbufring: 1183 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1184 bail_rspring: 1185 txp_dma_free(sc, &sc->sc_rspring_dma); 1186 bail_cmdring: 1187 txp_dma_free(sc, &sc->sc_cmdring_dma); 1188 bail_rxloring: 1189 txp_dma_free(sc, &sc->sc_rxloring_dma); 1190 bail_rxhiring: 1191 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1192 bail_txloring: 1193 txp_dma_free(sc, &sc->sc_txloring_dma); 1194 bail_txhiring: 1195 txp_dma_free(sc, &sc->sc_txhiring_dma); 1196 bail_host: 1197 txp_dma_free(sc, &sc->sc_host_dma); 1198 bail_boot: 1199 txp_dma_free(sc, &sc->sc_boot_dma); 1200 return (-1); 1201 } 1202 1203 int 1204 txp_dma_malloc(sc, size, dma, mapflags) 1205 struct txp_softc *sc; 1206 bus_size_t size; 1207 struct txp_dma_alloc *dma; 1208 int mapflags; 1209 { 1210 int r; 1211 1212 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1213 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1214 goto fail_0; 1215 1216 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1217 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1218 goto fail_1; 1219 1220 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1221 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1222 goto fail_2; 1223 1224 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1225 size, NULL, BUS_DMA_NOWAIT)) != 0) 1226 goto fail_3; 1227 1228 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1229 return (0); 1230 1231 fail_3: 1232 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1233 fail_2: 1234 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1235 fail_1: 1236 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1237 fail_0: 1238 return (r); 1239 } 1240 1241 void 1242 txp_dma_free(sc, dma) 1243 struct txp_softc *sc; 1244 struct txp_dma_alloc *dma; 1245 { 1246 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1247 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1248 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1249 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1250 } 1251 1252 int 1253 txp_ioctl(ifp, command, data) 1254 struct ifnet *ifp; 1255 u_long command; 1256 caddr_t data; 1257 { 1258 struct txp_softc *sc = ifp->if_softc; 1259 struct ifreq *ifr = (struct ifreq *)data; 1260 struct ifaddr *ifa = (struct ifaddr *)data; 1261 int s, error = 0; 1262 1263 s = splnet(); 1264 1265 #if 0 1266 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1267 splx(s); 1268 return error; 1269 } 1270 #endif 1271 1272 switch(command) { 1273 case SIOCSIFADDR: 1274 ifp->if_flags |= IFF_UP; 1275 switch (ifa->ifa_addr->sa_family) { 1276 #ifdef INET 1277 case AF_INET: 1278 txp_init(sc); 1279 arp_ifinit(ifp, ifa); 1280 break; 1281 #endif /* INET */ 1282 default: 1283 txp_init(sc); 1284 break; 1285 } 1286 break; 1287 case SIOCSIFFLAGS: 1288 if (ifp->if_flags & IFF_UP) { 1289 txp_init(sc); 1290 } else { 1291 if (ifp->if_flags & IFF_RUNNING) 1292 txp_stop(sc); 1293 } 1294 break; 1295 case SIOCADDMULTI: 1296 case SIOCDELMULTI: 1297 error = (command == SIOCADDMULTI) ? 1298 ether_addmulti(ifr, &sc->sc_arpcom) : 1299 ether_delmulti(ifr, &sc->sc_arpcom); 1300 1301 if (error == ENETRESET) { 1302 /* 1303 * Multicast list has changed; set the hardware 1304 * filter accordingly. 1305 */ 1306 if (ifp->if_flags & IFF_RUNNING) 1307 txp_set_filter(sc); 1308 error = 0; 1309 } 1310 break; 1311 case SIOCGIFMEDIA: 1312 case SIOCSIFMEDIA: 1313 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1314 break; 1315 default: 1316 error = EINVAL; 1317 break; 1318 } 1319 1320 splx(s); 1321 1322 return(error); 1323 } 1324 1325 void 1326 txp_init(sc) 1327 struct txp_softc *sc; 1328 { 1329 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1330 int s; 1331 1332 txp_stop(sc); 1333 1334 s = splnet(); 1335 1336 txp_set_filter(sc); 1337 1338 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1339 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1340 1341 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1342 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1343 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1344 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1345 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1346 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1347 1348 ifp->if_flags |= IFF_RUNNING; 1349 ifp->if_flags &= ~IFF_OACTIVE; 1350 ifp->if_timer = 0; 1351 1352 if (!callout_pending(&sc->sc_tick)) 1353 callout_schedule(&sc->sc_tick, hz); 1354 1355 splx(s); 1356 } 1357 1358 void 1359 txp_tick(vsc) 1360 void *vsc; 1361 { 1362 struct txp_softc *sc = vsc; 1363 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1364 struct txp_rsp_desc *rsp = NULL; 1365 struct txp_ext_desc *ext; 1366 int s; 1367 1368 s = splnet(); 1369 txp_rxbuf_reclaim(sc); 1370 1371 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1372 &rsp, 1)) 1373 goto out; 1374 if (rsp->rsp_numdesc != 6) 1375 goto out; 1376 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1377 NULL, NULL, NULL, 1)) 1378 goto out; 1379 ext = (struct txp_ext_desc *)(rsp + 1); 1380 1381 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1382 ext[4].ext_1 + ext[4].ext_4; 1383 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1384 ext[2].ext_1; 1385 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1386 ext[1].ext_3; 1387 ifp->if_opackets += rsp->rsp_par2; 1388 ifp->if_ipackets += ext[2].ext_3; 1389 1390 out: 1391 if (rsp != NULL) 1392 free(rsp, M_DEVBUF); 1393 1394 splx(s); 1395 callout_schedule(&sc->sc_tick, hz); 1396 } 1397 1398 void 1399 txp_start(ifp) 1400 struct ifnet *ifp; 1401 { 1402 struct txp_softc *sc = ifp->if_softc; 1403 struct txp_tx_ring *r = &sc->sc_txhir; 1404 struct txp_tx_desc *txd; 1405 int txdidx; 1406 struct txp_frag_desc *fxd; 1407 struct mbuf *m, *mnew; 1408 struct txp_swdesc *sd; 1409 u_int32_t firstprod, firstcnt, prod, cnt, i; 1410 struct m_tag *mtag; 1411 1412 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1413 return; 1414 1415 prod = r->r_prod; 1416 cnt = r->r_cnt; 1417 1418 while (1) { 1419 IFQ_POLL(&ifp->if_snd, m); 1420 if (m == NULL) 1421 break; 1422 mnew = NULL; 1423 1424 firstprod = prod; 1425 firstcnt = cnt; 1426 1427 sd = sc->sc_txd + prod; 1428 sd->sd_mbuf = m; 1429 1430 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1431 BUS_DMA_NOWAIT)) { 1432 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1433 if (mnew == NULL) 1434 goto oactive1; 1435 if (m->m_pkthdr.len > MHLEN) { 1436 MCLGET(mnew, M_DONTWAIT); 1437 if ((mnew->m_flags & M_EXT) == 0) { 1438 m_freem(mnew); 1439 goto oactive1; 1440 } 1441 } 1442 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1443 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1444 IFQ_DEQUEUE(&ifp->if_snd, m); 1445 m_freem(m); 1446 m = mnew; 1447 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1448 BUS_DMA_NOWAIT)) 1449 goto oactive1; 1450 } 1451 1452 if ((TX_ENTRIES - cnt) < 4) 1453 goto oactive; 1454 1455 txd = r->r_desc + prod; 1456 txdidx = prod; 1457 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1458 txd->tx_numdesc = 0; 1459 txd->tx_addrlo = 0; 1460 txd->tx_addrhi = 0; 1461 txd->tx_totlen = m->m_pkthdr.len; 1462 txd->tx_pflags = 0; 1463 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1464 1465 if (++prod == TX_ENTRIES) 1466 prod = 0; 1467 1468 if (++cnt >= (TX_ENTRIES - 4)) 1469 goto oactive; 1470 1471 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1472 txd->tx_pflags = TX_PFLAGS_VLAN | 1473 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1474 1475 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1476 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1477 #ifdef TRY_TX_TCP_CSUM 1478 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1479 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1480 #endif 1481 #ifdef TRY_TX_UDP_CSUM 1482 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1483 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1484 #endif 1485 1486 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1487 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1488 1489 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1490 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1491 if (++cnt >= (TX_ENTRIES - 4)) { 1492 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1493 0, sd->sd_map->dm_mapsize, 1494 BUS_DMASYNC_POSTWRITE); 1495 goto oactive; 1496 } 1497 1498 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1499 FRAG_FLAGS_VALID; 1500 fxd->frag_rsvd1 = 0; 1501 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1502 fxd->frag_addrlo = 1503 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1504 0xffffffff; 1505 fxd->frag_addrhi = 1506 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1507 32; 1508 fxd->frag_rsvd2 = 0; 1509 1510 bus_dmamap_sync(sc->sc_dmat, 1511 sc->sc_txhiring_dma.dma_map, 1512 prod * sizeof(struct txp_frag_desc), 1513 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1514 1515 if (++prod == TX_ENTRIES) { 1516 fxd = (struct txp_frag_desc *)r->r_desc; 1517 prod = 0; 1518 } else 1519 fxd++; 1520 1521 } 1522 1523 /* 1524 * if mnew isn't NULL, we already dequeued and copied 1525 * the packet. 1526 */ 1527 if (mnew == NULL) 1528 IFQ_DEQUEUE(&ifp->if_snd, m); 1529 1530 ifp->if_timer = 5; 1531 1532 #if NBPFILTER > 0 1533 if (ifp->if_bpf) 1534 bpf_mtap(ifp->if_bpf, m); 1535 #endif 1536 1537 txd->tx_flags |= TX_FLAGS_VALID; 1538 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1539 txdidx * sizeof(struct txp_tx_desc), 1540 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1541 1542 #if 0 1543 { 1544 struct mbuf *mx; 1545 int i; 1546 1547 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1548 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1549 txd->tx_pflags); 1550 for (mx = m; mx != NULL; mx = mx->m_next) { 1551 for (i = 0; i < mx->m_len; i++) { 1552 printf(":%02x", 1553 (u_int8_t)m->m_data[i]); 1554 } 1555 } 1556 printf("\n"); 1557 } 1558 #endif 1559 1560 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1561 } 1562 1563 r->r_prod = prod; 1564 r->r_cnt = cnt; 1565 return; 1566 1567 oactive: 1568 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1569 oactive1: 1570 ifp->if_flags |= IFF_OACTIVE; 1571 r->r_prod = firstprod; 1572 r->r_cnt = firstcnt; 1573 } 1574 1575 /* 1576 * Handle simple commands sent to the typhoon 1577 */ 1578 int 1579 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1580 struct txp_softc *sc; 1581 u_int16_t id, in1, *out1; 1582 u_int32_t in2, in3, *out2, *out3; 1583 int wait; 1584 { 1585 struct txp_rsp_desc *rsp = NULL; 1586 1587 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1588 return (-1); 1589 1590 if (!wait) 1591 return (0); 1592 1593 if (out1 != NULL) 1594 *out1 = le16toh(rsp->rsp_par1); 1595 if (out2 != NULL) 1596 *out2 = le32toh(rsp->rsp_par2); 1597 if (out3 != NULL) 1598 *out3 = le32toh(rsp->rsp_par3); 1599 free(rsp, M_DEVBUF); 1600 return (0); 1601 } 1602 1603 int 1604 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1605 struct txp_softc *sc; 1606 u_int16_t id, in1; 1607 u_int32_t in2, in3; 1608 struct txp_ext_desc *in_extp; 1609 u_int8_t in_extn; 1610 struct txp_rsp_desc **rspp; 1611 int wait; 1612 { 1613 struct txp_hostvar *hv = sc->sc_hostvar; 1614 struct txp_cmd_desc *cmd; 1615 struct txp_ext_desc *ext; 1616 u_int32_t idx, i; 1617 u_int16_t seq; 1618 1619 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1620 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1621 return (-1); 1622 } 1623 1624 idx = sc->sc_cmdring.lastwrite; 1625 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1626 bzero(cmd, sizeof(*cmd)); 1627 1628 cmd->cmd_numdesc = in_extn; 1629 seq = sc->sc_seq++; 1630 cmd->cmd_seq = htole16(seq); 1631 cmd->cmd_id = htole16(id); 1632 cmd->cmd_par1 = htole16(in1); 1633 cmd->cmd_par2 = htole32(in2); 1634 cmd->cmd_par3 = htole32(in3); 1635 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1636 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1637 1638 idx += sizeof(struct txp_cmd_desc); 1639 if (idx == sc->sc_cmdring.size) 1640 idx = 0; 1641 1642 for (i = 0; i < in_extn; i++) { 1643 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1644 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1645 in_extp++; 1646 idx += sizeof(struct txp_cmd_desc); 1647 if (idx == sc->sc_cmdring.size) 1648 idx = 0; 1649 } 1650 1651 sc->sc_cmdring.lastwrite = idx; 1652 1653 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1654 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1655 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1656 1657 if (!wait) 1658 return (0); 1659 1660 for (i = 0; i < 10000; i++) { 1661 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1662 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1663 idx = le32toh(hv->hv_resp_read_idx); 1664 if (idx != le32toh(hv->hv_resp_write_idx)) { 1665 *rspp = NULL; 1666 if (txp_response(sc, idx, id, seq, rspp)) 1667 return (-1); 1668 if (*rspp != NULL) 1669 break; 1670 } 1671 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1672 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1673 DELAY(50); 1674 } 1675 if (i == 1000 || (*rspp) == NULL) { 1676 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1677 return (-1); 1678 } 1679 1680 return (0); 1681 } 1682 1683 int 1684 txp_response(sc, ridx, id, seq, rspp) 1685 struct txp_softc *sc; 1686 u_int32_t ridx; 1687 u_int16_t id; 1688 u_int16_t seq; 1689 struct txp_rsp_desc **rspp; 1690 { 1691 struct txp_hostvar *hv = sc->sc_hostvar; 1692 struct txp_rsp_desc *rsp; 1693 1694 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1695 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1696 1697 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1698 *rspp = (struct txp_rsp_desc *)malloc( 1699 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1700 M_DEVBUF, M_NOWAIT); 1701 if ((*rspp) == NULL) 1702 return (-1); 1703 txp_rsp_fixup(sc, rsp, *rspp); 1704 return (0); 1705 } 1706 1707 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1708 printf("%s: response error: id 0x%x\n", 1709 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1710 txp_rsp_fixup(sc, rsp, NULL); 1711 ridx = le32toh(hv->hv_resp_read_idx); 1712 continue; 1713 } 1714 1715 switch (le16toh(rsp->rsp_id)) { 1716 case TXP_CMD_CYCLE_STATISTICS: 1717 case TXP_CMD_MEDIA_STATUS_READ: 1718 break; 1719 case TXP_CMD_HELLO_RESPONSE: 1720 printf("%s: hello\n", TXP_DEVNAME(sc)); 1721 break; 1722 default: 1723 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1724 le16toh(rsp->rsp_id)); 1725 } 1726 1727 txp_rsp_fixup(sc, rsp, NULL); 1728 ridx = le32toh(hv->hv_resp_read_idx); 1729 hv->hv_resp_read_idx = le32toh(ridx); 1730 } 1731 1732 return (0); 1733 } 1734 1735 void 1736 txp_rsp_fixup(sc, rsp, dst) 1737 struct txp_softc *sc; 1738 struct txp_rsp_desc *rsp, *dst; 1739 { 1740 struct txp_rsp_desc *src = rsp; 1741 struct txp_hostvar *hv = sc->sc_hostvar; 1742 u_int32_t i, ridx; 1743 1744 ridx = le32toh(hv->hv_resp_read_idx); 1745 1746 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1747 if (dst != NULL) 1748 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1749 ridx += sizeof(struct txp_rsp_desc); 1750 if (ridx == sc->sc_rspring.size) { 1751 src = sc->sc_rspring.base; 1752 ridx = 0; 1753 } else 1754 src++; 1755 sc->sc_rspring.lastwrite = ridx; 1756 hv->hv_resp_read_idx = htole32(ridx); 1757 } 1758 1759 hv->hv_resp_read_idx = htole32(ridx); 1760 } 1761 1762 int 1763 txp_cmd_desc_numfree(sc) 1764 struct txp_softc *sc; 1765 { 1766 struct txp_hostvar *hv = sc->sc_hostvar; 1767 struct txp_boot_record *br = sc->sc_boot; 1768 u_int32_t widx, ridx, nfree; 1769 1770 widx = sc->sc_cmdring.lastwrite; 1771 ridx = le32toh(hv->hv_cmd_read_idx); 1772 1773 if (widx == ridx) { 1774 /* Ring is completely free */ 1775 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1776 } else { 1777 if (widx > ridx) 1778 nfree = le32toh(br->br_cmd_siz) - 1779 (widx - ridx + sizeof(struct txp_cmd_desc)); 1780 else 1781 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1782 } 1783 1784 return (nfree / sizeof(struct txp_cmd_desc)); 1785 } 1786 1787 void 1788 txp_stop(sc) 1789 struct txp_softc *sc; 1790 { 1791 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1792 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1793 1794 if (callout_pending(&sc->sc_tick)) 1795 callout_stop(&sc->sc_tick); 1796 } 1797 1798 void 1799 txp_watchdog(ifp) 1800 struct ifnet *ifp; 1801 { 1802 } 1803 1804 int 1805 txp_ifmedia_upd(ifp) 1806 struct ifnet *ifp; 1807 { 1808 struct txp_softc *sc = ifp->if_softc; 1809 struct ifmedia *ifm = &sc->sc_ifmedia; 1810 u_int16_t new_xcvr; 1811 1812 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1813 return (EINVAL); 1814 1815 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1816 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1817 new_xcvr = TXP_XCVR_10_FDX; 1818 else 1819 new_xcvr = TXP_XCVR_10_HDX; 1820 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1821 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1822 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1823 new_xcvr = TXP_XCVR_100_FDX; 1824 else 1825 new_xcvr = TXP_XCVR_100_HDX; 1826 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1827 new_xcvr = TXP_XCVR_AUTO; 1828 } else 1829 return (EINVAL); 1830 1831 /* nothing to do */ 1832 if (sc->sc_xcvr == new_xcvr) 1833 return (0); 1834 1835 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1836 NULL, NULL, NULL, 0); 1837 sc->sc_xcvr = new_xcvr; 1838 1839 return (0); 1840 } 1841 1842 void 1843 txp_ifmedia_sts(ifp, ifmr) 1844 struct ifnet *ifp; 1845 struct ifmediareq *ifmr; 1846 { 1847 struct txp_softc *sc = ifp->if_softc; 1848 struct ifmedia *ifm = &sc->sc_ifmedia; 1849 u_int16_t bmsr, bmcr, anlpar; 1850 1851 ifmr->ifm_status = IFM_AVALID; 1852 ifmr->ifm_active = IFM_ETHER; 1853 1854 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1855 &bmsr, NULL, NULL, 1)) 1856 goto bail; 1857 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1858 &bmsr, NULL, NULL, 1)) 1859 goto bail; 1860 1861 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1862 &bmcr, NULL, NULL, 1)) 1863 goto bail; 1864 1865 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1866 &anlpar, NULL, NULL, 1)) 1867 goto bail; 1868 1869 if (bmsr & BMSR_LINK) 1870 ifmr->ifm_status |= IFM_ACTIVE; 1871 1872 if (bmcr & BMCR_ISO) { 1873 ifmr->ifm_active |= IFM_NONE; 1874 ifmr->ifm_status = 0; 1875 return; 1876 } 1877 1878 if (bmcr & BMCR_LOOP) 1879 ifmr->ifm_active |= IFM_LOOP; 1880 1881 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1882 if ((bmsr & BMSR_ACOMP) == 0) { 1883 ifmr->ifm_active |= IFM_NONE; 1884 return; 1885 } 1886 1887 if (anlpar & ANLPAR_T4) 1888 ifmr->ifm_active |= IFM_100_T4; 1889 else if (anlpar & ANLPAR_TX_FD) 1890 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1891 else if (anlpar & ANLPAR_TX) 1892 ifmr->ifm_active |= IFM_100_TX; 1893 else if (anlpar & ANLPAR_10_FD) 1894 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1895 else if (anlpar & ANLPAR_10) 1896 ifmr->ifm_active |= IFM_10_T; 1897 else 1898 ifmr->ifm_active |= IFM_NONE; 1899 } else 1900 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1901 return; 1902 1903 bail: 1904 ifmr->ifm_active |= IFM_NONE; 1905 ifmr->ifm_status &= ~IFM_AVALID; 1906 } 1907 1908 void 1909 txp_show_descriptor(d) 1910 void *d; 1911 { 1912 struct txp_cmd_desc *cmd = d; 1913 struct txp_rsp_desc *rsp = d; 1914 struct txp_tx_desc *txd = d; 1915 struct txp_frag_desc *frgd = d; 1916 1917 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1918 case CMD_FLAGS_TYPE_CMD: 1919 /* command descriptor */ 1920 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1921 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1922 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1923 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1924 break; 1925 case CMD_FLAGS_TYPE_RESP: 1926 /* response descriptor */ 1927 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1928 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1929 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1930 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1931 break; 1932 case CMD_FLAGS_TYPE_DATA: 1933 /* data header (assuming tx for now) */ 1934 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1935 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1936 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1937 break; 1938 case CMD_FLAGS_TYPE_FRAG: 1939 /* fragment descriptor */ 1940 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1941 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1942 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1943 break; 1944 default: 1945 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1946 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1947 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1948 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1949 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1950 break; 1951 } 1952 } 1953 1954 void 1955 txp_set_filter(sc) 1956 struct txp_softc *sc; 1957 { 1958 struct ethercom *ac = &sc->sc_arpcom; 1959 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1960 u_int32_t crc, carry, hashbit, hash[2]; 1961 u_int16_t filter; 1962 u_int8_t octet; 1963 int i, j, mcnt = 0; 1964 struct ether_multi *enm; 1965 struct ether_multistep step; 1966 1967 if (ifp->if_flags & IFF_PROMISC) { 1968 filter = TXP_RXFILT_PROMISC; 1969 goto setit; 1970 } 1971 1972 again: 1973 filter = TXP_RXFILT_DIRECT; 1974 1975 if (ifp->if_flags & IFF_BROADCAST) 1976 filter |= TXP_RXFILT_BROADCAST; 1977 1978 if (ifp->if_flags & IFF_ALLMULTI) 1979 filter |= TXP_RXFILT_ALLMULTI; 1980 else { 1981 hash[0] = hash[1] = 0; 1982 1983 ETHER_FIRST_MULTI(step, ac, enm); 1984 while (enm != NULL) { 1985 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1986 /* 1987 * We must listen to a range of multicast 1988 * addresses. For now, just accept all 1989 * multicasts, rather than trying to set only 1990 * those filter bits needed to match the range. 1991 * (At this time, the only use of address 1992 * ranges is for IP multicast routing, for 1993 * which the range is big enough to require 1994 * all bits set.) 1995 */ 1996 ifp->if_flags |= IFF_ALLMULTI; 1997 goto again; 1998 } 1999 2000 mcnt++; 2001 crc = 0xffffffff; 2002 2003 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2004 octet = enm->enm_addrlo[i]; 2005 for (j = 0; j < 8; j++) { 2006 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2007 (octet & 1); 2008 crc <<= 1; 2009 octet >>= 1; 2010 if (carry) 2011 crc = (crc ^ TXP_POLYNOMIAL) | 2012 carry; 2013 } 2014 } 2015 hashbit = (u_int16_t)(crc & (64 - 1)); 2016 hash[hashbit / 32] |= (1 << hashbit % 32); 2017 ETHER_NEXT_MULTI(step, enm); 2018 } 2019 2020 if (mcnt > 0) { 2021 filter |= TXP_RXFILT_HASHMULTI; 2022 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2023 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2024 } 2025 } 2026 2027 setit: 2028 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2029 NULL, NULL, NULL, 1); 2030 } 2031 2032 void 2033 txp_capabilities(sc) 2034 struct txp_softc *sc; 2035 { 2036 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2037 struct txp_rsp_desc *rsp = NULL; 2038 struct txp_ext_desc *ext; 2039 2040 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2041 goto out; 2042 2043 if (rsp->rsp_numdesc != 1) 2044 goto out; 2045 ext = (struct txp_ext_desc *)(rsp + 1); 2046 2047 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2048 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2049 2050 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2051 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2052 sc->sc_tx_capability |= OFFLOAD_VLAN; 2053 sc->sc_rx_capability |= OFFLOAD_VLAN; 2054 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2055 } 2056 2057 #if 0 2058 /* not ready yet */ 2059 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2060 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2061 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2062 ifp->if_capabilities |= IFCAP_IPSEC; 2063 } 2064 #endif 2065 2066 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2067 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2068 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2069 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2070 } 2071 2072 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2073 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2074 #ifdef TRY_TX_TCP_CSUM 2075 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2076 ifp->if_capabilities |= 2077 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2078 #endif 2079 } 2080 2081 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2082 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2083 #ifdef TRY_TX_UDP_CSUM 2084 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2085 ifp->if_capabilities |= 2086 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2087 #endif 2088 } 2089 2090 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2091 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2092 goto out; 2093 2094 out: 2095 if (rsp != NULL) 2096 free(rsp, M_DEVBUF); 2097 } 2098
Indexes created Tue Sep 30 20:09:53 GMT 2025