if_txp.c revision 1.2
1 /* $NetBSD: if_txp.c,v 1.2 2003/07/07 15:18:24 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include "bpfilter.h" 35 /* #include "vlan.h" XXX notyet */ 36 #include "opt_inet.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/sockio.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/device.h> 46 #include <sys/callout.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_types.h> 51 #include <net/if_ether.h> 52 #include <net/if_arp.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_inarp.h> 60 #endif 61 62 #include <net/if_media.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #endif 67 68 #if NVLAN > 0 69 #include <net/if_vlanvar.h> 70 #endif 71 72 #include <uvm/uvm_extern.h> /* for vtophys */ 73 #include <machine/bus.h> 74 75 #include <dev/mii/mii.h> 76 #include <dev/mii/miivar.h> 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/if_txpreg.h> 82 83 #include <dev/microcode/typhoon/3c990img.h> 84 85 /* 86 * These currently break the 3c990 firmware, hopefully will be resolved 87 * at some point. 88 */ 89 #undef TRY_TX_UDP_CSUM 90 #undef TRY_TX_TCP_CSUM 91 92 int txp_probe(struct device *, struct cfdata *, void *); 93 void txp_attach(struct device *, struct device *, void *); 94 int txp_intr(void *); 95 void txp_tick(void *); 96 void txp_shutdown(void *); 97 int txp_ioctl(struct ifnet *, u_long, caddr_t); 98 void txp_start(struct ifnet *); 99 void txp_stop(struct txp_softc *); 100 void txp_init(struct txp_softc *); 101 void txp_watchdog(struct ifnet *); 102 103 int txp_chip_init(struct txp_softc *); 104 int txp_reset_adapter(struct txp_softc *); 105 int txp_download_fw(struct txp_softc *); 106 int txp_download_fw_wait(struct txp_softc *); 107 int txp_download_fw_section(struct txp_softc *, 108 struct txp_fw_section_header *, int); 109 int txp_alloc_rings(struct txp_softc *); 110 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 111 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 112 void txp_set_filter(struct txp_softc *); 113 114 int txp_cmd_desc_numfree(struct txp_softc *); 115 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 116 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 117 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 118 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 119 struct txp_rsp_desc **, int); 120 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 121 struct txp_rsp_desc **); 122 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 123 struct txp_rsp_desc *); 124 void txp_capabilities(struct txp_softc *); 125 126 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 127 int txp_ifmedia_upd(struct ifnet *); 128 void txp_show_descriptor(void *); 129 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 130 struct txp_dma_alloc *); 131 void txp_rxbuf_reclaim(struct txp_softc *); 132 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 133 struct txp_dma_alloc *); 134 135 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 136 NULL, NULL); 137 138 const struct txp_pci_match { 139 int vid, did, flags; 140 } txp_devices[] = { 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 148 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 149 }; 150 151 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 152 153 static const struct { 154 u_int16_t mask, value; 155 int flags; 156 } txp_subsysinfo[] = { 157 {0xf000, 0x2000, TXP_SERVERVERSION}, 158 {0x0100, 0x0100, TXP_FIBER}, 159 #if 0 /* information from 3com header, unused */ 160 {0x0010, 0x0010, /* secured firmware */}, 161 {0x0003, 0x0000, /* variable DES */}, 162 {0x0003, 0x0001, /* single DES - "95" */}, 163 {0x0003, 0x0002, /* triple DES - "97" */}, 164 #endif 165 }; 166 167 static const struct txp_pci_match * 168 txp_pcilookup(id) 169 pcireg_t id; 170 { 171 int i; 172 173 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 174 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 175 (PCI_PRODUCT(id) == txp_devices[i].did)) 176 return (&txp_devices[i]); 177 return (0); 178 } 179 180 int 181 txp_probe(parent, match, aux) 182 struct device *parent; 183 struct cfdata *match; 184 void *aux; 185 { 186 struct pci_attach_args *pa = aux; 187 188 if (txp_pcilookup(pa->pa_id)) 189 return (1); 190 return (0); 191 } 192 193 void 194 txp_attach(parent, self, aux) 195 struct device *parent, *self; 196 void *aux; 197 { 198 struct txp_softc *sc = (struct txp_softc *)self; 199 struct pci_attach_args *pa = aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pci_intr_handle_t ih; 202 const char *intrstr = NULL; 203 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 204 u_int32_t command; 205 u_int16_t p1; 206 u_int32_t p2; 207 u_char enaddr[6]; 208 const struct txp_pci_match *pcimatch; 209 u_int16_t subsys; 210 int i, flags; 211 char devinfo[256]; 212 213 sc->sc_cold = 1; 214 215 pcimatch = txp_pcilookup(pa->pa_id); 216 flags = pcimatch->flags; 217 if (pcimatch->flags & TXP_USESUBSYSTEM) { 218 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 219 PCI_SUBSYS_ID_REG)); 220 for (i = 0; 221 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 222 i++) 223 if ((subsys & txp_subsysinfo[i].mask) == 224 txp_subsysinfo[i].value) 225 flags |= txp_subsysinfo[i].flags; 226 } 227 sc->sc_flags = flags; 228 229 pci_devinfo(pa->pa_id, 0, 0, devinfo); 230 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 231 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 232 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 233 234 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 235 236 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 237 printf(": failed to enable bus mastering\n"); 238 return; 239 } 240 241 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 242 printf(": failed to enable memory mapping\n"); 243 return; 244 } 245 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 246 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 247 printf(": can't map mem space %d\n", 0); 248 return; 249 } 250 251 sc->sc_dmat = pa->pa_dmat; 252 253 /* 254 * Allocate our interrupt. 255 */ 256 if (pci_intr_map(pa, &ih)) { 257 printf(": couldn't map interrupt\n"); 258 return; 259 } 260 261 intrstr = pci_intr_string(pc, ih); 262 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 263 if (sc->sc_ih == NULL) { 264 printf(": couldn't establish interrupt"); 265 if (intrstr != NULL) 266 printf(" at %s", intrstr); 267 printf("\n"); 268 return; 269 } 270 printf(": interrupting at %s\n", intrstr); 271 272 if (txp_chip_init(sc)) 273 return; 274 275 if (txp_download_fw(sc)) 276 return; 277 278 if (txp_alloc_rings(sc)) 279 return; 280 281 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 282 NULL, NULL, NULL, 1)) 283 return; 284 285 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 286 &p1, &p2, NULL, 1)) 287 return; 288 289 txp_set_filter(sc); 290 291 p1 = htole16(p1); 292 enaddr[0] = ((u_int8_t *)&p1)[1]; 293 enaddr[1] = ((u_int8_t *)&p1)[0]; 294 p2 = htole32(p2); 295 enaddr[2] = ((u_int8_t *)&p2)[3]; 296 enaddr[3] = ((u_int8_t *)&p2)[2]; 297 enaddr[4] = ((u_int8_t *)&p2)[1]; 298 enaddr[5] = ((u_int8_t *)&p2)[0]; 299 300 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 301 ether_sprintf(enaddr)); 302 sc->sc_cold = 0; 303 304 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 305 if (flags & TXP_FIBER) { 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 311 0, NULL); 312 } else { 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 318 0, NULL); 319 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 320 0, NULL); 321 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 322 0, NULL); 323 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 324 0, NULL); 325 } 326 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 327 328 sc->sc_xcvr = TXP_XCVR_AUTO; 329 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 330 NULL, NULL, NULL, 0); 331 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 332 333 ifp->if_softc = sc; 334 ifp->if_mtu = ETHERMTU; 335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 336 ifp->if_ioctl = txp_ioctl; 337 ifp->if_start = txp_start; 338 ifp->if_watchdog = txp_watchdog; 339 ifp->if_baudrate = 10000000; 340 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 341 IFQ_SET_READY(&ifp->if_snd); 342 ifp->if_capabilities = 0; 343 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 344 345 txp_capabilities(sc); 346 347 callout_setfunc(&sc->sc_tick, txp_tick, sc); 348 349 /* 350 * Attach us everywhere 351 */ 352 if_attach(ifp); 353 ether_ifattach(ifp, enaddr); 354 355 shutdownhook_establish(txp_shutdown, sc); 356 } 357 358 int 359 txp_chip_init(sc) 360 struct txp_softc *sc; 361 { 362 /* disable interrupts */ 363 WRITE_REG(sc, TXP_IER, 0); 364 WRITE_REG(sc, TXP_IMR, 365 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 366 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 367 TXP_INT_LATCH); 368 369 /* ack all interrupts */ 370 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 371 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 372 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 373 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 374 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 375 376 if (txp_reset_adapter(sc)) 377 return (-1); 378 379 /* disable interrupts */ 380 WRITE_REG(sc, TXP_IER, 0); 381 WRITE_REG(sc, TXP_IMR, 382 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 383 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 384 TXP_INT_LATCH); 385 386 /* ack all interrupts */ 387 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 388 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 389 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 390 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 391 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 392 393 return (0); 394 } 395 396 int 397 txp_reset_adapter(sc) 398 struct txp_softc *sc; 399 { 400 u_int32_t r; 401 int i; 402 403 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 404 DELAY(1000); 405 WRITE_REG(sc, TXP_SRR, 0); 406 407 /* Should wait max 6 seconds */ 408 for (i = 0; i < 6000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_HOST_REQUEST) 411 break; 412 DELAY(1000); 413 } 414 415 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 416 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 417 return (-1); 418 } 419 420 return (0); 421 } 422 423 int 424 txp_download_fw(sc) 425 struct txp_softc *sc; 426 { 427 struct txp_fw_file_header *fileheader; 428 struct txp_fw_section_header *secthead; 429 int sect; 430 u_int32_t r, i, ier, imr; 431 432 ier = READ_REG(sc, TXP_IER); 433 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 434 435 imr = READ_REG(sc, TXP_IMR); 436 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 437 438 for (i = 0; i < 10000; i++) { 439 r = READ_REG(sc, TXP_A2H_0); 440 if (r == STAT_WAITING_FOR_HOST_REQUEST) 441 break; 442 DELAY(50); 443 } 444 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 445 printf(": not waiting for host request\n"); 446 return (-1); 447 } 448 449 /* Ack the status */ 450 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 451 452 fileheader = (struct txp_fw_file_header *)tc990image; 453 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 454 printf(": fw invalid magic\n"); 455 return (-1); 456 } 457 458 /* Tell boot firmware to get ready for image */ 459 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 460 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 461 462 if (txp_download_fw_wait(sc)) { 463 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 464 return (-1); 465 } 466 467 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 468 sizeof(struct txp_fw_file_header)); 469 470 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 471 if (txp_download_fw_section(sc, secthead, sect)) 472 return (-1); 473 secthead = (struct txp_fw_section_header *) 474 (((u_int8_t *)secthead) + le32toh(secthead->nbytes) + 475 sizeof(*secthead)); 476 } 477 478 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 479 480 for (i = 0; i < 10000; i++) { 481 r = READ_REG(sc, TXP_A2H_0); 482 if (r == STAT_WAITING_FOR_BOOT) 483 break; 484 DELAY(50); 485 } 486 if (r != STAT_WAITING_FOR_BOOT) { 487 printf(": not waiting for boot\n"); 488 return (-1); 489 } 490 491 WRITE_REG(sc, TXP_IER, ier); 492 WRITE_REG(sc, TXP_IMR, imr); 493 494 return (0); 495 } 496 497 int 498 txp_download_fw_wait(sc) 499 struct txp_softc *sc; 500 { 501 u_int32_t i, r; 502 503 for (i = 0; i < 10000; i++) { 504 r = READ_REG(sc, TXP_ISR); 505 if (r & TXP_INT_A2H_0) 506 break; 507 DELAY(50); 508 } 509 510 if (!(r & TXP_INT_A2H_0)) { 511 printf(": fw wait failed comm0\n"); 512 return (-1); 513 } 514 515 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 516 517 r = READ_REG(sc, TXP_A2H_0); 518 if (r != STAT_WAITING_FOR_SEGMENT) { 519 printf(": fw not waiting for segment\n"); 520 return (-1); 521 } 522 return (0); 523 } 524 525 int 526 txp_download_fw_section(sc, sect, sectnum) 527 struct txp_softc *sc; 528 struct txp_fw_section_header *sect; 529 int sectnum; 530 { 531 struct txp_dma_alloc dma; 532 int rseg, err = 0; 533 struct mbuf m; 534 u_int16_t csum; 535 536 /* Skip zero length sections */ 537 if (sect->nbytes == 0) 538 return (0); 539 540 /* Make sure we aren't past the end of the image */ 541 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 542 if (rseg >= sizeof(tc990image)) { 543 printf(": fw invalid section address, section %d\n", sectnum); 544 return (-1); 545 } 546 547 /* Make sure this section doesn't go past the end */ 548 rseg += le32toh(sect->nbytes); 549 if (rseg >= sizeof(tc990image)) { 550 printf(": fw truncated section %d\n", sectnum); 551 return (-1); 552 } 553 554 /* map a buffer, copy segment to it, get physaddr */ 555 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 556 printf(": fw dma malloc failed, section %d\n", sectnum); 557 return (-1); 558 } 559 560 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 561 le32toh(sect->nbytes)); 562 563 /* 564 * dummy up mbuf and verify section checksum 565 */ 566 m.m_type = MT_DATA; 567 m.m_next = m.m_nextpkt = NULL; 568 m.m_len = le32toh(sect->nbytes); 569 m.m_data = dma.dma_vaddr; 570 m.m_flags = 0; 571 csum = in_cksum(&m, le32toh(sect->nbytes)); 572 if (csum != sect->cksum) { 573 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 574 sectnum, sect->cksum, csum); 575 err = -1; 576 goto bail; 577 } 578 579 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 580 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 581 582 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 583 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 584 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 585 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 586 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 587 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 588 589 if (txp_download_fw_wait(sc)) { 590 printf("%s: fw wait failed, section %d\n", 591 sc->sc_dev.dv_xname, sectnum); 592 err = -1; 593 } 594 595 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 596 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 597 598 bail: 599 txp_dma_free(sc, &dma); 600 601 return (err); 602 } 603 604 int 605 txp_intr(vsc) 606 void *vsc; 607 { 608 struct txp_softc *sc = vsc; 609 struct txp_hostvar *hv = sc->sc_hostvar; 610 u_int32_t isr; 611 int claimed = 0; 612 613 /* mask all interrupts */ 614 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 615 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 616 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 617 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 618 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 619 620 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 621 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 622 623 isr = READ_REG(sc, TXP_ISR); 624 while (isr) { 625 claimed = 1; 626 WRITE_REG(sc, TXP_ISR, isr); 627 628 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 629 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 630 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 631 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 632 633 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 634 txp_rxbuf_reclaim(sc); 635 636 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 637 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 638 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 639 640 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 641 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 642 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 643 644 isr = READ_REG(sc, TXP_ISR); 645 } 646 647 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 648 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 649 650 /* unmask all interrupts */ 651 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 652 653 txp_start(&sc->sc_arpcom.ec_if); 654 655 return (claimed); 656 } 657 658 void 659 txp_rx_reclaim(sc, r, dma) 660 struct txp_softc *sc; 661 struct txp_rx_ring *r; 662 struct txp_dma_alloc *dma; 663 { 664 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 665 struct txp_rx_desc *rxd; 666 struct mbuf *m; 667 struct txp_swdesc *sd; 668 u_int32_t roff, woff; 669 int sumflags = 0; 670 int idx; 671 672 roff = le32toh(*r->r_roff); 673 woff = le32toh(*r->r_woff); 674 idx = roff / sizeof(struct txp_rx_desc); 675 rxd = r->r_desc + idx; 676 677 while (roff != woff) { 678 679 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 680 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 681 BUS_DMASYNC_POSTREAD); 682 683 if (rxd->rx_flags & RX_FLAGS_ERROR) { 684 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 685 le32toh(rxd->rx_stat)); 686 ifp->if_ierrors++; 687 goto next; 688 } 689 690 /* retrieve stashed pointer */ 691 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 692 693 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 694 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 695 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 696 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 697 m = sd->sd_mbuf; 698 free(sd, M_DEVBUF); 699 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 700 701 #ifdef __STRICT_ALIGNMENT 702 { 703 /* 704 * XXX Nice chip, except it won't accept "off by 2" 705 * buffers, so we're force to copy. Supposedly 706 * this will be fixed in a newer firmware rev 707 * and this will be temporary. 708 */ 709 struct mbuf *mnew; 710 711 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 712 if (mnew == NULL) { 713 m_freem(m); 714 goto next; 715 } 716 if (m->m_len > (MHLEN - 2)) { 717 MCLGET(mnew, M_DONTWAIT); 718 if (!(mnew->m_flags & M_EXT)) { 719 m_freem(mnew); 720 m_freem(m); 721 goto next; 722 } 723 } 724 mnew->m_pkthdr.rcvif = ifp; 725 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 726 mnew->m_data += 2; 727 bcopy(m->m_data, mnew->m_data, m->m_len); 728 m_freem(m); 729 m = mnew; 730 } 731 #endif 732 733 #if NBPFILTER > 0 734 /* 735 * Handle BPF listeners. Let the BPF user see the packet. 736 */ 737 if (ifp->if_bpf) 738 bpf_mtap(ifp->if_bpf, m); 739 #endif 740 741 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 742 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 743 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 744 sumflags |= M_CSUM_IPv4; 745 746 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 747 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 748 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 749 sumflags |= M_CSUM_TCPv4; 750 751 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 752 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 753 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 754 sumflags |= M_CSUM_UDPv4; 755 756 m->m_pkthdr.csum_flags = sumflags; 757 758 #if NVLAN > 0 759 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 760 if (vlan_input_tag(m, htons(rxd->rx_vlan >> 16)) < 0) 761 ifp->if_noproto++; 762 goto next; 763 } 764 #endif 765 766 (*ifp->if_input)(ifp, m); 767 768 next: 769 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 770 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 771 BUS_DMASYNC_PREREAD); 772 773 roff += sizeof(struct txp_rx_desc); 774 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 775 idx = 0; 776 roff = 0; 777 rxd = r->r_desc; 778 } else { 779 idx++; 780 rxd++; 781 } 782 woff = le32toh(*r->r_woff); 783 } 784 785 *r->r_roff = htole32(woff); 786 } 787 788 void 789 txp_rxbuf_reclaim(sc) 790 struct txp_softc *sc; 791 { 792 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 793 struct txp_hostvar *hv = sc->sc_hostvar; 794 struct txp_rxbuf_desc *rbd; 795 struct txp_swdesc *sd; 796 u_int32_t i, end; 797 798 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 799 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 800 801 if (++i == RXBUF_ENTRIES) 802 i = 0; 803 804 rbd = sc->sc_rxbufs + i; 805 806 while (i != end) { 807 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 808 M_DEVBUF, M_NOWAIT); 809 if (sd == NULL) 810 break; 811 812 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 813 if (sd->sd_mbuf == NULL) 814 goto err_sd; 815 816 MCLGET(sd->sd_mbuf, M_DONTWAIT); 817 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 818 goto err_mbuf; 819 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 820 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 821 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 822 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 823 goto err_mbuf; 824 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 825 BUS_DMA_NOWAIT)) { 826 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 827 goto err_mbuf; 828 } 829 830 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 831 i * sizeof(struct txp_rxbuf_desc), 832 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 833 834 /* stash away pointer */ 835 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 836 837 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 838 & 0xffffffff; 839 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 840 >> 32; 841 842 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 843 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 844 845 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 846 i * sizeof(struct txp_rxbuf_desc), 847 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 848 849 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 850 851 if (++i == RXBUF_ENTRIES) { 852 i = 0; 853 rbd = sc->sc_rxbufs; 854 } else 855 rbd++; 856 } 857 return; 858 859 err_mbuf: 860 m_freem(sd->sd_mbuf); 861 err_sd: 862 free(sd, M_DEVBUF); 863 } 864 865 /* 866 * Reclaim mbufs and entries from a transmit ring. 867 */ 868 void 869 txp_tx_reclaim(sc, r, dma) 870 struct txp_softc *sc; 871 struct txp_tx_ring *r; 872 struct txp_dma_alloc *dma; 873 { 874 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 875 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 876 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 877 struct txp_tx_desc *txd = r->r_desc + cons; 878 struct txp_swdesc *sd = sc->sc_txd + cons; 879 struct mbuf *m; 880 881 while (cons != idx) { 882 if (cnt == 0) 883 break; 884 885 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 886 cons * sizeof(struct txp_tx_desc), 887 sizeof(struct txp_tx_desc), 888 BUS_DMASYNC_POSTWRITE); 889 890 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 891 TX_FLAGS_TYPE_DATA) { 892 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 893 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 894 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 895 m = sd->sd_mbuf; 896 if (m != NULL) { 897 m_freem(m); 898 txd->tx_addrlo = 0; 899 txd->tx_addrhi = 0; 900 ifp->if_opackets++; 901 } 902 } 903 ifp->if_flags &= ~IFF_OACTIVE; 904 905 if (++cons == TX_ENTRIES) { 906 txd = r->r_desc; 907 cons = 0; 908 sd = sc->sc_txd; 909 } else { 910 txd++; 911 sd++; 912 } 913 914 cnt--; 915 } 916 917 r->r_cons = cons; 918 r->r_cnt = cnt; 919 if (cnt == 0) 920 ifp->if_timer = 0; 921 } 922 923 void 924 txp_shutdown(vsc) 925 void *vsc; 926 { 927 struct txp_softc *sc = (struct txp_softc *)vsc; 928 929 /* mask all interrupts */ 930 WRITE_REG(sc, TXP_IMR, 931 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 932 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 933 TXP_INT_LATCH); 934 935 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 936 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 937 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 938 } 939 940 int 941 txp_alloc_rings(sc) 942 struct txp_softc *sc; 943 { 944 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 945 struct txp_boot_record *boot; 946 struct txp_swdesc *sd; 947 u_int32_t r; 948 int i, j; 949 950 /* boot record */ 951 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 952 BUS_DMA_COHERENT)) { 953 printf(": can't allocate boot record\n"); 954 return (-1); 955 } 956 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 957 bzero(boot, sizeof(*boot)); 958 sc->sc_boot = boot; 959 960 /* host variables */ 961 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 962 BUS_DMA_COHERENT)) { 963 printf(": can't allocate host ring\n"); 964 goto bail_boot; 965 } 966 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 967 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 968 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 969 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 970 971 /* high priority tx ring */ 972 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 973 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 974 printf(": can't allocate high tx ring\n"); 975 goto bail_host; 976 } 977 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 978 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 979 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 980 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 981 sc->sc_txhir.r_reg = TXP_H2A_1; 982 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 983 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 984 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 985 for (i = 0; i < TX_ENTRIES; i++) { 986 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 987 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 988 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 989 for (j = 0; j < i; j++) { 990 bus_dmamap_destroy(sc->sc_dmat, 991 sc->sc_txd[j].sd_map); 992 sc->sc_txd[j].sd_map = NULL; 993 } 994 goto bail_txhiring; 995 } 996 } 997 998 /* low priority tx ring */ 999 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1000 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1001 printf(": can't allocate low tx ring\n"); 1002 goto bail_txhiring; 1003 } 1004 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1005 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1006 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1007 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1008 sc->sc_txlor.r_reg = TXP_H2A_3; 1009 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1010 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1011 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1012 1013 /* high priority rx ring */ 1014 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1015 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1016 printf(": can't allocate high rx ring\n"); 1017 goto bail_txloring; 1018 } 1019 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1020 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1021 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1022 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1023 sc->sc_rxhir.r_desc = 1024 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1025 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1026 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1027 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1028 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1029 1030 /* low priority ring */ 1031 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1032 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1033 printf(": can't allocate low rx ring\n"); 1034 goto bail_rxhiring; 1035 } 1036 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1037 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1038 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1039 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1040 sc->sc_rxlor.r_desc = 1041 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1042 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1043 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1044 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1045 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1046 1047 /* command ring */ 1048 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1049 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1050 printf(": can't allocate command ring\n"); 1051 goto bail_rxloring; 1052 } 1053 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1054 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1055 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1056 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1057 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1058 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1059 sc->sc_cmdring.lastwrite = 0; 1060 1061 /* response ring */ 1062 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1063 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1064 printf(": can't allocate response ring\n"); 1065 goto bail_cmdring; 1066 } 1067 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1068 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1069 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1070 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1071 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1072 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1073 sc->sc_rspring.lastwrite = 0; 1074 1075 /* receive buffer ring */ 1076 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1077 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1078 printf(": can't allocate rx buffer ring\n"); 1079 goto bail_rspring; 1080 } 1081 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1082 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1083 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1084 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1085 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1086 for (i = 0; i < RXBUF_ENTRIES; i++) { 1087 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1088 M_DEVBUF, M_NOWAIT); 1089 if (sd == NULL) 1090 break; 1091 1092 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1093 if (sd->sd_mbuf == NULL) { 1094 goto bail_rxbufring; 1095 } 1096 1097 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1098 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1099 goto bail_rxbufring; 1100 } 1101 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1102 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1103 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1104 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1105 goto bail_rxbufring; 1106 } 1107 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1108 BUS_DMA_NOWAIT)) { 1109 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1110 goto bail_rxbufring; 1111 } 1112 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1113 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1114 1115 /* stash away pointer */ 1116 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1117 1118 sc->sc_rxbufs[i].rb_paddrlo = 1119 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1120 sc->sc_rxbufs[i].rb_paddrhi = 1121 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1122 } 1123 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1124 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1125 BUS_DMASYNC_PREWRITE); 1126 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1127 sizeof(struct txp_rxbuf_desc)); 1128 1129 /* zero dma */ 1130 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1131 BUS_DMA_COHERENT)) { 1132 printf(": can't allocate response ring\n"); 1133 goto bail_rxbufring; 1134 } 1135 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1136 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1137 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1138 1139 /* See if it's waiting for boot, and try to boot it */ 1140 for (i = 0; i < 10000; i++) { 1141 r = READ_REG(sc, TXP_A2H_0); 1142 if (r == STAT_WAITING_FOR_BOOT) 1143 break; 1144 DELAY(50); 1145 } 1146 if (r != STAT_WAITING_FOR_BOOT) { 1147 printf(": not waiting for boot\n"); 1148 goto bail; 1149 } 1150 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1151 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1152 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1153 1154 /* See if it booted */ 1155 for (i = 0; i < 10000; i++) { 1156 r = READ_REG(sc, TXP_A2H_0); 1157 if (r == STAT_RUNNING) 1158 break; 1159 DELAY(50); 1160 } 1161 if (r != STAT_RUNNING) { 1162 printf(": fw not running\n"); 1163 goto bail; 1164 } 1165 1166 /* Clear TX and CMD ring write registers */ 1167 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1168 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1169 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1170 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1171 1172 return (0); 1173 1174 bail: 1175 txp_dma_free(sc, &sc->sc_zero_dma); 1176 bail_rxbufring: 1177 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1178 bail_rspring: 1179 txp_dma_free(sc, &sc->sc_rspring_dma); 1180 bail_cmdring: 1181 txp_dma_free(sc, &sc->sc_cmdring_dma); 1182 bail_rxloring: 1183 txp_dma_free(sc, &sc->sc_rxloring_dma); 1184 bail_rxhiring: 1185 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1186 bail_txloring: 1187 txp_dma_free(sc, &sc->sc_txloring_dma); 1188 bail_txhiring: 1189 txp_dma_free(sc, &sc->sc_txhiring_dma); 1190 bail_host: 1191 txp_dma_free(sc, &sc->sc_host_dma); 1192 bail_boot: 1193 txp_dma_free(sc, &sc->sc_boot_dma); 1194 return (-1); 1195 } 1196 1197 int 1198 txp_dma_malloc(sc, size, dma, mapflags) 1199 struct txp_softc *sc; 1200 bus_size_t size; 1201 struct txp_dma_alloc *dma; 1202 int mapflags; 1203 { 1204 int r; 1205 1206 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1207 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1208 goto fail_0; 1209 1210 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1211 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1212 goto fail_1; 1213 1214 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1215 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1216 goto fail_2; 1217 1218 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1219 size, NULL, BUS_DMA_NOWAIT)) != 0) 1220 goto fail_3; 1221 1222 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1223 return (0); 1224 1225 fail_3: 1226 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1227 fail_2: 1228 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1229 fail_1: 1230 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1231 fail_0: 1232 return (r); 1233 } 1234 1235 void 1236 txp_dma_free(sc, dma) 1237 struct txp_softc *sc; 1238 struct txp_dma_alloc *dma; 1239 { 1240 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1241 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1242 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1243 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1244 } 1245 1246 int 1247 txp_ioctl(ifp, command, data) 1248 struct ifnet *ifp; 1249 u_long command; 1250 caddr_t data; 1251 { 1252 struct txp_softc *sc = ifp->if_softc; 1253 struct ifreq *ifr = (struct ifreq *)data; 1254 struct ifaddr *ifa = (struct ifaddr *)data; 1255 int s, error = 0; 1256 1257 s = splnet(); 1258 1259 #if 0 1260 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1261 splx(s); 1262 return error; 1263 } 1264 #endif 1265 1266 switch(command) { 1267 case SIOCSIFADDR: 1268 ifp->if_flags |= IFF_UP; 1269 switch (ifa->ifa_addr->sa_family) { 1270 #ifdef INET 1271 case AF_INET: 1272 txp_init(sc); 1273 arp_ifinit(ifp, ifa); 1274 break; 1275 #endif /* INET */ 1276 default: 1277 txp_init(sc); 1278 break; 1279 } 1280 break; 1281 case SIOCSIFFLAGS: 1282 if (ifp->if_flags & IFF_UP) { 1283 txp_init(sc); 1284 } else { 1285 if (ifp->if_flags & IFF_RUNNING) 1286 txp_stop(sc); 1287 } 1288 break; 1289 case SIOCADDMULTI: 1290 case SIOCDELMULTI: 1291 error = (command == SIOCADDMULTI) ? 1292 ether_addmulti(ifr, &sc->sc_arpcom) : 1293 ether_delmulti(ifr, &sc->sc_arpcom); 1294 1295 if (error == ENETRESET) { 1296 /* 1297 * Multicast list has changed; set the hardware 1298 * filter accordingly. 1299 */ 1300 txp_set_filter(sc); 1301 error = 0; 1302 } 1303 break; 1304 case SIOCGIFMEDIA: 1305 case SIOCSIFMEDIA: 1306 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1307 break; 1308 default: 1309 error = EINVAL; 1310 break; 1311 } 1312 1313 splx(s); 1314 1315 return(error); 1316 } 1317 1318 void 1319 txp_init(sc) 1320 struct txp_softc *sc; 1321 { 1322 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1323 int s; 1324 1325 txp_stop(sc); 1326 1327 s = splnet(); 1328 1329 txp_set_filter(sc); 1330 1331 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1332 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1333 1334 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1335 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1336 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1337 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1338 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1339 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1340 1341 ifp->if_flags |= IFF_RUNNING; 1342 ifp->if_flags &= ~IFF_OACTIVE; 1343 ifp->if_timer = 0; 1344 1345 if (!callout_pending(&sc->sc_tick)) 1346 callout_schedule(&sc->sc_tick, hz); 1347 1348 splx(s); 1349 } 1350 1351 void 1352 txp_tick(vsc) 1353 void *vsc; 1354 { 1355 struct txp_softc *sc = vsc; 1356 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1357 struct txp_rsp_desc *rsp = NULL; 1358 struct txp_ext_desc *ext; 1359 int s; 1360 1361 s = splnet(); 1362 txp_rxbuf_reclaim(sc); 1363 1364 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1365 &rsp, 1)) 1366 goto out; 1367 if (rsp->rsp_numdesc != 6) 1368 goto out; 1369 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1370 NULL, NULL, NULL, 1)) 1371 goto out; 1372 ext = (struct txp_ext_desc *)(rsp + 1); 1373 1374 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1375 ext[4].ext_1 + ext[4].ext_4; 1376 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1377 ext[2].ext_1; 1378 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1379 ext[1].ext_3; 1380 ifp->if_opackets += rsp->rsp_par2; 1381 ifp->if_ipackets += ext[2].ext_3; 1382 1383 out: 1384 if (rsp != NULL) 1385 free(rsp, M_DEVBUF); 1386 1387 splx(s); 1388 callout_schedule(&sc->sc_tick, hz); 1389 } 1390 1391 void 1392 txp_start(ifp) 1393 struct ifnet *ifp; 1394 { 1395 struct txp_softc *sc = ifp->if_softc; 1396 struct txp_tx_ring *r = &sc->sc_txhir; 1397 struct txp_tx_desc *txd; 1398 int txdidx; 1399 struct txp_frag_desc *fxd; 1400 struct mbuf *m, *mnew; 1401 struct txp_swdesc *sd; 1402 u_int32_t firstprod, firstcnt, prod, cnt, i; 1403 #if NVLAN > 0 1404 struct ifvlan *ifv; 1405 #endif 1406 1407 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1408 return; 1409 1410 prod = r->r_prod; 1411 cnt = r->r_cnt; 1412 1413 while (1) { 1414 IFQ_POLL(&ifp->if_snd, m); 1415 if (m == NULL) 1416 break; 1417 mnew = NULL; 1418 1419 firstprod = prod; 1420 firstcnt = cnt; 1421 1422 sd = sc->sc_txd + prod; 1423 sd->sd_mbuf = m; 1424 1425 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1426 BUS_DMA_NOWAIT)) { 1427 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1428 if (mnew == NULL) 1429 goto oactive1; 1430 if (m->m_pkthdr.len > MHLEN) { 1431 MCLGET(mnew, M_DONTWAIT); 1432 if ((mnew->m_flags & M_EXT) == 0) { 1433 m_freem(mnew); 1434 goto oactive1; 1435 } 1436 } 1437 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1438 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1439 IFQ_DEQUEUE(&ifp->if_snd, m); 1440 m_freem(m); 1441 m = mnew; 1442 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1443 BUS_DMA_NOWAIT)) 1444 goto oactive1; 1445 } 1446 1447 if ((TX_ENTRIES - cnt) < 4) 1448 goto oactive; 1449 1450 txd = r->r_desc + prod; 1451 txdidx = prod; 1452 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1453 txd->tx_numdesc = 0; 1454 txd->tx_addrlo = 0; 1455 txd->tx_addrhi = 0; 1456 txd->tx_totlen = m->m_pkthdr.len; 1457 txd->tx_pflags = 0; 1458 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1459 1460 if (++prod == TX_ENTRIES) 1461 prod = 0; 1462 1463 if (++cnt >= (TX_ENTRIES - 4)) 1464 goto oactive; 1465 1466 #if NVLAN > 0 1467 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1468 m->m_pkthdr.rcvif != NULL) { 1469 ifv = m->m_pkthdr.rcvif->if_softc; 1470 txd->tx_pflags = TX_PFLAGS_VLAN | 1471 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1472 } 1473 #endif 1474 1475 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1476 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1477 #ifdef TRY_TX_TCP_CSUM 1478 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1479 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1480 #endif 1481 #ifdef TRY_TX_UDP_CSUM 1482 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1483 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1484 #endif 1485 1486 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1487 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1488 1489 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1490 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1491 if (++cnt >= (TX_ENTRIES - 4)) { 1492 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1493 0, sd->sd_map->dm_mapsize, 1494 BUS_DMASYNC_POSTWRITE); 1495 goto oactive; 1496 } 1497 1498 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1499 FRAG_FLAGS_VALID; 1500 fxd->frag_rsvd1 = 0; 1501 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1502 fxd->frag_addrlo = 1503 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1504 0xffffffff; 1505 fxd->frag_addrhi = 1506 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1507 32; 1508 fxd->frag_rsvd2 = 0; 1509 1510 bus_dmamap_sync(sc->sc_dmat, 1511 sc->sc_txhiring_dma.dma_map, 1512 prod * sizeof(struct txp_frag_desc), 1513 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1514 1515 if (++prod == TX_ENTRIES) { 1516 fxd = (struct txp_frag_desc *)r->r_desc; 1517 prod = 0; 1518 } else 1519 fxd++; 1520 1521 } 1522 1523 /* 1524 * if mnew isn't NULL, we already dequeued and copied 1525 * the packet. 1526 */ 1527 if (mnew == NULL) 1528 IFQ_DEQUEUE(&ifp->if_snd, m); 1529 1530 ifp->if_timer = 5; 1531 1532 #if NBPFILTER > 0 1533 if (ifp->if_bpf) 1534 bpf_mtap(ifp->if_bpf, m); 1535 #endif 1536 1537 txd->tx_flags |= TX_FLAGS_VALID; 1538 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1539 txdidx * sizeof(struct txp_tx_desc), 1540 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1541 1542 #if 0 1543 { 1544 struct mbuf *mx; 1545 int i; 1546 1547 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1548 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1549 txd->tx_pflags); 1550 for (mx = m; mx != NULL; mx = mx->m_next) { 1551 for (i = 0; i < mx->m_len; i++) { 1552 printf(":%02x", 1553 (u_int8_t)m->m_data[i]); 1554 } 1555 } 1556 printf("\n"); 1557 } 1558 #endif 1559 1560 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1561 } 1562 1563 r->r_prod = prod; 1564 r->r_cnt = cnt; 1565 return; 1566 1567 oactive: 1568 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1569 oactive1: 1570 ifp->if_flags |= IFF_OACTIVE; 1571 r->r_prod = firstprod; 1572 r->r_cnt = firstcnt; 1573 } 1574 1575 /* 1576 * Handle simple commands sent to the typhoon 1577 */ 1578 int 1579 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1580 struct txp_softc *sc; 1581 u_int16_t id, in1, *out1; 1582 u_int32_t in2, in3, *out2, *out3; 1583 int wait; 1584 { 1585 struct txp_rsp_desc *rsp = NULL; 1586 1587 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1588 return (-1); 1589 1590 if (!wait) 1591 return (0); 1592 1593 if (out1 != NULL) 1594 *out1 = le16toh(rsp->rsp_par1); 1595 if (out2 != NULL) 1596 *out2 = le32toh(rsp->rsp_par2); 1597 if (out3 != NULL) 1598 *out3 = le32toh(rsp->rsp_par3); 1599 free(rsp, M_DEVBUF); 1600 return (0); 1601 } 1602 1603 int 1604 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1605 struct txp_softc *sc; 1606 u_int16_t id, in1; 1607 u_int32_t in2, in3; 1608 struct txp_ext_desc *in_extp; 1609 u_int8_t in_extn; 1610 struct txp_rsp_desc **rspp; 1611 int wait; 1612 { 1613 struct txp_hostvar *hv = sc->sc_hostvar; 1614 struct txp_cmd_desc *cmd; 1615 struct txp_ext_desc *ext; 1616 u_int32_t idx, i; 1617 u_int16_t seq; 1618 1619 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1620 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1621 return (-1); 1622 } 1623 1624 idx = sc->sc_cmdring.lastwrite; 1625 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1626 bzero(cmd, sizeof(*cmd)); 1627 1628 cmd->cmd_numdesc = in_extn; 1629 seq = sc->sc_seq++; 1630 cmd->cmd_seq = htole16(seq); 1631 cmd->cmd_id = htole16(id); 1632 cmd->cmd_par1 = htole16(in1); 1633 cmd->cmd_par2 = htole32(in2); 1634 cmd->cmd_par3 = htole32(in3); 1635 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1636 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1637 1638 idx += sizeof(struct txp_cmd_desc); 1639 if (idx == sc->sc_cmdring.size) 1640 idx = 0; 1641 1642 for (i = 0; i < in_extn; i++) { 1643 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1644 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1645 in_extp++; 1646 idx += sizeof(struct txp_cmd_desc); 1647 if (idx == sc->sc_cmdring.size) 1648 idx = 0; 1649 } 1650 1651 sc->sc_cmdring.lastwrite = idx; 1652 1653 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1654 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1655 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1656 1657 if (!wait) 1658 return (0); 1659 1660 for (i = 0; i < 10000; i++) { 1661 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1662 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1663 idx = le32toh(hv->hv_resp_read_idx); 1664 if (idx != le32toh(hv->hv_resp_write_idx)) { 1665 *rspp = NULL; 1666 if (txp_response(sc, idx, id, seq, rspp)) 1667 return (-1); 1668 if (*rspp != NULL) 1669 break; 1670 } 1671 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1672 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1673 DELAY(50); 1674 } 1675 if (i == 1000 || (*rspp) == NULL) { 1676 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1677 return (-1); 1678 } 1679 1680 return (0); 1681 } 1682 1683 int 1684 txp_response(sc, ridx, id, seq, rspp) 1685 struct txp_softc *sc; 1686 u_int32_t ridx; 1687 u_int16_t id; 1688 u_int16_t seq; 1689 struct txp_rsp_desc **rspp; 1690 { 1691 struct txp_hostvar *hv = sc->sc_hostvar; 1692 struct txp_rsp_desc *rsp; 1693 1694 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1695 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1696 1697 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1698 *rspp = (struct txp_rsp_desc *)malloc( 1699 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1700 M_DEVBUF, M_NOWAIT); 1701 if ((*rspp) == NULL) 1702 return (-1); 1703 txp_rsp_fixup(sc, rsp, *rspp); 1704 return (0); 1705 } 1706 1707 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1708 printf("%s: response error: id 0x%x\n", 1709 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1710 txp_rsp_fixup(sc, rsp, NULL); 1711 ridx = le32toh(hv->hv_resp_read_idx); 1712 continue; 1713 } 1714 1715 switch (le16toh(rsp->rsp_id)) { 1716 case TXP_CMD_CYCLE_STATISTICS: 1717 case TXP_CMD_MEDIA_STATUS_READ: 1718 break; 1719 case TXP_CMD_HELLO_RESPONSE: 1720 printf("%s: hello\n", TXP_DEVNAME(sc)); 1721 break; 1722 default: 1723 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1724 le16toh(rsp->rsp_id)); 1725 } 1726 1727 txp_rsp_fixup(sc, rsp, NULL); 1728 ridx = le32toh(hv->hv_resp_read_idx); 1729 hv->hv_resp_read_idx = le32toh(ridx); 1730 } 1731 1732 return (0); 1733 } 1734 1735 void 1736 txp_rsp_fixup(sc, rsp, dst) 1737 struct txp_softc *sc; 1738 struct txp_rsp_desc *rsp, *dst; 1739 { 1740 struct txp_rsp_desc *src = rsp; 1741 struct txp_hostvar *hv = sc->sc_hostvar; 1742 u_int32_t i, ridx; 1743 1744 ridx = le32toh(hv->hv_resp_read_idx); 1745 1746 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1747 if (dst != NULL) 1748 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1749 ridx += sizeof(struct txp_rsp_desc); 1750 if (ridx == sc->sc_rspring.size) { 1751 src = sc->sc_rspring.base; 1752 ridx = 0; 1753 } else 1754 src++; 1755 sc->sc_rspring.lastwrite = ridx; 1756 hv->hv_resp_read_idx = htole32(ridx); 1757 } 1758 1759 hv->hv_resp_read_idx = htole32(ridx); 1760 } 1761 1762 int 1763 txp_cmd_desc_numfree(sc) 1764 struct txp_softc *sc; 1765 { 1766 struct txp_hostvar *hv = sc->sc_hostvar; 1767 struct txp_boot_record *br = sc->sc_boot; 1768 u_int32_t widx, ridx, nfree; 1769 1770 widx = sc->sc_cmdring.lastwrite; 1771 ridx = le32toh(hv->hv_cmd_read_idx); 1772 1773 if (widx == ridx) { 1774 /* Ring is completely free */ 1775 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1776 } else { 1777 if (widx > ridx) 1778 nfree = le32toh(br->br_cmd_siz) - 1779 (widx - ridx + sizeof(struct txp_cmd_desc)); 1780 else 1781 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1782 } 1783 1784 return (nfree / sizeof(struct txp_cmd_desc)); 1785 } 1786 1787 void 1788 txp_stop(sc) 1789 struct txp_softc *sc; 1790 { 1791 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1792 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1793 1794 if (callout_pending(&sc->sc_tick)) 1795 callout_stop(&sc->sc_tick); 1796 } 1797 1798 void 1799 txp_watchdog(ifp) 1800 struct ifnet *ifp; 1801 { 1802 } 1803 1804 int 1805 txp_ifmedia_upd(ifp) 1806 struct ifnet *ifp; 1807 { 1808 struct txp_softc *sc = ifp->if_softc; 1809 struct ifmedia *ifm = &sc->sc_ifmedia; 1810 u_int16_t new_xcvr; 1811 1812 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1813 return (EINVAL); 1814 1815 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1816 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1817 new_xcvr = TXP_XCVR_10_FDX; 1818 else 1819 new_xcvr = TXP_XCVR_10_HDX; 1820 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1821 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1822 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1823 new_xcvr = TXP_XCVR_100_FDX; 1824 else 1825 new_xcvr = TXP_XCVR_100_HDX; 1826 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1827 new_xcvr = TXP_XCVR_AUTO; 1828 } else 1829 return (EINVAL); 1830 1831 /* nothing to do */ 1832 if (sc->sc_xcvr == new_xcvr) 1833 return (0); 1834 1835 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1836 NULL, NULL, NULL, 0); 1837 sc->sc_xcvr = new_xcvr; 1838 1839 return (0); 1840 } 1841 1842 void 1843 txp_ifmedia_sts(ifp, ifmr) 1844 struct ifnet *ifp; 1845 struct ifmediareq *ifmr; 1846 { 1847 struct txp_softc *sc = ifp->if_softc; 1848 struct ifmedia *ifm = &sc->sc_ifmedia; 1849 u_int16_t bmsr, bmcr, anlpar; 1850 1851 ifmr->ifm_status = IFM_AVALID; 1852 ifmr->ifm_active = IFM_ETHER; 1853 1854 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1855 &bmsr, NULL, NULL, 1)) 1856 goto bail; 1857 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1858 &bmsr, NULL, NULL, 1)) 1859 goto bail; 1860 1861 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1862 &bmcr, NULL, NULL, 1)) 1863 goto bail; 1864 1865 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1866 &anlpar, NULL, NULL, 1)) 1867 goto bail; 1868 1869 if (bmsr & BMSR_LINK) 1870 ifmr->ifm_status |= IFM_ACTIVE; 1871 1872 if (bmcr & BMCR_ISO) { 1873 ifmr->ifm_active |= IFM_NONE; 1874 ifmr->ifm_status = 0; 1875 return; 1876 } 1877 1878 if (bmcr & BMCR_LOOP) 1879 ifmr->ifm_active |= IFM_LOOP; 1880 1881 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1882 if ((bmsr & BMSR_ACOMP) == 0) { 1883 ifmr->ifm_active |= IFM_NONE; 1884 return; 1885 } 1886 1887 if (anlpar & ANLPAR_T4) 1888 ifmr->ifm_active |= IFM_100_T4; 1889 else if (anlpar & ANLPAR_TX_FD) 1890 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1891 else if (anlpar & ANLPAR_TX) 1892 ifmr->ifm_active |= IFM_100_TX; 1893 else if (anlpar & ANLPAR_10_FD) 1894 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1895 else if (anlpar & ANLPAR_10) 1896 ifmr->ifm_active |= IFM_10_T; 1897 else 1898 ifmr->ifm_active |= IFM_NONE; 1899 } else 1900 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1901 return; 1902 1903 bail: 1904 ifmr->ifm_active |= IFM_NONE; 1905 ifmr->ifm_status &= ~IFM_AVALID; 1906 } 1907 1908 void 1909 txp_show_descriptor(d) 1910 void *d; 1911 { 1912 struct txp_cmd_desc *cmd = d; 1913 struct txp_rsp_desc *rsp = d; 1914 struct txp_tx_desc *txd = d; 1915 struct txp_frag_desc *frgd = d; 1916 1917 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1918 case CMD_FLAGS_TYPE_CMD: 1919 /* command descriptor */ 1920 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1921 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1922 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1923 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1924 break; 1925 case CMD_FLAGS_TYPE_RESP: 1926 /* response descriptor */ 1927 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1928 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1929 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1930 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1931 break; 1932 case CMD_FLAGS_TYPE_DATA: 1933 /* data header (assuming tx for now) */ 1934 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1935 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1936 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1937 break; 1938 case CMD_FLAGS_TYPE_FRAG: 1939 /* fragment descriptor */ 1940 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1941 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1942 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1943 break; 1944 default: 1945 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1946 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1947 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1948 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1949 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1950 break; 1951 } 1952 } 1953 1954 void 1955 txp_set_filter(sc) 1956 struct txp_softc *sc; 1957 { 1958 struct ethercom *ac = &sc->sc_arpcom; 1959 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1960 u_int32_t crc, carry, hashbit, hash[2]; 1961 u_int16_t filter; 1962 u_int8_t octet; 1963 int i, j, mcnt = 0; 1964 struct ether_multi *enm; 1965 struct ether_multistep step; 1966 1967 if (ifp->if_flags & IFF_PROMISC) { 1968 filter = TXP_RXFILT_PROMISC; 1969 goto setit; 1970 } 1971 1972 again: 1973 filter = TXP_RXFILT_DIRECT; 1974 1975 if (ifp->if_flags & IFF_BROADCAST) 1976 filter |= TXP_RXFILT_BROADCAST; 1977 1978 if (ifp->if_flags & IFF_ALLMULTI) 1979 filter |= TXP_RXFILT_ALLMULTI; 1980 else { 1981 hash[0] = hash[1] = 0; 1982 1983 ETHER_FIRST_MULTI(step, ac, enm); 1984 while (enm != NULL) { 1985 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1986 /* 1987 * We must listen to a range of multicast 1988 * addresses. For now, just accept all 1989 * multicasts, rather than trying to set only 1990 * those filter bits needed to match the range. 1991 * (At this time, the only use of address 1992 * ranges is for IP multicast routing, for 1993 * which the range is big enough to require 1994 * all bits set.) 1995 */ 1996 ifp->if_flags |= IFF_ALLMULTI; 1997 goto again; 1998 } 1999 2000 mcnt++; 2001 crc = 0xffffffff; 2002 2003 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2004 octet = enm->enm_addrlo[i]; 2005 for (j = 0; j < 8; j++) { 2006 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2007 (octet & 1); 2008 crc <<= 1; 2009 octet >>= 1; 2010 if (carry) 2011 crc = (crc ^ TXP_POLYNOMIAL) | 2012 carry; 2013 } 2014 } 2015 hashbit = (u_int16_t)(crc & (64 - 1)); 2016 hash[hashbit / 32] |= (1 << hashbit % 32); 2017 ETHER_NEXT_MULTI(step, enm); 2018 } 2019 2020 if (mcnt > 0) { 2021 filter |= TXP_RXFILT_HASHMULTI; 2022 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2023 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2024 } 2025 } 2026 2027 setit: 2028 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2029 NULL, NULL, NULL, 1); 2030 } 2031 2032 void 2033 txp_capabilities(sc) 2034 struct txp_softc *sc; 2035 { 2036 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2037 struct txp_rsp_desc *rsp = NULL; 2038 struct txp_ext_desc *ext; 2039 2040 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2041 goto out; 2042 2043 if (rsp->rsp_numdesc != 1) 2044 goto out; 2045 ext = (struct txp_ext_desc *)(rsp + 1); 2046 2047 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2048 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2049 2050 #if NVLAN > 0 2051 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2052 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2053 sc->sc_tx_capability |= OFFLOAD_VLAN; 2054 sc->sc_rx_capability |= OFFLOAD_VLAN; 2055 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 2056 } 2057 #endif 2058 2059 #if 0 2060 /* not ready yet */ 2061 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2062 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2063 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2064 ifp->if_capabilities |= IFCAP_IPSEC; 2065 } 2066 #endif 2067 2068 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2069 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2070 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2071 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 2072 } 2073 2074 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2075 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2076 #ifdef TRY_TX_TCP_CSUM 2077 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2078 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 2079 #endif 2080 } 2081 2082 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2083 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2084 #ifdef TRY_TX_UDP_CSUM 2085 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2086 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 2087 #endif 2088 } 2089 2090 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2091 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2092 goto out; 2093 2094 out: 2095 if (rsp != NULL) 2096 free(rsp, M_DEVBUF); 2097 } 2098
Indexes created Tue Sep 30 20:09:53 GMT 2025