if_txp.c revision 1.21.4.1
1 /* $NetBSD: if_txp.c,v 1.21.4.1 2007/10/25 22:39:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.21.4.1 2007/10/25 22:39:06 bouyer Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 71 #include <sys/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(struct device *, struct cfdata *, void *); 91 void txp_attach(struct device *, struct device *, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, void *); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 const struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(id) 167 pcireg_t id; 168 { 169 int i; 170 171 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 172 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 173 (PCI_PRODUCT(id) == txp_devices[i].did)) 174 return (&txp_devices[i]); 175 return (0); 176 } 177 178 int 179 txp_probe(struct device *parent, struct cfdata *match, 180 void *aux) 181 { 182 struct pci_attach_args *pa = aux; 183 184 if (txp_pcilookup(pa->pa_id)) 185 return (1); 186 return (0); 187 } 188 189 void 190 txp_attach(struct device *parent, struct device *self, void *aux) 191 { 192 struct txp_softc *sc = (struct txp_softc *)self; 193 struct pci_attach_args *pa = aux; 194 pci_chipset_tag_t pc = pa->pa_pc; 195 pci_intr_handle_t ih; 196 const char *intrstr = NULL; 197 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 198 u_int32_t command; 199 u_int16_t p1; 200 u_int32_t p2; 201 u_char enaddr[6]; 202 const struct txp_pci_match *pcimatch; 203 u_int16_t subsys; 204 int i, flags; 205 char devinfo[256]; 206 207 sc->sc_cold = 1; 208 209 pcimatch = txp_pcilookup(pa->pa_id); 210 flags = pcimatch->flags; 211 if (pcimatch->flags & TXP_USESUBSYSTEM) { 212 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 213 PCI_SUBSYS_ID_REG)); 214 for (i = 0; 215 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 216 i++) 217 if ((subsys & txp_subsysinfo[i].mask) == 218 txp_subsysinfo[i].value) 219 flags |= txp_subsysinfo[i].flags; 220 } 221 sc->sc_flags = flags; 222 223 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 224 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 225 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 226 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 227 228 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 229 230 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 231 printf(": failed to enable bus mastering\n"); 232 return; 233 } 234 235 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 236 printf(": failed to enable memory mapping\n"); 237 return; 238 } 239 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 240 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 241 printf(": can't map mem space %d\n", 0); 242 return; 243 } 244 245 sc->sc_dmat = pa->pa_dmat; 246 247 /* 248 * Allocate our interrupt. 249 */ 250 if (pci_intr_map(pa, &ih)) { 251 printf(": couldn't map interrupt\n"); 252 return; 253 } 254 255 intrstr = pci_intr_string(pc, ih); 256 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 257 if (sc->sc_ih == NULL) { 258 printf(": couldn't establish interrupt"); 259 if (intrstr != NULL) 260 printf(" at %s", intrstr); 261 printf("\n"); 262 return; 263 } 264 printf(": interrupting at %s\n", intrstr); 265 266 if (txp_chip_init(sc)) 267 goto cleanupintr; 268 269 if (txp_download_fw(sc)) 270 goto cleanupintr; 271 272 if (txp_alloc_rings(sc)) 273 goto cleanupintr; 274 275 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 276 NULL, NULL, NULL, 1)) 277 goto cleanupintr; 278 279 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 280 &p1, &p2, NULL, 1)) 281 goto cleanupintr; 282 283 txp_set_filter(sc); 284 285 p1 = htole16(p1); 286 enaddr[0] = ((u_int8_t *)&p1)[1]; 287 enaddr[1] = ((u_int8_t *)&p1)[0]; 288 p2 = htole32(p2); 289 enaddr[2] = ((u_int8_t *)&p2)[3]; 290 enaddr[3] = ((u_int8_t *)&p2)[2]; 291 enaddr[4] = ((u_int8_t *)&p2)[1]; 292 enaddr[5] = ((u_int8_t *)&p2)[0]; 293 294 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 295 ether_sprintf(enaddr)); 296 sc->sc_cold = 0; 297 298 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 299 if (flags & TXP_FIBER) { 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 303 0, NULL); 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 305 0, NULL); 306 } else { 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 318 0, NULL); 319 } 320 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 321 322 sc->sc_xcvr = TXP_XCVR_AUTO; 323 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 324 NULL, NULL, NULL, 0); 325 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 326 327 ifp->if_softc = sc; 328 ifp->if_mtu = ETHERMTU; 329 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 330 ifp->if_ioctl = txp_ioctl; 331 ifp->if_start = txp_start; 332 ifp->if_watchdog = txp_watchdog; 333 ifp->if_baudrate = 10000000; 334 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 335 IFQ_SET_READY(&ifp->if_snd); 336 ifp->if_capabilities = 0; 337 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 338 339 txp_capabilities(sc); 340 341 callout_init(&sc->sc_tick, 0); 342 callout_setfunc(&sc->sc_tick, txp_tick, sc); 343 344 /* 345 * Attach us everywhere 346 */ 347 if_attach(ifp); 348 ether_ifattach(ifp, enaddr); 349 350 shutdownhook_establish(txp_shutdown, sc); 351 352 353 return; 354 355 cleanupintr: 356 pci_intr_disestablish(pc,sc->sc_ih); 357 358 return; 359 360 } 361 362 int 363 txp_chip_init(sc) 364 struct txp_softc *sc; 365 { 366 /* disable interrupts */ 367 WRITE_REG(sc, TXP_IER, 0); 368 WRITE_REG(sc, TXP_IMR, 369 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 370 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 371 TXP_INT_LATCH); 372 373 /* ack all interrupts */ 374 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 375 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 376 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 377 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 378 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 379 380 if (txp_reset_adapter(sc)) 381 return (-1); 382 383 /* disable interrupts */ 384 WRITE_REG(sc, TXP_IER, 0); 385 WRITE_REG(sc, TXP_IMR, 386 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 387 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 388 TXP_INT_LATCH); 389 390 /* ack all interrupts */ 391 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 392 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 393 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 394 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 395 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 396 397 return (0); 398 } 399 400 int 401 txp_reset_adapter(sc) 402 struct txp_softc *sc; 403 { 404 u_int32_t r; 405 int i; 406 407 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 408 DELAY(1000); 409 WRITE_REG(sc, TXP_SRR, 0); 410 411 /* Should wait max 6 seconds */ 412 for (i = 0; i < 6000; i++) { 413 r = READ_REG(sc, TXP_A2H_0); 414 if (r == STAT_WAITING_FOR_HOST_REQUEST) 415 break; 416 DELAY(1000); 417 } 418 419 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 420 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 421 return (-1); 422 } 423 424 return (0); 425 } 426 427 int 428 txp_download_fw(sc) 429 struct txp_softc *sc; 430 { 431 const struct txp_fw_file_header *fileheader; 432 const struct txp_fw_section_header *secthead; 433 int sect; 434 u_int32_t r, i, ier, imr; 435 436 ier = READ_REG(sc, TXP_IER); 437 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 438 439 imr = READ_REG(sc, TXP_IMR); 440 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 441 442 for (i = 0; i < 10000; i++) { 443 r = READ_REG(sc, TXP_A2H_0); 444 if (r == STAT_WAITING_FOR_HOST_REQUEST) 445 break; 446 DELAY(50); 447 } 448 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 449 printf(": not waiting for host request\n"); 450 return (-1); 451 } 452 453 /* Ack the status */ 454 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 455 456 fileheader = (const struct txp_fw_file_header *)tc990image; 457 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 458 printf(": fw invalid magic\n"); 459 return (-1); 460 } 461 462 /* Tell boot firmware to get ready for image */ 463 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 464 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 465 466 if (txp_download_fw_wait(sc)) { 467 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 468 return (-1); 469 } 470 471 secthead = (const struct txp_fw_section_header *) 472 (((const u_int8_t *)tc990image) + 473 sizeof(struct txp_fw_file_header)); 474 475 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 476 if (txp_download_fw_section(sc, secthead, sect)) 477 return (-1); 478 secthead = (const struct txp_fw_section_header *) 479 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 480 sizeof(*secthead)); 481 } 482 483 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 484 485 for (i = 0; i < 10000; i++) { 486 r = READ_REG(sc, TXP_A2H_0); 487 if (r == STAT_WAITING_FOR_BOOT) 488 break; 489 DELAY(50); 490 } 491 if (r != STAT_WAITING_FOR_BOOT) { 492 printf(": not waiting for boot\n"); 493 return (-1); 494 } 495 496 WRITE_REG(sc, TXP_IER, ier); 497 WRITE_REG(sc, TXP_IMR, imr); 498 499 return (0); 500 } 501 502 int 503 txp_download_fw_wait(sc) 504 struct txp_softc *sc; 505 { 506 u_int32_t i, r; 507 508 for (i = 0; i < 10000; i++) { 509 r = READ_REG(sc, TXP_ISR); 510 if (r & TXP_INT_A2H_0) 511 break; 512 DELAY(50); 513 } 514 515 if (!(r & TXP_INT_A2H_0)) { 516 printf(": fw wait failed comm0\n"); 517 return (-1); 518 } 519 520 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 521 522 r = READ_REG(sc, TXP_A2H_0); 523 if (r != STAT_WAITING_FOR_SEGMENT) { 524 printf(": fw not waiting for segment\n"); 525 return (-1); 526 } 527 return (0); 528 } 529 530 int 531 txp_download_fw_section(sc, sect, sectnum) 532 struct txp_softc *sc; 533 const struct txp_fw_section_header *sect; 534 int sectnum; 535 { 536 struct txp_dma_alloc dma; 537 int rseg, err = 0; 538 struct mbuf m; 539 #ifdef INET 540 u_int16_t csum; 541 #endif 542 543 /* Skip zero length sections */ 544 if (sect->nbytes == 0) 545 return (0); 546 547 /* Make sure we aren't past the end of the image */ 548 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 549 if (rseg >= sizeof(tc990image)) { 550 printf(": fw invalid section address, section %d\n", sectnum); 551 return (-1); 552 } 553 554 /* Make sure this section doesn't go past the end */ 555 rseg += le32toh(sect->nbytes); 556 if (rseg >= sizeof(tc990image)) { 557 printf(": fw truncated section %d\n", sectnum); 558 return (-1); 559 } 560 561 /* map a buffer, copy segment to it, get physaddr */ 562 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 563 printf(": fw dma malloc failed, section %d\n", sectnum); 564 return (-1); 565 } 566 567 bcopy(((const u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 568 le32toh(sect->nbytes)); 569 570 /* 571 * dummy up mbuf and verify section checksum 572 */ 573 m.m_type = MT_DATA; 574 m.m_next = m.m_nextpkt = NULL; 575 m.m_len = le32toh(sect->nbytes); 576 m.m_data = dma.dma_vaddr; 577 m.m_flags = 0; 578 #ifdef INET 579 csum = in_cksum(&m, le32toh(sect->nbytes)); 580 if (csum != sect->cksum) { 581 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 582 sectnum, sect->cksum, csum); 583 txp_dma_free(sc, &dma); 584 return -1; 585 } 586 #endif 587 588 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 589 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 590 591 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 592 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 593 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 594 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 595 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 596 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 597 598 if (txp_download_fw_wait(sc)) { 599 printf("%s: fw wait failed, section %d\n", 600 sc->sc_dev.dv_xname, sectnum); 601 err = -1; 602 } 603 604 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 605 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 606 607 txp_dma_free(sc, &dma); 608 return (err); 609 } 610 611 int 612 txp_intr(vsc) 613 void *vsc; 614 { 615 struct txp_softc *sc = vsc; 616 struct txp_hostvar *hv = sc->sc_hostvar; 617 u_int32_t isr; 618 int claimed = 0; 619 620 /* mask all interrupts */ 621 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 622 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 623 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 624 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 625 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 626 627 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 628 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 629 630 isr = READ_REG(sc, TXP_ISR); 631 while (isr) { 632 claimed = 1; 633 WRITE_REG(sc, TXP_ISR, isr); 634 635 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 636 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 637 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 638 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 639 640 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 641 txp_rxbuf_reclaim(sc); 642 643 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 644 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 645 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 646 647 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 648 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 649 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 650 651 isr = READ_REG(sc, TXP_ISR); 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 655 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 656 657 /* unmask all interrupts */ 658 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 659 660 txp_start(&sc->sc_arpcom.ec_if); 661 662 return (claimed); 663 } 664 665 void 666 txp_rx_reclaim(sc, r, dma) 667 struct txp_softc *sc; 668 struct txp_rx_ring *r; 669 struct txp_dma_alloc *dma; 670 { 671 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 672 struct txp_rx_desc *rxd; 673 struct mbuf *m; 674 struct txp_swdesc *sd; 675 u_int32_t roff, woff; 676 int sumflags = 0; 677 int idx; 678 679 roff = le32toh(*r->r_roff); 680 woff = le32toh(*r->r_woff); 681 idx = roff / sizeof(struct txp_rx_desc); 682 rxd = r->r_desc + idx; 683 684 while (roff != woff) { 685 686 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 687 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 688 BUS_DMASYNC_POSTREAD); 689 690 if (rxd->rx_flags & RX_FLAGS_ERROR) { 691 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 692 le32toh(rxd->rx_stat)); 693 ifp->if_ierrors++; 694 goto next; 695 } 696 697 /* retrieve stashed pointer */ 698 bcopy(__UNVOLATILE(&rxd->rx_vaddrlo), &sd, sizeof(sd)); 699 700 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 701 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 702 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 703 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 704 m = sd->sd_mbuf; 705 free(sd, M_DEVBUF); 706 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 707 708 #ifdef __STRICT_ALIGNMENT 709 { 710 /* 711 * XXX Nice chip, except it won't accept "off by 2" 712 * buffers, so we're force to copy. Supposedly 713 * this will be fixed in a newer firmware rev 714 * and this will be temporary. 715 */ 716 struct mbuf *mnew; 717 718 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 719 if (mnew == NULL) { 720 m_freem(m); 721 goto next; 722 } 723 if (m->m_len > (MHLEN - 2)) { 724 MCLGET(mnew, M_DONTWAIT); 725 if (!(mnew->m_flags & M_EXT)) { 726 m_freem(mnew); 727 m_freem(m); 728 goto next; 729 } 730 } 731 mnew->m_pkthdr.rcvif = ifp; 732 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 733 mnew->m_data += 2; 734 bcopy(m->m_data, mnew->m_data, m->m_len); 735 m_freem(m); 736 m = mnew; 737 } 738 #endif 739 740 #if NBPFILTER > 0 741 /* 742 * Handle BPF listeners. Let the BPF user see the packet. 743 */ 744 if (ifp->if_bpf) 745 bpf_mtap(ifp->if_bpf, m); 746 #endif 747 748 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 749 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 750 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 751 sumflags |= M_CSUM_IPv4; 752 753 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 754 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 755 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 756 sumflags |= M_CSUM_TCPv4; 757 758 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 759 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 760 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 761 sumflags |= M_CSUM_UDPv4; 762 763 m->m_pkthdr.csum_flags = sumflags; 764 765 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 766 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 767 continue); 768 } 769 770 (*ifp->if_input)(ifp, m); 771 772 next: 773 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 774 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 775 BUS_DMASYNC_PREREAD); 776 777 roff += sizeof(struct txp_rx_desc); 778 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 779 idx = 0; 780 roff = 0; 781 rxd = r->r_desc; 782 } else { 783 idx++; 784 rxd++; 785 } 786 woff = le32toh(*r->r_woff); 787 } 788 789 *r->r_roff = htole32(woff); 790 } 791 792 void 793 txp_rxbuf_reclaim(sc) 794 struct txp_softc *sc; 795 { 796 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 797 struct txp_hostvar *hv = sc->sc_hostvar; 798 struct txp_rxbuf_desc *rbd; 799 struct txp_swdesc *sd; 800 u_int32_t i, end; 801 802 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 803 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 804 805 if (++i == RXBUF_ENTRIES) 806 i = 0; 807 808 rbd = sc->sc_rxbufs + i; 809 810 while (i != end) { 811 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 812 M_DEVBUF, M_NOWAIT); 813 if (sd == NULL) 814 break; 815 816 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 817 if (sd->sd_mbuf == NULL) 818 goto err_sd; 819 820 MCLGET(sd->sd_mbuf, M_DONTWAIT); 821 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 822 goto err_mbuf; 823 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 824 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 825 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 826 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 827 goto err_mbuf; 828 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 829 BUS_DMA_NOWAIT)) { 830 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 831 goto err_mbuf; 832 } 833 834 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 835 i * sizeof(struct txp_rxbuf_desc), 836 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 837 838 /* stash away pointer */ 839 bcopy(&sd, __UNVOLATILE(&rbd->rb_vaddrlo), sizeof(sd)); 840 841 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 842 & 0xffffffff; 843 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 844 >> 32; 845 846 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 847 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 848 849 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 850 i * sizeof(struct txp_rxbuf_desc), 851 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 852 853 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 854 855 if (++i == RXBUF_ENTRIES) { 856 i = 0; 857 rbd = sc->sc_rxbufs; 858 } else 859 rbd++; 860 } 861 return; 862 863 err_mbuf: 864 m_freem(sd->sd_mbuf); 865 err_sd: 866 free(sd, M_DEVBUF); 867 } 868 869 /* 870 * Reclaim mbufs and entries from a transmit ring. 871 */ 872 void 873 txp_tx_reclaim(sc, r, dma) 874 struct txp_softc *sc; 875 struct txp_tx_ring *r; 876 struct txp_dma_alloc *dma; 877 { 878 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 879 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 880 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 881 struct txp_tx_desc *txd = r->r_desc + cons; 882 struct txp_swdesc *sd = sc->sc_txd + cons; 883 struct mbuf *m; 884 885 while (cons != idx) { 886 if (cnt == 0) 887 break; 888 889 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 890 cons * sizeof(struct txp_tx_desc), 891 sizeof(struct txp_tx_desc), 892 BUS_DMASYNC_POSTWRITE); 893 894 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 895 TX_FLAGS_TYPE_DATA) { 896 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 897 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 898 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 899 m = sd->sd_mbuf; 900 if (m != NULL) { 901 m_freem(m); 902 txd->tx_addrlo = 0; 903 txd->tx_addrhi = 0; 904 ifp->if_opackets++; 905 } 906 } 907 ifp->if_flags &= ~IFF_OACTIVE; 908 909 if (++cons == TX_ENTRIES) { 910 txd = r->r_desc; 911 cons = 0; 912 sd = sc->sc_txd; 913 } else { 914 txd++; 915 sd++; 916 } 917 918 cnt--; 919 } 920 921 r->r_cons = cons; 922 r->r_cnt = cnt; 923 if (cnt == 0) 924 ifp->if_timer = 0; 925 } 926 927 void 928 txp_shutdown(vsc) 929 void *vsc; 930 { 931 struct txp_softc *sc = (struct txp_softc *)vsc; 932 933 /* mask all interrupts */ 934 WRITE_REG(sc, TXP_IMR, 935 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 936 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 937 TXP_INT_LATCH); 938 939 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 940 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 941 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 942 } 943 944 int 945 txp_alloc_rings(sc) 946 struct txp_softc *sc; 947 { 948 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 949 struct txp_boot_record *boot; 950 struct txp_swdesc *sd; 951 u_int32_t r; 952 int i, j, nb; 953 954 /* boot record */ 955 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 956 BUS_DMA_COHERENT)) { 957 printf(": can't allocate boot record\n"); 958 return (-1); 959 } 960 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 961 bzero(boot, sizeof(*boot)); 962 sc->sc_boot = boot; 963 964 /* host variables */ 965 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 966 BUS_DMA_COHERENT)) { 967 printf(": can't allocate host ring\n"); 968 goto bail_boot; 969 } 970 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 971 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 972 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 973 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 974 975 /* high priority tx ring */ 976 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 977 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 978 printf(": can't allocate high tx ring\n"); 979 goto bail_host; 980 } 981 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 982 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 983 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 984 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 985 sc->sc_txhir.r_reg = TXP_H2A_1; 986 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 987 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 988 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 989 for (i = 0; i < TX_ENTRIES; i++) { 990 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 991 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 992 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 993 for (j = 0; j < i; j++) { 994 bus_dmamap_destroy(sc->sc_dmat, 995 sc->sc_txd[j].sd_map); 996 sc->sc_txd[j].sd_map = NULL; 997 } 998 goto bail_txhiring; 999 } 1000 } 1001 1002 /* low priority tx ring */ 1003 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1004 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1005 printf(": can't allocate low tx ring\n"); 1006 goto bail_txhiring; 1007 } 1008 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1009 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1010 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1011 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1012 sc->sc_txlor.r_reg = TXP_H2A_3; 1013 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1014 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1015 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1016 1017 /* high priority rx ring */ 1018 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1019 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1020 printf(": can't allocate high rx ring\n"); 1021 goto bail_txloring; 1022 } 1023 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1024 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1025 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1026 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1027 sc->sc_rxhir.r_desc = 1028 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1029 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1030 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1031 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1032 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1033 1034 /* low priority ring */ 1035 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1036 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1037 printf(": can't allocate low rx ring\n"); 1038 goto bail_rxhiring; 1039 } 1040 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1041 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1042 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1043 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1044 sc->sc_rxlor.r_desc = 1045 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1046 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1047 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1048 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1049 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1050 1051 /* command ring */ 1052 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1053 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1054 printf(": can't allocate command ring\n"); 1055 goto bail_rxloring; 1056 } 1057 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1058 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1059 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1060 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1061 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1062 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1063 sc->sc_cmdring.lastwrite = 0; 1064 1065 /* response ring */ 1066 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1067 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1068 printf(": can't allocate response ring\n"); 1069 goto bail_cmdring; 1070 } 1071 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1072 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1073 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1074 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1075 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1076 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1077 sc->sc_rspring.lastwrite = 0; 1078 1079 /* receive buffer ring */ 1080 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1081 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1082 printf(": can't allocate rx buffer ring\n"); 1083 goto bail_rspring; 1084 } 1085 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1086 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1087 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1088 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1089 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1090 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1091 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1092 M_DEVBUF, M_NOWAIT); 1093 /* stash away pointer */ 1094 bcopy(&sd, __UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), sizeof(sd)); 1095 if (sd == NULL) 1096 break; 1097 1098 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1099 if (sd->sd_mbuf == NULL) { 1100 goto bail_rxbufring; 1101 } 1102 1103 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1104 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1105 goto bail_rxbufring; 1106 } 1107 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1108 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1109 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1110 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1111 goto bail_rxbufring; 1112 } 1113 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1114 BUS_DMA_NOWAIT)) { 1115 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1116 goto bail_rxbufring; 1117 } 1118 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1119 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1120 1121 1122 sc->sc_rxbufs[nb].rb_paddrlo = 1123 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1124 sc->sc_rxbufs[nb].rb_paddrhi = 1125 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1126 } 1127 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1128 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1129 BUS_DMASYNC_PREWRITE); 1130 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1131 sizeof(struct txp_rxbuf_desc)); 1132 1133 /* zero dma */ 1134 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1135 BUS_DMA_COHERENT)) { 1136 printf(": can't allocate response ring\n"); 1137 goto bail_rxbufring; 1138 } 1139 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1140 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1141 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1142 1143 /* See if it's waiting for boot, and try to boot it */ 1144 for (i = 0; i < 10000; i++) { 1145 r = READ_REG(sc, TXP_A2H_0); 1146 if (r == STAT_WAITING_FOR_BOOT) 1147 break; 1148 DELAY(50); 1149 } 1150 if (r != STAT_WAITING_FOR_BOOT) { 1151 printf(": not waiting for boot\n"); 1152 goto bail; 1153 } 1154 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1155 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1156 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1157 1158 /* See if it booted */ 1159 for (i = 0; i < 10000; i++) { 1160 r = READ_REG(sc, TXP_A2H_0); 1161 if (r == STAT_RUNNING) 1162 break; 1163 DELAY(50); 1164 } 1165 if (r != STAT_RUNNING) { 1166 printf(": fw not running\n"); 1167 goto bail; 1168 } 1169 1170 /* Clear TX and CMD ring write registers */ 1171 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1172 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1173 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1174 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1175 1176 return (0); 1177 1178 bail: 1179 txp_dma_free(sc, &sc->sc_zero_dma); 1180 bail_rxbufring: 1181 if (nb == RXBUF_ENTRIES) 1182 nb--; 1183 for (i = 0; i <= nb; i++) { 1184 bcopy(__UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), &sd, 1185 sizeof(sd)); 1186 if (sd) 1187 free(sd, M_DEVBUF); 1188 } 1189 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1190 bail_rspring: 1191 txp_dma_free(sc, &sc->sc_rspring_dma); 1192 bail_cmdring: 1193 txp_dma_free(sc, &sc->sc_cmdring_dma); 1194 bail_rxloring: 1195 txp_dma_free(sc, &sc->sc_rxloring_dma); 1196 bail_rxhiring: 1197 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1198 bail_txloring: 1199 txp_dma_free(sc, &sc->sc_txloring_dma); 1200 bail_txhiring: 1201 txp_dma_free(sc, &sc->sc_txhiring_dma); 1202 bail_host: 1203 txp_dma_free(sc, &sc->sc_host_dma); 1204 bail_boot: 1205 txp_dma_free(sc, &sc->sc_boot_dma); 1206 return (-1); 1207 } 1208 1209 int 1210 txp_dma_malloc(sc, size, dma, mapflags) 1211 struct txp_softc *sc; 1212 bus_size_t size; 1213 struct txp_dma_alloc *dma; 1214 int mapflags; 1215 { 1216 int r; 1217 1218 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1219 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1220 goto fail_0; 1221 1222 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1223 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1224 goto fail_1; 1225 1226 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1227 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1228 goto fail_2; 1229 1230 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1231 size, NULL, BUS_DMA_NOWAIT)) != 0) 1232 goto fail_3; 1233 1234 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1235 return (0); 1236 1237 fail_3: 1238 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1239 fail_2: 1240 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1241 fail_1: 1242 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1243 fail_0: 1244 return (r); 1245 } 1246 1247 void 1248 txp_dma_free(sc, dma) 1249 struct txp_softc *sc; 1250 struct txp_dma_alloc *dma; 1251 { 1252 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1253 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1254 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1255 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1256 } 1257 1258 int 1259 txp_ioctl(ifp, command, data) 1260 struct ifnet *ifp; 1261 u_long command; 1262 void *data; 1263 { 1264 struct txp_softc *sc = ifp->if_softc; 1265 struct ifreq *ifr = (struct ifreq *)data; 1266 struct ifaddr *ifa = (struct ifaddr *)data; 1267 int s, error = 0; 1268 1269 s = splnet(); 1270 1271 #if 0 1272 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1273 splx(s); 1274 return error; 1275 } 1276 #endif 1277 1278 switch(command) { 1279 case SIOCSIFADDR: 1280 ifp->if_flags |= IFF_UP; 1281 switch (ifa->ifa_addr->sa_family) { 1282 #ifdef INET 1283 case AF_INET: 1284 txp_init(sc); 1285 arp_ifinit(ifp, ifa); 1286 break; 1287 #endif /* INET */ 1288 default: 1289 txp_init(sc); 1290 break; 1291 } 1292 break; 1293 case SIOCSIFFLAGS: 1294 if (ifp->if_flags & IFF_UP) { 1295 txp_init(sc); 1296 } else { 1297 if (ifp->if_flags & IFF_RUNNING) 1298 txp_stop(sc); 1299 } 1300 break; 1301 case SIOCADDMULTI: 1302 case SIOCDELMULTI: 1303 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 1304 /* 1305 * Multicast list has changed; set the hardware 1306 * filter accordingly. 1307 */ 1308 if (ifp->if_flags & IFF_RUNNING) 1309 txp_set_filter(sc); 1310 error = 0; 1311 } 1312 break; 1313 case SIOCGIFMEDIA: 1314 case SIOCSIFMEDIA: 1315 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1316 break; 1317 default: 1318 error = EINVAL; 1319 break; 1320 } 1321 1322 splx(s); 1323 1324 return(error); 1325 } 1326 1327 void 1328 txp_init(sc) 1329 struct txp_softc *sc; 1330 { 1331 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1332 int s; 1333 1334 txp_stop(sc); 1335 1336 s = splnet(); 1337 1338 txp_set_filter(sc); 1339 1340 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1341 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1342 1343 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1344 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1345 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1346 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1347 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1348 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1349 1350 ifp->if_flags |= IFF_RUNNING; 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 ifp->if_timer = 0; 1353 1354 if (!callout_pending(&sc->sc_tick)) 1355 callout_schedule(&sc->sc_tick, hz); 1356 1357 splx(s); 1358 } 1359 1360 void 1361 txp_tick(vsc) 1362 void *vsc; 1363 { 1364 struct txp_softc *sc = vsc; 1365 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1366 struct txp_rsp_desc *rsp = NULL; 1367 struct txp_ext_desc *ext; 1368 int s; 1369 1370 s = splnet(); 1371 txp_rxbuf_reclaim(sc); 1372 1373 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1374 &rsp, 1)) 1375 goto out; 1376 if (rsp->rsp_numdesc != 6) 1377 goto out; 1378 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1379 NULL, NULL, NULL, 1)) 1380 goto out; 1381 ext = (struct txp_ext_desc *)(rsp + 1); 1382 1383 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1384 ext[4].ext_1 + ext[4].ext_4; 1385 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1386 ext[2].ext_1; 1387 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1388 ext[1].ext_3; 1389 ifp->if_opackets += rsp->rsp_par2; 1390 ifp->if_ipackets += ext[2].ext_3; 1391 1392 out: 1393 if (rsp != NULL) 1394 free(rsp, M_DEVBUF); 1395 1396 splx(s); 1397 callout_schedule(&sc->sc_tick, hz); 1398 } 1399 1400 void 1401 txp_start(ifp) 1402 struct ifnet *ifp; 1403 { 1404 struct txp_softc *sc = ifp->if_softc; 1405 struct txp_tx_ring *r = &sc->sc_txhir; 1406 struct txp_tx_desc *txd; 1407 int txdidx; 1408 struct txp_frag_desc *fxd; 1409 struct mbuf *m, *mnew; 1410 struct txp_swdesc *sd; 1411 u_int32_t firstprod, firstcnt, prod, cnt, i; 1412 struct m_tag *mtag; 1413 1414 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1415 return; 1416 1417 prod = r->r_prod; 1418 cnt = r->r_cnt; 1419 1420 while (1) { 1421 IFQ_POLL(&ifp->if_snd, m); 1422 if (m == NULL) 1423 break; 1424 mnew = NULL; 1425 1426 firstprod = prod; 1427 firstcnt = cnt; 1428 1429 sd = sc->sc_txd + prod; 1430 sd->sd_mbuf = m; 1431 1432 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1433 BUS_DMA_NOWAIT)) { 1434 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1435 if (mnew == NULL) 1436 goto oactive1; 1437 if (m->m_pkthdr.len > MHLEN) { 1438 MCLGET(mnew, M_DONTWAIT); 1439 if ((mnew->m_flags & M_EXT) == 0) { 1440 m_freem(mnew); 1441 goto oactive1; 1442 } 1443 } 1444 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1445 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1446 IFQ_DEQUEUE(&ifp->if_snd, m); 1447 m_freem(m); 1448 m = mnew; 1449 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1450 BUS_DMA_NOWAIT)) 1451 goto oactive1; 1452 } 1453 1454 if ((TX_ENTRIES - cnt) < 4) 1455 goto oactive; 1456 1457 txd = r->r_desc + prod; 1458 txdidx = prod; 1459 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1460 txd->tx_numdesc = 0; 1461 txd->tx_addrlo = 0; 1462 txd->tx_addrhi = 0; 1463 txd->tx_totlen = m->m_pkthdr.len; 1464 txd->tx_pflags = 0; 1465 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1466 1467 if (++prod == TX_ENTRIES) 1468 prod = 0; 1469 1470 if (++cnt >= (TX_ENTRIES - 4)) 1471 goto oactive; 1472 1473 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1474 txd->tx_pflags = TX_PFLAGS_VLAN | 1475 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1476 1477 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1478 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1479 #ifdef TRY_TX_TCP_CSUM 1480 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1481 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1482 #endif 1483 #ifdef TRY_TX_UDP_CSUM 1484 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1485 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1486 #endif 1487 1488 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1489 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1490 1491 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1492 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1493 if (++cnt >= (TX_ENTRIES - 4)) { 1494 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1495 0, sd->sd_map->dm_mapsize, 1496 BUS_DMASYNC_POSTWRITE); 1497 goto oactive; 1498 } 1499 1500 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1501 FRAG_FLAGS_VALID; 1502 fxd->frag_rsvd1 = 0; 1503 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1504 fxd->frag_addrlo = 1505 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1506 0xffffffff; 1507 fxd->frag_addrhi = 1508 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1509 32; 1510 fxd->frag_rsvd2 = 0; 1511 1512 bus_dmamap_sync(sc->sc_dmat, 1513 sc->sc_txhiring_dma.dma_map, 1514 prod * sizeof(struct txp_frag_desc), 1515 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1516 1517 if (++prod == TX_ENTRIES) { 1518 fxd = (struct txp_frag_desc *)r->r_desc; 1519 prod = 0; 1520 } else 1521 fxd++; 1522 1523 } 1524 1525 /* 1526 * if mnew isn't NULL, we already dequeued and copied 1527 * the packet. 1528 */ 1529 if (mnew == NULL) 1530 IFQ_DEQUEUE(&ifp->if_snd, m); 1531 1532 ifp->if_timer = 5; 1533 1534 #if NBPFILTER > 0 1535 if (ifp->if_bpf) 1536 bpf_mtap(ifp->if_bpf, m); 1537 #endif 1538 1539 txd->tx_flags |= TX_FLAGS_VALID; 1540 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1541 txdidx * sizeof(struct txp_tx_desc), 1542 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1543 1544 #if 0 1545 { 1546 struct mbuf *mx; 1547 int i; 1548 1549 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1550 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1551 txd->tx_pflags); 1552 for (mx = m; mx != NULL; mx = mx->m_next) { 1553 for (i = 0; i < mx->m_len; i++) { 1554 printf(":%02x", 1555 (u_int8_t)m->m_data[i]); 1556 } 1557 } 1558 printf("\n"); 1559 } 1560 #endif 1561 1562 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1563 } 1564 1565 r->r_prod = prod; 1566 r->r_cnt = cnt; 1567 return; 1568 1569 oactive: 1570 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1571 oactive1: 1572 ifp->if_flags |= IFF_OACTIVE; 1573 r->r_prod = firstprod; 1574 r->r_cnt = firstcnt; 1575 } 1576 1577 /* 1578 * Handle simple commands sent to the typhoon 1579 */ 1580 int 1581 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1582 struct txp_softc *sc; 1583 u_int16_t id, in1, *out1; 1584 u_int32_t in2, in3, *out2, *out3; 1585 int wait; 1586 { 1587 struct txp_rsp_desc *rsp = NULL; 1588 1589 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1590 return (-1); 1591 1592 if (!wait) 1593 return (0); 1594 1595 if (out1 != NULL) 1596 *out1 = le16toh(rsp->rsp_par1); 1597 if (out2 != NULL) 1598 *out2 = le32toh(rsp->rsp_par2); 1599 if (out3 != NULL) 1600 *out3 = le32toh(rsp->rsp_par3); 1601 free(rsp, M_DEVBUF); 1602 return (0); 1603 } 1604 1605 int 1606 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1607 struct txp_softc *sc; 1608 u_int16_t id, in1; 1609 u_int32_t in2, in3; 1610 struct txp_ext_desc *in_extp; 1611 u_int8_t in_extn; 1612 struct txp_rsp_desc **rspp; 1613 int wait; 1614 { 1615 struct txp_hostvar *hv = sc->sc_hostvar; 1616 struct txp_cmd_desc *cmd; 1617 struct txp_ext_desc *ext; 1618 u_int32_t idx, i; 1619 u_int16_t seq; 1620 1621 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1622 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1623 return (-1); 1624 } 1625 1626 idx = sc->sc_cmdring.lastwrite; 1627 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1628 bzero(cmd, sizeof(*cmd)); 1629 1630 cmd->cmd_numdesc = in_extn; 1631 seq = sc->sc_seq++; 1632 cmd->cmd_seq = htole16(seq); 1633 cmd->cmd_id = htole16(id); 1634 cmd->cmd_par1 = htole16(in1); 1635 cmd->cmd_par2 = htole32(in2); 1636 cmd->cmd_par3 = htole32(in3); 1637 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1638 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1639 1640 idx += sizeof(struct txp_cmd_desc); 1641 if (idx == sc->sc_cmdring.size) 1642 idx = 0; 1643 1644 for (i = 0; i < in_extn; i++) { 1645 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1646 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1647 in_extp++; 1648 idx += sizeof(struct txp_cmd_desc); 1649 if (idx == sc->sc_cmdring.size) 1650 idx = 0; 1651 } 1652 1653 sc->sc_cmdring.lastwrite = idx; 1654 1655 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1656 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1657 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1658 1659 if (!wait) 1660 return (0); 1661 1662 for (i = 0; i < 10000; i++) { 1663 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1664 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1665 idx = le32toh(hv->hv_resp_read_idx); 1666 if (idx != le32toh(hv->hv_resp_write_idx)) { 1667 *rspp = NULL; 1668 if (txp_response(sc, idx, id, seq, rspp)) 1669 return (-1); 1670 if (*rspp != NULL) 1671 break; 1672 } 1673 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1674 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1675 DELAY(50); 1676 } 1677 if (i == 1000 || (*rspp) == NULL) { 1678 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1679 return (-1); 1680 } 1681 1682 return (0); 1683 } 1684 1685 int 1686 txp_response(sc, ridx, id, seq, rspp) 1687 struct txp_softc *sc; 1688 u_int32_t ridx; 1689 u_int16_t id; 1690 u_int16_t seq; 1691 struct txp_rsp_desc **rspp; 1692 { 1693 struct txp_hostvar *hv = sc->sc_hostvar; 1694 struct txp_rsp_desc *rsp; 1695 1696 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1697 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1698 1699 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1700 *rspp = (struct txp_rsp_desc *)malloc( 1701 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1702 M_DEVBUF, M_NOWAIT); 1703 if ((*rspp) == NULL) 1704 return (-1); 1705 txp_rsp_fixup(sc, rsp, *rspp); 1706 return (0); 1707 } 1708 1709 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1710 printf("%s: response error: id 0x%x\n", 1711 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1712 txp_rsp_fixup(sc, rsp, NULL); 1713 ridx = le32toh(hv->hv_resp_read_idx); 1714 continue; 1715 } 1716 1717 switch (le16toh(rsp->rsp_id)) { 1718 case TXP_CMD_CYCLE_STATISTICS: 1719 case TXP_CMD_MEDIA_STATUS_READ: 1720 break; 1721 case TXP_CMD_HELLO_RESPONSE: 1722 printf("%s: hello\n", TXP_DEVNAME(sc)); 1723 break; 1724 default: 1725 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1726 le16toh(rsp->rsp_id)); 1727 } 1728 1729 txp_rsp_fixup(sc, rsp, NULL); 1730 ridx = le32toh(hv->hv_resp_read_idx); 1731 hv->hv_resp_read_idx = le32toh(ridx); 1732 } 1733 1734 return (0); 1735 } 1736 1737 void 1738 txp_rsp_fixup(sc, rsp, dst) 1739 struct txp_softc *sc; 1740 struct txp_rsp_desc *rsp, *dst; 1741 { 1742 struct txp_rsp_desc *src = rsp; 1743 struct txp_hostvar *hv = sc->sc_hostvar; 1744 u_int32_t i, ridx; 1745 1746 ridx = le32toh(hv->hv_resp_read_idx); 1747 1748 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1749 if (dst != NULL) 1750 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1751 ridx += sizeof(struct txp_rsp_desc); 1752 if (ridx == sc->sc_rspring.size) { 1753 src = sc->sc_rspring.base; 1754 ridx = 0; 1755 } else 1756 src++; 1757 sc->sc_rspring.lastwrite = ridx; 1758 hv->hv_resp_read_idx = htole32(ridx); 1759 } 1760 1761 hv->hv_resp_read_idx = htole32(ridx); 1762 } 1763 1764 int 1765 txp_cmd_desc_numfree(sc) 1766 struct txp_softc *sc; 1767 { 1768 struct txp_hostvar *hv = sc->sc_hostvar; 1769 struct txp_boot_record *br = sc->sc_boot; 1770 u_int32_t widx, ridx, nfree; 1771 1772 widx = sc->sc_cmdring.lastwrite; 1773 ridx = le32toh(hv->hv_cmd_read_idx); 1774 1775 if (widx == ridx) { 1776 /* Ring is completely free */ 1777 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1778 } else { 1779 if (widx > ridx) 1780 nfree = le32toh(br->br_cmd_siz) - 1781 (widx - ridx + sizeof(struct txp_cmd_desc)); 1782 else 1783 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1784 } 1785 1786 return (nfree / sizeof(struct txp_cmd_desc)); 1787 } 1788 1789 void 1790 txp_stop(sc) 1791 struct txp_softc *sc; 1792 { 1793 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1794 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1795 1796 if (callout_pending(&sc->sc_tick)) 1797 callout_stop(&sc->sc_tick); 1798 } 1799 1800 void 1801 txp_watchdog(struct ifnet *ifp) 1802 { 1803 } 1804 1805 int 1806 txp_ifmedia_upd(ifp) 1807 struct ifnet *ifp; 1808 { 1809 struct txp_softc *sc = ifp->if_softc; 1810 struct ifmedia *ifm = &sc->sc_ifmedia; 1811 u_int16_t new_xcvr; 1812 1813 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1814 return (EINVAL); 1815 1816 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1817 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1818 new_xcvr = TXP_XCVR_10_FDX; 1819 else 1820 new_xcvr = TXP_XCVR_10_HDX; 1821 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1822 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1823 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1824 new_xcvr = TXP_XCVR_100_FDX; 1825 else 1826 new_xcvr = TXP_XCVR_100_HDX; 1827 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1828 new_xcvr = TXP_XCVR_AUTO; 1829 } else 1830 return (EINVAL); 1831 1832 /* nothing to do */ 1833 if (sc->sc_xcvr == new_xcvr) 1834 return (0); 1835 1836 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1837 NULL, NULL, NULL, 0); 1838 sc->sc_xcvr = new_xcvr; 1839 1840 return (0); 1841 } 1842 1843 void 1844 txp_ifmedia_sts(ifp, ifmr) 1845 struct ifnet *ifp; 1846 struct ifmediareq *ifmr; 1847 { 1848 struct txp_softc *sc = ifp->if_softc; 1849 struct ifmedia *ifm = &sc->sc_ifmedia; 1850 u_int16_t bmsr, bmcr, anlpar; 1851 1852 ifmr->ifm_status = IFM_AVALID; 1853 ifmr->ifm_active = IFM_ETHER; 1854 1855 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1856 &bmsr, NULL, NULL, 1)) 1857 goto bail; 1858 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1859 &bmsr, NULL, NULL, 1)) 1860 goto bail; 1861 1862 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1863 &bmcr, NULL, NULL, 1)) 1864 goto bail; 1865 1866 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1867 &anlpar, NULL, NULL, 1)) 1868 goto bail; 1869 1870 if (bmsr & BMSR_LINK) 1871 ifmr->ifm_status |= IFM_ACTIVE; 1872 1873 if (bmcr & BMCR_ISO) { 1874 ifmr->ifm_active |= IFM_NONE; 1875 ifmr->ifm_status = 0; 1876 return; 1877 } 1878 1879 if (bmcr & BMCR_LOOP) 1880 ifmr->ifm_active |= IFM_LOOP; 1881 1882 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1883 if ((bmsr & BMSR_ACOMP) == 0) { 1884 ifmr->ifm_active |= IFM_NONE; 1885 return; 1886 } 1887 1888 if (anlpar & ANLPAR_T4) 1889 ifmr->ifm_active |= IFM_100_T4; 1890 else if (anlpar & ANLPAR_TX_FD) 1891 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1892 else if (anlpar & ANLPAR_TX) 1893 ifmr->ifm_active |= IFM_100_TX; 1894 else if (anlpar & ANLPAR_10_FD) 1895 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1896 else if (anlpar & ANLPAR_10) 1897 ifmr->ifm_active |= IFM_10_T; 1898 else 1899 ifmr->ifm_active |= IFM_NONE; 1900 } else 1901 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1902 return; 1903 1904 bail: 1905 ifmr->ifm_active |= IFM_NONE; 1906 ifmr->ifm_status &= ~IFM_AVALID; 1907 } 1908 1909 void 1910 txp_show_descriptor(d) 1911 void *d; 1912 { 1913 struct txp_cmd_desc *cmd = d; 1914 struct txp_rsp_desc *rsp = d; 1915 struct txp_tx_desc *txd = d; 1916 struct txp_frag_desc *frgd = d; 1917 1918 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1919 case CMD_FLAGS_TYPE_CMD: 1920 /* command descriptor */ 1921 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1922 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1923 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1924 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1925 break; 1926 case CMD_FLAGS_TYPE_RESP: 1927 /* response descriptor */ 1928 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1929 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1930 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1931 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1932 break; 1933 case CMD_FLAGS_TYPE_DATA: 1934 /* data header (assuming tx for now) */ 1935 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1936 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1937 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1938 break; 1939 case CMD_FLAGS_TYPE_FRAG: 1940 /* fragment descriptor */ 1941 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1942 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1943 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1944 break; 1945 default: 1946 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1947 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1948 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1949 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1950 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1951 break; 1952 } 1953 } 1954 1955 void 1956 txp_set_filter(sc) 1957 struct txp_softc *sc; 1958 { 1959 struct ethercom *ac = &sc->sc_arpcom; 1960 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1961 u_int32_t crc, carry, hashbit, hash[2]; 1962 u_int16_t filter; 1963 u_int8_t octet; 1964 int i, j, mcnt = 0; 1965 struct ether_multi *enm; 1966 struct ether_multistep step; 1967 1968 if (ifp->if_flags & IFF_PROMISC) { 1969 filter = TXP_RXFILT_PROMISC; 1970 goto setit; 1971 } 1972 1973 again: 1974 filter = TXP_RXFILT_DIRECT; 1975 1976 if (ifp->if_flags & IFF_BROADCAST) 1977 filter |= TXP_RXFILT_BROADCAST; 1978 1979 if (ifp->if_flags & IFF_ALLMULTI) 1980 filter |= TXP_RXFILT_ALLMULTI; 1981 else { 1982 hash[0] = hash[1] = 0; 1983 1984 ETHER_FIRST_MULTI(step, ac, enm); 1985 while (enm != NULL) { 1986 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1987 /* 1988 * We must listen to a range of multicast 1989 * addresses. For now, just accept all 1990 * multicasts, rather than trying to set only 1991 * those filter bits needed to match the range. 1992 * (At this time, the only use of address 1993 * ranges is for IP multicast routing, for 1994 * which the range is big enough to require 1995 * all bits set.) 1996 */ 1997 ifp->if_flags |= IFF_ALLMULTI; 1998 goto again; 1999 } 2000 2001 mcnt++; 2002 crc = 0xffffffff; 2003 2004 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2005 octet = enm->enm_addrlo[i]; 2006 for (j = 0; j < 8; j++) { 2007 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2008 (octet & 1); 2009 crc <<= 1; 2010 octet >>= 1; 2011 if (carry) 2012 crc = (crc ^ TXP_POLYNOMIAL) | 2013 carry; 2014 } 2015 } 2016 hashbit = (u_int16_t)(crc & (64 - 1)); 2017 hash[hashbit / 32] |= (1 << hashbit % 32); 2018 ETHER_NEXT_MULTI(step, enm); 2019 } 2020 2021 if (mcnt > 0) { 2022 filter |= TXP_RXFILT_HASHMULTI; 2023 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2024 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2025 } 2026 } 2027 2028 setit: 2029 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2030 NULL, NULL, NULL, 1); 2031 } 2032 2033 void 2034 txp_capabilities(sc) 2035 struct txp_softc *sc; 2036 { 2037 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2038 struct txp_rsp_desc *rsp = NULL; 2039 struct txp_ext_desc *ext; 2040 2041 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2042 goto out; 2043 2044 if (rsp->rsp_numdesc != 1) 2045 goto out; 2046 ext = (struct txp_ext_desc *)(rsp + 1); 2047 2048 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2049 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2050 2051 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2052 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2053 sc->sc_tx_capability |= OFFLOAD_VLAN; 2054 sc->sc_rx_capability |= OFFLOAD_VLAN; 2055 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2056 } 2057 2058 #if 0 2059 /* not ready yet */ 2060 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2061 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2062 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2063 ifp->if_capabilities |= IFCAP_IPSEC; 2064 } 2065 #endif 2066 2067 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2068 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2069 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2070 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2071 } 2072 2073 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2074 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2075 #ifdef TRY_TX_TCP_CSUM 2076 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2077 ifp->if_capabilities |= 2078 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2079 #endif 2080 } 2081 2082 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2083 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2084 #ifdef TRY_TX_UDP_CSUM 2085 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2086 ifp->if_capabilities |= 2087 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2088 #endif 2089 } 2090 2091 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2092 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2093 goto out; 2094 2095 out: 2096 if (rsp != NULL) 2097 free(rsp, M_DEVBUF); 2098 } 2099
Indexes created Tue Sep 30 20:09:53 GMT 2025