if_txp.c revision 1.26
1 /* $NetBSD: if_txp.c,v 1.26 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.26 2008/04/10 19:13:37 cegger Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 71 #include <sys/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(device_t, cfdata_t, void *); 91 void txp_attach(device_t, device_t, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, void *); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 const struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(pcireg_t id) 167 { 168 int i; 169 170 for (i = 0; i < __arraycount(txp_devices); i++) 171 if (PCI_VENDOR(id) == txp_devices[i].vid && 172 PCI_PRODUCT(id) == txp_devices[i].did) 173 return &txp_devices[i]; 174 return (0); 175 } 176 177 int 178 txp_probe(device_t parent, cfdata_t match, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (txp_pcilookup(pa->pa_id)) 183 return (1); 184 return (0); 185 } 186 187 void 188 txp_attach(device_t parent, device_t self, void *aux) 189 { 190 struct txp_softc *sc = device_private(self); 191 struct pci_attach_args *pa = aux; 192 pci_chipset_tag_t pc = pa->pa_pc; 193 pci_intr_handle_t ih; 194 const char *intrstr = NULL; 195 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 196 u_int32_t command; 197 u_int16_t p1; 198 u_int32_t p2; 199 u_char enaddr[6]; 200 const struct txp_pci_match *match; 201 u_int16_t subsys; 202 int i, flags; 203 char devinfo[256]; 204 205 sc->sc_cold = 1; 206 207 match = txp_pcilookup(pa->pa_id); 208 flags = match->flags; 209 if (match->flags & TXP_USESUBSYSTEM) { 210 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 211 PCI_SUBSYS_ID_REG)); 212 for (i = 0; 213 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 214 i++) 215 if ((subsys & txp_subsysinfo[i].mask) == 216 txp_subsysinfo[i].value) 217 flags |= txp_subsysinfo[i].flags; 218 } 219 sc->sc_flags = flags; 220 221 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 222 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 223 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 224 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, device_xname(&sc->sc_dev)); 225 226 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 227 228 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 229 printf(": failed to enable bus mastering\n"); 230 return; 231 } 232 233 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 234 printf(": failed to enable memory mapping\n"); 235 return; 236 } 237 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 238 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 239 printf(": can't map mem space %d\n", 0); 240 return; 241 } 242 243 sc->sc_dmat = pa->pa_dmat; 244 245 /* 246 * Allocate our interrupt. 247 */ 248 if (pci_intr_map(pa, &ih)) { 249 printf(": couldn't map interrupt\n"); 250 return; 251 } 252 253 intrstr = pci_intr_string(pc, ih); 254 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 255 if (sc->sc_ih == NULL) { 256 printf(": couldn't establish interrupt"); 257 if (intrstr != NULL) 258 printf(" at %s", intrstr); 259 printf("\n"); 260 return; 261 } 262 printf(": interrupting at %s\n", intrstr); 263 264 if (txp_chip_init(sc)) 265 goto cleanupintr; 266 267 if (txp_download_fw(sc)) 268 goto cleanupintr; 269 270 if (txp_alloc_rings(sc)) 271 goto cleanupintr; 272 273 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 274 NULL, NULL, NULL, 1)) 275 goto cleanupintr; 276 277 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 278 &p1, &p2, NULL, 1)) 279 goto cleanupintr; 280 281 txp_set_filter(sc); 282 283 p1 = htole16(p1); 284 enaddr[0] = ((u_int8_t *)&p1)[1]; 285 enaddr[1] = ((u_int8_t *)&p1)[0]; 286 p2 = htole32(p2); 287 enaddr[2] = ((u_int8_t *)&p2)[3]; 288 enaddr[3] = ((u_int8_t *)&p2)[2]; 289 enaddr[4] = ((u_int8_t *)&p2)[1]; 290 enaddr[5] = ((u_int8_t *)&p2)[0]; 291 292 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 293 ether_sprintf(enaddr)); 294 sc->sc_cold = 0; 295 296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 297 if (flags & TXP_FIBER) { 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 303 0, NULL); 304 } else { 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 316 0, NULL); 317 } 318 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 319 320 sc->sc_xcvr = TXP_XCVR_AUTO; 321 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 322 NULL, NULL, NULL, 0); 323 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 324 325 ifp->if_softc = sc; 326 ifp->if_mtu = ETHERMTU; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = txp_ioctl; 329 ifp->if_start = txp_start; 330 ifp->if_watchdog = txp_watchdog; 331 ifp->if_baudrate = 10000000; 332 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 333 IFQ_SET_READY(&ifp->if_snd); 334 ifp->if_capabilities = 0; 335 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 336 337 txp_capabilities(sc); 338 339 callout_init(&sc->sc_tick, 0); 340 callout_setfunc(&sc->sc_tick, txp_tick, sc); 341 342 /* 343 * Attach us everywhere 344 */ 345 if_attach(ifp); 346 ether_ifattach(ifp, enaddr); 347 348 shutdownhook_establish(txp_shutdown, sc); 349 350 351 return; 352 353 cleanupintr: 354 pci_intr_disestablish(pc,sc->sc_ih); 355 356 return; 357 358 } 359 360 int 361 txp_chip_init(sc) 362 struct txp_softc *sc; 363 { 364 /* disable interrupts */ 365 WRITE_REG(sc, TXP_IER, 0); 366 WRITE_REG(sc, TXP_IMR, 367 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 368 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 369 TXP_INT_LATCH); 370 371 /* ack all interrupts */ 372 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 373 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 374 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 375 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 376 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 377 378 if (txp_reset_adapter(sc)) 379 return (-1); 380 381 /* disable interrupts */ 382 WRITE_REG(sc, TXP_IER, 0); 383 WRITE_REG(sc, TXP_IMR, 384 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 385 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 386 TXP_INT_LATCH); 387 388 /* ack all interrupts */ 389 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 390 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 391 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 392 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 393 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 394 395 return (0); 396 } 397 398 int 399 txp_reset_adapter(sc) 400 struct txp_softc *sc; 401 { 402 u_int32_t r; 403 int i; 404 405 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 406 DELAY(1000); 407 WRITE_REG(sc, TXP_SRR, 0); 408 409 /* Should wait max 6 seconds */ 410 for (i = 0; i < 6000; i++) { 411 r = READ_REG(sc, TXP_A2H_0); 412 if (r == STAT_WAITING_FOR_HOST_REQUEST) 413 break; 414 DELAY(1000); 415 } 416 417 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 418 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 419 return (-1); 420 } 421 422 return (0); 423 } 424 425 int 426 txp_download_fw(sc) 427 struct txp_softc *sc; 428 { 429 const struct txp_fw_file_header *fileheader; 430 const struct txp_fw_section_header *secthead; 431 int sect; 432 u_int32_t r, i, ier, imr; 433 434 ier = READ_REG(sc, TXP_IER); 435 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 436 437 imr = READ_REG(sc, TXP_IMR); 438 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 439 440 for (i = 0; i < 10000; i++) { 441 r = READ_REG(sc, TXP_A2H_0); 442 if (r == STAT_WAITING_FOR_HOST_REQUEST) 443 break; 444 DELAY(50); 445 } 446 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 447 printf(": not waiting for host request\n"); 448 return (-1); 449 } 450 451 /* Ack the status */ 452 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 453 454 fileheader = (const struct txp_fw_file_header *)tc990image; 455 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 456 printf(": fw invalid magic\n"); 457 return (-1); 458 } 459 460 /* Tell boot firmware to get ready for image */ 461 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 462 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 463 464 if (txp_download_fw_wait(sc)) { 465 printf("%s: fw wait failed, initial\n", device_xname(&sc->sc_dev)); 466 return (-1); 467 } 468 469 secthead = (const struct txp_fw_section_header *) 470 (((const u_int8_t *)tc990image) + 471 sizeof(struct txp_fw_file_header)); 472 473 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 474 if (txp_download_fw_section(sc, secthead, sect)) 475 return (-1); 476 secthead = (const struct txp_fw_section_header *) 477 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 478 sizeof(*secthead)); 479 } 480 481 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 482 483 for (i = 0; i < 10000; i++) { 484 r = READ_REG(sc, TXP_A2H_0); 485 if (r == STAT_WAITING_FOR_BOOT) 486 break; 487 DELAY(50); 488 } 489 if (r != STAT_WAITING_FOR_BOOT) { 490 printf(": not waiting for boot\n"); 491 return (-1); 492 } 493 494 WRITE_REG(sc, TXP_IER, ier); 495 WRITE_REG(sc, TXP_IMR, imr); 496 497 return (0); 498 } 499 500 int 501 txp_download_fw_wait(sc) 502 struct txp_softc *sc; 503 { 504 u_int32_t i, r; 505 506 for (i = 0; i < 10000; i++) { 507 r = READ_REG(sc, TXP_ISR); 508 if (r & TXP_INT_A2H_0) 509 break; 510 DELAY(50); 511 } 512 513 if (!(r & TXP_INT_A2H_0)) { 514 printf(": fw wait failed comm0\n"); 515 return (-1); 516 } 517 518 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 519 520 r = READ_REG(sc, TXP_A2H_0); 521 if (r != STAT_WAITING_FOR_SEGMENT) { 522 printf(": fw not waiting for segment\n"); 523 return (-1); 524 } 525 return (0); 526 } 527 528 int 529 txp_download_fw_section(sc, sect, sectnum) 530 struct txp_softc *sc; 531 const struct txp_fw_section_header *sect; 532 int sectnum; 533 { 534 struct txp_dma_alloc dma; 535 int rseg, err = 0; 536 struct mbuf m; 537 #ifdef INET 538 u_int16_t csum; 539 #endif 540 541 /* Skip zero length sections */ 542 if (sect->nbytes == 0) 543 return (0); 544 545 /* Make sure we aren't past the end of the image */ 546 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 547 if (rseg >= sizeof(tc990image)) { 548 printf(": fw invalid section address, section %d\n", sectnum); 549 return (-1); 550 } 551 552 /* Make sure this section doesn't go past the end */ 553 rseg += le32toh(sect->nbytes); 554 if (rseg >= sizeof(tc990image)) { 555 printf(": fw truncated section %d\n", sectnum); 556 return (-1); 557 } 558 559 /* map a buffer, copy segment to it, get physaddr */ 560 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 561 printf(": fw dma malloc failed, section %d\n", sectnum); 562 return (-1); 563 } 564 565 bcopy(((const u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 566 le32toh(sect->nbytes)); 567 568 /* 569 * dummy up mbuf and verify section checksum 570 */ 571 m.m_type = MT_DATA; 572 m.m_next = m.m_nextpkt = NULL; 573 m.m_len = le32toh(sect->nbytes); 574 m.m_data = dma.dma_vaddr; 575 m.m_flags = 0; 576 #ifdef INET 577 csum = in_cksum(&m, le32toh(sect->nbytes)); 578 if (csum != sect->cksum) { 579 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 580 sectnum, sect->cksum, csum); 581 txp_dma_free(sc, &dma); 582 return -1; 583 } 584 #endif 585 586 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 587 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 588 589 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 590 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 591 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 592 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 593 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 594 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 595 596 if (txp_download_fw_wait(sc)) { 597 printf("%s: fw wait failed, section %d\n", 598 device_xname(&sc->sc_dev), sectnum); 599 err = -1; 600 } 601 602 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 603 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 604 605 txp_dma_free(sc, &dma); 606 return (err); 607 } 608 609 int 610 txp_intr(vsc) 611 void *vsc; 612 { 613 struct txp_softc *sc = vsc; 614 struct txp_hostvar *hv = sc->sc_hostvar; 615 u_int32_t isr; 616 int claimed = 0; 617 618 /* mask all interrupts */ 619 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 620 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 621 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 622 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 623 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 624 625 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 626 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 627 628 isr = READ_REG(sc, TXP_ISR); 629 while (isr) { 630 claimed = 1; 631 WRITE_REG(sc, TXP_ISR, isr); 632 633 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 635 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 636 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 637 638 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 639 txp_rxbuf_reclaim(sc); 640 641 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 642 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 643 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 644 645 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 646 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 647 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 648 649 isr = READ_REG(sc, TXP_ISR); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 653 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 654 655 /* unmask all interrupts */ 656 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 657 658 txp_start(&sc->sc_arpcom.ec_if); 659 660 return (claimed); 661 } 662 663 void 664 txp_rx_reclaim(sc, r, dma) 665 struct txp_softc *sc; 666 struct txp_rx_ring *r; 667 struct txp_dma_alloc *dma; 668 { 669 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 670 struct txp_rx_desc *rxd; 671 struct mbuf *m; 672 struct txp_swdesc *sd; 673 u_int32_t roff, woff; 674 int sumflags = 0; 675 int idx; 676 677 roff = le32toh(*r->r_roff); 678 woff = le32toh(*r->r_woff); 679 idx = roff / sizeof(struct txp_rx_desc); 680 rxd = r->r_desc + idx; 681 682 while (roff != woff) { 683 684 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 685 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 686 BUS_DMASYNC_POSTREAD); 687 688 if (rxd->rx_flags & RX_FLAGS_ERROR) { 689 printf("%s: error 0x%x\n", device_xname(&sc->sc_dev), 690 le32toh(rxd->rx_stat)); 691 ifp->if_ierrors++; 692 goto next; 693 } 694 695 /* retrieve stashed pointer */ 696 bcopy(__UNVOLATILE(&rxd->rx_vaddrlo), &sd, sizeof(sd)); 697 698 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 699 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 700 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 701 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 702 m = sd->sd_mbuf; 703 free(sd, M_DEVBUF); 704 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 705 706 #ifdef __STRICT_ALIGNMENT 707 { 708 /* 709 * XXX Nice chip, except it won't accept "off by 2" 710 * buffers, so we're force to copy. Supposedly 711 * this will be fixed in a newer firmware rev 712 * and this will be temporary. 713 */ 714 struct mbuf *mnew; 715 716 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 717 if (mnew == NULL) { 718 m_freem(m); 719 goto next; 720 } 721 if (m->m_len > (MHLEN - 2)) { 722 MCLGET(mnew, M_DONTWAIT); 723 if (!(mnew->m_flags & M_EXT)) { 724 m_freem(mnew); 725 m_freem(m); 726 goto next; 727 } 728 } 729 mnew->m_pkthdr.rcvif = ifp; 730 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 731 mnew->m_data += 2; 732 bcopy(m->m_data, mnew->m_data, m->m_len); 733 m_freem(m); 734 m = mnew; 735 } 736 #endif 737 738 #if NBPFILTER > 0 739 /* 740 * Handle BPF listeners. Let the BPF user see the packet. 741 */ 742 if (ifp->if_bpf) 743 bpf_mtap(ifp->if_bpf, m); 744 #endif 745 746 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 747 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 748 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 749 sumflags |= M_CSUM_IPv4; 750 751 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 752 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 753 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 754 sumflags |= M_CSUM_TCPv4; 755 756 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 757 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 758 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 759 sumflags |= M_CSUM_UDPv4; 760 761 m->m_pkthdr.csum_flags = sumflags; 762 763 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 764 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 765 continue); 766 } 767 768 (*ifp->if_input)(ifp, m); 769 770 next: 771 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 772 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 773 BUS_DMASYNC_PREREAD); 774 775 roff += sizeof(struct txp_rx_desc); 776 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 777 idx = 0; 778 roff = 0; 779 rxd = r->r_desc; 780 } else { 781 idx++; 782 rxd++; 783 } 784 woff = le32toh(*r->r_woff); 785 } 786 787 *r->r_roff = htole32(woff); 788 } 789 790 void 791 txp_rxbuf_reclaim(sc) 792 struct txp_softc *sc; 793 { 794 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 795 struct txp_hostvar *hv = sc->sc_hostvar; 796 struct txp_rxbuf_desc *rbd; 797 struct txp_swdesc *sd; 798 u_int32_t i, end; 799 800 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 801 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 802 803 if (++i == RXBUF_ENTRIES) 804 i = 0; 805 806 rbd = sc->sc_rxbufs + i; 807 808 while (i != end) { 809 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 810 M_DEVBUF, M_NOWAIT); 811 if (sd == NULL) 812 break; 813 814 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 815 if (sd->sd_mbuf == NULL) 816 goto err_sd; 817 818 MCLGET(sd->sd_mbuf, M_DONTWAIT); 819 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 820 goto err_mbuf; 821 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 822 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 823 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 824 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 825 goto err_mbuf; 826 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 827 BUS_DMA_NOWAIT)) { 828 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 829 goto err_mbuf; 830 } 831 832 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 833 i * sizeof(struct txp_rxbuf_desc), 834 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 835 836 /* stash away pointer */ 837 bcopy(&sd, __UNVOLATILE(&rbd->rb_vaddrlo), sizeof(sd)); 838 839 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 840 & 0xffffffff; 841 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 842 >> 32; 843 844 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 845 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 846 847 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 848 i * sizeof(struct txp_rxbuf_desc), 849 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 850 851 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 852 853 if (++i == RXBUF_ENTRIES) { 854 i = 0; 855 rbd = sc->sc_rxbufs; 856 } else 857 rbd++; 858 } 859 return; 860 861 err_mbuf: 862 m_freem(sd->sd_mbuf); 863 err_sd: 864 free(sd, M_DEVBUF); 865 } 866 867 /* 868 * Reclaim mbufs and entries from a transmit ring. 869 */ 870 void 871 txp_tx_reclaim(sc, r, dma) 872 struct txp_softc *sc; 873 struct txp_tx_ring *r; 874 struct txp_dma_alloc *dma; 875 { 876 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 877 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 878 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 879 struct txp_tx_desc *txd = r->r_desc + cons; 880 struct txp_swdesc *sd = sc->sc_txd + cons; 881 struct mbuf *m; 882 883 while (cons != idx) { 884 if (cnt == 0) 885 break; 886 887 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 888 cons * sizeof(struct txp_tx_desc), 889 sizeof(struct txp_tx_desc), 890 BUS_DMASYNC_POSTWRITE); 891 892 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 893 TX_FLAGS_TYPE_DATA) { 894 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 895 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 896 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 897 m = sd->sd_mbuf; 898 if (m != NULL) { 899 m_freem(m); 900 txd->tx_addrlo = 0; 901 txd->tx_addrhi = 0; 902 ifp->if_opackets++; 903 } 904 } 905 ifp->if_flags &= ~IFF_OACTIVE; 906 907 if (++cons == TX_ENTRIES) { 908 txd = r->r_desc; 909 cons = 0; 910 sd = sc->sc_txd; 911 } else { 912 txd++; 913 sd++; 914 } 915 916 cnt--; 917 } 918 919 r->r_cons = cons; 920 r->r_cnt = cnt; 921 if (cnt == 0) 922 ifp->if_timer = 0; 923 } 924 925 void 926 txp_shutdown(vsc) 927 void *vsc; 928 { 929 struct txp_softc *sc = (struct txp_softc *)vsc; 930 931 /* mask all interrupts */ 932 WRITE_REG(sc, TXP_IMR, 933 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 934 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 935 TXP_INT_LATCH); 936 937 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 938 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 939 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 940 } 941 942 int 943 txp_alloc_rings(sc) 944 struct txp_softc *sc; 945 { 946 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 947 struct txp_boot_record *boot; 948 struct txp_swdesc *sd; 949 u_int32_t r; 950 int i, j, nb; 951 952 /* boot record */ 953 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 954 BUS_DMA_COHERENT)) { 955 printf(": can't allocate boot record\n"); 956 return (-1); 957 } 958 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 959 bzero(boot, sizeof(*boot)); 960 sc->sc_boot = boot; 961 962 /* host variables */ 963 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 964 BUS_DMA_COHERENT)) { 965 printf(": can't allocate host ring\n"); 966 goto bail_boot; 967 } 968 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 969 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 970 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 971 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 972 973 /* high priority tx ring */ 974 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 975 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 976 printf(": can't allocate high tx ring\n"); 977 goto bail_host; 978 } 979 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 980 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 981 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 982 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 983 sc->sc_txhir.r_reg = TXP_H2A_1; 984 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 985 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 986 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 987 for (i = 0; i < TX_ENTRIES; i++) { 988 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 989 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 990 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 991 for (j = 0; j < i; j++) { 992 bus_dmamap_destroy(sc->sc_dmat, 993 sc->sc_txd[j].sd_map); 994 sc->sc_txd[j].sd_map = NULL; 995 } 996 goto bail_txhiring; 997 } 998 } 999 1000 /* low priority tx ring */ 1001 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1002 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1003 printf(": can't allocate low tx ring\n"); 1004 goto bail_txhiring; 1005 } 1006 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1007 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1008 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1009 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1010 sc->sc_txlor.r_reg = TXP_H2A_3; 1011 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1012 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1013 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1014 1015 /* high priority rx ring */ 1016 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1017 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1018 printf(": can't allocate high rx ring\n"); 1019 goto bail_txloring; 1020 } 1021 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1022 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1023 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1024 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1025 sc->sc_rxhir.r_desc = 1026 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1027 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1028 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1029 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1030 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1031 1032 /* low priority ring */ 1033 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1034 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1035 printf(": can't allocate low rx ring\n"); 1036 goto bail_rxhiring; 1037 } 1038 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1039 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1040 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1041 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1042 sc->sc_rxlor.r_desc = 1043 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1044 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1045 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1046 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1047 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1048 1049 /* command ring */ 1050 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1051 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1052 printf(": can't allocate command ring\n"); 1053 goto bail_rxloring; 1054 } 1055 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1056 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1057 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1058 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1059 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1060 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1061 sc->sc_cmdring.lastwrite = 0; 1062 1063 /* response ring */ 1064 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1065 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1066 printf(": can't allocate response ring\n"); 1067 goto bail_cmdring; 1068 } 1069 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1070 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1071 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1072 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1073 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1074 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1075 sc->sc_rspring.lastwrite = 0; 1076 1077 /* receive buffer ring */ 1078 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1079 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1080 printf(": can't allocate rx buffer ring\n"); 1081 goto bail_rspring; 1082 } 1083 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1084 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1085 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1086 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1087 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1088 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1089 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1090 M_DEVBUF, M_NOWAIT); 1091 /* stash away pointer */ 1092 bcopy(&sd, __UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), sizeof(sd)); 1093 if (sd == NULL) 1094 break; 1095 1096 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1097 if (sd->sd_mbuf == NULL) { 1098 goto bail_rxbufring; 1099 } 1100 1101 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1102 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1103 goto bail_rxbufring; 1104 } 1105 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1106 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1107 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1108 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1109 goto bail_rxbufring; 1110 } 1111 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1112 BUS_DMA_NOWAIT)) { 1113 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1114 goto bail_rxbufring; 1115 } 1116 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1117 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1118 1119 1120 sc->sc_rxbufs[nb].rb_paddrlo = 1121 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1122 sc->sc_rxbufs[nb].rb_paddrhi = 1123 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1124 } 1125 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1126 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1127 BUS_DMASYNC_PREWRITE); 1128 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1129 sizeof(struct txp_rxbuf_desc)); 1130 1131 /* zero dma */ 1132 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1133 BUS_DMA_COHERENT)) { 1134 printf(": can't allocate response ring\n"); 1135 goto bail_rxbufring; 1136 } 1137 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1138 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1139 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1140 1141 /* See if it's waiting for boot, and try to boot it */ 1142 for (i = 0; i < 10000; i++) { 1143 r = READ_REG(sc, TXP_A2H_0); 1144 if (r == STAT_WAITING_FOR_BOOT) 1145 break; 1146 DELAY(50); 1147 } 1148 if (r != STAT_WAITING_FOR_BOOT) { 1149 printf(": not waiting for boot\n"); 1150 goto bail; 1151 } 1152 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1153 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1154 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1155 1156 /* See if it booted */ 1157 for (i = 0; i < 10000; i++) { 1158 r = READ_REG(sc, TXP_A2H_0); 1159 if (r == STAT_RUNNING) 1160 break; 1161 DELAY(50); 1162 } 1163 if (r != STAT_RUNNING) { 1164 printf(": fw not running\n"); 1165 goto bail; 1166 } 1167 1168 /* Clear TX and CMD ring write registers */ 1169 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1170 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1171 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1172 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1173 1174 return (0); 1175 1176 bail: 1177 txp_dma_free(sc, &sc->sc_zero_dma); 1178 bail_rxbufring: 1179 if (nb == RXBUF_ENTRIES) 1180 nb--; 1181 for (i = 0; i <= nb; i++) { 1182 bcopy(__UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), &sd, 1183 sizeof(sd)); 1184 if (sd) 1185 free(sd, M_DEVBUF); 1186 } 1187 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1188 bail_rspring: 1189 txp_dma_free(sc, &sc->sc_rspring_dma); 1190 bail_cmdring: 1191 txp_dma_free(sc, &sc->sc_cmdring_dma); 1192 bail_rxloring: 1193 txp_dma_free(sc, &sc->sc_rxloring_dma); 1194 bail_rxhiring: 1195 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1196 bail_txloring: 1197 txp_dma_free(sc, &sc->sc_txloring_dma); 1198 bail_txhiring: 1199 txp_dma_free(sc, &sc->sc_txhiring_dma); 1200 bail_host: 1201 txp_dma_free(sc, &sc->sc_host_dma); 1202 bail_boot: 1203 txp_dma_free(sc, &sc->sc_boot_dma); 1204 return (-1); 1205 } 1206 1207 int 1208 txp_dma_malloc(sc, size, dma, mapflags) 1209 struct txp_softc *sc; 1210 bus_size_t size; 1211 struct txp_dma_alloc *dma; 1212 int mapflags; 1213 { 1214 int r; 1215 1216 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1217 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1218 goto fail_0; 1219 1220 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1221 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1222 goto fail_1; 1223 1224 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1225 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1226 goto fail_2; 1227 1228 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1229 size, NULL, BUS_DMA_NOWAIT)) != 0) 1230 goto fail_3; 1231 1232 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1233 return (0); 1234 1235 fail_3: 1236 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1237 fail_2: 1238 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1239 fail_1: 1240 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1241 fail_0: 1242 return (r); 1243 } 1244 1245 void 1246 txp_dma_free(sc, dma) 1247 struct txp_softc *sc; 1248 struct txp_dma_alloc *dma; 1249 { 1250 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1251 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1252 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1253 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1254 } 1255 1256 int 1257 txp_ioctl(ifp, command, data) 1258 struct ifnet *ifp; 1259 u_long command; 1260 void *data; 1261 { 1262 struct txp_softc *sc = ifp->if_softc; 1263 struct ifreq *ifr = (struct ifreq *)data; 1264 struct ifaddr *ifa = (struct ifaddr *)data; 1265 int s, error = 0; 1266 1267 s = splnet(); 1268 1269 #if 0 1270 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1271 splx(s); 1272 return error; 1273 } 1274 #endif 1275 1276 switch(command) { 1277 case SIOCSIFADDR: 1278 ifp->if_flags |= IFF_UP; 1279 switch (ifa->ifa_addr->sa_family) { 1280 #ifdef INET 1281 case AF_INET: 1282 txp_init(sc); 1283 arp_ifinit(ifp, ifa); 1284 break; 1285 #endif /* INET */ 1286 default: 1287 txp_init(sc); 1288 break; 1289 } 1290 break; 1291 case SIOCSIFFLAGS: 1292 if (ifp->if_flags & IFF_UP) { 1293 txp_init(sc); 1294 } else { 1295 if (ifp->if_flags & IFF_RUNNING) 1296 txp_stop(sc); 1297 } 1298 break; 1299 case SIOCADDMULTI: 1300 case SIOCDELMULTI: 1301 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1302 break; 1303 1304 error = 0; 1305 1306 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1307 ; 1308 else if (ifp->if_flags & IFF_RUNNING) { 1309 /* 1310 * Multicast list has changed; set the hardware 1311 * filter accordingly. 1312 */ 1313 txp_set_filter(sc); 1314 } 1315 break; 1316 case SIOCGIFMEDIA: 1317 case SIOCSIFMEDIA: 1318 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1319 break; 1320 default: 1321 error = EINVAL; 1322 break; 1323 } 1324 1325 splx(s); 1326 1327 return(error); 1328 } 1329 1330 void 1331 txp_init(sc) 1332 struct txp_softc *sc; 1333 { 1334 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1335 int s; 1336 1337 txp_stop(sc); 1338 1339 s = splnet(); 1340 1341 txp_set_filter(sc); 1342 1343 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1344 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1345 1346 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1347 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1348 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1349 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1350 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1351 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1352 1353 ifp->if_flags |= IFF_RUNNING; 1354 ifp->if_flags &= ~IFF_OACTIVE; 1355 ifp->if_timer = 0; 1356 1357 if (!callout_pending(&sc->sc_tick)) 1358 callout_schedule(&sc->sc_tick, hz); 1359 1360 splx(s); 1361 } 1362 1363 void 1364 txp_tick(vsc) 1365 void *vsc; 1366 { 1367 struct txp_softc *sc = vsc; 1368 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1369 struct txp_rsp_desc *rsp = NULL; 1370 struct txp_ext_desc *ext; 1371 int s; 1372 1373 s = splnet(); 1374 txp_rxbuf_reclaim(sc); 1375 1376 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1377 &rsp, 1)) 1378 goto out; 1379 if (rsp->rsp_numdesc != 6) 1380 goto out; 1381 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1382 NULL, NULL, NULL, 1)) 1383 goto out; 1384 ext = (struct txp_ext_desc *)(rsp + 1); 1385 1386 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1387 ext[4].ext_1 + ext[4].ext_4; 1388 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1389 ext[2].ext_1; 1390 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1391 ext[1].ext_3; 1392 ifp->if_opackets += rsp->rsp_par2; 1393 ifp->if_ipackets += ext[2].ext_3; 1394 1395 out: 1396 if (rsp != NULL) 1397 free(rsp, M_DEVBUF); 1398 1399 splx(s); 1400 callout_schedule(&sc->sc_tick, hz); 1401 } 1402 1403 void 1404 txp_start(ifp) 1405 struct ifnet *ifp; 1406 { 1407 struct txp_softc *sc = ifp->if_softc; 1408 struct txp_tx_ring *r = &sc->sc_txhir; 1409 struct txp_tx_desc *txd; 1410 int txdidx; 1411 struct txp_frag_desc *fxd; 1412 struct mbuf *m, *mnew; 1413 struct txp_swdesc *sd; 1414 u_int32_t firstprod, firstcnt, prod, cnt, i; 1415 struct m_tag *mtag; 1416 1417 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1418 return; 1419 1420 prod = r->r_prod; 1421 cnt = r->r_cnt; 1422 1423 while (1) { 1424 IFQ_POLL(&ifp->if_snd, m); 1425 if (m == NULL) 1426 break; 1427 mnew = NULL; 1428 1429 firstprod = prod; 1430 firstcnt = cnt; 1431 1432 sd = sc->sc_txd + prod; 1433 sd->sd_mbuf = m; 1434 1435 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1436 BUS_DMA_NOWAIT)) { 1437 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1438 if (mnew == NULL) 1439 goto oactive1; 1440 if (m->m_pkthdr.len > MHLEN) { 1441 MCLGET(mnew, M_DONTWAIT); 1442 if ((mnew->m_flags & M_EXT) == 0) { 1443 m_freem(mnew); 1444 goto oactive1; 1445 } 1446 } 1447 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1448 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1449 IFQ_DEQUEUE(&ifp->if_snd, m); 1450 m_freem(m); 1451 m = mnew; 1452 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1453 BUS_DMA_NOWAIT)) 1454 goto oactive1; 1455 } 1456 1457 if ((TX_ENTRIES - cnt) < 4) 1458 goto oactive; 1459 1460 txd = r->r_desc + prod; 1461 txdidx = prod; 1462 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1463 txd->tx_numdesc = 0; 1464 txd->tx_addrlo = 0; 1465 txd->tx_addrhi = 0; 1466 txd->tx_totlen = m->m_pkthdr.len; 1467 txd->tx_pflags = 0; 1468 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1469 1470 if (++prod == TX_ENTRIES) 1471 prod = 0; 1472 1473 if (++cnt >= (TX_ENTRIES - 4)) 1474 goto oactive; 1475 1476 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1477 txd->tx_pflags = TX_PFLAGS_VLAN | 1478 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1479 1480 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1481 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1482 #ifdef TRY_TX_TCP_CSUM 1483 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1484 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1485 #endif 1486 #ifdef TRY_TX_UDP_CSUM 1487 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1488 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1489 #endif 1490 1491 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1492 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1493 1494 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1495 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1496 if (++cnt >= (TX_ENTRIES - 4)) { 1497 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1498 0, sd->sd_map->dm_mapsize, 1499 BUS_DMASYNC_POSTWRITE); 1500 goto oactive; 1501 } 1502 1503 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1504 FRAG_FLAGS_VALID; 1505 fxd->frag_rsvd1 = 0; 1506 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1507 fxd->frag_addrlo = 1508 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1509 0xffffffff; 1510 fxd->frag_addrhi = 1511 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1512 32; 1513 fxd->frag_rsvd2 = 0; 1514 1515 bus_dmamap_sync(sc->sc_dmat, 1516 sc->sc_txhiring_dma.dma_map, 1517 prod * sizeof(struct txp_frag_desc), 1518 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1519 1520 if (++prod == TX_ENTRIES) { 1521 fxd = (struct txp_frag_desc *)r->r_desc; 1522 prod = 0; 1523 } else 1524 fxd++; 1525 1526 } 1527 1528 /* 1529 * if mnew isn't NULL, we already dequeued and copied 1530 * the packet. 1531 */ 1532 if (mnew == NULL) 1533 IFQ_DEQUEUE(&ifp->if_snd, m); 1534 1535 ifp->if_timer = 5; 1536 1537 #if NBPFILTER > 0 1538 if (ifp->if_bpf) 1539 bpf_mtap(ifp->if_bpf, m); 1540 #endif 1541 1542 txd->tx_flags |= TX_FLAGS_VALID; 1543 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1544 txdidx * sizeof(struct txp_tx_desc), 1545 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1546 1547 #if 0 1548 { 1549 struct mbuf *mx; 1550 int i; 1551 1552 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1553 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1554 txd->tx_pflags); 1555 for (mx = m; mx != NULL; mx = mx->m_next) { 1556 for (i = 0; i < mx->m_len; i++) { 1557 printf(":%02x", 1558 (u_int8_t)m->m_data[i]); 1559 } 1560 } 1561 printf("\n"); 1562 } 1563 #endif 1564 1565 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1566 } 1567 1568 r->r_prod = prod; 1569 r->r_cnt = cnt; 1570 return; 1571 1572 oactive: 1573 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1574 oactive1: 1575 ifp->if_flags |= IFF_OACTIVE; 1576 r->r_prod = firstprod; 1577 r->r_cnt = firstcnt; 1578 } 1579 1580 /* 1581 * Handle simple commands sent to the typhoon 1582 */ 1583 int 1584 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1585 struct txp_softc *sc; 1586 u_int16_t id, in1, *out1; 1587 u_int32_t in2, in3, *out2, *out3; 1588 int wait; 1589 { 1590 struct txp_rsp_desc *rsp = NULL; 1591 1592 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1593 return (-1); 1594 1595 if (!wait) 1596 return (0); 1597 1598 if (out1 != NULL) 1599 *out1 = le16toh(rsp->rsp_par1); 1600 if (out2 != NULL) 1601 *out2 = le32toh(rsp->rsp_par2); 1602 if (out3 != NULL) 1603 *out3 = le32toh(rsp->rsp_par3); 1604 free(rsp, M_DEVBUF); 1605 return (0); 1606 } 1607 1608 int 1609 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1610 struct txp_softc *sc; 1611 u_int16_t id, in1; 1612 u_int32_t in2, in3; 1613 struct txp_ext_desc *in_extp; 1614 u_int8_t in_extn; 1615 struct txp_rsp_desc **rspp; 1616 int wait; 1617 { 1618 struct txp_hostvar *hv = sc->sc_hostvar; 1619 struct txp_cmd_desc *cmd; 1620 struct txp_ext_desc *ext; 1621 u_int32_t idx, i; 1622 u_int16_t seq; 1623 1624 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1625 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1626 return (-1); 1627 } 1628 1629 idx = sc->sc_cmdring.lastwrite; 1630 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1631 bzero(cmd, sizeof(*cmd)); 1632 1633 cmd->cmd_numdesc = in_extn; 1634 seq = sc->sc_seq++; 1635 cmd->cmd_seq = htole16(seq); 1636 cmd->cmd_id = htole16(id); 1637 cmd->cmd_par1 = htole16(in1); 1638 cmd->cmd_par2 = htole32(in2); 1639 cmd->cmd_par3 = htole32(in3); 1640 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1641 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1642 1643 idx += sizeof(struct txp_cmd_desc); 1644 if (idx == sc->sc_cmdring.size) 1645 idx = 0; 1646 1647 for (i = 0; i < in_extn; i++) { 1648 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1649 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1650 in_extp++; 1651 idx += sizeof(struct txp_cmd_desc); 1652 if (idx == sc->sc_cmdring.size) 1653 idx = 0; 1654 } 1655 1656 sc->sc_cmdring.lastwrite = idx; 1657 1658 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1659 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1660 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1661 1662 if (!wait) 1663 return (0); 1664 1665 for (i = 0; i < 10000; i++) { 1666 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1667 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1668 idx = le32toh(hv->hv_resp_read_idx); 1669 if (idx != le32toh(hv->hv_resp_write_idx)) { 1670 *rspp = NULL; 1671 if (txp_response(sc, idx, id, seq, rspp)) 1672 return (-1); 1673 if (*rspp != NULL) 1674 break; 1675 } 1676 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1677 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1678 DELAY(50); 1679 } 1680 if (i == 1000 || (*rspp) == NULL) { 1681 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1682 return (-1); 1683 } 1684 1685 return (0); 1686 } 1687 1688 int 1689 txp_response(sc, ridx, id, seq, rspp) 1690 struct txp_softc *sc; 1691 u_int32_t ridx; 1692 u_int16_t id; 1693 u_int16_t seq; 1694 struct txp_rsp_desc **rspp; 1695 { 1696 struct txp_hostvar *hv = sc->sc_hostvar; 1697 struct txp_rsp_desc *rsp; 1698 1699 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1700 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1701 1702 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1703 *rspp = (struct txp_rsp_desc *)malloc( 1704 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1705 M_DEVBUF, M_NOWAIT); 1706 if ((*rspp) == NULL) 1707 return (-1); 1708 txp_rsp_fixup(sc, rsp, *rspp); 1709 return (0); 1710 } 1711 1712 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1713 printf("%s: response error: id 0x%x\n", 1714 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1715 txp_rsp_fixup(sc, rsp, NULL); 1716 ridx = le32toh(hv->hv_resp_read_idx); 1717 continue; 1718 } 1719 1720 switch (le16toh(rsp->rsp_id)) { 1721 case TXP_CMD_CYCLE_STATISTICS: 1722 case TXP_CMD_MEDIA_STATUS_READ: 1723 break; 1724 case TXP_CMD_HELLO_RESPONSE: 1725 printf("%s: hello\n", TXP_DEVNAME(sc)); 1726 break; 1727 default: 1728 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1729 le16toh(rsp->rsp_id)); 1730 } 1731 1732 txp_rsp_fixup(sc, rsp, NULL); 1733 ridx = le32toh(hv->hv_resp_read_idx); 1734 hv->hv_resp_read_idx = le32toh(ridx); 1735 } 1736 1737 return (0); 1738 } 1739 1740 void 1741 txp_rsp_fixup(sc, rsp, dst) 1742 struct txp_softc *sc; 1743 struct txp_rsp_desc *rsp, *dst; 1744 { 1745 struct txp_rsp_desc *src = rsp; 1746 struct txp_hostvar *hv = sc->sc_hostvar; 1747 u_int32_t i, ridx; 1748 1749 ridx = le32toh(hv->hv_resp_read_idx); 1750 1751 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1752 if (dst != NULL) 1753 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1754 ridx += sizeof(struct txp_rsp_desc); 1755 if (ridx == sc->sc_rspring.size) { 1756 src = sc->sc_rspring.base; 1757 ridx = 0; 1758 } else 1759 src++; 1760 sc->sc_rspring.lastwrite = ridx; 1761 hv->hv_resp_read_idx = htole32(ridx); 1762 } 1763 1764 hv->hv_resp_read_idx = htole32(ridx); 1765 } 1766 1767 int 1768 txp_cmd_desc_numfree(sc) 1769 struct txp_softc *sc; 1770 { 1771 struct txp_hostvar *hv = sc->sc_hostvar; 1772 struct txp_boot_record *br = sc->sc_boot; 1773 u_int32_t widx, ridx, nfree; 1774 1775 widx = sc->sc_cmdring.lastwrite; 1776 ridx = le32toh(hv->hv_cmd_read_idx); 1777 1778 if (widx == ridx) { 1779 /* Ring is completely free */ 1780 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1781 } else { 1782 if (widx > ridx) 1783 nfree = le32toh(br->br_cmd_siz) - 1784 (widx - ridx + sizeof(struct txp_cmd_desc)); 1785 else 1786 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1787 } 1788 1789 return (nfree / sizeof(struct txp_cmd_desc)); 1790 } 1791 1792 void 1793 txp_stop(sc) 1794 struct txp_softc *sc; 1795 { 1796 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1797 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1798 1799 if (callout_pending(&sc->sc_tick)) 1800 callout_stop(&sc->sc_tick); 1801 } 1802 1803 void 1804 txp_watchdog(struct ifnet *ifp) 1805 { 1806 } 1807 1808 int 1809 txp_ifmedia_upd(ifp) 1810 struct ifnet *ifp; 1811 { 1812 struct txp_softc *sc = ifp->if_softc; 1813 struct ifmedia *ifm = &sc->sc_ifmedia; 1814 u_int16_t new_xcvr; 1815 1816 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1817 return (EINVAL); 1818 1819 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1820 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1821 new_xcvr = TXP_XCVR_10_FDX; 1822 else 1823 new_xcvr = TXP_XCVR_10_HDX; 1824 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1825 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1826 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1827 new_xcvr = TXP_XCVR_100_FDX; 1828 else 1829 new_xcvr = TXP_XCVR_100_HDX; 1830 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1831 new_xcvr = TXP_XCVR_AUTO; 1832 } else 1833 return (EINVAL); 1834 1835 /* nothing to do */ 1836 if (sc->sc_xcvr == new_xcvr) 1837 return (0); 1838 1839 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1840 NULL, NULL, NULL, 0); 1841 sc->sc_xcvr = new_xcvr; 1842 1843 return (0); 1844 } 1845 1846 void 1847 txp_ifmedia_sts(ifp, ifmr) 1848 struct ifnet *ifp; 1849 struct ifmediareq *ifmr; 1850 { 1851 struct txp_softc *sc = ifp->if_softc; 1852 struct ifmedia *ifm = &sc->sc_ifmedia; 1853 u_int16_t bmsr, bmcr, anlpar; 1854 1855 ifmr->ifm_status = IFM_AVALID; 1856 ifmr->ifm_active = IFM_ETHER; 1857 1858 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1859 &bmsr, NULL, NULL, 1)) 1860 goto bail; 1861 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1862 &bmsr, NULL, NULL, 1)) 1863 goto bail; 1864 1865 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1866 &bmcr, NULL, NULL, 1)) 1867 goto bail; 1868 1869 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1870 &anlpar, NULL, NULL, 1)) 1871 goto bail; 1872 1873 if (bmsr & BMSR_LINK) 1874 ifmr->ifm_status |= IFM_ACTIVE; 1875 1876 if (bmcr & BMCR_ISO) { 1877 ifmr->ifm_active |= IFM_NONE; 1878 ifmr->ifm_status = 0; 1879 return; 1880 } 1881 1882 if (bmcr & BMCR_LOOP) 1883 ifmr->ifm_active |= IFM_LOOP; 1884 1885 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1886 if ((bmsr & BMSR_ACOMP) == 0) { 1887 ifmr->ifm_active |= IFM_NONE; 1888 return; 1889 } 1890 1891 if (anlpar & ANLPAR_T4) 1892 ifmr->ifm_active |= IFM_100_T4; 1893 else if (anlpar & ANLPAR_TX_FD) 1894 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1895 else if (anlpar & ANLPAR_TX) 1896 ifmr->ifm_active |= IFM_100_TX; 1897 else if (anlpar & ANLPAR_10_FD) 1898 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1899 else if (anlpar & ANLPAR_10) 1900 ifmr->ifm_active |= IFM_10_T; 1901 else 1902 ifmr->ifm_active |= IFM_NONE; 1903 } else 1904 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1905 return; 1906 1907 bail: 1908 ifmr->ifm_active |= IFM_NONE; 1909 ifmr->ifm_status &= ~IFM_AVALID; 1910 } 1911 1912 void 1913 txp_show_descriptor(d) 1914 void *d; 1915 { 1916 struct txp_cmd_desc *cmd = d; 1917 struct txp_rsp_desc *rsp = d; 1918 struct txp_tx_desc *txd = d; 1919 struct txp_frag_desc *frgd = d; 1920 1921 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1922 case CMD_FLAGS_TYPE_CMD: 1923 /* command descriptor */ 1924 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1925 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1926 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1927 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1928 break; 1929 case CMD_FLAGS_TYPE_RESP: 1930 /* response descriptor */ 1931 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1932 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1933 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1934 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1935 break; 1936 case CMD_FLAGS_TYPE_DATA: 1937 /* data header (assuming tx for now) */ 1938 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1939 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1940 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1941 break; 1942 case CMD_FLAGS_TYPE_FRAG: 1943 /* fragment descriptor */ 1944 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1945 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1946 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1947 break; 1948 default: 1949 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1950 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1951 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1952 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1953 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1954 break; 1955 } 1956 } 1957 1958 void 1959 txp_set_filter(sc) 1960 struct txp_softc *sc; 1961 { 1962 struct ethercom *ac = &sc->sc_arpcom; 1963 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1964 u_int32_t crc, carry, hashbit, hash[2]; 1965 u_int16_t filter; 1966 u_int8_t octet; 1967 int i, j, mcnt = 0; 1968 struct ether_multi *enm; 1969 struct ether_multistep step; 1970 1971 if (ifp->if_flags & IFF_PROMISC) { 1972 filter = TXP_RXFILT_PROMISC; 1973 goto setit; 1974 } 1975 1976 again: 1977 filter = TXP_RXFILT_DIRECT; 1978 1979 if (ifp->if_flags & IFF_BROADCAST) 1980 filter |= TXP_RXFILT_BROADCAST; 1981 1982 if (ifp->if_flags & IFF_ALLMULTI) 1983 filter |= TXP_RXFILT_ALLMULTI; 1984 else { 1985 hash[0] = hash[1] = 0; 1986 1987 ETHER_FIRST_MULTI(step, ac, enm); 1988 while (enm != NULL) { 1989 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1990 /* 1991 * We must listen to a range of multicast 1992 * addresses. For now, just accept all 1993 * multicasts, rather than trying to set only 1994 * those filter bits needed to match the range. 1995 * (At this time, the only use of address 1996 * ranges is for IP multicast routing, for 1997 * which the range is big enough to require 1998 * all bits set.) 1999 */ 2000 ifp->if_flags |= IFF_ALLMULTI; 2001 goto again; 2002 } 2003 2004 mcnt++; 2005 crc = 0xffffffff; 2006 2007 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2008 octet = enm->enm_addrlo[i]; 2009 for (j = 0; j < 8; j++) { 2010 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2011 (octet & 1); 2012 crc <<= 1; 2013 octet >>= 1; 2014 if (carry) 2015 crc = (crc ^ TXP_POLYNOMIAL) | 2016 carry; 2017 } 2018 } 2019 hashbit = (u_int16_t)(crc & (64 - 1)); 2020 hash[hashbit / 32] |= (1 << hashbit % 32); 2021 ETHER_NEXT_MULTI(step, enm); 2022 } 2023 2024 if (mcnt > 0) { 2025 filter |= TXP_RXFILT_HASHMULTI; 2026 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2027 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2028 } 2029 } 2030 2031 setit: 2032 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2033 NULL, NULL, NULL, 1); 2034 } 2035 2036 void 2037 txp_capabilities(sc) 2038 struct txp_softc *sc; 2039 { 2040 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2041 struct txp_rsp_desc *rsp = NULL; 2042 struct txp_ext_desc *ext; 2043 2044 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2045 goto out; 2046 2047 if (rsp->rsp_numdesc != 1) 2048 goto out; 2049 ext = (struct txp_ext_desc *)(rsp + 1); 2050 2051 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2052 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2053 2054 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2055 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2056 sc->sc_tx_capability |= OFFLOAD_VLAN; 2057 sc->sc_rx_capability |= OFFLOAD_VLAN; 2058 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2059 } 2060 2061 #if 0 2062 /* not ready yet */ 2063 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2064 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2065 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2066 ifp->if_capabilities |= IFCAP_IPSEC; 2067 } 2068 #endif 2069 2070 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2071 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2072 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2073 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2074 } 2075 2076 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2077 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2078 #ifdef TRY_TX_TCP_CSUM 2079 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2080 ifp->if_capabilities |= 2081 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2082 #endif 2083 } 2084 2085 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2086 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2087 #ifdef TRY_TX_UDP_CSUM 2088 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2089 ifp->if_capabilities |= 2090 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2091 #endif 2092 } 2093 2094 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2095 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2096 goto out; 2097 2098 out: 2099 if (rsp != NULL) 2100 free(rsp, M_DEVBUF); 2101 } 2102
Indexes created Tue Sep 30 20:09:53 GMT 2025