if_txp.c revision 1.36.2.1
1 /* $NetBSD: if_txp.c,v 1.36.2.1 2010/04/30 14:43:38 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.36.2.1 2010/04/30 14:43:38 uebayasi Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #include <net/bpf.h> 66 67 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 68 #include <sys/bus.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <dev/pci/if_txpreg.h> 77 78 #include <dev/microcode/typhoon/3c990img.h> 79 80 /* 81 * These currently break the 3c990 firmware, hopefully will be resolved 82 * at some point. 83 */ 84 #undef TRY_TX_UDP_CSUM 85 #undef TRY_TX_TCP_CSUM 86 87 int txp_probe(device_t, cfdata_t, void *); 88 void txp_attach(device_t, device_t, void *); 89 int txp_intr(void *); 90 void txp_tick(void *); 91 bool txp_shutdown(device_t, int); 92 int txp_ioctl(struct ifnet *, u_long, void *); 93 void txp_start(struct ifnet *); 94 void txp_stop(struct txp_softc *); 95 void txp_init(struct txp_softc *); 96 void txp_watchdog(struct ifnet *); 97 98 int txp_chip_init(struct txp_softc *); 99 int txp_reset_adapter(struct txp_softc *); 100 int txp_download_fw(struct txp_softc *); 101 int txp_download_fw_wait(struct txp_softc *); 102 int txp_download_fw_section(struct txp_softc *, 103 const struct txp_fw_section_header *, int); 104 int txp_alloc_rings(struct txp_softc *); 105 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 106 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 107 void txp_set_filter(struct txp_softc *); 108 109 int txp_cmd_desc_numfree(struct txp_softc *); 110 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 111 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 112 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 113 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 114 struct txp_rsp_desc **, int); 115 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 116 struct txp_rsp_desc **); 117 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 118 struct txp_rsp_desc *); 119 void txp_capabilities(struct txp_softc *); 120 121 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 122 int txp_ifmedia_upd(struct ifnet *); 123 void txp_show_descriptor(void *); 124 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 125 struct txp_dma_alloc *); 126 void txp_rxbuf_reclaim(struct txp_softc *); 127 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 128 struct txp_dma_alloc *); 129 130 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 131 NULL, NULL); 132 133 const struct txp_pci_match { 134 int vid, did, flags; 135 } txp_devices[] = { 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 144 }; 145 146 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 147 148 static const struct { 149 u_int16_t mask, value; 150 int flags; 151 } txp_subsysinfo[] = { 152 {0xf000, 0x2000, TXP_SERVERVERSION}, 153 {0x0100, 0x0100, TXP_FIBER}, 154 #if 0 /* information from 3com header, unused */ 155 {0x0010, 0x0010, /* secured firmware */}, 156 {0x0003, 0x0000, /* variable DES */}, 157 {0x0003, 0x0001, /* single DES - "95" */}, 158 {0x0003, 0x0002, /* triple DES - "97" */}, 159 #endif 160 }; 161 162 static const struct txp_pci_match * 163 txp_pcilookup(pcireg_t id) 164 { 165 int i; 166 167 for (i = 0; i < __arraycount(txp_devices); i++) 168 if (PCI_VENDOR(id) == txp_devices[i].vid && 169 PCI_PRODUCT(id) == txp_devices[i].did) 170 return &txp_devices[i]; 171 return (0); 172 } 173 174 int 175 txp_probe(device_t parent, cfdata_t match, void *aux) 176 { 177 struct pci_attach_args *pa = aux; 178 179 if (txp_pcilookup(pa->pa_id)) 180 return (1); 181 return (0); 182 } 183 184 void 185 txp_attach(device_t parent, device_t self, void *aux) 186 { 187 struct txp_softc *sc = device_private(self); 188 struct pci_attach_args *pa = aux; 189 pci_chipset_tag_t pc = pa->pa_pc; 190 pci_intr_handle_t ih; 191 const char *intrstr = NULL; 192 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 193 u_int32_t command; 194 u_int16_t p1; 195 u_int32_t p2; 196 u_char enaddr[6]; 197 const struct txp_pci_match *match; 198 u_int16_t subsys; 199 int i, flags; 200 char devinfo[256]; 201 202 sc->sc_cold = 1; 203 204 match = txp_pcilookup(pa->pa_id); 205 flags = match->flags; 206 if (match->flags & TXP_USESUBSYSTEM) { 207 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 208 PCI_SUBSYS_ID_REG)); 209 for (i = 0; 210 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 211 i++) 212 if ((subsys & txp_subsysinfo[i].mask) == 213 txp_subsysinfo[i].value) 214 flags |= txp_subsysinfo[i].flags; 215 } 216 sc->sc_flags = flags; 217 218 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 219 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 220 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 221 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, device_xname(&sc->sc_dev)); 222 223 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 224 225 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 226 printf(": failed to enable bus mastering\n"); 227 return; 228 } 229 230 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 231 printf(": failed to enable memory mapping\n"); 232 return; 233 } 234 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 235 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 236 printf(": can't map mem space %d\n", 0); 237 return; 238 } 239 240 sc->sc_dmat = pa->pa_dmat; 241 242 /* 243 * Allocate our interrupt. 244 */ 245 if (pci_intr_map(pa, &ih)) { 246 printf(": couldn't map interrupt\n"); 247 return; 248 } 249 250 intrstr = pci_intr_string(pc, ih); 251 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 252 if (sc->sc_ih == NULL) { 253 printf(": couldn't establish interrupt"); 254 if (intrstr != NULL) 255 printf(" at %s", intrstr); 256 printf("\n"); 257 return; 258 } 259 printf(": interrupting at %s\n", intrstr); 260 261 if (txp_chip_init(sc)) 262 goto cleanupintr; 263 264 if (txp_download_fw(sc)) 265 goto cleanupintr; 266 267 if (txp_alloc_rings(sc)) 268 goto cleanupintr; 269 270 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 271 NULL, NULL, NULL, 1)) 272 goto cleanupintr; 273 274 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 275 &p1, &p2, NULL, 1)) 276 goto cleanupintr; 277 278 txp_set_filter(sc); 279 280 p1 = htole16(p1); 281 enaddr[0] = ((u_int8_t *)&p1)[1]; 282 enaddr[1] = ((u_int8_t *)&p1)[0]; 283 p2 = htole32(p2); 284 enaddr[2] = ((u_int8_t *)&p2)[3]; 285 enaddr[3] = ((u_int8_t *)&p2)[2]; 286 enaddr[4] = ((u_int8_t *)&p2)[1]; 287 enaddr[5] = ((u_int8_t *)&p2)[0]; 288 289 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 290 ether_sprintf(enaddr)); 291 sc->sc_cold = 0; 292 293 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 294 if (flags & TXP_FIBER) { 295 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 296 0, NULL); 297 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 298 0, NULL); 299 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 300 0, NULL); 301 } else { 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 303 0, NULL); 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 305 0, NULL); 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 313 0, NULL); 314 } 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 316 317 sc->sc_xcvr = TXP_XCVR_AUTO; 318 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 319 NULL, NULL, NULL, 0); 320 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 321 322 ifp->if_softc = sc; 323 ifp->if_mtu = ETHERMTU; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_ioctl = txp_ioctl; 326 ifp->if_start = txp_start; 327 ifp->if_watchdog = txp_watchdog; 328 ifp->if_baudrate = 10000000; 329 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 330 IFQ_SET_READY(&ifp->if_snd); 331 ifp->if_capabilities = 0; 332 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 333 334 txp_capabilities(sc); 335 336 callout_init(&sc->sc_tick, 0); 337 callout_setfunc(&sc->sc_tick, txp_tick, sc); 338 339 /* 340 * Attach us everywhere 341 */ 342 if_attach(ifp); 343 ether_ifattach(ifp, enaddr); 344 345 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 346 pmf_class_network_register(self, ifp); 347 else 348 aprint_error_dev(self, "couldn't establish power handler\n"); 349 350 return; 351 352 cleanupintr: 353 pci_intr_disestablish(pc,sc->sc_ih); 354 355 return; 356 357 } 358 359 int 360 txp_chip_init(struct txp_softc *sc) 361 { 362 /* disable interrupts */ 363 WRITE_REG(sc, TXP_IER, 0); 364 WRITE_REG(sc, TXP_IMR, 365 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 366 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 367 TXP_INT_LATCH); 368 369 /* ack all interrupts */ 370 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 371 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 372 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 373 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 374 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 375 376 if (txp_reset_adapter(sc)) 377 return (-1); 378 379 /* disable interrupts */ 380 WRITE_REG(sc, TXP_IER, 0); 381 WRITE_REG(sc, TXP_IMR, 382 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 383 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 384 TXP_INT_LATCH); 385 386 /* ack all interrupts */ 387 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 388 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 389 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 390 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 391 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 392 393 return (0); 394 } 395 396 int 397 txp_reset_adapter(struct txp_softc *sc) 398 { 399 u_int32_t r; 400 int i; 401 402 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 403 DELAY(1000); 404 WRITE_REG(sc, TXP_SRR, 0); 405 406 /* Should wait max 6 seconds */ 407 for (i = 0; i < 6000; i++) { 408 r = READ_REG(sc, TXP_A2H_0); 409 if (r == STAT_WAITING_FOR_HOST_REQUEST) 410 break; 411 DELAY(1000); 412 } 413 414 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 415 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 416 return (-1); 417 } 418 419 return (0); 420 } 421 422 int 423 txp_download_fw(struct txp_softc *sc) 424 { 425 const struct txp_fw_file_header *fileheader; 426 const struct txp_fw_section_header *secthead; 427 int sect; 428 u_int32_t r, i, ier, imr; 429 430 ier = READ_REG(sc, TXP_IER); 431 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 432 433 imr = READ_REG(sc, TXP_IMR); 434 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 435 436 for (i = 0; i < 10000; i++) { 437 r = READ_REG(sc, TXP_A2H_0); 438 if (r == STAT_WAITING_FOR_HOST_REQUEST) 439 break; 440 DELAY(50); 441 } 442 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 443 printf(": not waiting for host request\n"); 444 return (-1); 445 } 446 447 /* Ack the status */ 448 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 449 450 fileheader = (const struct txp_fw_file_header *)tc990image; 451 if (memcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 452 printf(": fw invalid magic\n"); 453 return (-1); 454 } 455 456 /* Tell boot firmware to get ready for image */ 457 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 458 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 459 460 if (txp_download_fw_wait(sc)) { 461 printf("%s: fw wait failed, initial\n", device_xname(&sc->sc_dev)); 462 return (-1); 463 } 464 465 secthead = (const struct txp_fw_section_header *) 466 (((const u_int8_t *)tc990image) + 467 sizeof(struct txp_fw_file_header)); 468 469 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 470 if (txp_download_fw_section(sc, secthead, sect)) 471 return (-1); 472 secthead = (const struct txp_fw_section_header *) 473 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 474 sizeof(*secthead)); 475 } 476 477 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 478 479 for (i = 0; i < 10000; i++) { 480 r = READ_REG(sc, TXP_A2H_0); 481 if (r == STAT_WAITING_FOR_BOOT) 482 break; 483 DELAY(50); 484 } 485 if (r != STAT_WAITING_FOR_BOOT) { 486 printf(": not waiting for boot\n"); 487 return (-1); 488 } 489 490 WRITE_REG(sc, TXP_IER, ier); 491 WRITE_REG(sc, TXP_IMR, imr); 492 493 return (0); 494 } 495 496 int 497 txp_download_fw_wait(struct txp_softc *sc) 498 { 499 u_int32_t i, r; 500 501 for (i = 0; i < 10000; i++) { 502 r = READ_REG(sc, TXP_ISR); 503 if (r & TXP_INT_A2H_0) 504 break; 505 DELAY(50); 506 } 507 508 if (!(r & TXP_INT_A2H_0)) { 509 printf(": fw wait failed comm0\n"); 510 return (-1); 511 } 512 513 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 514 515 r = READ_REG(sc, TXP_A2H_0); 516 if (r != STAT_WAITING_FOR_SEGMENT) { 517 printf(": fw not waiting for segment\n"); 518 return (-1); 519 } 520 return (0); 521 } 522 523 int 524 txp_download_fw_section(struct txp_softc *sc, const struct txp_fw_section_header *sect, int sectnum) 525 { 526 struct txp_dma_alloc dma; 527 int rseg, err = 0; 528 struct mbuf m; 529 #ifdef INET 530 u_int16_t csum; 531 #endif 532 533 /* Skip zero length sections */ 534 if (sect->nbytes == 0) 535 return (0); 536 537 /* Make sure we aren't past the end of the image */ 538 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 539 if (rseg >= sizeof(tc990image)) { 540 printf(": fw invalid section address, section %d\n", sectnum); 541 return (-1); 542 } 543 544 /* Make sure this section doesn't go past the end */ 545 rseg += le32toh(sect->nbytes); 546 if (rseg >= sizeof(tc990image)) { 547 printf(": fw truncated section %d\n", sectnum); 548 return (-1); 549 } 550 551 /* map a buffer, copy segment to it, get physaddr */ 552 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 553 printf(": fw dma malloc failed, section %d\n", sectnum); 554 return (-1); 555 } 556 557 memcpy(dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 558 le32toh(sect->nbytes)); 559 560 /* 561 * dummy up mbuf and verify section checksum 562 */ 563 m.m_type = MT_DATA; 564 m.m_next = m.m_nextpkt = NULL; 565 m.m_len = le32toh(sect->nbytes); 566 m.m_data = dma.dma_vaddr; 567 m.m_flags = 0; 568 #ifdef INET 569 csum = in_cksum(&m, le32toh(sect->nbytes)); 570 if (csum != sect->cksum) { 571 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 572 sectnum, sect->cksum, csum); 573 txp_dma_free(sc, &dma); 574 return -1; 575 } 576 #endif 577 578 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 579 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 580 581 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 582 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 583 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 584 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 585 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 586 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 587 588 if (txp_download_fw_wait(sc)) { 589 printf("%s: fw wait failed, section %d\n", 590 device_xname(&sc->sc_dev), sectnum); 591 err = -1; 592 } 593 594 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 595 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 596 597 txp_dma_free(sc, &dma); 598 return (err); 599 } 600 601 int 602 txp_intr(void *vsc) 603 { 604 struct txp_softc *sc = vsc; 605 struct txp_hostvar *hv = sc->sc_hostvar; 606 u_int32_t isr; 607 int claimed = 0; 608 609 /* mask all interrupts */ 610 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 611 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 612 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 613 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 614 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 615 616 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 617 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 618 619 isr = READ_REG(sc, TXP_ISR); 620 while (isr) { 621 claimed = 1; 622 WRITE_REG(sc, TXP_ISR, isr); 623 624 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 625 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 626 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 627 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 628 629 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 630 txp_rxbuf_reclaim(sc); 631 632 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 633 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 634 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 635 636 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 637 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 638 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 639 640 isr = READ_REG(sc, TXP_ISR); 641 } 642 643 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 644 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 645 646 /* unmask all interrupts */ 647 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 648 649 txp_start(&sc->sc_arpcom.ec_if); 650 651 return (claimed); 652 } 653 654 void 655 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, struct txp_dma_alloc *dma) 656 { 657 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 658 struct txp_rx_desc *rxd; 659 struct mbuf *m; 660 struct txp_swdesc *sd; 661 u_int32_t roff, woff; 662 int sumflags = 0; 663 int idx; 664 665 roff = le32toh(*r->r_roff); 666 woff = le32toh(*r->r_woff); 667 idx = roff / sizeof(struct txp_rx_desc); 668 rxd = r->r_desc + idx; 669 670 while (roff != woff) { 671 672 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 673 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 674 BUS_DMASYNC_POSTREAD); 675 676 if (rxd->rx_flags & RX_FLAGS_ERROR) { 677 printf("%s: error 0x%x\n", device_xname(&sc->sc_dev), 678 le32toh(rxd->rx_stat)); 679 ifp->if_ierrors++; 680 goto next; 681 } 682 683 /* retrieve stashed pointer */ 684 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 685 686 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 687 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 688 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 689 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 690 m = sd->sd_mbuf; 691 free(sd, M_DEVBUF); 692 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 693 694 #ifdef __STRICT_ALIGNMENT 695 { 696 /* 697 * XXX Nice chip, except it won't accept "off by 2" 698 * buffers, so we're force to copy. Supposedly 699 * this will be fixed in a newer firmware rev 700 * and this will be temporary. 701 */ 702 struct mbuf *mnew; 703 704 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 705 if (mnew == NULL) { 706 m_freem(m); 707 goto next; 708 } 709 if (m->m_len > (MHLEN - 2)) { 710 MCLGET(mnew, M_DONTWAIT); 711 if (!(mnew->m_flags & M_EXT)) { 712 m_freem(mnew); 713 m_freem(m); 714 goto next; 715 } 716 } 717 mnew->m_pkthdr.rcvif = ifp; 718 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 719 mnew->m_data += 2; 720 memcpy(mnew->m_data, m->m_data, m->m_len); 721 m_freem(m); 722 m = mnew; 723 } 724 #endif 725 726 /* 727 * Handle BPF listeners. Let the BPF user see the packet. 728 */ 729 bpf_mtap(ifp, m); 730 731 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 732 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 733 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 734 sumflags |= M_CSUM_IPv4; 735 736 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 737 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 738 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 739 sumflags |= M_CSUM_TCPv4; 740 741 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 742 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 743 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 744 sumflags |= M_CSUM_UDPv4; 745 746 m->m_pkthdr.csum_flags = sumflags; 747 748 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 749 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 750 continue); 751 } 752 753 (*ifp->if_input)(ifp, m); 754 755 next: 756 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 757 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 758 BUS_DMASYNC_PREREAD); 759 760 roff += sizeof(struct txp_rx_desc); 761 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 762 idx = 0; 763 roff = 0; 764 rxd = r->r_desc; 765 } else { 766 idx++; 767 rxd++; 768 } 769 woff = le32toh(*r->r_woff); 770 } 771 772 *r->r_roff = htole32(woff); 773 } 774 775 void 776 txp_rxbuf_reclaim(struct txp_softc *sc) 777 { 778 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 779 struct txp_hostvar *hv = sc->sc_hostvar; 780 struct txp_rxbuf_desc *rbd; 781 struct txp_swdesc *sd; 782 u_int32_t i, end; 783 784 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 785 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 786 787 if (++i == RXBUF_ENTRIES) 788 i = 0; 789 790 rbd = sc->sc_rxbufs + i; 791 792 while (i != end) { 793 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 794 M_DEVBUF, M_NOWAIT); 795 if (sd == NULL) 796 break; 797 798 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 799 if (sd->sd_mbuf == NULL) 800 goto err_sd; 801 802 MCLGET(sd->sd_mbuf, M_DONTWAIT); 803 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 804 goto err_mbuf; 805 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 806 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 807 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 808 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 809 goto err_mbuf; 810 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 811 BUS_DMA_NOWAIT)) { 812 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 813 goto err_mbuf; 814 } 815 816 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 817 i * sizeof(struct txp_rxbuf_desc), 818 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 819 820 /* stash away pointer */ 821 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 822 823 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 824 & 0xffffffff; 825 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 826 >> 32; 827 828 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 829 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 830 831 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 832 i * sizeof(struct txp_rxbuf_desc), 833 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 834 835 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 836 837 if (++i == RXBUF_ENTRIES) { 838 i = 0; 839 rbd = sc->sc_rxbufs; 840 } else 841 rbd++; 842 } 843 return; 844 845 err_mbuf: 846 m_freem(sd->sd_mbuf); 847 err_sd: 848 free(sd, M_DEVBUF); 849 } 850 851 /* 852 * Reclaim mbufs and entries from a transmit ring. 853 */ 854 void 855 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, struct txp_dma_alloc *dma) 856 { 857 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 858 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 859 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 860 struct txp_tx_desc *txd = r->r_desc + cons; 861 struct txp_swdesc *sd = sc->sc_txd + cons; 862 struct mbuf *m; 863 864 while (cons != idx) { 865 if (cnt == 0) 866 break; 867 868 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 869 cons * sizeof(struct txp_tx_desc), 870 sizeof(struct txp_tx_desc), 871 BUS_DMASYNC_POSTWRITE); 872 873 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 874 TX_FLAGS_TYPE_DATA) { 875 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 876 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 877 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 878 m = sd->sd_mbuf; 879 if (m != NULL) { 880 m_freem(m); 881 txd->tx_addrlo = 0; 882 txd->tx_addrhi = 0; 883 ifp->if_opackets++; 884 } 885 } 886 ifp->if_flags &= ~IFF_OACTIVE; 887 888 if (++cons == TX_ENTRIES) { 889 txd = r->r_desc; 890 cons = 0; 891 sd = sc->sc_txd; 892 } else { 893 txd++; 894 sd++; 895 } 896 897 cnt--; 898 } 899 900 r->r_cons = cons; 901 r->r_cnt = cnt; 902 if (cnt == 0) 903 ifp->if_timer = 0; 904 } 905 906 bool 907 txp_shutdown(device_t self, int howto) 908 { 909 struct txp_softc *sc; 910 911 sc = device_private(self); 912 913 /* mask all interrupts */ 914 WRITE_REG(sc, TXP_IMR, 915 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 916 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 917 TXP_INT_LATCH); 918 919 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 920 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 921 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 922 923 return true; 924 } 925 926 int 927 txp_alloc_rings(struct txp_softc *sc) 928 { 929 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 930 struct txp_boot_record *boot; 931 struct txp_swdesc *sd; 932 u_int32_t r; 933 int i, j, nb; 934 935 /* boot record */ 936 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 937 BUS_DMA_COHERENT)) { 938 printf(": can't allocate boot record\n"); 939 return (-1); 940 } 941 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 942 memset(boot, 0, sizeof(*boot)); 943 sc->sc_boot = boot; 944 945 /* host variables */ 946 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 947 BUS_DMA_COHERENT)) { 948 printf(": can't allocate host ring\n"); 949 goto bail_boot; 950 } 951 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 952 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 953 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 954 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 955 956 /* high priority tx ring */ 957 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 958 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 959 printf(": can't allocate high tx ring\n"); 960 goto bail_host; 961 } 962 memset(sc->sc_txhiring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 963 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 964 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 965 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 966 sc->sc_txhir.r_reg = TXP_H2A_1; 967 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 968 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 969 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 970 for (i = 0; i < TX_ENTRIES; i++) { 971 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 972 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 973 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 974 for (j = 0; j < i; j++) { 975 bus_dmamap_destroy(sc->sc_dmat, 976 sc->sc_txd[j].sd_map); 977 sc->sc_txd[j].sd_map = NULL; 978 } 979 goto bail_txhiring; 980 } 981 } 982 983 /* low priority tx ring */ 984 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 985 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 986 printf(": can't allocate low tx ring\n"); 987 goto bail_txhiring; 988 } 989 memset(sc->sc_txloring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 990 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 991 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 992 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 993 sc->sc_txlor.r_reg = TXP_H2A_3; 994 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 995 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 996 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 997 998 /* high priority rx ring */ 999 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1000 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1001 printf(": can't allocate high rx ring\n"); 1002 goto bail_txloring; 1003 } 1004 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1005 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1006 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1007 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1008 sc->sc_rxhir.r_desc = 1009 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1010 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1011 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1012 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1013 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1014 1015 /* low priority ring */ 1016 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1017 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1018 printf(": can't allocate low rx ring\n"); 1019 goto bail_rxhiring; 1020 } 1021 memset(sc->sc_rxloring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1022 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1023 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1024 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1025 sc->sc_rxlor.r_desc = 1026 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1027 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1028 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1029 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1030 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1031 1032 /* command ring */ 1033 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1034 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1035 printf(": can't allocate command ring\n"); 1036 goto bail_rxloring; 1037 } 1038 memset(sc->sc_cmdring_dma.dma_vaddr, 0, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1039 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1040 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1041 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1042 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1043 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1044 sc->sc_cmdring.lastwrite = 0; 1045 1046 /* response ring */ 1047 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1048 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1049 printf(": can't allocate response ring\n"); 1050 goto bail_cmdring; 1051 } 1052 memset(sc->sc_rspring_dma.dma_vaddr, 0, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1053 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1054 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1055 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1056 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1057 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1058 sc->sc_rspring.lastwrite = 0; 1059 1060 /* receive buffer ring */ 1061 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1062 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1063 printf(": can't allocate rx buffer ring\n"); 1064 goto bail_rspring; 1065 } 1066 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1067 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1068 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1069 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1070 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1071 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1072 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1073 M_DEVBUF, M_NOWAIT); 1074 /* stash away pointer */ 1075 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, sizeof(sd)); 1076 if (sd == NULL) 1077 break; 1078 1079 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1080 if (sd->sd_mbuf == NULL) { 1081 goto bail_rxbufring; 1082 } 1083 1084 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1085 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1086 goto bail_rxbufring; 1087 } 1088 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1089 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1090 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1091 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1092 goto bail_rxbufring; 1093 } 1094 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1095 BUS_DMA_NOWAIT)) { 1096 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1097 goto bail_rxbufring; 1098 } 1099 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1100 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1101 1102 1103 sc->sc_rxbufs[nb].rb_paddrlo = 1104 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1105 sc->sc_rxbufs[nb].rb_paddrhi = 1106 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1107 } 1108 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1109 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1110 BUS_DMASYNC_PREWRITE); 1111 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1112 sizeof(struct txp_rxbuf_desc)); 1113 1114 /* zero dma */ 1115 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1116 BUS_DMA_COHERENT)) { 1117 printf(": can't allocate response ring\n"); 1118 goto bail_rxbufring; 1119 } 1120 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1121 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1122 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1123 1124 /* See if it's waiting for boot, and try to boot it */ 1125 for (i = 0; i < 10000; i++) { 1126 r = READ_REG(sc, TXP_A2H_0); 1127 if (r == STAT_WAITING_FOR_BOOT) 1128 break; 1129 DELAY(50); 1130 } 1131 if (r != STAT_WAITING_FOR_BOOT) { 1132 printf(": not waiting for boot\n"); 1133 goto bail; 1134 } 1135 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1136 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1137 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1138 1139 /* See if it booted */ 1140 for (i = 0; i < 10000; i++) { 1141 r = READ_REG(sc, TXP_A2H_0); 1142 if (r == STAT_RUNNING) 1143 break; 1144 DELAY(50); 1145 } 1146 if (r != STAT_RUNNING) { 1147 printf(": fw not running\n"); 1148 goto bail; 1149 } 1150 1151 /* Clear TX and CMD ring write registers */ 1152 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1153 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1154 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1155 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1156 1157 return (0); 1158 1159 bail: 1160 txp_dma_free(sc, &sc->sc_zero_dma); 1161 bail_rxbufring: 1162 if (nb == RXBUF_ENTRIES) 1163 nb--; 1164 for (i = 0; i <= nb; i++) { 1165 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1166 sizeof(sd)); 1167 if (sd) 1168 free(sd, M_DEVBUF); 1169 } 1170 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1171 bail_rspring: 1172 txp_dma_free(sc, &sc->sc_rspring_dma); 1173 bail_cmdring: 1174 txp_dma_free(sc, &sc->sc_cmdring_dma); 1175 bail_rxloring: 1176 txp_dma_free(sc, &sc->sc_rxloring_dma); 1177 bail_rxhiring: 1178 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1179 bail_txloring: 1180 txp_dma_free(sc, &sc->sc_txloring_dma); 1181 bail_txhiring: 1182 txp_dma_free(sc, &sc->sc_txhiring_dma); 1183 bail_host: 1184 txp_dma_free(sc, &sc->sc_host_dma); 1185 bail_boot: 1186 txp_dma_free(sc, &sc->sc_boot_dma); 1187 return (-1); 1188 } 1189 1190 int 1191 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, struct txp_dma_alloc *dma, int mapflags) 1192 { 1193 int r; 1194 1195 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1196 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1197 goto fail_0; 1198 1199 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1200 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1201 goto fail_1; 1202 1203 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1204 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1205 goto fail_2; 1206 1207 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1208 size, NULL, BUS_DMA_NOWAIT)) != 0) 1209 goto fail_3; 1210 1211 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1212 return (0); 1213 1214 fail_3: 1215 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1216 fail_2: 1217 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1218 fail_1: 1219 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1220 fail_0: 1221 return (r); 1222 } 1223 1224 void 1225 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1226 { 1227 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1228 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1229 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1230 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1231 } 1232 1233 int 1234 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1235 { 1236 struct txp_softc *sc = ifp->if_softc; 1237 struct ifreq *ifr = (struct ifreq *)data; 1238 struct ifaddr *ifa = (struct ifaddr *)data; 1239 int s, error = 0; 1240 1241 s = splnet(); 1242 1243 #if 0 1244 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1245 splx(s); 1246 return error; 1247 } 1248 #endif 1249 1250 switch(command) { 1251 case SIOCINITIFADDR: 1252 ifp->if_flags |= IFF_UP; 1253 txp_init(sc); 1254 switch (ifa->ifa_addr->sa_family) { 1255 #ifdef INET 1256 case AF_INET: 1257 arp_ifinit(ifp, ifa); 1258 break; 1259 #endif /* INET */ 1260 default: 1261 break; 1262 } 1263 break; 1264 case SIOCSIFFLAGS: 1265 if ((error = ifioctl_common(ifp, command, data)) != 0) 1266 break; 1267 if (ifp->if_flags & IFF_UP) { 1268 txp_init(sc); 1269 } else { 1270 if (ifp->if_flags & IFF_RUNNING) 1271 txp_stop(sc); 1272 } 1273 break; 1274 case SIOCADDMULTI: 1275 case SIOCDELMULTI: 1276 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1277 break; 1278 1279 error = 0; 1280 1281 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1282 ; 1283 else if (ifp->if_flags & IFF_RUNNING) { 1284 /* 1285 * Multicast list has changed; set the hardware 1286 * filter accordingly. 1287 */ 1288 txp_set_filter(sc); 1289 } 1290 break; 1291 case SIOCGIFMEDIA: 1292 case SIOCSIFMEDIA: 1293 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1294 break; 1295 default: 1296 error = ether_ioctl(ifp, command, data); 1297 break; 1298 } 1299 1300 splx(s); 1301 1302 return(error); 1303 } 1304 1305 void 1306 txp_init(struct txp_softc *sc) 1307 { 1308 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1309 int s; 1310 1311 txp_stop(sc); 1312 1313 s = splnet(); 1314 1315 txp_set_filter(sc); 1316 1317 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1318 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1319 1320 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1321 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1322 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1323 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1324 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1325 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1326 1327 ifp->if_flags |= IFF_RUNNING; 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 ifp->if_timer = 0; 1330 1331 if (!callout_pending(&sc->sc_tick)) 1332 callout_schedule(&sc->sc_tick, hz); 1333 1334 splx(s); 1335 } 1336 1337 void 1338 txp_tick(void *vsc) 1339 { 1340 struct txp_softc *sc = vsc; 1341 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1342 struct txp_rsp_desc *rsp = NULL; 1343 struct txp_ext_desc *ext; 1344 int s; 1345 1346 s = splnet(); 1347 txp_rxbuf_reclaim(sc); 1348 1349 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1350 &rsp, 1)) 1351 goto out; 1352 if (rsp->rsp_numdesc != 6) 1353 goto out; 1354 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1355 NULL, NULL, NULL, 1)) 1356 goto out; 1357 ext = (struct txp_ext_desc *)(rsp + 1); 1358 1359 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1360 ext[4].ext_1 + ext[4].ext_4; 1361 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1362 ext[2].ext_1; 1363 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1364 ext[1].ext_3; 1365 ifp->if_opackets += rsp->rsp_par2; 1366 ifp->if_ipackets += ext[2].ext_3; 1367 1368 out: 1369 if (rsp != NULL) 1370 free(rsp, M_DEVBUF); 1371 1372 splx(s); 1373 callout_schedule(&sc->sc_tick, hz); 1374 } 1375 1376 void 1377 txp_start(struct ifnet *ifp) 1378 { 1379 struct txp_softc *sc = ifp->if_softc; 1380 struct txp_tx_ring *r = &sc->sc_txhir; 1381 struct txp_tx_desc *txd; 1382 int txdidx; 1383 struct txp_frag_desc *fxd; 1384 struct mbuf *m, *mnew; 1385 struct txp_swdesc *sd; 1386 u_int32_t firstprod, firstcnt, prod, cnt, i; 1387 struct m_tag *mtag; 1388 1389 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1390 return; 1391 1392 prod = r->r_prod; 1393 cnt = r->r_cnt; 1394 1395 while (1) { 1396 IFQ_POLL(&ifp->if_snd, m); 1397 if (m == NULL) 1398 break; 1399 mnew = NULL; 1400 1401 firstprod = prod; 1402 firstcnt = cnt; 1403 1404 sd = sc->sc_txd + prod; 1405 sd->sd_mbuf = m; 1406 1407 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1408 BUS_DMA_NOWAIT)) { 1409 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1410 if (mnew == NULL) 1411 goto oactive1; 1412 if (m->m_pkthdr.len > MHLEN) { 1413 MCLGET(mnew, M_DONTWAIT); 1414 if ((mnew->m_flags & M_EXT) == 0) { 1415 m_freem(mnew); 1416 goto oactive1; 1417 } 1418 } 1419 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1420 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1421 IFQ_DEQUEUE(&ifp->if_snd, m); 1422 m_freem(m); 1423 m = mnew; 1424 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1425 BUS_DMA_NOWAIT)) 1426 goto oactive1; 1427 } 1428 1429 if ((TX_ENTRIES - cnt) < 4) 1430 goto oactive; 1431 1432 txd = r->r_desc + prod; 1433 txdidx = prod; 1434 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1435 txd->tx_numdesc = 0; 1436 txd->tx_addrlo = 0; 1437 txd->tx_addrhi = 0; 1438 txd->tx_totlen = m->m_pkthdr.len; 1439 txd->tx_pflags = 0; 1440 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1441 1442 if (++prod == TX_ENTRIES) 1443 prod = 0; 1444 1445 if (++cnt >= (TX_ENTRIES - 4)) 1446 goto oactive; 1447 1448 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1449 txd->tx_pflags = TX_PFLAGS_VLAN | 1450 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1451 1452 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1453 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1454 #ifdef TRY_TX_TCP_CSUM 1455 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1456 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1457 #endif 1458 #ifdef TRY_TX_UDP_CSUM 1459 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1460 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1461 #endif 1462 1463 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1464 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1465 1466 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1467 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1468 if (++cnt >= (TX_ENTRIES - 4)) { 1469 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1470 0, sd->sd_map->dm_mapsize, 1471 BUS_DMASYNC_POSTWRITE); 1472 goto oactive; 1473 } 1474 1475 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1476 FRAG_FLAGS_VALID; 1477 fxd->frag_rsvd1 = 0; 1478 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1479 fxd->frag_addrlo = 1480 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1481 0xffffffff; 1482 fxd->frag_addrhi = 1483 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1484 32; 1485 fxd->frag_rsvd2 = 0; 1486 1487 bus_dmamap_sync(sc->sc_dmat, 1488 sc->sc_txhiring_dma.dma_map, 1489 prod * sizeof(struct txp_frag_desc), 1490 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1491 1492 if (++prod == TX_ENTRIES) { 1493 fxd = (struct txp_frag_desc *)r->r_desc; 1494 prod = 0; 1495 } else 1496 fxd++; 1497 1498 } 1499 1500 /* 1501 * if mnew isn't NULL, we already dequeued and copied 1502 * the packet. 1503 */ 1504 if (mnew == NULL) 1505 IFQ_DEQUEUE(&ifp->if_snd, m); 1506 1507 ifp->if_timer = 5; 1508 1509 bpf_mtap(ifp, m); 1510 1511 txd->tx_flags |= TX_FLAGS_VALID; 1512 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1513 txdidx * sizeof(struct txp_tx_desc), 1514 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1515 1516 #if 0 1517 { 1518 struct mbuf *mx; 1519 int i; 1520 1521 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1522 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1523 txd->tx_pflags); 1524 for (mx = m; mx != NULL; mx = mx->m_next) { 1525 for (i = 0; i < mx->m_len; i++) { 1526 printf(":%02x", 1527 (u_int8_t)m->m_data[i]); 1528 } 1529 } 1530 printf("\n"); 1531 } 1532 #endif 1533 1534 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1535 } 1536 1537 r->r_prod = prod; 1538 r->r_cnt = cnt; 1539 return; 1540 1541 oactive: 1542 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1543 oactive1: 1544 ifp->if_flags |= IFF_OACTIVE; 1545 r->r_prod = firstprod; 1546 r->r_cnt = firstcnt; 1547 } 1548 1549 /* 1550 * Handle simple commands sent to the typhoon 1551 */ 1552 int 1553 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1554 { 1555 struct txp_rsp_desc *rsp = NULL; 1556 1557 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1558 return (-1); 1559 1560 if (!wait) 1561 return (0); 1562 1563 if (out1 != NULL) 1564 *out1 = le16toh(rsp->rsp_par1); 1565 if (out2 != NULL) 1566 *out2 = le32toh(rsp->rsp_par2); 1567 if (out3 != NULL) 1568 *out3 = le32toh(rsp->rsp_par3); 1569 free(rsp, M_DEVBUF); 1570 return (0); 1571 } 1572 1573 int 1574 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, struct txp_rsp_desc **rspp, int wait) 1575 { 1576 struct txp_hostvar *hv = sc->sc_hostvar; 1577 struct txp_cmd_desc *cmd; 1578 struct txp_ext_desc *ext; 1579 u_int32_t idx, i; 1580 u_int16_t seq; 1581 1582 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1583 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1584 return (-1); 1585 } 1586 1587 idx = sc->sc_cmdring.lastwrite; 1588 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1589 memset(cmd, 0, sizeof(*cmd)); 1590 1591 cmd->cmd_numdesc = in_extn; 1592 seq = sc->sc_seq++; 1593 cmd->cmd_seq = htole16(seq); 1594 cmd->cmd_id = htole16(id); 1595 cmd->cmd_par1 = htole16(in1); 1596 cmd->cmd_par2 = htole32(in2); 1597 cmd->cmd_par3 = htole32(in3); 1598 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1599 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1600 1601 idx += sizeof(struct txp_cmd_desc); 1602 if (idx == sc->sc_cmdring.size) 1603 idx = 0; 1604 1605 for (i = 0; i < in_extn; i++) { 1606 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1607 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1608 in_extp++; 1609 idx += sizeof(struct txp_cmd_desc); 1610 if (idx == sc->sc_cmdring.size) 1611 idx = 0; 1612 } 1613 1614 sc->sc_cmdring.lastwrite = idx; 1615 1616 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1617 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1618 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1619 1620 if (!wait) 1621 return (0); 1622 1623 for (i = 0; i < 10000; i++) { 1624 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1625 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1626 idx = le32toh(hv->hv_resp_read_idx); 1627 if (idx != le32toh(hv->hv_resp_write_idx)) { 1628 *rspp = NULL; 1629 if (txp_response(sc, idx, id, seq, rspp)) 1630 return (-1); 1631 if (*rspp != NULL) 1632 break; 1633 } 1634 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1635 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1636 DELAY(50); 1637 } 1638 if (i == 1000 || (*rspp) == NULL) { 1639 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1640 return (-1); 1641 } 1642 1643 return (0); 1644 } 1645 1646 int 1647 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, struct txp_rsp_desc **rspp) 1648 { 1649 struct txp_hostvar *hv = sc->sc_hostvar; 1650 struct txp_rsp_desc *rsp; 1651 1652 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1653 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1654 1655 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1656 *rspp = (struct txp_rsp_desc *)malloc( 1657 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1658 M_DEVBUF, M_NOWAIT); 1659 if ((*rspp) == NULL) 1660 return (-1); 1661 txp_rsp_fixup(sc, rsp, *rspp); 1662 return (0); 1663 } 1664 1665 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1666 printf("%s: response error: id 0x%x\n", 1667 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1668 txp_rsp_fixup(sc, rsp, NULL); 1669 ridx = le32toh(hv->hv_resp_read_idx); 1670 continue; 1671 } 1672 1673 switch (le16toh(rsp->rsp_id)) { 1674 case TXP_CMD_CYCLE_STATISTICS: 1675 case TXP_CMD_MEDIA_STATUS_READ: 1676 break; 1677 case TXP_CMD_HELLO_RESPONSE: 1678 printf("%s: hello\n", TXP_DEVNAME(sc)); 1679 break; 1680 default: 1681 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1682 le16toh(rsp->rsp_id)); 1683 } 1684 1685 txp_rsp_fixup(sc, rsp, NULL); 1686 ridx = le32toh(hv->hv_resp_read_idx); 1687 hv->hv_resp_read_idx = le32toh(ridx); 1688 } 1689 1690 return (0); 1691 } 1692 1693 void 1694 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, struct txp_rsp_desc *dst) 1695 { 1696 struct txp_rsp_desc *src = rsp; 1697 struct txp_hostvar *hv = sc->sc_hostvar; 1698 u_int32_t i, ridx; 1699 1700 ridx = le32toh(hv->hv_resp_read_idx); 1701 1702 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1703 if (dst != NULL) 1704 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1705 ridx += sizeof(struct txp_rsp_desc); 1706 if (ridx == sc->sc_rspring.size) { 1707 src = sc->sc_rspring.base; 1708 ridx = 0; 1709 } else 1710 src++; 1711 sc->sc_rspring.lastwrite = ridx; 1712 hv->hv_resp_read_idx = htole32(ridx); 1713 } 1714 1715 hv->hv_resp_read_idx = htole32(ridx); 1716 } 1717 1718 int 1719 txp_cmd_desc_numfree(struct txp_softc *sc) 1720 { 1721 struct txp_hostvar *hv = sc->sc_hostvar; 1722 struct txp_boot_record *br = sc->sc_boot; 1723 u_int32_t widx, ridx, nfree; 1724 1725 widx = sc->sc_cmdring.lastwrite; 1726 ridx = le32toh(hv->hv_cmd_read_idx); 1727 1728 if (widx == ridx) { 1729 /* Ring is completely free */ 1730 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1731 } else { 1732 if (widx > ridx) 1733 nfree = le32toh(br->br_cmd_siz) - 1734 (widx - ridx + sizeof(struct txp_cmd_desc)); 1735 else 1736 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1737 } 1738 1739 return (nfree / sizeof(struct txp_cmd_desc)); 1740 } 1741 1742 void 1743 txp_stop(struct txp_softc *sc) 1744 { 1745 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1746 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1747 1748 if (callout_pending(&sc->sc_tick)) 1749 callout_stop(&sc->sc_tick); 1750 } 1751 1752 void 1753 txp_watchdog(struct ifnet *ifp) 1754 { 1755 } 1756 1757 int 1758 txp_ifmedia_upd(struct ifnet *ifp) 1759 { 1760 struct txp_softc *sc = ifp->if_softc; 1761 struct ifmedia *ifm = &sc->sc_ifmedia; 1762 u_int16_t new_xcvr; 1763 1764 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1765 return (EINVAL); 1766 1767 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1768 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1769 new_xcvr = TXP_XCVR_10_FDX; 1770 else 1771 new_xcvr = TXP_XCVR_10_HDX; 1772 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1773 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1774 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1775 new_xcvr = TXP_XCVR_100_FDX; 1776 else 1777 new_xcvr = TXP_XCVR_100_HDX; 1778 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1779 new_xcvr = TXP_XCVR_AUTO; 1780 } else 1781 return (EINVAL); 1782 1783 /* nothing to do */ 1784 if (sc->sc_xcvr == new_xcvr) 1785 return (0); 1786 1787 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1788 NULL, NULL, NULL, 0); 1789 sc->sc_xcvr = new_xcvr; 1790 1791 return (0); 1792 } 1793 1794 void 1795 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1796 { 1797 struct txp_softc *sc = ifp->if_softc; 1798 struct ifmedia *ifm = &sc->sc_ifmedia; 1799 u_int16_t bmsr, bmcr, anlpar; 1800 1801 ifmr->ifm_status = IFM_AVALID; 1802 ifmr->ifm_active = IFM_ETHER; 1803 1804 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1805 &bmsr, NULL, NULL, 1)) 1806 goto bail; 1807 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1808 &bmsr, NULL, NULL, 1)) 1809 goto bail; 1810 1811 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1812 &bmcr, NULL, NULL, 1)) 1813 goto bail; 1814 1815 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1816 &anlpar, NULL, NULL, 1)) 1817 goto bail; 1818 1819 if (bmsr & BMSR_LINK) 1820 ifmr->ifm_status |= IFM_ACTIVE; 1821 1822 if (bmcr & BMCR_ISO) { 1823 ifmr->ifm_active |= IFM_NONE; 1824 ifmr->ifm_status = 0; 1825 return; 1826 } 1827 1828 if (bmcr & BMCR_LOOP) 1829 ifmr->ifm_active |= IFM_LOOP; 1830 1831 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1832 if ((bmsr & BMSR_ACOMP) == 0) { 1833 ifmr->ifm_active |= IFM_NONE; 1834 return; 1835 } 1836 1837 if (anlpar & ANLPAR_TX_FD) 1838 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1839 else if (anlpar & ANLPAR_T4) 1840 ifmr->ifm_active |= IFM_100_T4; 1841 else if (anlpar & ANLPAR_TX) 1842 ifmr->ifm_active |= IFM_100_TX; 1843 else if (anlpar & ANLPAR_10_FD) 1844 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1845 else if (anlpar & ANLPAR_10) 1846 ifmr->ifm_active |= IFM_10_T; 1847 else 1848 ifmr->ifm_active |= IFM_NONE; 1849 } else 1850 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1851 return; 1852 1853 bail: 1854 ifmr->ifm_active |= IFM_NONE; 1855 ifmr->ifm_status &= ~IFM_AVALID; 1856 } 1857 1858 void 1859 txp_show_descriptor(void *d) 1860 { 1861 struct txp_cmd_desc *cmd = d; 1862 struct txp_rsp_desc *rsp = d; 1863 struct txp_tx_desc *txd = d; 1864 struct txp_frag_desc *frgd = d; 1865 1866 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1867 case CMD_FLAGS_TYPE_CMD: 1868 /* command descriptor */ 1869 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1870 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1871 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1872 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1873 break; 1874 case CMD_FLAGS_TYPE_RESP: 1875 /* response descriptor */ 1876 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1877 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1878 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1879 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1880 break; 1881 case CMD_FLAGS_TYPE_DATA: 1882 /* data header (assuming tx for now) */ 1883 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1884 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1885 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1886 break; 1887 case CMD_FLAGS_TYPE_FRAG: 1888 /* fragment descriptor */ 1889 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1890 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1891 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1892 break; 1893 default: 1894 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1895 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1896 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1897 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1898 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1899 break; 1900 } 1901 } 1902 1903 void 1904 txp_set_filter(struct txp_softc *sc) 1905 { 1906 struct ethercom *ac = &sc->sc_arpcom; 1907 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1908 u_int32_t crc, carry, hashbit, hash[2]; 1909 u_int16_t filter; 1910 u_int8_t octet; 1911 int i, j, mcnt = 0; 1912 struct ether_multi *enm; 1913 struct ether_multistep step; 1914 1915 if (ifp->if_flags & IFF_PROMISC) { 1916 filter = TXP_RXFILT_PROMISC; 1917 goto setit; 1918 } 1919 1920 again: 1921 filter = TXP_RXFILT_DIRECT; 1922 1923 if (ifp->if_flags & IFF_BROADCAST) 1924 filter |= TXP_RXFILT_BROADCAST; 1925 1926 if (ifp->if_flags & IFF_ALLMULTI) 1927 filter |= TXP_RXFILT_ALLMULTI; 1928 else { 1929 hash[0] = hash[1] = 0; 1930 1931 ETHER_FIRST_MULTI(step, ac, enm); 1932 while (enm != NULL) { 1933 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1934 /* 1935 * We must listen to a range of multicast 1936 * addresses. For now, just accept all 1937 * multicasts, rather than trying to set only 1938 * those filter bits needed to match the range. 1939 * (At this time, the only use of address 1940 * ranges is for IP multicast routing, for 1941 * which the range is big enough to require 1942 * all bits set.) 1943 */ 1944 ifp->if_flags |= IFF_ALLMULTI; 1945 goto again; 1946 } 1947 1948 mcnt++; 1949 crc = 0xffffffff; 1950 1951 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1952 octet = enm->enm_addrlo[i]; 1953 for (j = 0; j < 8; j++) { 1954 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1955 (octet & 1); 1956 crc <<= 1; 1957 octet >>= 1; 1958 if (carry) 1959 crc = (crc ^ TXP_POLYNOMIAL) | 1960 carry; 1961 } 1962 } 1963 hashbit = (u_int16_t)(crc & (64 - 1)); 1964 hash[hashbit / 32] |= (1 << hashbit % 32); 1965 ETHER_NEXT_MULTI(step, enm); 1966 } 1967 1968 if (mcnt > 0) { 1969 filter |= TXP_RXFILT_HASHMULTI; 1970 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1971 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1972 } 1973 } 1974 1975 setit: 1976 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1977 NULL, NULL, NULL, 1); 1978 } 1979 1980 void 1981 txp_capabilities(struct txp_softc *sc) 1982 { 1983 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1984 struct txp_rsp_desc *rsp = NULL; 1985 struct txp_ext_desc *ext; 1986 1987 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1988 goto out; 1989 1990 if (rsp->rsp_numdesc != 1) 1991 goto out; 1992 ext = (struct txp_ext_desc *)(rsp + 1); 1993 1994 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1995 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1996 1997 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1998 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1999 sc->sc_tx_capability |= OFFLOAD_VLAN; 2000 sc->sc_rx_capability |= OFFLOAD_VLAN; 2001 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2002 } 2003 2004 #if 0 2005 /* not ready yet */ 2006 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2007 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2008 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2009 ifp->if_capabilities |= IFCAP_IPSEC; 2010 } 2011 #endif 2012 2013 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2014 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2015 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2016 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2017 } 2018 2019 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2020 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2021 #ifdef TRY_TX_TCP_CSUM 2022 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2023 ifp->if_capabilities |= 2024 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2025 #endif 2026 } 2027 2028 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2029 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2030 #ifdef TRY_TX_UDP_CSUM 2031 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2032 ifp->if_capabilities |= 2033 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2034 #endif 2035 } 2036 2037 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2038 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2039 goto out; 2040 2041 out: 2042 if (rsp != NULL) 2043 free(rsp, M_DEVBUF); 2044 } 2045
Indexes created Tue Sep 30 20:09:53 GMT 2025