if_txp.c revision 1.38.14.1
1 /* $NetBSD: if_txp.c,v 1.38.14.1 2014/11/09 12:13:15 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.38.14.1 2014/11/09 12:13:15 martin Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #include <net/bpf.h> 66 67 #include <sys/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_txpreg.h> 76 77 #include <dev/microcode/typhoon/3c990img.h> 78 79 /* 80 * These currently break the 3c990 firmware, hopefully will be resolved 81 * at some point. 82 */ 83 #undef TRY_TX_UDP_CSUM 84 #undef TRY_TX_TCP_CSUM 85 86 int txp_probe(device_t, cfdata_t, void *); 87 void txp_attach(device_t, device_t, void *); 88 int txp_intr(void *); 89 void txp_tick(void *); 90 bool txp_shutdown(device_t, int); 91 int txp_ioctl(struct ifnet *, u_long, void *); 92 void txp_start(struct ifnet *); 93 void txp_stop(struct txp_softc *); 94 void txp_init(struct txp_softc *); 95 void txp_watchdog(struct ifnet *); 96 97 int txp_chip_init(struct txp_softc *); 98 int txp_reset_adapter(struct txp_softc *); 99 int txp_download_fw(struct txp_softc *); 100 int txp_download_fw_wait(struct txp_softc *); 101 int txp_download_fw_section(struct txp_softc *, 102 const struct txp_fw_section_header *, int); 103 int txp_alloc_rings(struct txp_softc *); 104 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 105 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 106 void txp_set_filter(struct txp_softc *); 107 108 int txp_cmd_desc_numfree(struct txp_softc *); 109 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 110 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 111 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 112 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 113 struct txp_rsp_desc **, int); 114 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 115 struct txp_rsp_desc **); 116 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 117 struct txp_rsp_desc *); 118 void txp_capabilities(struct txp_softc *); 119 120 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 int txp_ifmedia_upd(struct ifnet *); 122 void txp_show_descriptor(void *); 123 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 124 struct txp_dma_alloc *); 125 void txp_rxbuf_reclaim(struct txp_softc *); 126 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 127 struct txp_dma_alloc *); 128 129 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 130 NULL, NULL); 131 132 const struct txp_pci_match { 133 int vid, did, flags; 134 } txp_devices[] = { 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 143 }; 144 145 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 146 147 static const struct { 148 u_int16_t mask, value; 149 int flags; 150 } txp_subsysinfo[] = { 151 {0xf000, 0x2000, TXP_SERVERVERSION}, 152 {0x0100, 0x0100, TXP_FIBER}, 153 #if 0 /* information from 3com header, unused */ 154 {0x0010, 0x0010, /* secured firmware */}, 155 {0x0003, 0x0000, /* variable DES */}, 156 {0x0003, 0x0001, /* single DES - "95" */}, 157 {0x0003, 0x0002, /* triple DES - "97" */}, 158 #endif 159 }; 160 161 static const struct txp_pci_match * 162 txp_pcilookup(pcireg_t id) 163 { 164 int i; 165 166 for (i = 0; i < __arraycount(txp_devices); i++) 167 if (PCI_VENDOR(id) == txp_devices[i].vid && 168 PCI_PRODUCT(id) == txp_devices[i].did) 169 return &txp_devices[i]; 170 return (0); 171 } 172 173 int 174 txp_probe(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 178 if (txp_pcilookup(pa->pa_id)) 179 return (1); 180 return (0); 181 } 182 183 void 184 txp_attach(device_t parent, device_t self, void *aux) 185 { 186 struct txp_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr = NULL; 191 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 192 u_int32_t command; 193 u_int16_t p1; 194 u_int32_t p2; 195 u_char enaddr[6]; 196 const struct txp_pci_match *match; 197 u_int16_t subsys; 198 int i, flags; 199 char devinfo[256]; 200 201 sc->sc_cold = 1; 202 203 match = txp_pcilookup(pa->pa_id); 204 flags = match->flags; 205 if (match->flags & TXP_USESUBSYSTEM) { 206 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 207 PCI_SUBSYS_ID_REG)); 208 for (i = 0; 209 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 210 i++) 211 if ((subsys & txp_subsysinfo[i].mask) == 212 txp_subsysinfo[i].value) 213 flags |= txp_subsysinfo[i].flags; 214 } 215 sc->sc_flags = flags; 216 217 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 218 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 219 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 220 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, device_xname(&sc->sc_dev)); 221 222 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 223 224 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 225 printf(": failed to enable bus mastering\n"); 226 return; 227 } 228 229 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 230 printf(": failed to enable memory mapping\n"); 231 return; 232 } 233 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 234 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 235 printf(": can't map mem space %d\n", 0); 236 return; 237 } 238 239 sc->sc_dmat = pa->pa_dmat; 240 241 /* 242 * Allocate our interrupt. 243 */ 244 if (pci_intr_map(pa, &ih)) { 245 printf(": couldn't map interrupt\n"); 246 return; 247 } 248 249 intrstr = pci_intr_string(pc, ih); 250 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 251 if (sc->sc_ih == NULL) { 252 printf(": couldn't establish interrupt"); 253 if (intrstr != NULL) 254 printf(" at %s", intrstr); 255 printf("\n"); 256 return; 257 } 258 printf(": interrupting at %s\n", intrstr); 259 260 if (txp_chip_init(sc)) 261 goto cleanupintr; 262 263 if (txp_download_fw(sc)) 264 goto cleanupintr; 265 266 if (txp_alloc_rings(sc)) 267 goto cleanupintr; 268 269 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 270 NULL, NULL, NULL, 1)) 271 goto cleanupintr; 272 273 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 274 &p1, &p2, NULL, 1)) 275 goto cleanupintr; 276 277 txp_set_filter(sc); 278 279 p1 = htole16(p1); 280 enaddr[0] = ((u_int8_t *)&p1)[1]; 281 enaddr[1] = ((u_int8_t *)&p1)[0]; 282 p2 = htole32(p2); 283 enaddr[2] = ((u_int8_t *)&p2)[3]; 284 enaddr[3] = ((u_int8_t *)&p2)[2]; 285 enaddr[4] = ((u_int8_t *)&p2)[1]; 286 enaddr[5] = ((u_int8_t *)&p2)[0]; 287 288 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 289 ether_sprintf(enaddr)); 290 sc->sc_cold = 0; 291 292 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 293 if (flags & TXP_FIBER) { 294 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 295 0, NULL); 296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 297 0, NULL); 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 299 0, NULL); 300 } else { 301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 302 0, NULL); 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 304 0, NULL); 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 312 0, NULL); 313 } 314 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 315 316 sc->sc_xcvr = TXP_XCVR_AUTO; 317 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 318 NULL, NULL, NULL, 0); 319 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 320 321 ifp->if_softc = sc; 322 ifp->if_mtu = ETHERMTU; 323 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 324 ifp->if_ioctl = txp_ioctl; 325 ifp->if_start = txp_start; 326 ifp->if_watchdog = txp_watchdog; 327 ifp->if_baudrate = 10000000; 328 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 329 IFQ_SET_READY(&ifp->if_snd); 330 ifp->if_capabilities = 0; 331 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 332 333 txp_capabilities(sc); 334 335 callout_init(&sc->sc_tick, 0); 336 callout_setfunc(&sc->sc_tick, txp_tick, sc); 337 338 /* 339 * Attach us everywhere 340 */ 341 if_attach(ifp); 342 ether_ifattach(ifp, enaddr); 343 344 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 345 pmf_class_network_register(self, ifp); 346 else 347 aprint_error_dev(self, "couldn't establish power handler\n"); 348 349 return; 350 351 cleanupintr: 352 pci_intr_disestablish(pc,sc->sc_ih); 353 354 return; 355 356 } 357 358 int 359 txp_chip_init(struct txp_softc *sc) 360 { 361 /* disable interrupts */ 362 WRITE_REG(sc, TXP_IER, 0); 363 WRITE_REG(sc, TXP_IMR, 364 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 365 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 366 TXP_INT_LATCH); 367 368 /* ack all interrupts */ 369 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 370 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 371 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 372 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 373 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 374 375 if (txp_reset_adapter(sc)) 376 return (-1); 377 378 /* disable interrupts */ 379 WRITE_REG(sc, TXP_IER, 0); 380 WRITE_REG(sc, TXP_IMR, 381 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 382 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 383 TXP_INT_LATCH); 384 385 /* ack all interrupts */ 386 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 387 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 388 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 389 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 390 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 391 392 return (0); 393 } 394 395 int 396 txp_reset_adapter(struct txp_softc *sc) 397 { 398 u_int32_t r; 399 int i; 400 401 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 402 DELAY(1000); 403 WRITE_REG(sc, TXP_SRR, 0); 404 405 /* Should wait max 6 seconds */ 406 for (i = 0; i < 6000; i++) { 407 r = READ_REG(sc, TXP_A2H_0); 408 if (r == STAT_WAITING_FOR_HOST_REQUEST) 409 break; 410 DELAY(1000); 411 } 412 413 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 414 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 415 return (-1); 416 } 417 418 return (0); 419 } 420 421 int 422 txp_download_fw(struct txp_softc *sc) 423 { 424 const struct txp_fw_file_header *fileheader; 425 const struct txp_fw_section_header *secthead; 426 int sect; 427 u_int32_t r, i, ier, imr; 428 429 ier = READ_REG(sc, TXP_IER); 430 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 431 432 imr = READ_REG(sc, TXP_IMR); 433 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 434 435 for (i = 0; i < 10000; i++) { 436 r = READ_REG(sc, TXP_A2H_0); 437 if (r == STAT_WAITING_FOR_HOST_REQUEST) 438 break; 439 DELAY(50); 440 } 441 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 442 printf(": not waiting for host request\n"); 443 return (-1); 444 } 445 446 /* Ack the status */ 447 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 448 449 fileheader = (const struct txp_fw_file_header *)tc990image; 450 if (memcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 451 printf(": fw invalid magic\n"); 452 return (-1); 453 } 454 455 /* Tell boot firmware to get ready for image */ 456 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 457 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 458 459 if (txp_download_fw_wait(sc)) { 460 printf("%s: fw wait failed, initial\n", device_xname(&sc->sc_dev)); 461 return (-1); 462 } 463 464 secthead = (const struct txp_fw_section_header *) 465 (((const u_int8_t *)tc990image) + 466 sizeof(struct txp_fw_file_header)); 467 468 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 469 if (txp_download_fw_section(sc, secthead, sect)) 470 return (-1); 471 secthead = (const struct txp_fw_section_header *) 472 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 473 sizeof(*secthead)); 474 } 475 476 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 477 478 for (i = 0; i < 10000; i++) { 479 r = READ_REG(sc, TXP_A2H_0); 480 if (r == STAT_WAITING_FOR_BOOT) 481 break; 482 DELAY(50); 483 } 484 if (r != STAT_WAITING_FOR_BOOT) { 485 printf(": not waiting for boot\n"); 486 return (-1); 487 } 488 489 WRITE_REG(sc, TXP_IER, ier); 490 WRITE_REG(sc, TXP_IMR, imr); 491 492 return (0); 493 } 494 495 int 496 txp_download_fw_wait(struct txp_softc *sc) 497 { 498 u_int32_t i, r; 499 500 for (i = 0; i < 10000; i++) { 501 r = READ_REG(sc, TXP_ISR); 502 if (r & TXP_INT_A2H_0) 503 break; 504 DELAY(50); 505 } 506 507 if (!(r & TXP_INT_A2H_0)) { 508 printf(": fw wait failed comm0\n"); 509 return (-1); 510 } 511 512 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 513 514 r = READ_REG(sc, TXP_A2H_0); 515 if (r != STAT_WAITING_FOR_SEGMENT) { 516 printf(": fw not waiting for segment\n"); 517 return (-1); 518 } 519 return (0); 520 } 521 522 int 523 txp_download_fw_section(struct txp_softc *sc, const struct txp_fw_section_header *sect, int sectnum) 524 { 525 struct txp_dma_alloc dma; 526 int rseg, err = 0; 527 struct mbuf m; 528 #ifdef INET 529 u_int16_t csum; 530 #endif 531 532 /* Skip zero length sections */ 533 if (sect->nbytes == 0) 534 return (0); 535 536 /* Make sure we aren't past the end of the image */ 537 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 538 if (rseg >= sizeof(tc990image)) { 539 printf(": fw invalid section address, section %d\n", sectnum); 540 return (-1); 541 } 542 543 /* Make sure this section doesn't go past the end */ 544 rseg += le32toh(sect->nbytes); 545 if (rseg >= sizeof(tc990image)) { 546 printf(": fw truncated section %d\n", sectnum); 547 return (-1); 548 } 549 550 /* map a buffer, copy segment to it, get physaddr */ 551 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 552 printf(": fw dma malloc failed, section %d\n", sectnum); 553 return (-1); 554 } 555 556 memcpy(dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 557 le32toh(sect->nbytes)); 558 559 /* 560 * dummy up mbuf and verify section checksum 561 */ 562 m.m_type = MT_DATA; 563 m.m_next = m.m_nextpkt = NULL; 564 m.m_len = le32toh(sect->nbytes); 565 m.m_data = dma.dma_vaddr; 566 m.m_flags = 0; 567 #ifdef INET 568 csum = in_cksum(&m, le32toh(sect->nbytes)); 569 if (csum != sect->cksum) { 570 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 571 sectnum, sect->cksum, csum); 572 txp_dma_free(sc, &dma); 573 return -1; 574 } 575 #endif 576 577 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 578 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 579 580 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 581 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 582 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 583 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 584 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 585 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 586 587 if (txp_download_fw_wait(sc)) { 588 printf("%s: fw wait failed, section %d\n", 589 device_xname(&sc->sc_dev), sectnum); 590 err = -1; 591 } 592 593 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 594 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 595 596 txp_dma_free(sc, &dma); 597 return (err); 598 } 599 600 int 601 txp_intr(void *vsc) 602 { 603 struct txp_softc *sc = vsc; 604 struct txp_hostvar *hv = sc->sc_hostvar; 605 u_int32_t isr; 606 int claimed = 0; 607 608 /* mask all interrupts */ 609 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 610 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 611 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 612 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 613 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 614 615 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 616 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 617 618 isr = READ_REG(sc, TXP_ISR); 619 while (isr) { 620 claimed = 1; 621 WRITE_REG(sc, TXP_ISR, isr); 622 623 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 624 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 625 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 626 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 627 628 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 629 txp_rxbuf_reclaim(sc); 630 631 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 632 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 633 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 634 635 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 636 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 637 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 638 639 isr = READ_REG(sc, TXP_ISR); 640 } 641 642 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 643 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 644 645 /* unmask all interrupts */ 646 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 647 648 txp_start(&sc->sc_arpcom.ec_if); 649 650 return (claimed); 651 } 652 653 void 654 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, struct txp_dma_alloc *dma) 655 { 656 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 657 struct txp_rx_desc *rxd; 658 struct mbuf *m; 659 struct txp_swdesc *sd; 660 u_int32_t roff, woff; 661 int sumflags = 0; 662 int idx; 663 664 roff = le32toh(*r->r_roff); 665 woff = le32toh(*r->r_woff); 666 idx = roff / sizeof(struct txp_rx_desc); 667 rxd = r->r_desc + idx; 668 669 while (roff != woff) { 670 671 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 672 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 673 BUS_DMASYNC_POSTREAD); 674 675 if (rxd->rx_flags & RX_FLAGS_ERROR) { 676 printf("%s: error 0x%x\n", device_xname(&sc->sc_dev), 677 le32toh(rxd->rx_stat)); 678 ifp->if_ierrors++; 679 goto next; 680 } 681 682 /* retrieve stashed pointer */ 683 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 684 685 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 686 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 687 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 688 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 689 m = sd->sd_mbuf; 690 free(sd, M_DEVBUF); 691 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 692 693 #ifdef __STRICT_ALIGNMENT 694 { 695 /* 696 * XXX Nice chip, except it won't accept "off by 2" 697 * buffers, so we're force to copy. Supposedly 698 * this will be fixed in a newer firmware rev 699 * and this will be temporary. 700 */ 701 struct mbuf *mnew; 702 703 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 704 if (mnew == NULL) { 705 m_freem(m); 706 goto next; 707 } 708 if (m->m_len > (MHLEN - 2)) { 709 MCLGET(mnew, M_DONTWAIT); 710 if (!(mnew->m_flags & M_EXT)) { 711 m_freem(mnew); 712 m_freem(m); 713 goto next; 714 } 715 } 716 mnew->m_pkthdr.rcvif = ifp; 717 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 718 mnew->m_data += 2; 719 memcpy(mnew->m_data, m->m_data, m->m_len); 720 m_freem(m); 721 m = mnew; 722 } 723 #endif 724 725 /* 726 * Handle BPF listeners. Let the BPF user see the packet. 727 */ 728 bpf_mtap(ifp, m); 729 730 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 731 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 732 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 733 sumflags |= M_CSUM_IPv4; 734 735 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 736 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 737 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 738 sumflags |= M_CSUM_TCPv4; 739 740 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 741 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 742 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 743 sumflags |= M_CSUM_UDPv4; 744 745 m->m_pkthdr.csum_flags = sumflags; 746 747 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 748 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 749 continue); 750 } 751 752 (*ifp->if_input)(ifp, m); 753 754 next: 755 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 756 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 757 BUS_DMASYNC_PREREAD); 758 759 roff += sizeof(struct txp_rx_desc); 760 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 761 idx = 0; 762 roff = 0; 763 rxd = r->r_desc; 764 } else { 765 idx++; 766 rxd++; 767 } 768 woff = le32toh(*r->r_woff); 769 } 770 771 *r->r_roff = htole32(woff); 772 } 773 774 void 775 txp_rxbuf_reclaim(struct txp_softc *sc) 776 { 777 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 778 struct txp_hostvar *hv = sc->sc_hostvar; 779 struct txp_rxbuf_desc *rbd; 780 struct txp_swdesc *sd; 781 u_int32_t i, end; 782 783 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 784 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 785 786 if (++i == RXBUF_ENTRIES) 787 i = 0; 788 789 rbd = sc->sc_rxbufs + i; 790 791 while (i != end) { 792 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 793 M_DEVBUF, M_NOWAIT); 794 if (sd == NULL) 795 break; 796 797 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 798 if (sd->sd_mbuf == NULL) 799 goto err_sd; 800 801 MCLGET(sd->sd_mbuf, M_DONTWAIT); 802 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 803 goto err_mbuf; 804 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 805 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 806 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 807 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 808 goto err_mbuf; 809 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 810 BUS_DMA_NOWAIT)) { 811 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 812 goto err_mbuf; 813 } 814 815 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 816 i * sizeof(struct txp_rxbuf_desc), 817 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 818 819 /* stash away pointer */ 820 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 821 822 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 823 & 0xffffffff; 824 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 825 >> 32; 826 827 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 828 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 829 830 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 831 i * sizeof(struct txp_rxbuf_desc), 832 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 833 834 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 835 836 if (++i == RXBUF_ENTRIES) { 837 i = 0; 838 rbd = sc->sc_rxbufs; 839 } else 840 rbd++; 841 } 842 return; 843 844 err_mbuf: 845 m_freem(sd->sd_mbuf); 846 err_sd: 847 free(sd, M_DEVBUF); 848 } 849 850 /* 851 * Reclaim mbufs and entries from a transmit ring. 852 */ 853 void 854 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, struct txp_dma_alloc *dma) 855 { 856 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 857 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 858 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 859 struct txp_tx_desc *txd = r->r_desc + cons; 860 struct txp_swdesc *sd = sc->sc_txd + cons; 861 struct mbuf *m; 862 863 while (cons != idx) { 864 if (cnt == 0) 865 break; 866 867 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 868 cons * sizeof(struct txp_tx_desc), 869 sizeof(struct txp_tx_desc), 870 BUS_DMASYNC_POSTWRITE); 871 872 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 873 TX_FLAGS_TYPE_DATA) { 874 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 875 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 876 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 877 m = sd->sd_mbuf; 878 if (m != NULL) { 879 m_freem(m); 880 txd->tx_addrlo = 0; 881 txd->tx_addrhi = 0; 882 ifp->if_opackets++; 883 } 884 } 885 ifp->if_flags &= ~IFF_OACTIVE; 886 887 if (++cons == TX_ENTRIES) { 888 txd = r->r_desc; 889 cons = 0; 890 sd = sc->sc_txd; 891 } else { 892 txd++; 893 sd++; 894 } 895 896 cnt--; 897 } 898 899 r->r_cons = cons; 900 r->r_cnt = cnt; 901 if (cnt == 0) 902 ifp->if_timer = 0; 903 } 904 905 bool 906 txp_shutdown(device_t self, int howto) 907 { 908 struct txp_softc *sc; 909 910 sc = device_private(self); 911 912 /* mask all interrupts */ 913 WRITE_REG(sc, TXP_IMR, 914 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 915 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 916 TXP_INT_LATCH); 917 918 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 919 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 920 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 921 922 return true; 923 } 924 925 int 926 txp_alloc_rings(struct txp_softc *sc) 927 { 928 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 929 struct txp_boot_record *boot; 930 struct txp_swdesc *sd; 931 u_int32_t r; 932 int i, j, nb; 933 934 /* boot record */ 935 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 936 BUS_DMA_COHERENT)) { 937 printf(": can't allocate boot record\n"); 938 return (-1); 939 } 940 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 941 memset(boot, 0, sizeof(*boot)); 942 sc->sc_boot = boot; 943 944 /* host variables */ 945 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 946 BUS_DMA_COHERENT)) { 947 printf(": can't allocate host ring\n"); 948 goto bail_boot; 949 } 950 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 951 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 952 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 953 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 954 955 /* high priority tx ring */ 956 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 957 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 958 printf(": can't allocate high tx ring\n"); 959 goto bail_host; 960 } 961 memset(sc->sc_txhiring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 962 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 963 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 964 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 965 sc->sc_txhir.r_reg = TXP_H2A_1; 966 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 967 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 968 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 969 for (i = 0; i < TX_ENTRIES; i++) { 970 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 971 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 972 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 973 for (j = 0; j < i; j++) { 974 bus_dmamap_destroy(sc->sc_dmat, 975 sc->sc_txd[j].sd_map); 976 sc->sc_txd[j].sd_map = NULL; 977 } 978 goto bail_txhiring; 979 } 980 } 981 982 /* low priority tx ring */ 983 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 984 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 985 printf(": can't allocate low tx ring\n"); 986 goto bail_txhiring; 987 } 988 memset(sc->sc_txloring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 989 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 990 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 991 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 992 sc->sc_txlor.r_reg = TXP_H2A_3; 993 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 994 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 995 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 996 997 /* high priority rx ring */ 998 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 999 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1000 printf(": can't allocate high rx ring\n"); 1001 goto bail_txloring; 1002 } 1003 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1004 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1005 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1006 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1007 sc->sc_rxhir.r_desc = 1008 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1009 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1010 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1011 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1012 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1013 1014 /* low priority ring */ 1015 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1016 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1017 printf(": can't allocate low rx ring\n"); 1018 goto bail_rxhiring; 1019 } 1020 memset(sc->sc_rxloring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1021 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1022 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1023 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1024 sc->sc_rxlor.r_desc = 1025 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1026 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1027 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1028 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1029 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1030 1031 /* command ring */ 1032 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1033 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1034 printf(": can't allocate command ring\n"); 1035 goto bail_rxloring; 1036 } 1037 memset(sc->sc_cmdring_dma.dma_vaddr, 0, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1038 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1039 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1040 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1041 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1042 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1043 sc->sc_cmdring.lastwrite = 0; 1044 1045 /* response ring */ 1046 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1047 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1048 printf(": can't allocate response ring\n"); 1049 goto bail_cmdring; 1050 } 1051 memset(sc->sc_rspring_dma.dma_vaddr, 0, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1052 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1053 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1054 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1055 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1056 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1057 sc->sc_rspring.lastwrite = 0; 1058 1059 /* receive buffer ring */ 1060 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1061 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1062 printf(": can't allocate rx buffer ring\n"); 1063 goto bail_rspring; 1064 } 1065 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1066 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1067 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1068 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1069 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1070 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1071 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1072 M_DEVBUF, M_NOWAIT); 1073 /* stash away pointer */ 1074 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, sizeof(sd)); 1075 if (sd == NULL) 1076 break; 1077 1078 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1079 if (sd->sd_mbuf == NULL) { 1080 goto bail_rxbufring; 1081 } 1082 1083 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1084 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1085 goto bail_rxbufring; 1086 } 1087 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1088 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1089 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1090 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1091 goto bail_rxbufring; 1092 } 1093 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1094 BUS_DMA_NOWAIT)) { 1095 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1096 goto bail_rxbufring; 1097 } 1098 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1099 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1100 1101 1102 sc->sc_rxbufs[nb].rb_paddrlo = 1103 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1104 sc->sc_rxbufs[nb].rb_paddrhi = 1105 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1106 } 1107 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1108 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1109 BUS_DMASYNC_PREWRITE); 1110 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1111 sizeof(struct txp_rxbuf_desc)); 1112 1113 /* zero dma */ 1114 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1115 BUS_DMA_COHERENT)) { 1116 printf(": can't allocate response ring\n"); 1117 goto bail_rxbufring; 1118 } 1119 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1120 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1121 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1122 1123 /* See if it's waiting for boot, and try to boot it */ 1124 for (i = 0; i < 10000; i++) { 1125 r = READ_REG(sc, TXP_A2H_0); 1126 if (r == STAT_WAITING_FOR_BOOT) 1127 break; 1128 DELAY(50); 1129 } 1130 if (r != STAT_WAITING_FOR_BOOT) { 1131 printf(": not waiting for boot\n"); 1132 goto bail; 1133 } 1134 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1135 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1136 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1137 1138 /* See if it booted */ 1139 for (i = 0; i < 10000; i++) { 1140 r = READ_REG(sc, TXP_A2H_0); 1141 if (r == STAT_RUNNING) 1142 break; 1143 DELAY(50); 1144 } 1145 if (r != STAT_RUNNING) { 1146 printf(": fw not running\n"); 1147 goto bail; 1148 } 1149 1150 /* Clear TX and CMD ring write registers */ 1151 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1152 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1153 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1154 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1155 1156 return (0); 1157 1158 bail: 1159 txp_dma_free(sc, &sc->sc_zero_dma); 1160 bail_rxbufring: 1161 if (nb == RXBUF_ENTRIES) 1162 nb--; 1163 for (i = 0; i <= nb; i++) { 1164 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1165 sizeof(sd)); 1166 if (sd) 1167 free(sd, M_DEVBUF); 1168 } 1169 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1170 bail_rspring: 1171 txp_dma_free(sc, &sc->sc_rspring_dma); 1172 bail_cmdring: 1173 txp_dma_free(sc, &sc->sc_cmdring_dma); 1174 bail_rxloring: 1175 txp_dma_free(sc, &sc->sc_rxloring_dma); 1176 bail_rxhiring: 1177 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1178 bail_txloring: 1179 txp_dma_free(sc, &sc->sc_txloring_dma); 1180 bail_txhiring: 1181 txp_dma_free(sc, &sc->sc_txhiring_dma); 1182 bail_host: 1183 txp_dma_free(sc, &sc->sc_host_dma); 1184 bail_boot: 1185 txp_dma_free(sc, &sc->sc_boot_dma); 1186 return (-1); 1187 } 1188 1189 int 1190 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, struct txp_dma_alloc *dma, int mapflags) 1191 { 1192 int r; 1193 1194 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1195 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1196 goto fail_0; 1197 1198 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1199 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1200 goto fail_1; 1201 1202 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1203 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1204 goto fail_2; 1205 1206 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1207 size, NULL, BUS_DMA_NOWAIT)) != 0) 1208 goto fail_3; 1209 1210 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1211 return (0); 1212 1213 fail_3: 1214 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1215 fail_2: 1216 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1217 fail_1: 1218 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1219 fail_0: 1220 return (r); 1221 } 1222 1223 void 1224 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1225 { 1226 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1227 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1228 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1229 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1230 } 1231 1232 int 1233 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1234 { 1235 struct txp_softc *sc = ifp->if_softc; 1236 struct ifreq *ifr = (struct ifreq *)data; 1237 struct ifaddr *ifa = (struct ifaddr *)data; 1238 int s, error = 0; 1239 1240 s = splnet(); 1241 1242 #if 0 1243 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1244 splx(s); 1245 return error; 1246 } 1247 #endif 1248 1249 switch(command) { 1250 case SIOCINITIFADDR: 1251 ifp->if_flags |= IFF_UP; 1252 txp_init(sc); 1253 switch (ifa->ifa_addr->sa_family) { 1254 #ifdef INET 1255 case AF_INET: 1256 arp_ifinit(ifp, ifa); 1257 break; 1258 #endif /* INET */ 1259 default: 1260 break; 1261 } 1262 break; 1263 case SIOCSIFFLAGS: 1264 if ((error = ifioctl_common(ifp, command, data)) != 0) 1265 break; 1266 if (ifp->if_flags & IFF_UP) { 1267 txp_init(sc); 1268 } else { 1269 if (ifp->if_flags & IFF_RUNNING) 1270 txp_stop(sc); 1271 } 1272 break; 1273 case SIOCADDMULTI: 1274 case SIOCDELMULTI: 1275 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1276 break; 1277 1278 error = 0; 1279 1280 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1281 ; 1282 else if (ifp->if_flags & IFF_RUNNING) { 1283 /* 1284 * Multicast list has changed; set the hardware 1285 * filter accordingly. 1286 */ 1287 txp_set_filter(sc); 1288 } 1289 break; 1290 case SIOCGIFMEDIA: 1291 case SIOCSIFMEDIA: 1292 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1293 break; 1294 default: 1295 error = ether_ioctl(ifp, command, data); 1296 break; 1297 } 1298 1299 splx(s); 1300 1301 return(error); 1302 } 1303 1304 void 1305 txp_init(struct txp_softc *sc) 1306 { 1307 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1308 int s; 1309 1310 txp_stop(sc); 1311 1312 s = splnet(); 1313 1314 txp_set_filter(sc); 1315 1316 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1317 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1318 1319 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1320 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1321 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1322 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1323 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1324 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1325 1326 ifp->if_flags |= IFF_RUNNING; 1327 ifp->if_flags &= ~IFF_OACTIVE; 1328 ifp->if_timer = 0; 1329 1330 if (!callout_pending(&sc->sc_tick)) 1331 callout_schedule(&sc->sc_tick, hz); 1332 1333 splx(s); 1334 } 1335 1336 void 1337 txp_tick(void *vsc) 1338 { 1339 struct txp_softc *sc = vsc; 1340 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1341 struct txp_rsp_desc *rsp = NULL; 1342 struct txp_ext_desc *ext; 1343 int s; 1344 1345 s = splnet(); 1346 txp_rxbuf_reclaim(sc); 1347 1348 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1349 &rsp, 1)) 1350 goto out; 1351 if (rsp->rsp_numdesc != 6) 1352 goto out; 1353 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1354 NULL, NULL, NULL, 1)) 1355 goto out; 1356 ext = (struct txp_ext_desc *)(rsp + 1); 1357 1358 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1359 ext[4].ext_1 + ext[4].ext_4; 1360 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1361 ext[2].ext_1; 1362 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1363 ext[1].ext_3; 1364 ifp->if_opackets += rsp->rsp_par2; 1365 ifp->if_ipackets += ext[2].ext_3; 1366 1367 out: 1368 if (rsp != NULL) 1369 free(rsp, M_DEVBUF); 1370 1371 splx(s); 1372 callout_schedule(&sc->sc_tick, hz); 1373 } 1374 1375 void 1376 txp_start(struct ifnet *ifp) 1377 { 1378 struct txp_softc *sc = ifp->if_softc; 1379 struct txp_tx_ring *r = &sc->sc_txhir; 1380 struct txp_tx_desc *txd; 1381 int txdidx; 1382 struct txp_frag_desc *fxd; 1383 struct mbuf *m, *mnew; 1384 struct txp_swdesc *sd; 1385 u_int32_t firstprod, firstcnt, prod, cnt, i; 1386 struct m_tag *mtag; 1387 1388 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1389 return; 1390 1391 prod = r->r_prod; 1392 cnt = r->r_cnt; 1393 1394 while (1) { 1395 IFQ_POLL(&ifp->if_snd, m); 1396 if (m == NULL) 1397 break; 1398 mnew = NULL; 1399 1400 firstprod = prod; 1401 firstcnt = cnt; 1402 1403 sd = sc->sc_txd + prod; 1404 sd->sd_mbuf = m; 1405 1406 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1407 BUS_DMA_NOWAIT)) { 1408 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1409 if (mnew == NULL) 1410 goto oactive1; 1411 if (m->m_pkthdr.len > MHLEN) { 1412 MCLGET(mnew, M_DONTWAIT); 1413 if ((mnew->m_flags & M_EXT) == 0) { 1414 m_freem(mnew); 1415 goto oactive1; 1416 } 1417 } 1418 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1419 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1420 IFQ_DEQUEUE(&ifp->if_snd, m); 1421 m_freem(m); 1422 m = mnew; 1423 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1424 BUS_DMA_NOWAIT)) 1425 goto oactive1; 1426 } 1427 1428 if ((TX_ENTRIES - cnt) < 4) 1429 goto oactive; 1430 1431 txd = r->r_desc + prod; 1432 txdidx = prod; 1433 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1434 txd->tx_numdesc = 0; 1435 txd->tx_addrlo = 0; 1436 txd->tx_addrhi = 0; 1437 txd->tx_totlen = m->m_pkthdr.len; 1438 txd->tx_pflags = 0; 1439 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1440 1441 if (++prod == TX_ENTRIES) 1442 prod = 0; 1443 1444 if (++cnt >= (TX_ENTRIES - 4)) 1445 goto oactive; 1446 1447 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1448 txd->tx_pflags = TX_PFLAGS_VLAN | 1449 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1450 1451 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1452 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1453 #ifdef TRY_TX_TCP_CSUM 1454 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1455 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1456 #endif 1457 #ifdef TRY_TX_UDP_CSUM 1458 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1459 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1460 #endif 1461 1462 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1463 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1464 1465 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1466 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1467 if (++cnt >= (TX_ENTRIES - 4)) { 1468 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1469 0, sd->sd_map->dm_mapsize, 1470 BUS_DMASYNC_POSTWRITE); 1471 goto oactive; 1472 } 1473 1474 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1475 FRAG_FLAGS_VALID; 1476 fxd->frag_rsvd1 = 0; 1477 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1478 fxd->frag_addrlo = 1479 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1480 0xffffffff; 1481 fxd->frag_addrhi = 1482 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1483 32; 1484 fxd->frag_rsvd2 = 0; 1485 1486 bus_dmamap_sync(sc->sc_dmat, 1487 sc->sc_txhiring_dma.dma_map, 1488 prod * sizeof(struct txp_frag_desc), 1489 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1490 1491 if (++prod == TX_ENTRIES) { 1492 fxd = (struct txp_frag_desc *)r->r_desc; 1493 prod = 0; 1494 } else 1495 fxd++; 1496 1497 } 1498 1499 /* 1500 * if mnew isn't NULL, we already dequeued and copied 1501 * the packet. 1502 */ 1503 if (mnew == NULL) 1504 IFQ_DEQUEUE(&ifp->if_snd, m); 1505 1506 ifp->if_timer = 5; 1507 1508 bpf_mtap(ifp, m); 1509 1510 txd->tx_flags |= TX_FLAGS_VALID; 1511 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1512 txdidx * sizeof(struct txp_tx_desc), 1513 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1514 1515 #if 0 1516 { 1517 struct mbuf *mx; 1518 int i; 1519 1520 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1521 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1522 txd->tx_pflags); 1523 for (mx = m; mx != NULL; mx = mx->m_next) { 1524 for (i = 0; i < mx->m_len; i++) { 1525 printf(":%02x", 1526 (u_int8_t)m->m_data[i]); 1527 } 1528 } 1529 printf("\n"); 1530 } 1531 #endif 1532 1533 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1534 } 1535 1536 r->r_prod = prod; 1537 r->r_cnt = cnt; 1538 return; 1539 1540 oactive: 1541 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1542 oactive1: 1543 ifp->if_flags |= IFF_OACTIVE; 1544 r->r_prod = firstprod; 1545 r->r_cnt = firstcnt; 1546 } 1547 1548 /* 1549 * Handle simple commands sent to the typhoon 1550 */ 1551 int 1552 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1553 { 1554 struct txp_rsp_desc *rsp = NULL; 1555 1556 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1557 return (-1); 1558 1559 if (!wait) 1560 return (0); 1561 1562 if (out1 != NULL) 1563 *out1 = le16toh(rsp->rsp_par1); 1564 if (out2 != NULL) 1565 *out2 = le32toh(rsp->rsp_par2); 1566 if (out3 != NULL) 1567 *out3 = le32toh(rsp->rsp_par3); 1568 free(rsp, M_DEVBUF); 1569 return (0); 1570 } 1571 1572 int 1573 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, struct txp_rsp_desc **rspp, int wait) 1574 { 1575 struct txp_hostvar *hv = sc->sc_hostvar; 1576 struct txp_cmd_desc *cmd; 1577 struct txp_ext_desc *ext; 1578 u_int32_t idx, i; 1579 u_int16_t seq; 1580 1581 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1582 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1583 return (-1); 1584 } 1585 1586 idx = sc->sc_cmdring.lastwrite; 1587 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1588 memset(cmd, 0, sizeof(*cmd)); 1589 1590 cmd->cmd_numdesc = in_extn; 1591 seq = sc->sc_seq++; 1592 cmd->cmd_seq = htole16(seq); 1593 cmd->cmd_id = htole16(id); 1594 cmd->cmd_par1 = htole16(in1); 1595 cmd->cmd_par2 = htole32(in2); 1596 cmd->cmd_par3 = htole32(in3); 1597 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1598 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1599 1600 idx += sizeof(struct txp_cmd_desc); 1601 if (idx == sc->sc_cmdring.size) 1602 idx = 0; 1603 1604 for (i = 0; i < in_extn; i++) { 1605 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1606 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1607 in_extp++; 1608 idx += sizeof(struct txp_cmd_desc); 1609 if (idx == sc->sc_cmdring.size) 1610 idx = 0; 1611 } 1612 1613 sc->sc_cmdring.lastwrite = idx; 1614 1615 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1616 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1617 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1618 1619 if (!wait) 1620 return (0); 1621 1622 for (i = 0; i < 10000; i++) { 1623 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1624 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1625 idx = le32toh(hv->hv_resp_read_idx); 1626 if (idx != le32toh(hv->hv_resp_write_idx)) { 1627 *rspp = NULL; 1628 if (txp_response(sc, idx, id, seq, rspp)) 1629 return (-1); 1630 if (*rspp != NULL) 1631 break; 1632 } 1633 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1634 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1635 DELAY(50); 1636 } 1637 if (i == 1000 || (*rspp) == NULL) { 1638 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1639 return (-1); 1640 } 1641 1642 return (0); 1643 } 1644 1645 int 1646 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, struct txp_rsp_desc **rspp) 1647 { 1648 struct txp_hostvar *hv = sc->sc_hostvar; 1649 struct txp_rsp_desc *rsp; 1650 1651 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1652 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1653 1654 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1655 *rspp = (struct txp_rsp_desc *)malloc( 1656 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1657 M_DEVBUF, M_NOWAIT); 1658 if ((*rspp) == NULL) 1659 return (-1); 1660 txp_rsp_fixup(sc, rsp, *rspp); 1661 return (0); 1662 } 1663 1664 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1665 printf("%s: response error: id 0x%x\n", 1666 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1667 txp_rsp_fixup(sc, rsp, NULL); 1668 ridx = le32toh(hv->hv_resp_read_idx); 1669 continue; 1670 } 1671 1672 switch (le16toh(rsp->rsp_id)) { 1673 case TXP_CMD_CYCLE_STATISTICS: 1674 case TXP_CMD_MEDIA_STATUS_READ: 1675 break; 1676 case TXP_CMD_HELLO_RESPONSE: 1677 printf("%s: hello\n", TXP_DEVNAME(sc)); 1678 break; 1679 default: 1680 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1681 le16toh(rsp->rsp_id)); 1682 } 1683 1684 txp_rsp_fixup(sc, rsp, NULL); 1685 ridx = le32toh(hv->hv_resp_read_idx); 1686 hv->hv_resp_read_idx = le32toh(ridx); 1687 } 1688 1689 return (0); 1690 } 1691 1692 void 1693 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, struct txp_rsp_desc *dst) 1694 { 1695 struct txp_rsp_desc *src = rsp; 1696 struct txp_hostvar *hv = sc->sc_hostvar; 1697 u_int32_t i, ridx; 1698 1699 ridx = le32toh(hv->hv_resp_read_idx); 1700 1701 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1702 if (dst != NULL) 1703 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1704 ridx += sizeof(struct txp_rsp_desc); 1705 if (ridx == sc->sc_rspring.size) { 1706 src = sc->sc_rspring.base; 1707 ridx = 0; 1708 } else 1709 src++; 1710 sc->sc_rspring.lastwrite = ridx; 1711 hv->hv_resp_read_idx = htole32(ridx); 1712 } 1713 1714 hv->hv_resp_read_idx = htole32(ridx); 1715 } 1716 1717 int 1718 txp_cmd_desc_numfree(struct txp_softc *sc) 1719 { 1720 struct txp_hostvar *hv = sc->sc_hostvar; 1721 struct txp_boot_record *br = sc->sc_boot; 1722 u_int32_t widx, ridx, nfree; 1723 1724 widx = sc->sc_cmdring.lastwrite; 1725 ridx = le32toh(hv->hv_cmd_read_idx); 1726 1727 if (widx == ridx) { 1728 /* Ring is completely free */ 1729 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1730 } else { 1731 if (widx > ridx) 1732 nfree = le32toh(br->br_cmd_siz) - 1733 (widx - ridx + sizeof(struct txp_cmd_desc)); 1734 else 1735 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1736 } 1737 1738 return (nfree / sizeof(struct txp_cmd_desc)); 1739 } 1740 1741 void 1742 txp_stop(struct txp_softc *sc) 1743 { 1744 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1745 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1746 1747 if (callout_pending(&sc->sc_tick)) 1748 callout_stop(&sc->sc_tick); 1749 } 1750 1751 void 1752 txp_watchdog(struct ifnet *ifp) 1753 { 1754 } 1755 1756 int 1757 txp_ifmedia_upd(struct ifnet *ifp) 1758 { 1759 struct txp_softc *sc = ifp->if_softc; 1760 struct ifmedia *ifm = &sc->sc_ifmedia; 1761 u_int16_t new_xcvr; 1762 1763 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1764 return (EINVAL); 1765 1766 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1767 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1768 new_xcvr = TXP_XCVR_10_FDX; 1769 else 1770 new_xcvr = TXP_XCVR_10_HDX; 1771 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1772 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1773 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1774 new_xcvr = TXP_XCVR_100_FDX; 1775 else 1776 new_xcvr = TXP_XCVR_100_HDX; 1777 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1778 new_xcvr = TXP_XCVR_AUTO; 1779 } else 1780 return (EINVAL); 1781 1782 /* nothing to do */ 1783 if (sc->sc_xcvr == new_xcvr) 1784 return (0); 1785 1786 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1787 NULL, NULL, NULL, 0); 1788 sc->sc_xcvr = new_xcvr; 1789 1790 return (0); 1791 } 1792 1793 void 1794 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1795 { 1796 struct txp_softc *sc = ifp->if_softc; 1797 struct ifmedia *ifm = &sc->sc_ifmedia; 1798 u_int16_t bmsr, bmcr, anlpar; 1799 1800 ifmr->ifm_status = IFM_AVALID; 1801 ifmr->ifm_active = IFM_ETHER; 1802 1803 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1804 &bmsr, NULL, NULL, 1)) 1805 goto bail; 1806 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1807 &bmsr, NULL, NULL, 1)) 1808 goto bail; 1809 1810 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1811 &bmcr, NULL, NULL, 1)) 1812 goto bail; 1813 1814 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1815 &anlpar, NULL, NULL, 1)) 1816 goto bail; 1817 1818 if (bmsr & BMSR_LINK) 1819 ifmr->ifm_status |= IFM_ACTIVE; 1820 1821 if (bmcr & BMCR_ISO) { 1822 ifmr->ifm_active |= IFM_NONE; 1823 ifmr->ifm_status = 0; 1824 return; 1825 } 1826 1827 if (bmcr & BMCR_LOOP) 1828 ifmr->ifm_active |= IFM_LOOP; 1829 1830 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1831 if ((bmsr & BMSR_ACOMP) == 0) { 1832 ifmr->ifm_active |= IFM_NONE; 1833 return; 1834 } 1835 1836 if (anlpar & ANLPAR_TX_FD) 1837 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1838 else if (anlpar & ANLPAR_T4) 1839 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1840 else if (anlpar & ANLPAR_TX) 1841 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1842 else if (anlpar & ANLPAR_10_FD) 1843 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1844 else if (anlpar & ANLPAR_10) 1845 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1846 else 1847 ifmr->ifm_active |= IFM_NONE; 1848 } else 1849 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1850 return; 1851 1852 bail: 1853 ifmr->ifm_active |= IFM_NONE; 1854 ifmr->ifm_status &= ~IFM_AVALID; 1855 } 1856 1857 void 1858 txp_show_descriptor(void *d) 1859 { 1860 struct txp_cmd_desc *cmd = d; 1861 struct txp_rsp_desc *rsp = d; 1862 struct txp_tx_desc *txd = d; 1863 struct txp_frag_desc *frgd = d; 1864 1865 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1866 case CMD_FLAGS_TYPE_CMD: 1867 /* command descriptor */ 1868 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1869 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1870 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1871 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1872 break; 1873 case CMD_FLAGS_TYPE_RESP: 1874 /* response descriptor */ 1875 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1876 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1877 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1878 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1879 break; 1880 case CMD_FLAGS_TYPE_DATA: 1881 /* data header (assuming tx for now) */ 1882 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1883 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1884 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1885 break; 1886 case CMD_FLAGS_TYPE_FRAG: 1887 /* fragment descriptor */ 1888 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1889 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1890 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1891 break; 1892 default: 1893 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1894 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1895 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1896 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1897 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1898 break; 1899 } 1900 } 1901 1902 void 1903 txp_set_filter(struct txp_softc *sc) 1904 { 1905 struct ethercom *ac = &sc->sc_arpcom; 1906 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1907 u_int32_t crc, carry, hashbit, hash[2]; 1908 u_int16_t filter; 1909 u_int8_t octet; 1910 int i, j, mcnt = 0; 1911 struct ether_multi *enm; 1912 struct ether_multistep step; 1913 1914 if (ifp->if_flags & IFF_PROMISC) { 1915 filter = TXP_RXFILT_PROMISC; 1916 goto setit; 1917 } 1918 1919 again: 1920 filter = TXP_RXFILT_DIRECT; 1921 1922 if (ifp->if_flags & IFF_BROADCAST) 1923 filter |= TXP_RXFILT_BROADCAST; 1924 1925 if (ifp->if_flags & IFF_ALLMULTI) 1926 filter |= TXP_RXFILT_ALLMULTI; 1927 else { 1928 hash[0] = hash[1] = 0; 1929 1930 ETHER_FIRST_MULTI(step, ac, enm); 1931 while (enm != NULL) { 1932 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1933 /* 1934 * We must listen to a range of multicast 1935 * addresses. For now, just accept all 1936 * multicasts, rather than trying to set only 1937 * those filter bits needed to match the range. 1938 * (At this time, the only use of address 1939 * ranges is for IP multicast routing, for 1940 * which the range is big enough to require 1941 * all bits set.) 1942 */ 1943 ifp->if_flags |= IFF_ALLMULTI; 1944 goto again; 1945 } 1946 1947 mcnt++; 1948 crc = 0xffffffff; 1949 1950 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1951 octet = enm->enm_addrlo[i]; 1952 for (j = 0; j < 8; j++) { 1953 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1954 (octet & 1); 1955 crc <<= 1; 1956 octet >>= 1; 1957 if (carry) 1958 crc = (crc ^ TXP_POLYNOMIAL) | 1959 carry; 1960 } 1961 } 1962 hashbit = (u_int16_t)(crc & (64 - 1)); 1963 hash[hashbit / 32] |= (1 << hashbit % 32); 1964 ETHER_NEXT_MULTI(step, enm); 1965 } 1966 1967 if (mcnt > 0) { 1968 filter |= TXP_RXFILT_HASHMULTI; 1969 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1970 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1971 } 1972 } 1973 1974 setit: 1975 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1976 NULL, NULL, NULL, 1); 1977 } 1978 1979 void 1980 txp_capabilities(struct txp_softc *sc) 1981 { 1982 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1983 struct txp_rsp_desc *rsp = NULL; 1984 struct txp_ext_desc *ext; 1985 1986 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1987 goto out; 1988 1989 if (rsp->rsp_numdesc != 1) 1990 goto out; 1991 ext = (struct txp_ext_desc *)(rsp + 1); 1992 1993 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1994 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1995 1996 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1997 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1998 sc->sc_tx_capability |= OFFLOAD_VLAN; 1999 sc->sc_rx_capability |= OFFLOAD_VLAN; 2000 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2001 } 2002 2003 #if 0 2004 /* not ready yet */ 2005 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2006 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2007 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2008 ifp->if_capabilities |= IFCAP_IPSEC; 2009 } 2010 #endif 2011 2012 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2013 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2014 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2015 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2016 } 2017 2018 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2019 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2020 #ifdef TRY_TX_TCP_CSUM 2021 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2022 ifp->if_capabilities |= 2023 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2024 #endif 2025 } 2026 2027 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2028 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2029 #ifdef TRY_TX_UDP_CSUM 2030 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2031 ifp->if_capabilities |= 2032 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2033 #endif 2034 } 2035 2036 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2037 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2038 goto out; 2039 2040 out: 2041 if (rsp != NULL) 2042 free(rsp, M_DEVBUF); 2043 } 2044
Indexes created Tue Sep 30 20:09:53 GMT 2025