if_txp.c revision 1.42
1 /* $NetBSD: if_txp.c,v 1.42 2016/02/09 08:32:11 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.42 2016/02/09 08:32:11 ozaki-r Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #include <net/bpf.h> 66 67 #include <sys/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_txpreg.h> 76 77 #include <dev/microcode/typhoon/3c990img.h> 78 79 /* 80 * These currently break the 3c990 firmware, hopefully will be resolved 81 * at some point. 82 */ 83 #undef TRY_TX_UDP_CSUM 84 #undef TRY_TX_TCP_CSUM 85 86 int txp_probe(device_t, cfdata_t, void *); 87 void txp_attach(device_t, device_t, void *); 88 int txp_intr(void *); 89 void txp_tick(void *); 90 bool txp_shutdown(device_t, int); 91 int txp_ioctl(struct ifnet *, u_long, void *); 92 void txp_start(struct ifnet *); 93 void txp_stop(struct txp_softc *); 94 void txp_init(struct txp_softc *); 95 void txp_watchdog(struct ifnet *); 96 97 int txp_chip_init(struct txp_softc *); 98 int txp_reset_adapter(struct txp_softc *); 99 int txp_download_fw(struct txp_softc *); 100 int txp_download_fw_wait(struct txp_softc *); 101 int txp_download_fw_section(struct txp_softc *, 102 const struct txp_fw_section_header *, int); 103 int txp_alloc_rings(struct txp_softc *); 104 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 105 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 106 void txp_set_filter(struct txp_softc *); 107 108 int txp_cmd_desc_numfree(struct txp_softc *); 109 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 110 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 111 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 112 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 113 struct txp_rsp_desc **, int); 114 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 115 struct txp_rsp_desc **); 116 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 117 struct txp_rsp_desc *); 118 void txp_capabilities(struct txp_softc *); 119 120 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 int txp_ifmedia_upd(struct ifnet *); 122 void txp_show_descriptor(void *); 123 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 124 struct txp_dma_alloc *); 125 void txp_rxbuf_reclaim(struct txp_softc *); 126 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 127 struct txp_dma_alloc *); 128 129 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 130 NULL, NULL); 131 132 const struct txp_pci_match { 133 int vid, did, flags; 134 } txp_devices[] = { 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 143 }; 144 145 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 146 147 static const struct { 148 u_int16_t mask, value; 149 int flags; 150 } txp_subsysinfo[] = { 151 {0xf000, 0x2000, TXP_SERVERVERSION}, 152 {0x0100, 0x0100, TXP_FIBER}, 153 #if 0 /* information from 3com header, unused */ 154 {0x0010, 0x0010, /* secured firmware */}, 155 {0x0003, 0x0000, /* variable DES */}, 156 {0x0003, 0x0001, /* single DES - "95" */}, 157 {0x0003, 0x0002, /* triple DES - "97" */}, 158 #endif 159 }; 160 161 static const struct txp_pci_match * 162 txp_pcilookup(pcireg_t id) 163 { 164 int i; 165 166 for (i = 0; i < __arraycount(txp_devices); i++) 167 if (PCI_VENDOR(id) == txp_devices[i].vid && 168 PCI_PRODUCT(id) == txp_devices[i].did) 169 return &txp_devices[i]; 170 return (0); 171 } 172 173 int 174 txp_probe(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 178 if (txp_pcilookup(pa->pa_id)) 179 return (1); 180 return (0); 181 } 182 183 void 184 txp_attach(device_t parent, device_t self, void *aux) 185 { 186 struct txp_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr = NULL; 191 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 192 u_int32_t command; 193 u_int16_t p1; 194 u_int32_t p2; 195 u_char enaddr[6]; 196 const struct txp_pci_match *match; 197 u_int16_t subsys; 198 int i, flags; 199 char devinfo[256]; 200 char intrbuf[PCI_INTRSTR_LEN]; 201 202 sc->sc_dev = self; 203 sc->sc_cold = 1; 204 205 match = txp_pcilookup(pa->pa_id); 206 flags = match->flags; 207 if (match->flags & TXP_USESUBSYSTEM) { 208 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 209 PCI_SUBSYS_ID_REG)); 210 for (i = 0; 211 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 212 i++) 213 if ((subsys & txp_subsysinfo[i].mask) == 214 txp_subsysinfo[i].value) 215 flags |= txp_subsysinfo[i].flags; 216 } 217 sc->sc_flags = flags; 218 219 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 220 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 221 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 222 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, device_xname(sc->sc_dev)); 223 224 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 225 226 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 227 printf(": failed to enable bus mastering\n"); 228 return; 229 } 230 231 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 232 printf(": failed to enable memory mapping\n"); 233 return; 234 } 235 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 236 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 237 printf(": can't map mem space %d\n", 0); 238 return; 239 } 240 241 sc->sc_dmat = pa->pa_dmat; 242 243 /* 244 * Allocate our interrupt. 245 */ 246 if (pci_intr_map(pa, &ih)) { 247 printf(": couldn't map interrupt\n"); 248 return; 249 } 250 251 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 252 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 253 if (sc->sc_ih == NULL) { 254 printf(": couldn't establish interrupt"); 255 if (intrstr != NULL) 256 printf(" at %s", intrstr); 257 printf("\n"); 258 return; 259 } 260 printf(": interrupting at %s\n", intrstr); 261 262 if (txp_chip_init(sc)) 263 goto cleanupintr; 264 265 if (txp_download_fw(sc)) 266 goto cleanupintr; 267 268 if (txp_alloc_rings(sc)) 269 goto cleanupintr; 270 271 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 272 NULL, NULL, NULL, 1)) 273 goto cleanupintr; 274 275 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 276 &p1, &p2, NULL, 1)) 277 goto cleanupintr; 278 279 txp_set_filter(sc); 280 281 p1 = htole16(p1); 282 enaddr[0] = ((u_int8_t *)&p1)[1]; 283 enaddr[1] = ((u_int8_t *)&p1)[0]; 284 p2 = htole32(p2); 285 enaddr[2] = ((u_int8_t *)&p2)[3]; 286 enaddr[3] = ((u_int8_t *)&p2)[2]; 287 enaddr[4] = ((u_int8_t *)&p2)[1]; 288 enaddr[5] = ((u_int8_t *)&p2)[0]; 289 290 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 291 ether_sprintf(enaddr)); 292 sc->sc_cold = 0; 293 294 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 295 if (flags & TXP_FIBER) { 296 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 297 0, NULL); 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 301 0, NULL); 302 } else { 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 304 0, NULL); 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 314 0, NULL); 315 } 316 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 317 318 sc->sc_xcvr = TXP_XCVR_AUTO; 319 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 320 NULL, NULL, NULL, 0); 321 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 322 323 ifp->if_softc = sc; 324 ifp->if_mtu = ETHERMTU; 325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 326 ifp->if_ioctl = txp_ioctl; 327 ifp->if_start = txp_start; 328 ifp->if_watchdog = txp_watchdog; 329 ifp->if_baudrate = 10000000; 330 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 331 IFQ_SET_READY(&ifp->if_snd); 332 ifp->if_capabilities = 0; 333 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 334 335 txp_capabilities(sc); 336 337 callout_init(&sc->sc_tick, 0); 338 callout_setfunc(&sc->sc_tick, txp_tick, sc); 339 340 /* 341 * Attach us everywhere 342 */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 346 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 347 pmf_class_network_register(self, ifp); 348 else 349 aprint_error_dev(self, "couldn't establish power handler\n"); 350 351 return; 352 353 cleanupintr: 354 pci_intr_disestablish(pc,sc->sc_ih); 355 356 return; 357 358 } 359 360 int 361 txp_chip_init(struct txp_softc *sc) 362 { 363 /* disable interrupts */ 364 WRITE_REG(sc, TXP_IER, 0); 365 WRITE_REG(sc, TXP_IMR, 366 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 367 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 368 TXP_INT_LATCH); 369 370 /* ack all interrupts */ 371 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 372 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 376 377 if (txp_reset_adapter(sc)) 378 return (-1); 379 380 /* disable interrupts */ 381 WRITE_REG(sc, TXP_IER, 0); 382 WRITE_REG(sc, TXP_IMR, 383 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 384 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 385 TXP_INT_LATCH); 386 387 /* ack all interrupts */ 388 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 389 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 393 394 return (0); 395 } 396 397 int 398 txp_reset_adapter(struct txp_softc *sc) 399 { 400 u_int32_t r; 401 int i; 402 403 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 404 DELAY(1000); 405 WRITE_REG(sc, TXP_SRR, 0); 406 407 /* Should wait max 6 seconds */ 408 for (i = 0; i < 6000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_HOST_REQUEST) 411 break; 412 DELAY(1000); 413 } 414 415 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 416 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 417 return (-1); 418 } 419 420 return (0); 421 } 422 423 int 424 txp_download_fw(struct txp_softc *sc) 425 { 426 const struct txp_fw_file_header *fileheader; 427 const struct txp_fw_section_header *secthead; 428 int sect; 429 u_int32_t r, i, ier, imr; 430 431 ier = READ_REG(sc, TXP_IER); 432 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 433 434 imr = READ_REG(sc, TXP_IMR); 435 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 436 437 for (i = 0; i < 10000; i++) { 438 r = READ_REG(sc, TXP_A2H_0); 439 if (r == STAT_WAITING_FOR_HOST_REQUEST) 440 break; 441 DELAY(50); 442 } 443 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 444 printf(": not waiting for host request\n"); 445 return (-1); 446 } 447 448 /* Ack the status */ 449 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 450 451 fileheader = (const struct txp_fw_file_header *)tc990image; 452 if (memcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 453 printf(": fw invalid magic\n"); 454 return (-1); 455 } 456 457 /* Tell boot firmware to get ready for image */ 458 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 459 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 460 461 if (txp_download_fw_wait(sc)) { 462 printf("%s: fw wait failed, initial\n", device_xname(sc->sc_dev)); 463 return (-1); 464 } 465 466 secthead = (const struct txp_fw_section_header *) 467 (((const u_int8_t *)tc990image) + 468 sizeof(struct txp_fw_file_header)); 469 470 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 471 if (txp_download_fw_section(sc, secthead, sect)) 472 return (-1); 473 secthead = (const struct txp_fw_section_header *) 474 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 475 sizeof(*secthead)); 476 } 477 478 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 479 480 for (i = 0; i < 10000; i++) { 481 r = READ_REG(sc, TXP_A2H_0); 482 if (r == STAT_WAITING_FOR_BOOT) 483 break; 484 DELAY(50); 485 } 486 if (r != STAT_WAITING_FOR_BOOT) { 487 printf(": not waiting for boot\n"); 488 return (-1); 489 } 490 491 WRITE_REG(sc, TXP_IER, ier); 492 WRITE_REG(sc, TXP_IMR, imr); 493 494 return (0); 495 } 496 497 int 498 txp_download_fw_wait(struct txp_softc *sc) 499 { 500 u_int32_t i, r; 501 502 for (i = 0; i < 10000; i++) { 503 r = READ_REG(sc, TXP_ISR); 504 if (r & TXP_INT_A2H_0) 505 break; 506 DELAY(50); 507 } 508 509 if (!(r & TXP_INT_A2H_0)) { 510 printf(": fw wait failed comm0\n"); 511 return (-1); 512 } 513 514 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 515 516 r = READ_REG(sc, TXP_A2H_0); 517 if (r != STAT_WAITING_FOR_SEGMENT) { 518 printf(": fw not waiting for segment\n"); 519 return (-1); 520 } 521 return (0); 522 } 523 524 int 525 txp_download_fw_section(struct txp_softc *sc, const struct txp_fw_section_header *sect, int sectnum) 526 { 527 struct txp_dma_alloc dma; 528 int rseg, err = 0; 529 struct mbuf m; 530 #ifdef INET 531 u_int16_t csum; 532 #endif 533 534 /* Skip zero length sections */ 535 if (sect->nbytes == 0) 536 return (0); 537 538 /* Make sure we aren't past the end of the image */ 539 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 540 if (rseg >= sizeof(tc990image)) { 541 printf(": fw invalid section address, section %d\n", sectnum); 542 return (-1); 543 } 544 545 /* Make sure this section doesn't go past the end */ 546 rseg += le32toh(sect->nbytes); 547 if (rseg >= sizeof(tc990image)) { 548 printf(": fw truncated section %d\n", sectnum); 549 return (-1); 550 } 551 552 /* map a buffer, copy segment to it, get physaddr */ 553 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 554 printf(": fw dma malloc failed, section %d\n", sectnum); 555 return (-1); 556 } 557 558 memcpy(dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 559 le32toh(sect->nbytes)); 560 561 /* 562 * dummy up mbuf and verify section checksum 563 */ 564 m.m_type = MT_DATA; 565 m.m_next = m.m_nextpkt = NULL; 566 m.m_len = le32toh(sect->nbytes); 567 m.m_data = dma.dma_vaddr; 568 m.m_flags = 0; 569 #ifdef INET 570 csum = in_cksum(&m, le32toh(sect->nbytes)); 571 if (csum != sect->cksum) { 572 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 573 sectnum, sect->cksum, csum); 574 txp_dma_free(sc, &dma); 575 return -1; 576 } 577 #endif 578 579 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 580 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 581 582 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 583 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 584 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 585 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 586 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 587 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 588 589 if (txp_download_fw_wait(sc)) { 590 printf("%s: fw wait failed, section %d\n", 591 device_xname(sc->sc_dev), sectnum); 592 err = -1; 593 } 594 595 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 596 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 597 598 txp_dma_free(sc, &dma); 599 return (err); 600 } 601 602 int 603 txp_intr(void *vsc) 604 { 605 struct txp_softc *sc = vsc; 606 struct txp_hostvar *hv = sc->sc_hostvar; 607 u_int32_t isr; 608 int claimed = 0; 609 610 /* mask all interrupts */ 611 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 612 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 613 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 614 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 615 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 616 617 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 618 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 619 620 isr = READ_REG(sc, TXP_ISR); 621 while (isr) { 622 claimed = 1; 623 WRITE_REG(sc, TXP_ISR, isr); 624 625 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 626 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 627 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 628 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 629 630 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 631 txp_rxbuf_reclaim(sc); 632 633 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 634 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 635 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 636 637 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 638 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 639 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 640 641 isr = READ_REG(sc, TXP_ISR); 642 } 643 644 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 645 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 646 647 /* unmask all interrupts */ 648 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 649 650 txp_start(&sc->sc_arpcom.ec_if); 651 652 return (claimed); 653 } 654 655 void 656 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, struct txp_dma_alloc *dma) 657 { 658 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 659 struct txp_rx_desc *rxd; 660 struct mbuf *m; 661 struct txp_swdesc *sd; 662 u_int32_t roff, woff; 663 int sumflags = 0; 664 int idx; 665 666 roff = le32toh(*r->r_roff); 667 woff = le32toh(*r->r_woff); 668 idx = roff / sizeof(struct txp_rx_desc); 669 rxd = r->r_desc + idx; 670 671 while (roff != woff) { 672 673 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 674 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 675 BUS_DMASYNC_POSTREAD); 676 677 if (rxd->rx_flags & RX_FLAGS_ERROR) { 678 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 679 le32toh(rxd->rx_stat)); 680 ifp->if_ierrors++; 681 goto next; 682 } 683 684 /* retrieve stashed pointer */ 685 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 686 687 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 688 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 689 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 690 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 691 m = sd->sd_mbuf; 692 free(sd, M_DEVBUF); 693 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 694 695 #ifdef __STRICT_ALIGNMENT 696 { 697 /* 698 * XXX Nice chip, except it won't accept "off by 2" 699 * buffers, so we're force to copy. Supposedly 700 * this will be fixed in a newer firmware rev 701 * and this will be temporary. 702 */ 703 struct mbuf *mnew; 704 705 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 706 if (mnew == NULL) { 707 m_freem(m); 708 goto next; 709 } 710 if (m->m_len > (MHLEN - 2)) { 711 MCLGET(mnew, M_DONTWAIT); 712 if (!(mnew->m_flags & M_EXT)) { 713 m_freem(mnew); 714 m_freem(m); 715 goto next; 716 } 717 } 718 mnew->m_pkthdr.rcvif = ifp; 719 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 720 mnew->m_data += 2; 721 memcpy(mnew->m_data, m->m_data, m->m_len); 722 m_freem(m); 723 m = mnew; 724 } 725 #endif 726 727 /* 728 * Handle BPF listeners. Let the BPF user see the packet. 729 */ 730 bpf_mtap(ifp, m); 731 732 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 733 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 734 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 735 sumflags |= M_CSUM_IPv4; 736 737 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 738 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 739 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 740 sumflags |= M_CSUM_TCPv4; 741 742 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 743 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 744 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 745 sumflags |= M_CSUM_UDPv4; 746 747 m->m_pkthdr.csum_flags = sumflags; 748 749 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 750 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 751 continue); 752 } 753 754 if_percpuq_enqueue(ifp->if_percpuq, m); 755 756 next: 757 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 758 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 759 BUS_DMASYNC_PREREAD); 760 761 roff += sizeof(struct txp_rx_desc); 762 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 763 idx = 0; 764 roff = 0; 765 rxd = r->r_desc; 766 } else { 767 idx++; 768 rxd++; 769 } 770 woff = le32toh(*r->r_woff); 771 } 772 773 *r->r_roff = htole32(woff); 774 } 775 776 void 777 txp_rxbuf_reclaim(struct txp_softc *sc) 778 { 779 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 780 struct txp_hostvar *hv = sc->sc_hostvar; 781 struct txp_rxbuf_desc *rbd; 782 struct txp_swdesc *sd; 783 u_int32_t i, end; 784 785 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 786 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 787 788 if (++i == RXBUF_ENTRIES) 789 i = 0; 790 791 rbd = sc->sc_rxbufs + i; 792 793 while (i != end) { 794 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 795 M_DEVBUF, M_NOWAIT); 796 if (sd == NULL) 797 break; 798 799 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 800 if (sd->sd_mbuf == NULL) 801 goto err_sd; 802 803 MCLGET(sd->sd_mbuf, M_DONTWAIT); 804 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 805 goto err_mbuf; 806 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 807 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 808 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 809 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 810 goto err_mbuf; 811 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 812 BUS_DMA_NOWAIT)) { 813 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 814 goto err_mbuf; 815 } 816 817 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 818 i * sizeof(struct txp_rxbuf_desc), 819 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 820 821 /* stash away pointer */ 822 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 823 824 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 825 & 0xffffffff; 826 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 827 >> 32; 828 829 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 830 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 831 832 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 833 i * sizeof(struct txp_rxbuf_desc), 834 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 835 836 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 837 838 if (++i == RXBUF_ENTRIES) { 839 i = 0; 840 rbd = sc->sc_rxbufs; 841 } else 842 rbd++; 843 } 844 return; 845 846 err_mbuf: 847 m_freem(sd->sd_mbuf); 848 err_sd: 849 free(sd, M_DEVBUF); 850 } 851 852 /* 853 * Reclaim mbufs and entries from a transmit ring. 854 */ 855 void 856 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, struct txp_dma_alloc *dma) 857 { 858 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 859 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 860 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 861 struct txp_tx_desc *txd = r->r_desc + cons; 862 struct txp_swdesc *sd = sc->sc_txd + cons; 863 struct mbuf *m; 864 865 while (cons != idx) { 866 if (cnt == 0) 867 break; 868 869 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 870 cons * sizeof(struct txp_tx_desc), 871 sizeof(struct txp_tx_desc), 872 BUS_DMASYNC_POSTWRITE); 873 874 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 875 TX_FLAGS_TYPE_DATA) { 876 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 877 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 878 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 879 m = sd->sd_mbuf; 880 if (m != NULL) { 881 m_freem(m); 882 txd->tx_addrlo = 0; 883 txd->tx_addrhi = 0; 884 ifp->if_opackets++; 885 } 886 } 887 ifp->if_flags &= ~IFF_OACTIVE; 888 889 if (++cons == TX_ENTRIES) { 890 txd = r->r_desc; 891 cons = 0; 892 sd = sc->sc_txd; 893 } else { 894 txd++; 895 sd++; 896 } 897 898 cnt--; 899 } 900 901 r->r_cons = cons; 902 r->r_cnt = cnt; 903 if (cnt == 0) 904 ifp->if_timer = 0; 905 } 906 907 bool 908 txp_shutdown(device_t self, int howto) 909 { 910 struct txp_softc *sc; 911 912 sc = device_private(self); 913 914 /* mask all interrupts */ 915 WRITE_REG(sc, TXP_IMR, 916 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 917 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 918 TXP_INT_LATCH); 919 920 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 921 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 922 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 923 924 return true; 925 } 926 927 int 928 txp_alloc_rings(struct txp_softc *sc) 929 { 930 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 931 struct txp_boot_record *boot; 932 struct txp_swdesc *sd; 933 u_int32_t r; 934 int i, j, nb; 935 936 /* boot record */ 937 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 938 BUS_DMA_COHERENT)) { 939 printf(": can't allocate boot record\n"); 940 return (-1); 941 } 942 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 943 memset(boot, 0, sizeof(*boot)); 944 sc->sc_boot = boot; 945 946 /* host variables */ 947 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 948 BUS_DMA_COHERENT)) { 949 printf(": can't allocate host ring\n"); 950 goto bail_boot; 951 } 952 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 953 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 954 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 955 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 956 957 /* high priority tx ring */ 958 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 959 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 960 printf(": can't allocate high tx ring\n"); 961 goto bail_host; 962 } 963 memset(sc->sc_txhiring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 964 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 965 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 966 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 967 sc->sc_txhir.r_reg = TXP_H2A_1; 968 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 969 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 970 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 971 for (i = 0; i < TX_ENTRIES; i++) { 972 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 973 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 974 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 975 for (j = 0; j < i; j++) { 976 bus_dmamap_destroy(sc->sc_dmat, 977 sc->sc_txd[j].sd_map); 978 sc->sc_txd[j].sd_map = NULL; 979 } 980 goto bail_txhiring; 981 } 982 } 983 984 /* low priority tx ring */ 985 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 986 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 987 printf(": can't allocate low tx ring\n"); 988 goto bail_txhiring; 989 } 990 memset(sc->sc_txloring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 991 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 992 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 993 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 994 sc->sc_txlor.r_reg = TXP_H2A_3; 995 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 996 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 997 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 998 999 /* high priority rx ring */ 1000 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1001 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1002 printf(": can't allocate high rx ring\n"); 1003 goto bail_txloring; 1004 } 1005 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1006 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1007 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1008 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1009 sc->sc_rxhir.r_desc = 1010 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1011 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1012 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1013 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1014 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1015 1016 /* low priority ring */ 1017 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1018 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1019 printf(": can't allocate low rx ring\n"); 1020 goto bail_rxhiring; 1021 } 1022 memset(sc->sc_rxloring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1023 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1024 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1025 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1026 sc->sc_rxlor.r_desc = 1027 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1028 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1029 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1030 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1031 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1032 1033 /* command ring */ 1034 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1035 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1036 printf(": can't allocate command ring\n"); 1037 goto bail_rxloring; 1038 } 1039 memset(sc->sc_cmdring_dma.dma_vaddr, 0, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1040 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1041 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1042 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1043 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1044 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1045 sc->sc_cmdring.lastwrite = 0; 1046 1047 /* response ring */ 1048 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1049 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1050 printf(": can't allocate response ring\n"); 1051 goto bail_cmdring; 1052 } 1053 memset(sc->sc_rspring_dma.dma_vaddr, 0, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1054 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1055 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1056 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1057 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1058 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1059 sc->sc_rspring.lastwrite = 0; 1060 1061 /* receive buffer ring */ 1062 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1063 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1064 printf(": can't allocate rx buffer ring\n"); 1065 goto bail_rspring; 1066 } 1067 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1068 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1069 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1070 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1071 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1072 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1073 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1074 M_DEVBUF, M_NOWAIT); 1075 /* stash away pointer */ 1076 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, sizeof(sd)); 1077 if (sd == NULL) 1078 break; 1079 1080 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1081 if (sd->sd_mbuf == NULL) { 1082 goto bail_rxbufring; 1083 } 1084 1085 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1086 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1087 goto bail_rxbufring; 1088 } 1089 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1090 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1091 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1092 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1093 goto bail_rxbufring; 1094 } 1095 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1096 BUS_DMA_NOWAIT)) { 1097 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1098 goto bail_rxbufring; 1099 } 1100 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1101 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1102 1103 1104 sc->sc_rxbufs[nb].rb_paddrlo = 1105 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1106 sc->sc_rxbufs[nb].rb_paddrhi = 1107 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1108 } 1109 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1110 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1111 BUS_DMASYNC_PREWRITE); 1112 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1113 sizeof(struct txp_rxbuf_desc)); 1114 1115 /* zero dma */ 1116 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1117 BUS_DMA_COHERENT)) { 1118 printf(": can't allocate response ring\n"); 1119 goto bail_rxbufring; 1120 } 1121 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1122 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1123 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1124 1125 /* See if it's waiting for boot, and try to boot it */ 1126 for (i = 0; i < 10000; i++) { 1127 r = READ_REG(sc, TXP_A2H_0); 1128 if (r == STAT_WAITING_FOR_BOOT) 1129 break; 1130 DELAY(50); 1131 } 1132 if (r != STAT_WAITING_FOR_BOOT) { 1133 printf(": not waiting for boot\n"); 1134 goto bail; 1135 } 1136 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1137 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1138 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1139 1140 /* See if it booted */ 1141 for (i = 0; i < 10000; i++) { 1142 r = READ_REG(sc, TXP_A2H_0); 1143 if (r == STAT_RUNNING) 1144 break; 1145 DELAY(50); 1146 } 1147 if (r != STAT_RUNNING) { 1148 printf(": fw not running\n"); 1149 goto bail; 1150 } 1151 1152 /* Clear TX and CMD ring write registers */ 1153 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1154 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1155 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1156 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1157 1158 return (0); 1159 1160 bail: 1161 txp_dma_free(sc, &sc->sc_zero_dma); 1162 bail_rxbufring: 1163 if (nb == RXBUF_ENTRIES) 1164 nb--; 1165 for (i = 0; i <= nb; i++) { 1166 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1167 sizeof(sd)); 1168 if (sd) 1169 free(sd, M_DEVBUF); 1170 } 1171 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1172 bail_rspring: 1173 txp_dma_free(sc, &sc->sc_rspring_dma); 1174 bail_cmdring: 1175 txp_dma_free(sc, &sc->sc_cmdring_dma); 1176 bail_rxloring: 1177 txp_dma_free(sc, &sc->sc_rxloring_dma); 1178 bail_rxhiring: 1179 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1180 bail_txloring: 1181 txp_dma_free(sc, &sc->sc_txloring_dma); 1182 bail_txhiring: 1183 txp_dma_free(sc, &sc->sc_txhiring_dma); 1184 bail_host: 1185 txp_dma_free(sc, &sc->sc_host_dma); 1186 bail_boot: 1187 txp_dma_free(sc, &sc->sc_boot_dma); 1188 return (-1); 1189 } 1190 1191 int 1192 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, struct txp_dma_alloc *dma, int mapflags) 1193 { 1194 int r; 1195 1196 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1197 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1198 goto fail_0; 1199 1200 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1201 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1202 goto fail_1; 1203 1204 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1205 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1206 goto fail_2; 1207 1208 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1209 size, NULL, BUS_DMA_NOWAIT)) != 0) 1210 goto fail_3; 1211 1212 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1213 return (0); 1214 1215 fail_3: 1216 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1217 fail_2: 1218 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1219 fail_1: 1220 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1221 fail_0: 1222 return (r); 1223 } 1224 1225 void 1226 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1227 { 1228 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1229 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1230 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1231 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1232 } 1233 1234 int 1235 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1236 { 1237 struct txp_softc *sc = ifp->if_softc; 1238 struct ifreq *ifr = (struct ifreq *)data; 1239 struct ifaddr *ifa = (struct ifaddr *)data; 1240 int s, error = 0; 1241 1242 s = splnet(); 1243 1244 #if 0 1245 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1246 splx(s); 1247 return error; 1248 } 1249 #endif 1250 1251 switch(command) { 1252 case SIOCINITIFADDR: 1253 ifp->if_flags |= IFF_UP; 1254 txp_init(sc); 1255 switch (ifa->ifa_addr->sa_family) { 1256 #ifdef INET 1257 case AF_INET: 1258 arp_ifinit(ifp, ifa); 1259 break; 1260 #endif /* INET */ 1261 default: 1262 break; 1263 } 1264 break; 1265 case SIOCSIFFLAGS: 1266 if ((error = ifioctl_common(ifp, command, data)) != 0) 1267 break; 1268 if (ifp->if_flags & IFF_UP) { 1269 txp_init(sc); 1270 } else { 1271 if (ifp->if_flags & IFF_RUNNING) 1272 txp_stop(sc); 1273 } 1274 break; 1275 case SIOCADDMULTI: 1276 case SIOCDELMULTI: 1277 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1278 break; 1279 1280 error = 0; 1281 1282 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1283 ; 1284 else if (ifp->if_flags & IFF_RUNNING) { 1285 /* 1286 * Multicast list has changed; set the hardware 1287 * filter accordingly. 1288 */ 1289 txp_set_filter(sc); 1290 } 1291 break; 1292 case SIOCGIFMEDIA: 1293 case SIOCSIFMEDIA: 1294 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1295 break; 1296 default: 1297 error = ether_ioctl(ifp, command, data); 1298 break; 1299 } 1300 1301 splx(s); 1302 1303 return(error); 1304 } 1305 1306 void 1307 txp_init(struct txp_softc *sc) 1308 { 1309 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1310 int s; 1311 1312 txp_stop(sc); 1313 1314 s = splnet(); 1315 1316 txp_set_filter(sc); 1317 1318 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1319 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1320 1321 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1322 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1323 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1324 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1325 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1326 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1327 1328 ifp->if_flags |= IFF_RUNNING; 1329 ifp->if_flags &= ~IFF_OACTIVE; 1330 ifp->if_timer = 0; 1331 1332 if (!callout_pending(&sc->sc_tick)) 1333 callout_schedule(&sc->sc_tick, hz); 1334 1335 splx(s); 1336 } 1337 1338 void 1339 txp_tick(void *vsc) 1340 { 1341 struct txp_softc *sc = vsc; 1342 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1343 struct txp_rsp_desc *rsp = NULL; 1344 struct txp_ext_desc *ext; 1345 int s; 1346 1347 s = splnet(); 1348 txp_rxbuf_reclaim(sc); 1349 1350 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1351 &rsp, 1)) 1352 goto out; 1353 if (rsp->rsp_numdesc != 6) 1354 goto out; 1355 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1356 NULL, NULL, NULL, 1)) 1357 goto out; 1358 ext = (struct txp_ext_desc *)(rsp + 1); 1359 1360 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1361 ext[4].ext_1 + ext[4].ext_4; 1362 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1363 ext[2].ext_1; 1364 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1365 ext[1].ext_3; 1366 ifp->if_opackets += rsp->rsp_par2; 1367 ifp->if_ipackets += ext[2].ext_3; 1368 1369 out: 1370 if (rsp != NULL) 1371 free(rsp, M_DEVBUF); 1372 1373 splx(s); 1374 callout_schedule(&sc->sc_tick, hz); 1375 } 1376 1377 void 1378 txp_start(struct ifnet *ifp) 1379 { 1380 struct txp_softc *sc = ifp->if_softc; 1381 struct txp_tx_ring *r = &sc->sc_txhir; 1382 struct txp_tx_desc *txd; 1383 int txdidx; 1384 struct txp_frag_desc *fxd; 1385 struct mbuf *m, *mnew; 1386 struct txp_swdesc *sd; 1387 u_int32_t firstprod, firstcnt, prod, cnt, i; 1388 struct m_tag *mtag; 1389 1390 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1391 return; 1392 1393 prod = r->r_prod; 1394 cnt = r->r_cnt; 1395 1396 while (1) { 1397 IFQ_POLL(&ifp->if_snd, m); 1398 if (m == NULL) 1399 break; 1400 mnew = NULL; 1401 1402 firstprod = prod; 1403 firstcnt = cnt; 1404 1405 sd = sc->sc_txd + prod; 1406 sd->sd_mbuf = m; 1407 1408 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1409 BUS_DMA_NOWAIT)) { 1410 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1411 if (mnew == NULL) 1412 goto oactive1; 1413 if (m->m_pkthdr.len > MHLEN) { 1414 MCLGET(mnew, M_DONTWAIT); 1415 if ((mnew->m_flags & M_EXT) == 0) { 1416 m_freem(mnew); 1417 goto oactive1; 1418 } 1419 } 1420 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1421 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1422 IFQ_DEQUEUE(&ifp->if_snd, m); 1423 m_freem(m); 1424 m = mnew; 1425 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1426 BUS_DMA_NOWAIT)) 1427 goto oactive1; 1428 } 1429 1430 if ((TX_ENTRIES - cnt) < 4) 1431 goto oactive; 1432 1433 txd = r->r_desc + prod; 1434 txdidx = prod; 1435 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1436 txd->tx_numdesc = 0; 1437 txd->tx_addrlo = 0; 1438 txd->tx_addrhi = 0; 1439 txd->tx_totlen = m->m_pkthdr.len; 1440 txd->tx_pflags = 0; 1441 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1442 1443 if (++prod == TX_ENTRIES) 1444 prod = 0; 1445 1446 if (++cnt >= (TX_ENTRIES - 4)) 1447 goto oactive; 1448 1449 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1450 txd->tx_pflags = TX_PFLAGS_VLAN | 1451 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1452 1453 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1454 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1455 #ifdef TRY_TX_TCP_CSUM 1456 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1457 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1458 #endif 1459 #ifdef TRY_TX_UDP_CSUM 1460 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1461 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1462 #endif 1463 1464 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1465 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1466 1467 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1468 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1469 if (++cnt >= (TX_ENTRIES - 4)) { 1470 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1471 0, sd->sd_map->dm_mapsize, 1472 BUS_DMASYNC_POSTWRITE); 1473 goto oactive; 1474 } 1475 1476 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1477 FRAG_FLAGS_VALID; 1478 fxd->frag_rsvd1 = 0; 1479 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1480 fxd->frag_addrlo = 1481 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1482 0xffffffff; 1483 fxd->frag_addrhi = 1484 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1485 32; 1486 fxd->frag_rsvd2 = 0; 1487 1488 bus_dmamap_sync(sc->sc_dmat, 1489 sc->sc_txhiring_dma.dma_map, 1490 prod * sizeof(struct txp_frag_desc), 1491 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1492 1493 if (++prod == TX_ENTRIES) { 1494 fxd = (struct txp_frag_desc *)r->r_desc; 1495 prod = 0; 1496 } else 1497 fxd++; 1498 1499 } 1500 1501 /* 1502 * if mnew isn't NULL, we already dequeued and copied 1503 * the packet. 1504 */ 1505 if (mnew == NULL) 1506 IFQ_DEQUEUE(&ifp->if_snd, m); 1507 1508 ifp->if_timer = 5; 1509 1510 bpf_mtap(ifp, m); 1511 1512 txd->tx_flags |= TX_FLAGS_VALID; 1513 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1514 txdidx * sizeof(struct txp_tx_desc), 1515 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1516 1517 #if 0 1518 { 1519 struct mbuf *mx; 1520 int i; 1521 1522 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1523 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1524 txd->tx_pflags); 1525 for (mx = m; mx != NULL; mx = mx->m_next) { 1526 for (i = 0; i < mx->m_len; i++) { 1527 printf(":%02x", 1528 (u_int8_t)m->m_data[i]); 1529 } 1530 } 1531 printf("\n"); 1532 } 1533 #endif 1534 1535 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1536 } 1537 1538 r->r_prod = prod; 1539 r->r_cnt = cnt; 1540 return; 1541 1542 oactive: 1543 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1544 oactive1: 1545 ifp->if_flags |= IFF_OACTIVE; 1546 r->r_prod = firstprod; 1547 r->r_cnt = firstcnt; 1548 } 1549 1550 /* 1551 * Handle simple commands sent to the typhoon 1552 */ 1553 int 1554 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1555 { 1556 struct txp_rsp_desc *rsp = NULL; 1557 1558 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1559 return (-1); 1560 1561 if (!wait) 1562 return (0); 1563 1564 if (out1 != NULL) 1565 *out1 = le16toh(rsp->rsp_par1); 1566 if (out2 != NULL) 1567 *out2 = le32toh(rsp->rsp_par2); 1568 if (out3 != NULL) 1569 *out3 = le32toh(rsp->rsp_par3); 1570 free(rsp, M_DEVBUF); 1571 return (0); 1572 } 1573 1574 int 1575 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, struct txp_rsp_desc **rspp, int wait) 1576 { 1577 struct txp_hostvar *hv = sc->sc_hostvar; 1578 struct txp_cmd_desc *cmd; 1579 struct txp_ext_desc *ext; 1580 u_int32_t idx, i; 1581 u_int16_t seq; 1582 1583 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1584 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1585 return (-1); 1586 } 1587 1588 idx = sc->sc_cmdring.lastwrite; 1589 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1590 memset(cmd, 0, sizeof(*cmd)); 1591 1592 cmd->cmd_numdesc = in_extn; 1593 seq = sc->sc_seq++; 1594 cmd->cmd_seq = htole16(seq); 1595 cmd->cmd_id = htole16(id); 1596 cmd->cmd_par1 = htole16(in1); 1597 cmd->cmd_par2 = htole32(in2); 1598 cmd->cmd_par3 = htole32(in3); 1599 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1600 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1601 1602 idx += sizeof(struct txp_cmd_desc); 1603 if (idx == sc->sc_cmdring.size) 1604 idx = 0; 1605 1606 for (i = 0; i < in_extn; i++) { 1607 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1608 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1609 in_extp++; 1610 idx += sizeof(struct txp_cmd_desc); 1611 if (idx == sc->sc_cmdring.size) 1612 idx = 0; 1613 } 1614 1615 sc->sc_cmdring.lastwrite = idx; 1616 1617 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1618 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1619 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1620 1621 if (!wait) 1622 return (0); 1623 1624 for (i = 0; i < 10000; i++) { 1625 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1626 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1627 idx = le32toh(hv->hv_resp_read_idx); 1628 if (idx != le32toh(hv->hv_resp_write_idx)) { 1629 *rspp = NULL; 1630 if (txp_response(sc, idx, id, seq, rspp)) 1631 return (-1); 1632 if (*rspp != NULL) 1633 break; 1634 } 1635 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1636 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1637 DELAY(50); 1638 } 1639 if (i == 1000 || (*rspp) == NULL) { 1640 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1641 return (-1); 1642 } 1643 1644 return (0); 1645 } 1646 1647 int 1648 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, struct txp_rsp_desc **rspp) 1649 { 1650 struct txp_hostvar *hv = sc->sc_hostvar; 1651 struct txp_rsp_desc *rsp; 1652 1653 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1654 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1655 1656 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1657 *rspp = (struct txp_rsp_desc *)malloc( 1658 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1659 M_DEVBUF, M_NOWAIT); 1660 if ((*rspp) == NULL) 1661 return (-1); 1662 txp_rsp_fixup(sc, rsp, *rspp); 1663 return (0); 1664 } 1665 1666 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1667 printf("%s: response error: id 0x%x\n", 1668 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1669 txp_rsp_fixup(sc, rsp, NULL); 1670 ridx = le32toh(hv->hv_resp_read_idx); 1671 continue; 1672 } 1673 1674 switch (le16toh(rsp->rsp_id)) { 1675 case TXP_CMD_CYCLE_STATISTICS: 1676 case TXP_CMD_MEDIA_STATUS_READ: 1677 break; 1678 case TXP_CMD_HELLO_RESPONSE: 1679 printf("%s: hello\n", TXP_DEVNAME(sc)); 1680 break; 1681 default: 1682 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1683 le16toh(rsp->rsp_id)); 1684 } 1685 1686 txp_rsp_fixup(sc, rsp, NULL); 1687 ridx = le32toh(hv->hv_resp_read_idx); 1688 hv->hv_resp_read_idx = le32toh(ridx); 1689 } 1690 1691 return (0); 1692 } 1693 1694 void 1695 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, struct txp_rsp_desc *dst) 1696 { 1697 struct txp_rsp_desc *src = rsp; 1698 struct txp_hostvar *hv = sc->sc_hostvar; 1699 u_int32_t i, ridx; 1700 1701 ridx = le32toh(hv->hv_resp_read_idx); 1702 1703 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1704 if (dst != NULL) 1705 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1706 ridx += sizeof(struct txp_rsp_desc); 1707 if (ridx == sc->sc_rspring.size) { 1708 src = sc->sc_rspring.base; 1709 ridx = 0; 1710 } else 1711 src++; 1712 sc->sc_rspring.lastwrite = ridx; 1713 hv->hv_resp_read_idx = htole32(ridx); 1714 } 1715 1716 hv->hv_resp_read_idx = htole32(ridx); 1717 } 1718 1719 int 1720 txp_cmd_desc_numfree(struct txp_softc *sc) 1721 { 1722 struct txp_hostvar *hv = sc->sc_hostvar; 1723 struct txp_boot_record *br = sc->sc_boot; 1724 u_int32_t widx, ridx, nfree; 1725 1726 widx = sc->sc_cmdring.lastwrite; 1727 ridx = le32toh(hv->hv_cmd_read_idx); 1728 1729 if (widx == ridx) { 1730 /* Ring is completely free */ 1731 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1732 } else { 1733 if (widx > ridx) 1734 nfree = le32toh(br->br_cmd_siz) - 1735 (widx - ridx + sizeof(struct txp_cmd_desc)); 1736 else 1737 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1738 } 1739 1740 return (nfree / sizeof(struct txp_cmd_desc)); 1741 } 1742 1743 void 1744 txp_stop(struct txp_softc *sc) 1745 { 1746 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1747 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1748 1749 if (callout_pending(&sc->sc_tick)) 1750 callout_stop(&sc->sc_tick); 1751 } 1752 1753 void 1754 txp_watchdog(struct ifnet *ifp) 1755 { 1756 } 1757 1758 int 1759 txp_ifmedia_upd(struct ifnet *ifp) 1760 { 1761 struct txp_softc *sc = ifp->if_softc; 1762 struct ifmedia *ifm = &sc->sc_ifmedia; 1763 u_int16_t new_xcvr; 1764 1765 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1766 return (EINVAL); 1767 1768 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1769 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1770 new_xcvr = TXP_XCVR_10_FDX; 1771 else 1772 new_xcvr = TXP_XCVR_10_HDX; 1773 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1774 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1775 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1776 new_xcvr = TXP_XCVR_100_FDX; 1777 else 1778 new_xcvr = TXP_XCVR_100_HDX; 1779 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1780 new_xcvr = TXP_XCVR_AUTO; 1781 } else 1782 return (EINVAL); 1783 1784 /* nothing to do */ 1785 if (sc->sc_xcvr == new_xcvr) 1786 return (0); 1787 1788 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1789 NULL, NULL, NULL, 0); 1790 sc->sc_xcvr = new_xcvr; 1791 1792 return (0); 1793 } 1794 1795 void 1796 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1797 { 1798 struct txp_softc *sc = ifp->if_softc; 1799 struct ifmedia *ifm = &sc->sc_ifmedia; 1800 u_int16_t bmsr, bmcr, anlpar; 1801 1802 ifmr->ifm_status = IFM_AVALID; 1803 ifmr->ifm_active = IFM_ETHER; 1804 1805 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1806 &bmsr, NULL, NULL, 1)) 1807 goto bail; 1808 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1809 &bmsr, NULL, NULL, 1)) 1810 goto bail; 1811 1812 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1813 &bmcr, NULL, NULL, 1)) 1814 goto bail; 1815 1816 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1817 &anlpar, NULL, NULL, 1)) 1818 goto bail; 1819 1820 if (bmsr & BMSR_LINK) 1821 ifmr->ifm_status |= IFM_ACTIVE; 1822 1823 if (bmcr & BMCR_ISO) { 1824 ifmr->ifm_active |= IFM_NONE; 1825 ifmr->ifm_status = 0; 1826 return; 1827 } 1828 1829 if (bmcr & BMCR_LOOP) 1830 ifmr->ifm_active |= IFM_LOOP; 1831 1832 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1833 if ((bmsr & BMSR_ACOMP) == 0) { 1834 ifmr->ifm_active |= IFM_NONE; 1835 return; 1836 } 1837 1838 if (anlpar & ANLPAR_TX_FD) 1839 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1840 else if (anlpar & ANLPAR_T4) 1841 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1842 else if (anlpar & ANLPAR_TX) 1843 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1844 else if (anlpar & ANLPAR_10_FD) 1845 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1846 else if (anlpar & ANLPAR_10) 1847 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1848 else 1849 ifmr->ifm_active |= IFM_NONE; 1850 } else 1851 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1852 return; 1853 1854 bail: 1855 ifmr->ifm_active |= IFM_NONE; 1856 ifmr->ifm_status &= ~IFM_AVALID; 1857 } 1858 1859 void 1860 txp_show_descriptor(void *d) 1861 { 1862 struct txp_cmd_desc *cmd = d; 1863 struct txp_rsp_desc *rsp = d; 1864 struct txp_tx_desc *txd = d; 1865 struct txp_frag_desc *frgd = d; 1866 1867 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1868 case CMD_FLAGS_TYPE_CMD: 1869 /* command descriptor */ 1870 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1871 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1872 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1873 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1874 break; 1875 case CMD_FLAGS_TYPE_RESP: 1876 /* response descriptor */ 1877 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1878 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1879 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1880 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1881 break; 1882 case CMD_FLAGS_TYPE_DATA: 1883 /* data header (assuming tx for now) */ 1884 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1885 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1886 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1887 break; 1888 case CMD_FLAGS_TYPE_FRAG: 1889 /* fragment descriptor */ 1890 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1891 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1892 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1893 break; 1894 default: 1895 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1896 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1897 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1898 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1899 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1900 break; 1901 } 1902 } 1903 1904 void 1905 txp_set_filter(struct txp_softc *sc) 1906 { 1907 struct ethercom *ac = &sc->sc_arpcom; 1908 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1909 u_int32_t crc, carry, hashbit, hash[2]; 1910 u_int16_t filter; 1911 u_int8_t octet; 1912 int i, j, mcnt = 0; 1913 struct ether_multi *enm; 1914 struct ether_multistep step; 1915 1916 if (ifp->if_flags & IFF_PROMISC) { 1917 filter = TXP_RXFILT_PROMISC; 1918 goto setit; 1919 } 1920 1921 again: 1922 filter = TXP_RXFILT_DIRECT; 1923 1924 if (ifp->if_flags & IFF_BROADCAST) 1925 filter |= TXP_RXFILT_BROADCAST; 1926 1927 if (ifp->if_flags & IFF_ALLMULTI) 1928 filter |= TXP_RXFILT_ALLMULTI; 1929 else { 1930 hash[0] = hash[1] = 0; 1931 1932 ETHER_FIRST_MULTI(step, ac, enm); 1933 while (enm != NULL) { 1934 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1935 /* 1936 * We must listen to a range of multicast 1937 * addresses. For now, just accept all 1938 * multicasts, rather than trying to set only 1939 * those filter bits needed to match the range. 1940 * (At this time, the only use of address 1941 * ranges is for IP multicast routing, for 1942 * which the range is big enough to require 1943 * all bits set.) 1944 */ 1945 ifp->if_flags |= IFF_ALLMULTI; 1946 goto again; 1947 } 1948 1949 mcnt++; 1950 crc = 0xffffffff; 1951 1952 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1953 octet = enm->enm_addrlo[i]; 1954 for (j = 0; j < 8; j++) { 1955 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1956 (octet & 1); 1957 crc <<= 1; 1958 octet >>= 1; 1959 if (carry) 1960 crc = (crc ^ TXP_POLYNOMIAL) | 1961 carry; 1962 } 1963 } 1964 hashbit = (u_int16_t)(crc & (64 - 1)); 1965 hash[hashbit / 32] |= (1 << hashbit % 32); 1966 ETHER_NEXT_MULTI(step, enm); 1967 } 1968 1969 if (mcnt > 0) { 1970 filter |= TXP_RXFILT_HASHMULTI; 1971 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1972 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1973 } 1974 } 1975 1976 setit: 1977 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1978 NULL, NULL, NULL, 1); 1979 } 1980 1981 void 1982 txp_capabilities(struct txp_softc *sc) 1983 { 1984 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1985 struct txp_rsp_desc *rsp = NULL; 1986 struct txp_ext_desc *ext; 1987 1988 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1989 goto out; 1990 1991 if (rsp->rsp_numdesc != 1) 1992 goto out; 1993 ext = (struct txp_ext_desc *)(rsp + 1); 1994 1995 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1996 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1997 1998 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1999 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2000 sc->sc_tx_capability |= OFFLOAD_VLAN; 2001 sc->sc_rx_capability |= OFFLOAD_VLAN; 2002 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2003 } 2004 2005 #if 0 2006 /* not ready yet */ 2007 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2008 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2009 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2010 ifp->if_capabilities |= IFCAP_IPSEC; 2011 } 2012 #endif 2013 2014 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2015 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2016 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2017 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2018 } 2019 2020 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2021 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2022 #ifdef TRY_TX_TCP_CSUM 2023 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2024 ifp->if_capabilities |= 2025 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2026 #endif 2027 } 2028 2029 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2030 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2031 #ifdef TRY_TX_UDP_CSUM 2032 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2033 ifp->if_capabilities |= 2034 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2035 #endif 2036 } 2037 2038 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2039 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2040 goto out; 2041 2042 out: 2043 if (rsp != NULL) 2044 free(rsp, M_DEVBUF); 2045 } 2046
Indexes created Tue Sep 30 20:09:53 GMT 2025