if_txp.c revision 1.46
1 /* $NetBSD: if_txp.c,v 1.46 2016/12/08 01:12:01 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.46 2016/12/08 01:12:01 ozaki-r Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_types.h> 52 #include <net/if_ether.h> 53 #include <net/if_arp.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_inarp.h> 61 #endif 62 63 #include <net/if_media.h> 64 65 #include <net/bpf.h> 66 67 #include <sys/bus.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 75 #include <dev/pci/if_txpreg.h> 76 77 #include <dev/microcode/typhoon/3c990img.h> 78 79 /* 80 * These currently break the 3c990 firmware, hopefully will be resolved 81 * at some point. 82 */ 83 #undef TRY_TX_UDP_CSUM 84 #undef TRY_TX_TCP_CSUM 85 86 int txp_probe(device_t, cfdata_t, void *); 87 void txp_attach(device_t, device_t, void *); 88 int txp_intr(void *); 89 void txp_tick(void *); 90 bool txp_shutdown(device_t, int); 91 int txp_ioctl(struct ifnet *, u_long, void *); 92 void txp_start(struct ifnet *); 93 void txp_stop(struct txp_softc *); 94 void txp_init(struct txp_softc *); 95 void txp_watchdog(struct ifnet *); 96 97 int txp_chip_init(struct txp_softc *); 98 int txp_reset_adapter(struct txp_softc *); 99 int txp_download_fw(struct txp_softc *); 100 int txp_download_fw_wait(struct txp_softc *); 101 int txp_download_fw_section(struct txp_softc *, 102 const struct txp_fw_section_header *, int); 103 int txp_alloc_rings(struct txp_softc *); 104 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 105 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 106 void txp_set_filter(struct txp_softc *); 107 108 int txp_cmd_desc_numfree(struct txp_softc *); 109 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 110 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 111 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 112 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 113 struct txp_rsp_desc **, int); 114 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 115 struct txp_rsp_desc **); 116 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 117 struct txp_rsp_desc *); 118 void txp_capabilities(struct txp_softc *); 119 120 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 121 int txp_ifmedia_upd(struct ifnet *); 122 void txp_show_descriptor(void *); 123 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 124 struct txp_dma_alloc *); 125 void txp_rxbuf_reclaim(struct txp_softc *); 126 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 127 struct txp_dma_alloc *); 128 129 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 130 NULL, NULL); 131 132 const struct txp_pci_match { 133 int vid, did, flags; 134 } txp_devices[] = { 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 143 }; 144 145 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 146 147 static const struct { 148 u_int16_t mask, value; 149 int flags; 150 } txp_subsysinfo[] = { 151 {0xf000, 0x2000, TXP_SERVERVERSION}, 152 {0x0100, 0x0100, TXP_FIBER}, 153 #if 0 /* information from 3com header, unused */ 154 {0x0010, 0x0010, /* secured firmware */}, 155 {0x0003, 0x0000, /* variable DES */}, 156 {0x0003, 0x0001, /* single DES - "95" */}, 157 {0x0003, 0x0002, /* triple DES - "97" */}, 158 #endif 159 }; 160 161 static const struct txp_pci_match * 162 txp_pcilookup(pcireg_t id) 163 { 164 int i; 165 166 for (i = 0; i < __arraycount(txp_devices); i++) 167 if (PCI_VENDOR(id) == txp_devices[i].vid && 168 PCI_PRODUCT(id) == txp_devices[i].did) 169 return &txp_devices[i]; 170 return (0); 171 } 172 173 int 174 txp_probe(device_t parent, cfdata_t match, void *aux) 175 { 176 struct pci_attach_args *pa = aux; 177 178 if (txp_pcilookup(pa->pa_id)) 179 return (1); 180 return (0); 181 } 182 183 void 184 txp_attach(device_t parent, device_t self, void *aux) 185 { 186 struct txp_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pci_chipset_tag_t pc = pa->pa_pc; 189 pci_intr_handle_t ih; 190 const char *intrstr = NULL; 191 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 192 u_int32_t command; 193 u_int16_t p1; 194 u_int32_t p2; 195 u_char enaddr[6]; 196 const struct txp_pci_match *match; 197 u_int16_t subsys; 198 int i, flags; 199 char devinfo[256]; 200 char intrbuf[PCI_INTRSTR_LEN]; 201 202 sc->sc_dev = self; 203 sc->sc_cold = 1; 204 205 match = txp_pcilookup(pa->pa_id); 206 flags = match->flags; 207 if (match->flags & TXP_USESUBSYSTEM) { 208 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 209 PCI_SUBSYS_ID_REG)); 210 for (i = 0; 211 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 212 i++) 213 if ((subsys & txp_subsysinfo[i].mask) == 214 txp_subsysinfo[i].value) 215 flags |= txp_subsysinfo[i].flags; 216 } 217 sc->sc_flags = flags; 218 219 aprint_naive("\n"); 220 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 221 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 222 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 223 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 224 device_xname(sc->sc_dev)); 225 226 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 227 228 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 229 aprint_error(": failed to enable bus mastering\n"); 230 return; 231 } 232 233 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 234 aprint_error(": failed to enable memory mapping\n"); 235 return; 236 } 237 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 238 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 239 aprint_error(": can't map mem space %d\n", 0); 240 return; 241 } 242 243 sc->sc_dmat = pa->pa_dmat; 244 245 /* 246 * Allocate our interrupt. 247 */ 248 if (pci_intr_map(pa, &ih)) { 249 aprint_error(": couldn't map interrupt\n"); 250 return; 251 } 252 253 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 254 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 255 if (sc->sc_ih == NULL) { 256 aprint_error(": couldn't establish interrupt"); 257 if (intrstr != NULL) 258 aprint_normal(" at %s", intrstr); 259 aprint_normal("\n"); 260 return; 261 } 262 aprint_error(": interrupting at %s\n", intrstr); 263 264 if (txp_chip_init(sc)) 265 goto cleanupintr; 266 267 if (txp_download_fw(sc)) 268 goto cleanupintr; 269 270 if (txp_alloc_rings(sc)) 271 goto cleanupintr; 272 273 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 274 NULL, NULL, NULL, 1)) 275 goto cleanupintr; 276 277 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 278 &p1, &p2, NULL, 1)) 279 goto cleanupintr; 280 281 txp_set_filter(sc); 282 283 p1 = htole16(p1); 284 enaddr[0] = ((u_int8_t *)&p1)[1]; 285 enaddr[1] = ((u_int8_t *)&p1)[0]; 286 p2 = htole32(p2); 287 enaddr[2] = ((u_int8_t *)&p2)[3]; 288 enaddr[3] = ((u_int8_t *)&p2)[2]; 289 enaddr[4] = ((u_int8_t *)&p2)[1]; 290 enaddr[5] = ((u_int8_t *)&p2)[0]; 291 292 aprint_normal_dev(self, "Ethernet address %s\n", 293 ether_sprintf(enaddr)); 294 sc->sc_cold = 0; 295 296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 297 if (flags & TXP_FIBER) { 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 303 0, NULL); 304 } else { 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 316 0, NULL); 317 } 318 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 319 320 sc->sc_xcvr = TXP_XCVR_AUTO; 321 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 322 NULL, NULL, NULL, 0); 323 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 324 325 ifp->if_softc = sc; 326 ifp->if_mtu = ETHERMTU; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = txp_ioctl; 329 ifp->if_start = txp_start; 330 ifp->if_watchdog = txp_watchdog; 331 ifp->if_baudrate = 10000000; 332 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 333 IFQ_SET_READY(&ifp->if_snd); 334 ifp->if_capabilities = 0; 335 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 336 337 txp_capabilities(sc); 338 339 callout_init(&sc->sc_tick, 0); 340 callout_setfunc(&sc->sc_tick, txp_tick, sc); 341 342 /* 343 * Attach us everywhere 344 */ 345 if_attach(ifp); 346 if_deferred_start_init(ifp, NULL); 347 ether_ifattach(ifp, enaddr); 348 349 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 350 pmf_class_network_register(self, ifp); 351 else 352 aprint_error_dev(self, "couldn't establish power handler\n"); 353 354 return; 355 356 cleanupintr: 357 pci_intr_disestablish(pc,sc->sc_ih); 358 359 return; 360 361 } 362 363 int 364 txp_chip_init(struct txp_softc *sc) 365 { 366 /* disable interrupts */ 367 WRITE_REG(sc, TXP_IER, 0); 368 WRITE_REG(sc, TXP_IMR, 369 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 370 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 371 TXP_INT_LATCH); 372 373 /* ack all interrupts */ 374 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 375 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 376 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 377 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 378 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 379 380 if (txp_reset_adapter(sc)) 381 return (-1); 382 383 /* disable interrupts */ 384 WRITE_REG(sc, TXP_IER, 0); 385 WRITE_REG(sc, TXP_IMR, 386 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 387 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 388 TXP_INT_LATCH); 389 390 /* ack all interrupts */ 391 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 392 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 393 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 394 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 395 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 396 397 return (0); 398 } 399 400 int 401 txp_reset_adapter(struct txp_softc *sc) 402 { 403 u_int32_t r; 404 int i; 405 406 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 407 DELAY(1000); 408 WRITE_REG(sc, TXP_SRR, 0); 409 410 /* Should wait max 6 seconds */ 411 for (i = 0; i < 6000; i++) { 412 r = READ_REG(sc, TXP_A2H_0); 413 if (r == STAT_WAITING_FOR_HOST_REQUEST) 414 break; 415 DELAY(1000); 416 } 417 418 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 419 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 420 return (-1); 421 } 422 423 return (0); 424 } 425 426 int 427 txp_download_fw(struct txp_softc *sc) 428 { 429 const struct txp_fw_file_header *fileheader; 430 const struct txp_fw_section_header *secthead; 431 int sect; 432 u_int32_t r, i, ier, imr; 433 434 ier = READ_REG(sc, TXP_IER); 435 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 436 437 imr = READ_REG(sc, TXP_IMR); 438 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 439 440 for (i = 0; i < 10000; i++) { 441 r = READ_REG(sc, TXP_A2H_0); 442 if (r == STAT_WAITING_FOR_HOST_REQUEST) 443 break; 444 DELAY(50); 445 } 446 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 447 printf(": not waiting for host request\n"); 448 return (-1); 449 } 450 451 /* Ack the status */ 452 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 453 454 fileheader = (const struct txp_fw_file_header *)tc990image; 455 if (memcmp("TYPHOON", fileheader->magicid, 456 sizeof(fileheader->magicid))) { 457 printf(": fw invalid magic\n"); 458 return (-1); 459 } 460 461 /* Tell boot firmware to get ready for image */ 462 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 463 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 464 465 if (txp_download_fw_wait(sc)) { 466 printf("%s: fw wait failed, initial\n", 467 device_xname(sc->sc_dev)); 468 return (-1); 469 } 470 471 secthead = (const struct txp_fw_section_header *) 472 (((const u_int8_t *)tc990image) + 473 sizeof(struct txp_fw_file_header)); 474 475 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 476 if (txp_download_fw_section(sc, secthead, sect)) 477 return (-1); 478 secthead = (const struct txp_fw_section_header *) 479 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 480 sizeof(*secthead)); 481 } 482 483 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 484 485 for (i = 0; i < 10000; i++) { 486 r = READ_REG(sc, TXP_A2H_0); 487 if (r == STAT_WAITING_FOR_BOOT) 488 break; 489 DELAY(50); 490 } 491 if (r != STAT_WAITING_FOR_BOOT) { 492 printf(": not waiting for boot\n"); 493 return (-1); 494 } 495 496 WRITE_REG(sc, TXP_IER, ier); 497 WRITE_REG(sc, TXP_IMR, imr); 498 499 return (0); 500 } 501 502 int 503 txp_download_fw_wait(struct txp_softc *sc) 504 { 505 u_int32_t i, r; 506 507 for (i = 0; i < 10000; i++) { 508 r = READ_REG(sc, TXP_ISR); 509 if (r & TXP_INT_A2H_0) 510 break; 511 DELAY(50); 512 } 513 514 if (!(r & TXP_INT_A2H_0)) { 515 printf(": fw wait failed comm0\n"); 516 return (-1); 517 } 518 519 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 520 521 r = READ_REG(sc, TXP_A2H_0); 522 if (r != STAT_WAITING_FOR_SEGMENT) { 523 printf(": fw not waiting for segment\n"); 524 return (-1); 525 } 526 return (0); 527 } 528 529 int 530 txp_download_fw_section(struct txp_softc *sc, 531 const struct txp_fw_section_header *sect, int sectnum) 532 { 533 struct txp_dma_alloc dma; 534 int rseg, err = 0; 535 struct mbuf m; 536 #ifdef INET 537 u_int16_t csum; 538 #endif 539 540 /* Skip zero length sections */ 541 if (sect->nbytes == 0) 542 return (0); 543 544 /* Make sure we aren't past the end of the image */ 545 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 546 if (rseg >= sizeof(tc990image)) { 547 printf(": fw invalid section address, section %d\n", sectnum); 548 return (-1); 549 } 550 551 /* Make sure this section doesn't go past the end */ 552 rseg += le32toh(sect->nbytes); 553 if (rseg >= sizeof(tc990image)) { 554 printf(": fw truncated section %d\n", sectnum); 555 return (-1); 556 } 557 558 /* map a buffer, copy segment to it, get physaddr */ 559 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 560 printf(": fw dma malloc failed, section %d\n", sectnum); 561 return (-1); 562 } 563 564 memcpy(dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 565 le32toh(sect->nbytes)); 566 567 /* 568 * dummy up mbuf and verify section checksum 569 */ 570 m.m_type = MT_DATA; 571 m.m_next = m.m_nextpkt = NULL; 572 m.m_len = le32toh(sect->nbytes); 573 m.m_data = dma.dma_vaddr; 574 m.m_flags = 0; 575 #ifdef INET 576 csum = in_cksum(&m, le32toh(sect->nbytes)); 577 if (csum != sect->cksum) { 578 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 579 sectnum, sect->cksum, csum); 580 txp_dma_free(sc, &dma); 581 return -1; 582 } 583 #endif 584 585 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 586 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 587 588 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 589 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 590 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 591 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 592 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 593 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 594 595 if (txp_download_fw_wait(sc)) { 596 printf("%s: fw wait failed, section %d\n", 597 device_xname(sc->sc_dev), sectnum); 598 err = -1; 599 } 600 601 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 602 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 603 604 txp_dma_free(sc, &dma); 605 return (err); 606 } 607 608 int 609 txp_intr(void *vsc) 610 { 611 struct txp_softc *sc = vsc; 612 struct txp_hostvar *hv = sc->sc_hostvar; 613 u_int32_t isr; 614 int claimed = 0; 615 616 /* mask all interrupts */ 617 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 618 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 619 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 620 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 621 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 622 623 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 624 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 625 626 isr = READ_REG(sc, TXP_ISR); 627 while (isr) { 628 claimed = 1; 629 WRITE_REG(sc, TXP_ISR, isr); 630 631 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 632 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 633 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 635 636 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 637 txp_rxbuf_reclaim(sc); 638 639 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 640 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 641 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 642 643 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 644 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 645 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 646 647 isr = READ_REG(sc, TXP_ISR); 648 } 649 650 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 651 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 652 653 /* unmask all interrupts */ 654 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 655 656 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 657 658 return (claimed); 659 } 660 661 void 662 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 663 struct txp_dma_alloc *dma) 664 { 665 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 666 struct txp_rx_desc *rxd; 667 struct mbuf *m; 668 struct txp_swdesc *sd; 669 u_int32_t roff, woff; 670 int sumflags = 0; 671 int idx; 672 673 roff = le32toh(*r->r_roff); 674 woff = le32toh(*r->r_woff); 675 idx = roff / sizeof(struct txp_rx_desc); 676 rxd = r->r_desc + idx; 677 678 while (roff != woff) { 679 680 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 681 idx * sizeof(struct txp_rx_desc), 682 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 683 684 if (rxd->rx_flags & RX_FLAGS_ERROR) { 685 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 686 le32toh(rxd->rx_stat)); 687 ifp->if_ierrors++; 688 goto next; 689 } 690 691 /* retrieve stashed pointer */ 692 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 693 694 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 695 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 696 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 697 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 698 m = sd->sd_mbuf; 699 free(sd, M_DEVBUF); 700 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 701 702 #ifdef __STRICT_ALIGNMENT 703 { 704 /* 705 * XXX Nice chip, except it won't accept "off by 2" 706 * buffers, so we're force to copy. Supposedly 707 * this will be fixed in a newer firmware rev 708 * and this will be temporary. 709 */ 710 struct mbuf *mnew; 711 712 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 713 if (mnew == NULL) { 714 m_freem(m); 715 goto next; 716 } 717 if (m->m_len > (MHLEN - 2)) { 718 MCLGET(mnew, M_DONTWAIT); 719 if (!(mnew->m_flags & M_EXT)) { 720 m_freem(mnew); 721 m_freem(m); 722 goto next; 723 } 724 } 725 m_set_rcvif(mnew, ifp); 726 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 727 mnew->m_data += 2; 728 memcpy(mnew->m_data, m->m_data, m->m_len); 729 m_freem(m); 730 m = mnew; 731 } 732 #endif 733 734 /* 735 * Handle BPF listeners. Let the BPF user see the packet. 736 */ 737 bpf_mtap(ifp, m); 738 739 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 740 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 741 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 742 sumflags |= M_CSUM_IPv4; 743 744 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 745 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 746 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 747 sumflags |= M_CSUM_TCPv4; 748 749 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 750 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 751 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 752 sumflags |= M_CSUM_UDPv4; 753 754 m->m_pkthdr.csum_flags = sumflags; 755 756 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 757 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 758 continue); 759 } 760 761 if_percpuq_enqueue(ifp->if_percpuq, m); 762 763 next: 764 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 765 idx * sizeof(struct txp_rx_desc), 766 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 767 768 roff += sizeof(struct txp_rx_desc); 769 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 770 idx = 0; 771 roff = 0; 772 rxd = r->r_desc; 773 } else { 774 idx++; 775 rxd++; 776 } 777 woff = le32toh(*r->r_woff); 778 } 779 780 *r->r_roff = htole32(woff); 781 } 782 783 void 784 txp_rxbuf_reclaim(struct txp_softc *sc) 785 { 786 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 787 struct txp_hostvar *hv = sc->sc_hostvar; 788 struct txp_rxbuf_desc *rbd; 789 struct txp_swdesc *sd; 790 u_int32_t i, end; 791 792 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 793 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 794 795 if (++i == RXBUF_ENTRIES) 796 i = 0; 797 798 rbd = sc->sc_rxbufs + i; 799 800 while (i != end) { 801 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 802 M_DEVBUF, M_NOWAIT); 803 if (sd == NULL) 804 break; 805 806 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 807 if (sd->sd_mbuf == NULL) 808 goto err_sd; 809 810 MCLGET(sd->sd_mbuf, M_DONTWAIT); 811 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 812 goto err_mbuf; 813 m_set_rcvif(sd->sd_mbuf, ifp); 814 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 815 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 816 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 817 goto err_mbuf; 818 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 819 BUS_DMA_NOWAIT)) { 820 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 821 goto err_mbuf; 822 } 823 824 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 825 i * sizeof(struct txp_rxbuf_desc), 826 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 827 828 /* stash away pointer */ 829 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 830 831 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 832 & 0xffffffff; 833 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 834 >> 32; 835 836 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 837 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 838 839 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 840 i * sizeof(struct txp_rxbuf_desc), 841 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 842 843 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 844 845 if (++i == RXBUF_ENTRIES) { 846 i = 0; 847 rbd = sc->sc_rxbufs; 848 } else 849 rbd++; 850 } 851 return; 852 853 err_mbuf: 854 m_freem(sd->sd_mbuf); 855 err_sd: 856 free(sd, M_DEVBUF); 857 } 858 859 /* 860 * Reclaim mbufs and entries from a transmit ring. 861 */ 862 void 863 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 864 struct txp_dma_alloc *dma) 865 { 866 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 867 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 868 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 869 struct txp_tx_desc *txd = r->r_desc + cons; 870 struct txp_swdesc *sd = sc->sc_txd + cons; 871 struct mbuf *m; 872 873 while (cons != idx) { 874 if (cnt == 0) 875 break; 876 877 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 878 cons * sizeof(struct txp_tx_desc), 879 sizeof(struct txp_tx_desc), 880 BUS_DMASYNC_POSTWRITE); 881 882 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 883 TX_FLAGS_TYPE_DATA) { 884 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 885 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 886 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 887 m = sd->sd_mbuf; 888 if (m != NULL) { 889 m_freem(m); 890 txd->tx_addrlo = 0; 891 txd->tx_addrhi = 0; 892 ifp->if_opackets++; 893 } 894 } 895 ifp->if_flags &= ~IFF_OACTIVE; 896 897 if (++cons == TX_ENTRIES) { 898 txd = r->r_desc; 899 cons = 0; 900 sd = sc->sc_txd; 901 } else { 902 txd++; 903 sd++; 904 } 905 906 cnt--; 907 } 908 909 r->r_cons = cons; 910 r->r_cnt = cnt; 911 if (cnt == 0) 912 ifp->if_timer = 0; 913 } 914 915 bool 916 txp_shutdown(device_t self, int howto) 917 { 918 struct txp_softc *sc; 919 920 sc = device_private(self); 921 922 /* mask all interrupts */ 923 WRITE_REG(sc, TXP_IMR, 924 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 925 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 926 TXP_INT_LATCH); 927 928 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 929 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 930 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 931 932 return true; 933 } 934 935 int 936 txp_alloc_rings(struct txp_softc *sc) 937 { 938 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 939 struct txp_boot_record *boot; 940 struct txp_swdesc *sd; 941 u_int32_t r; 942 int i, j, nb; 943 944 /* boot record */ 945 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 946 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 947 printf(": can't allocate boot record\n"); 948 return (-1); 949 } 950 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 951 memset(boot, 0, sizeof(*boot)); 952 sc->sc_boot = boot; 953 954 /* host variables */ 955 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 956 BUS_DMA_COHERENT)) { 957 printf(": can't allocate host ring\n"); 958 goto bail_boot; 959 } 960 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 961 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 962 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 963 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 964 965 /* high priority tx ring */ 966 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 967 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 968 printf(": can't allocate high tx ring\n"); 969 goto bail_host; 970 } 971 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 972 sizeof(struct txp_tx_desc) * TX_ENTRIES); 973 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 974 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 975 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 976 sc->sc_txhir.r_reg = TXP_H2A_1; 977 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 978 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 979 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 980 for (i = 0; i < TX_ENTRIES; i++) { 981 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 982 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 983 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 984 for (j = 0; j < i; j++) { 985 bus_dmamap_destroy(sc->sc_dmat, 986 sc->sc_txd[j].sd_map); 987 sc->sc_txd[j].sd_map = NULL; 988 } 989 goto bail_txhiring; 990 } 991 } 992 993 /* low priority tx ring */ 994 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 995 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 996 printf(": can't allocate low tx ring\n"); 997 goto bail_txhiring; 998 } 999 memset(sc->sc_txloring_dma.dma_vaddr, 0, 1000 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1001 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1002 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1003 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1004 sc->sc_txlor.r_reg = TXP_H2A_3; 1005 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1006 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1007 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1008 1009 /* high priority rx ring */ 1010 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1011 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1012 printf(": can't allocate high rx ring\n"); 1013 goto bail_txloring; 1014 } 1015 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1016 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1017 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1018 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1019 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1020 sc->sc_rxhir.r_desc = 1021 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1022 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1023 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1024 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1025 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1026 1027 /* low priority ring */ 1028 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1029 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1030 printf(": can't allocate low rx ring\n"); 1031 goto bail_rxhiring; 1032 } 1033 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1034 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1035 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1036 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1037 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1038 sc->sc_rxlor.r_desc = 1039 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1040 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1041 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1042 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1043 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1044 1045 /* command ring */ 1046 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1047 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1048 printf(": can't allocate command ring\n"); 1049 goto bail_rxloring; 1050 } 1051 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1052 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1053 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1054 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1055 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1056 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1057 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1058 sc->sc_cmdring.lastwrite = 0; 1059 1060 /* response ring */ 1061 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1062 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1063 printf(": can't allocate response ring\n"); 1064 goto bail_cmdring; 1065 } 1066 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1067 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1068 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1069 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1070 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1071 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1072 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1073 sc->sc_rspring.lastwrite = 0; 1074 1075 /* receive buffer ring */ 1076 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1077 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1078 printf(": can't allocate rx buffer ring\n"); 1079 goto bail_rspring; 1080 } 1081 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1082 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1083 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1084 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1085 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1086 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1087 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1088 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1089 M_DEVBUF, M_NOWAIT); 1090 /* stash away pointer */ 1091 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1092 sizeof(sd)); 1093 if (sd == NULL) 1094 break; 1095 1096 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1097 if (sd->sd_mbuf == NULL) { 1098 goto bail_rxbufring; 1099 } 1100 1101 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1102 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1103 goto bail_rxbufring; 1104 } 1105 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1106 m_set_rcvif(sd->sd_mbuf, ifp); 1107 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1108 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1109 goto bail_rxbufring; 1110 } 1111 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1112 BUS_DMA_NOWAIT)) { 1113 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1114 goto bail_rxbufring; 1115 } 1116 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1117 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1118 1119 1120 sc->sc_rxbufs[nb].rb_paddrlo = 1121 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1122 sc->sc_rxbufs[nb].rb_paddrhi = 1123 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1124 } 1125 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1126 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1127 BUS_DMASYNC_PREWRITE); 1128 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1129 sizeof(struct txp_rxbuf_desc)); 1130 1131 /* zero dma */ 1132 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1133 BUS_DMA_COHERENT)) { 1134 printf(": can't allocate response ring\n"); 1135 goto bail_rxbufring; 1136 } 1137 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1138 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1139 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1140 1141 /* See if it's waiting for boot, and try to boot it */ 1142 for (i = 0; i < 10000; i++) { 1143 r = READ_REG(sc, TXP_A2H_0); 1144 if (r == STAT_WAITING_FOR_BOOT) 1145 break; 1146 DELAY(50); 1147 } 1148 if (r != STAT_WAITING_FOR_BOOT) { 1149 printf(": not waiting for boot\n"); 1150 goto bail; 1151 } 1152 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1153 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1154 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1155 1156 /* See if it booted */ 1157 for (i = 0; i < 10000; i++) { 1158 r = READ_REG(sc, TXP_A2H_0); 1159 if (r == STAT_RUNNING) 1160 break; 1161 DELAY(50); 1162 } 1163 if (r != STAT_RUNNING) { 1164 printf(": fw not running\n"); 1165 goto bail; 1166 } 1167 1168 /* Clear TX and CMD ring write registers */ 1169 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1170 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1171 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1172 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1173 1174 return (0); 1175 1176 bail: 1177 txp_dma_free(sc, &sc->sc_zero_dma); 1178 bail_rxbufring: 1179 if (nb == RXBUF_ENTRIES) 1180 nb--; 1181 for (i = 0; i <= nb; i++) { 1182 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1183 sizeof(sd)); 1184 if (sd) 1185 free(sd, M_DEVBUF); 1186 } 1187 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1188 bail_rspring: 1189 txp_dma_free(sc, &sc->sc_rspring_dma); 1190 bail_cmdring: 1191 txp_dma_free(sc, &sc->sc_cmdring_dma); 1192 bail_rxloring: 1193 txp_dma_free(sc, &sc->sc_rxloring_dma); 1194 bail_rxhiring: 1195 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1196 bail_txloring: 1197 txp_dma_free(sc, &sc->sc_txloring_dma); 1198 bail_txhiring: 1199 txp_dma_free(sc, &sc->sc_txhiring_dma); 1200 bail_host: 1201 txp_dma_free(sc, &sc->sc_host_dma); 1202 bail_boot: 1203 txp_dma_free(sc, &sc->sc_boot_dma); 1204 return (-1); 1205 } 1206 1207 int 1208 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1209 struct txp_dma_alloc *dma, int mapflags) 1210 { 1211 int r; 1212 1213 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1214 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1215 goto fail_0; 1216 1217 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1218 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1219 goto fail_1; 1220 1221 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1222 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1223 goto fail_2; 1224 1225 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1226 size, NULL, BUS_DMA_NOWAIT)) != 0) 1227 goto fail_3; 1228 1229 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1230 return (0); 1231 1232 fail_3: 1233 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1234 fail_2: 1235 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1236 fail_1: 1237 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1238 fail_0: 1239 return (r); 1240 } 1241 1242 void 1243 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1244 { 1245 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1246 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1247 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1248 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1249 } 1250 1251 int 1252 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1253 { 1254 struct txp_softc *sc = ifp->if_softc; 1255 struct ifreq *ifr = (struct ifreq *)data; 1256 struct ifaddr *ifa = (struct ifaddr *)data; 1257 int s, error = 0; 1258 1259 s = splnet(); 1260 1261 #if 0 1262 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1263 splx(s); 1264 return error; 1265 } 1266 #endif 1267 1268 switch(command) { 1269 case SIOCINITIFADDR: 1270 ifp->if_flags |= IFF_UP; 1271 txp_init(sc); 1272 switch (ifa->ifa_addr->sa_family) { 1273 #ifdef INET 1274 case AF_INET: 1275 arp_ifinit(ifp, ifa); 1276 break; 1277 #endif /* INET */ 1278 default: 1279 break; 1280 } 1281 break; 1282 case SIOCSIFFLAGS: 1283 if ((error = ifioctl_common(ifp, command, data)) != 0) 1284 break; 1285 if (ifp->if_flags & IFF_UP) { 1286 txp_init(sc); 1287 } else { 1288 if (ifp->if_flags & IFF_RUNNING) 1289 txp_stop(sc); 1290 } 1291 break; 1292 case SIOCADDMULTI: 1293 case SIOCDELMULTI: 1294 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1295 break; 1296 1297 error = 0; 1298 1299 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1300 ; 1301 else if (ifp->if_flags & IFF_RUNNING) { 1302 /* 1303 * Multicast list has changed; set the hardware 1304 * filter accordingly. 1305 */ 1306 txp_set_filter(sc); 1307 } 1308 break; 1309 case SIOCGIFMEDIA: 1310 case SIOCSIFMEDIA: 1311 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1312 break; 1313 default: 1314 error = ether_ioctl(ifp, command, data); 1315 break; 1316 } 1317 1318 splx(s); 1319 1320 return(error); 1321 } 1322 1323 void 1324 txp_init(struct txp_softc *sc) 1325 { 1326 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1327 int s; 1328 1329 txp_stop(sc); 1330 1331 s = splnet(); 1332 1333 txp_set_filter(sc); 1334 1335 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1336 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1337 1338 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1339 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1340 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1341 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1342 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1343 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1344 1345 ifp->if_flags |= IFF_RUNNING; 1346 ifp->if_flags &= ~IFF_OACTIVE; 1347 ifp->if_timer = 0; 1348 1349 if (!callout_pending(&sc->sc_tick)) 1350 callout_schedule(&sc->sc_tick, hz); 1351 1352 splx(s); 1353 } 1354 1355 void 1356 txp_tick(void *vsc) 1357 { 1358 struct txp_softc *sc = vsc; 1359 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1360 struct txp_rsp_desc *rsp = NULL; 1361 struct txp_ext_desc *ext; 1362 int s; 1363 1364 s = splnet(); 1365 txp_rxbuf_reclaim(sc); 1366 1367 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1368 &rsp, 1)) 1369 goto out; 1370 if (rsp->rsp_numdesc != 6) 1371 goto out; 1372 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1373 NULL, NULL, NULL, 1)) 1374 goto out; 1375 ext = (struct txp_ext_desc *)(rsp + 1); 1376 1377 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1378 ext[4].ext_1 + ext[4].ext_4; 1379 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1380 ext[2].ext_1; 1381 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1382 ext[1].ext_3; 1383 ifp->if_opackets += rsp->rsp_par2; 1384 ifp->if_ipackets += ext[2].ext_3; 1385 1386 out: 1387 if (rsp != NULL) 1388 free(rsp, M_DEVBUF); 1389 1390 splx(s); 1391 callout_schedule(&sc->sc_tick, hz); 1392 } 1393 1394 void 1395 txp_start(struct ifnet *ifp) 1396 { 1397 struct txp_softc *sc = ifp->if_softc; 1398 struct txp_tx_ring *r = &sc->sc_txhir; 1399 struct txp_tx_desc *txd; 1400 int txdidx; 1401 struct txp_frag_desc *fxd; 1402 struct mbuf *m, *mnew; 1403 struct txp_swdesc *sd; 1404 u_int32_t firstprod, firstcnt, prod, cnt, i; 1405 struct m_tag *mtag; 1406 1407 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1408 return; 1409 1410 prod = r->r_prod; 1411 cnt = r->r_cnt; 1412 1413 while (1) { 1414 IFQ_POLL(&ifp->if_snd, m); 1415 if (m == NULL) 1416 break; 1417 mnew = NULL; 1418 1419 firstprod = prod; 1420 firstcnt = cnt; 1421 1422 sd = sc->sc_txd + prod; 1423 sd->sd_mbuf = m; 1424 1425 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1426 BUS_DMA_NOWAIT)) { 1427 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1428 if (mnew == NULL) 1429 goto oactive1; 1430 if (m->m_pkthdr.len > MHLEN) { 1431 MCLGET(mnew, M_DONTWAIT); 1432 if ((mnew->m_flags & M_EXT) == 0) { 1433 m_freem(mnew); 1434 goto oactive1; 1435 } 1436 } 1437 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1438 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1439 IFQ_DEQUEUE(&ifp->if_snd, m); 1440 m_freem(m); 1441 m = mnew; 1442 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1443 BUS_DMA_NOWAIT)) 1444 goto oactive1; 1445 } 1446 1447 if ((TX_ENTRIES - cnt) < 4) 1448 goto oactive; 1449 1450 txd = r->r_desc + prod; 1451 txdidx = prod; 1452 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1453 txd->tx_numdesc = 0; 1454 txd->tx_addrlo = 0; 1455 txd->tx_addrhi = 0; 1456 txd->tx_totlen = m->m_pkthdr.len; 1457 txd->tx_pflags = 0; 1458 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1459 1460 if (++prod == TX_ENTRIES) 1461 prod = 0; 1462 1463 if (++cnt >= (TX_ENTRIES - 4)) 1464 goto oactive; 1465 1466 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1467 txd->tx_pflags = TX_PFLAGS_VLAN | 1468 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1469 1470 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1471 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1472 #ifdef TRY_TX_TCP_CSUM 1473 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1474 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1475 #endif 1476 #ifdef TRY_TX_UDP_CSUM 1477 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1478 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1479 #endif 1480 1481 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1482 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1483 1484 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1485 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1486 if (++cnt >= (TX_ENTRIES - 4)) { 1487 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1488 0, sd->sd_map->dm_mapsize, 1489 BUS_DMASYNC_POSTWRITE); 1490 goto oactive; 1491 } 1492 1493 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1494 FRAG_FLAGS_VALID; 1495 fxd->frag_rsvd1 = 0; 1496 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1497 fxd->frag_addrlo = 1498 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1499 0xffffffff; 1500 fxd->frag_addrhi = 1501 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1502 32; 1503 fxd->frag_rsvd2 = 0; 1504 1505 bus_dmamap_sync(sc->sc_dmat, 1506 sc->sc_txhiring_dma.dma_map, 1507 prod * sizeof(struct txp_frag_desc), 1508 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1509 1510 if (++prod == TX_ENTRIES) { 1511 fxd = (struct txp_frag_desc *)r->r_desc; 1512 prod = 0; 1513 } else 1514 fxd++; 1515 1516 } 1517 1518 /* 1519 * if mnew isn't NULL, we already dequeued and copied 1520 * the packet. 1521 */ 1522 if (mnew == NULL) 1523 IFQ_DEQUEUE(&ifp->if_snd, m); 1524 1525 ifp->if_timer = 5; 1526 1527 bpf_mtap(ifp, m); 1528 1529 txd->tx_flags |= TX_FLAGS_VALID; 1530 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1531 txdidx * sizeof(struct txp_tx_desc), 1532 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1533 1534 #if 0 1535 { 1536 struct mbuf *mx; 1537 int i; 1538 1539 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1540 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1541 txd->tx_pflags); 1542 for (mx = m; mx != NULL; mx = mx->m_next) { 1543 for (i = 0; i < mx->m_len; i++) { 1544 printf(":%02x", 1545 (u_int8_t)m->m_data[i]); 1546 } 1547 } 1548 printf("\n"); 1549 } 1550 #endif 1551 1552 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1553 } 1554 1555 r->r_prod = prod; 1556 r->r_cnt = cnt; 1557 return; 1558 1559 oactive: 1560 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1561 oactive1: 1562 ifp->if_flags |= IFF_OACTIVE; 1563 r->r_prod = firstprod; 1564 r->r_cnt = firstcnt; 1565 } 1566 1567 /* 1568 * Handle simple commands sent to the typhoon 1569 */ 1570 int 1571 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1572 u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1573 { 1574 struct txp_rsp_desc *rsp = NULL; 1575 1576 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1577 return (-1); 1578 1579 if (!wait) 1580 return (0); 1581 1582 if (out1 != NULL) 1583 *out1 = le16toh(rsp->rsp_par1); 1584 if (out2 != NULL) 1585 *out2 = le32toh(rsp->rsp_par2); 1586 if (out3 != NULL) 1587 *out3 = le32toh(rsp->rsp_par3); 1588 free(rsp, M_DEVBUF); 1589 return (0); 1590 } 1591 1592 int 1593 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, 1594 u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, 1595 struct txp_rsp_desc **rspp, int wait) 1596 { 1597 struct txp_hostvar *hv = sc->sc_hostvar; 1598 struct txp_cmd_desc *cmd; 1599 struct txp_ext_desc *ext; 1600 u_int32_t idx, i; 1601 u_int16_t seq; 1602 1603 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1604 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1605 return (-1); 1606 } 1607 1608 idx = sc->sc_cmdring.lastwrite; 1609 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1610 memset(cmd, 0, sizeof(*cmd)); 1611 1612 cmd->cmd_numdesc = in_extn; 1613 seq = sc->sc_seq++; 1614 cmd->cmd_seq = htole16(seq); 1615 cmd->cmd_id = htole16(id); 1616 cmd->cmd_par1 = htole16(in1); 1617 cmd->cmd_par2 = htole32(in2); 1618 cmd->cmd_par3 = htole32(in3); 1619 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1620 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1621 1622 idx += sizeof(struct txp_cmd_desc); 1623 if (idx == sc->sc_cmdring.size) 1624 idx = 0; 1625 1626 for (i = 0; i < in_extn; i++) { 1627 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1628 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1629 in_extp++; 1630 idx += sizeof(struct txp_cmd_desc); 1631 if (idx == sc->sc_cmdring.size) 1632 idx = 0; 1633 } 1634 1635 sc->sc_cmdring.lastwrite = idx; 1636 1637 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1638 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1639 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1640 1641 if (!wait) 1642 return (0); 1643 1644 for (i = 0; i < 10000; i++) { 1645 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1646 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1647 idx = le32toh(hv->hv_resp_read_idx); 1648 if (idx != le32toh(hv->hv_resp_write_idx)) { 1649 *rspp = NULL; 1650 if (txp_response(sc, idx, id, seq, rspp)) 1651 return (-1); 1652 if (*rspp != NULL) 1653 break; 1654 } 1655 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1656 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1657 DELAY(50); 1658 } 1659 if (i == 1000 || (*rspp) == NULL) { 1660 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1661 return (-1); 1662 } 1663 1664 return (0); 1665 } 1666 1667 int 1668 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, 1669 struct txp_rsp_desc **rspp) 1670 { 1671 struct txp_hostvar *hv = sc->sc_hostvar; 1672 struct txp_rsp_desc *rsp; 1673 1674 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1675 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1676 1677 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1678 *rspp = (struct txp_rsp_desc *)malloc( 1679 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1680 M_DEVBUF, M_NOWAIT); 1681 if ((*rspp) == NULL) 1682 return (-1); 1683 txp_rsp_fixup(sc, rsp, *rspp); 1684 return (0); 1685 } 1686 1687 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1688 printf("%s: response error: id 0x%x\n", 1689 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1690 txp_rsp_fixup(sc, rsp, NULL); 1691 ridx = le32toh(hv->hv_resp_read_idx); 1692 continue; 1693 } 1694 1695 switch (le16toh(rsp->rsp_id)) { 1696 case TXP_CMD_CYCLE_STATISTICS: 1697 case TXP_CMD_MEDIA_STATUS_READ: 1698 break; 1699 case TXP_CMD_HELLO_RESPONSE: 1700 printf("%s: hello\n", TXP_DEVNAME(sc)); 1701 break; 1702 default: 1703 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1704 le16toh(rsp->rsp_id)); 1705 } 1706 1707 txp_rsp_fixup(sc, rsp, NULL); 1708 ridx = le32toh(hv->hv_resp_read_idx); 1709 hv->hv_resp_read_idx = le32toh(ridx); 1710 } 1711 1712 return (0); 1713 } 1714 1715 void 1716 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1717 struct txp_rsp_desc *dst) 1718 { 1719 struct txp_rsp_desc *src = rsp; 1720 struct txp_hostvar *hv = sc->sc_hostvar; 1721 u_int32_t i, ridx; 1722 1723 ridx = le32toh(hv->hv_resp_read_idx); 1724 1725 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1726 if (dst != NULL) 1727 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1728 ridx += sizeof(struct txp_rsp_desc); 1729 if (ridx == sc->sc_rspring.size) { 1730 src = sc->sc_rspring.base; 1731 ridx = 0; 1732 } else 1733 src++; 1734 sc->sc_rspring.lastwrite = ridx; 1735 hv->hv_resp_read_idx = htole32(ridx); 1736 } 1737 1738 hv->hv_resp_read_idx = htole32(ridx); 1739 } 1740 1741 int 1742 txp_cmd_desc_numfree(struct txp_softc *sc) 1743 { 1744 struct txp_hostvar *hv = sc->sc_hostvar; 1745 struct txp_boot_record *br = sc->sc_boot; 1746 u_int32_t widx, ridx, nfree; 1747 1748 widx = sc->sc_cmdring.lastwrite; 1749 ridx = le32toh(hv->hv_cmd_read_idx); 1750 1751 if (widx == ridx) { 1752 /* Ring is completely free */ 1753 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1754 } else { 1755 if (widx > ridx) 1756 nfree = le32toh(br->br_cmd_siz) - 1757 (widx - ridx + sizeof(struct txp_cmd_desc)); 1758 else 1759 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1760 } 1761 1762 return (nfree / sizeof(struct txp_cmd_desc)); 1763 } 1764 1765 void 1766 txp_stop(struct txp_softc *sc) 1767 { 1768 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1769 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1770 1771 if (callout_pending(&sc->sc_tick)) 1772 callout_stop(&sc->sc_tick); 1773 } 1774 1775 void 1776 txp_watchdog(struct ifnet *ifp) 1777 { 1778 } 1779 1780 int 1781 txp_ifmedia_upd(struct ifnet *ifp) 1782 { 1783 struct txp_softc *sc = ifp->if_softc; 1784 struct ifmedia *ifm = &sc->sc_ifmedia; 1785 u_int16_t new_xcvr; 1786 1787 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1788 return (EINVAL); 1789 1790 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1791 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1792 new_xcvr = TXP_XCVR_10_FDX; 1793 else 1794 new_xcvr = TXP_XCVR_10_HDX; 1795 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1796 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1797 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1798 new_xcvr = TXP_XCVR_100_FDX; 1799 else 1800 new_xcvr = TXP_XCVR_100_HDX; 1801 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1802 new_xcvr = TXP_XCVR_AUTO; 1803 } else 1804 return (EINVAL); 1805 1806 /* nothing to do */ 1807 if (sc->sc_xcvr == new_xcvr) 1808 return (0); 1809 1810 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1811 NULL, NULL, NULL, 0); 1812 sc->sc_xcvr = new_xcvr; 1813 1814 return (0); 1815 } 1816 1817 void 1818 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1819 { 1820 struct txp_softc *sc = ifp->if_softc; 1821 struct ifmedia *ifm = &sc->sc_ifmedia; 1822 u_int16_t bmsr, bmcr, anlpar; 1823 1824 ifmr->ifm_status = IFM_AVALID; 1825 ifmr->ifm_active = IFM_ETHER; 1826 1827 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1828 &bmsr, NULL, NULL, 1)) 1829 goto bail; 1830 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1831 &bmsr, NULL, NULL, 1)) 1832 goto bail; 1833 1834 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1835 &bmcr, NULL, NULL, 1)) 1836 goto bail; 1837 1838 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1839 &anlpar, NULL, NULL, 1)) 1840 goto bail; 1841 1842 if (bmsr & BMSR_LINK) 1843 ifmr->ifm_status |= IFM_ACTIVE; 1844 1845 if (bmcr & BMCR_ISO) { 1846 ifmr->ifm_active |= IFM_NONE; 1847 ifmr->ifm_status = 0; 1848 return; 1849 } 1850 1851 if (bmcr & BMCR_LOOP) 1852 ifmr->ifm_active |= IFM_LOOP; 1853 1854 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1855 if ((bmsr & BMSR_ACOMP) == 0) { 1856 ifmr->ifm_active |= IFM_NONE; 1857 return; 1858 } 1859 1860 if (anlpar & ANLPAR_TX_FD) 1861 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1862 else if (anlpar & ANLPAR_T4) 1863 ifmr->ifm_active |= IFM_100_T4|IFM_HDX; 1864 else if (anlpar & ANLPAR_TX) 1865 ifmr->ifm_active |= IFM_100_TX|IFM_HDX; 1866 else if (anlpar & ANLPAR_10_FD) 1867 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1868 else if (anlpar & ANLPAR_10) 1869 ifmr->ifm_active |= IFM_10_T|IFM_HDX; 1870 else 1871 ifmr->ifm_active |= IFM_NONE; 1872 } else 1873 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1874 return; 1875 1876 bail: 1877 ifmr->ifm_active |= IFM_NONE; 1878 ifmr->ifm_status &= ~IFM_AVALID; 1879 } 1880 1881 void 1882 txp_show_descriptor(void *d) 1883 { 1884 struct txp_cmd_desc *cmd = d; 1885 struct txp_rsp_desc *rsp = d; 1886 struct txp_tx_desc *txd = d; 1887 struct txp_frag_desc *frgd = d; 1888 1889 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1890 case CMD_FLAGS_TYPE_CMD: 1891 /* command descriptor */ 1892 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1893 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1894 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1895 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1896 break; 1897 case CMD_FLAGS_TYPE_RESP: 1898 /* response descriptor */ 1899 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1900 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1901 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1902 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1903 break; 1904 case CMD_FLAGS_TYPE_DATA: 1905 /* data header (assuming tx for now) */ 1906 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1907 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1908 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1909 break; 1910 case CMD_FLAGS_TYPE_FRAG: 1911 /* fragment descriptor */ 1912 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1913 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1914 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1915 break; 1916 default: 1917 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1918 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1919 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1920 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1921 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1922 break; 1923 } 1924 } 1925 1926 void 1927 txp_set_filter(struct txp_softc *sc) 1928 { 1929 struct ethercom *ac = &sc->sc_arpcom; 1930 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1931 u_int32_t crc, carry, hashbit, hash[2]; 1932 u_int16_t filter; 1933 u_int8_t octet; 1934 int i, j, mcnt = 0; 1935 struct ether_multi *enm; 1936 struct ether_multistep step; 1937 1938 if (ifp->if_flags & IFF_PROMISC) { 1939 filter = TXP_RXFILT_PROMISC; 1940 goto setit; 1941 } 1942 1943 again: 1944 filter = TXP_RXFILT_DIRECT; 1945 1946 if (ifp->if_flags & IFF_BROADCAST) 1947 filter |= TXP_RXFILT_BROADCAST; 1948 1949 if (ifp->if_flags & IFF_ALLMULTI) 1950 filter |= TXP_RXFILT_ALLMULTI; 1951 else { 1952 hash[0] = hash[1] = 0; 1953 1954 ETHER_FIRST_MULTI(step, ac, enm); 1955 while (enm != NULL) { 1956 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1957 ETHER_ADDR_LEN)) { 1958 /* 1959 * We must listen to a range of multicast 1960 * addresses. For now, just accept all 1961 * multicasts, rather than trying to set only 1962 * those filter bits needed to match the range. 1963 * (At this time, the only use of address 1964 * ranges is for IP multicast routing, for 1965 * which the range is big enough to require 1966 * all bits set.) 1967 */ 1968 ifp->if_flags |= IFF_ALLMULTI; 1969 goto again; 1970 } 1971 1972 mcnt++; 1973 crc = 0xffffffff; 1974 1975 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1976 octet = enm->enm_addrlo[i]; 1977 for (j = 0; j < 8; j++) { 1978 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1979 (octet & 1); 1980 crc <<= 1; 1981 octet >>= 1; 1982 if (carry) 1983 crc = (crc ^ TXP_POLYNOMIAL) | 1984 carry; 1985 } 1986 } 1987 hashbit = (u_int16_t)(crc & (64 - 1)); 1988 hash[hashbit / 32] |= (1 << hashbit % 32); 1989 ETHER_NEXT_MULTI(step, enm); 1990 } 1991 1992 if (mcnt > 0) { 1993 filter |= TXP_RXFILT_HASHMULTI; 1994 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1995 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1996 } 1997 } 1998 1999 setit: 2000 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2001 NULL, NULL, NULL, 1); 2002 } 2003 2004 void 2005 txp_capabilities(struct txp_softc *sc) 2006 { 2007 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2008 struct txp_rsp_desc *rsp = NULL; 2009 struct txp_ext_desc *ext; 2010 2011 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2012 goto out; 2013 2014 if (rsp->rsp_numdesc != 1) 2015 goto out; 2016 ext = (struct txp_ext_desc *)(rsp + 1); 2017 2018 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2019 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2020 2021 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2022 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2023 sc->sc_tx_capability |= OFFLOAD_VLAN; 2024 sc->sc_rx_capability |= OFFLOAD_VLAN; 2025 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2026 } 2027 2028 #if 0 2029 /* not ready yet */ 2030 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2031 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2032 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2033 ifp->if_capabilities |= IFCAP_IPSEC; 2034 } 2035 #endif 2036 2037 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2038 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2039 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2040 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2041 } 2042 2043 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2044 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2045 #ifdef TRY_TX_TCP_CSUM 2046 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2047 ifp->if_capabilities |= 2048 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2049 #endif 2050 } 2051 2052 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2053 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2054 #ifdef TRY_TX_UDP_CSUM 2055 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2056 ifp->if_capabilities |= 2057 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2058 #endif 2059 } 2060 2061 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2062 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2063 goto out; 2064 2065 out: 2066 if (rsp != NULL) 2067 free(rsp, M_DEVBUF); 2068 } 2069
Indexes created Tue Sep 30 20:09:53 GMT 2025