if_txp.c revision 1.49.2.1
1 /* $NetBSD: if_txp.c,v 1.49.2.1 2019/06/10 22:07:16 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.49.2.1 2019/06/10 22:07:16 christos Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 int txp_probe(device_t, cfdata_t, void *); 84 void txp_attach(device_t, device_t, void *); 85 int txp_intr(void *); 86 void txp_tick(void *); 87 bool txp_shutdown(device_t, int); 88 int txp_ioctl(struct ifnet *, u_long, void *); 89 void txp_start(struct ifnet *); 90 void txp_stop(struct txp_softc *); 91 void txp_init(struct txp_softc *); 92 void txp_watchdog(struct ifnet *); 93 94 int txp_chip_init(struct txp_softc *); 95 int txp_reset_adapter(struct txp_softc *); 96 int txp_download_fw(struct txp_softc *); 97 int txp_download_fw_wait(struct txp_softc *); 98 int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 int txp_alloc_rings(struct txp_softc *); 101 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 void txp_set_filter(struct txp_softc *); 104 105 int txp_cmd_desc_numfree(struct txp_softc *); 106 int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 void txp_capabilities(struct txp_softc *); 116 117 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 int txp_ifmedia_upd(struct ifnet *); 119 void txp_show_descriptor(void *); 120 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 121 struct txp_dma_alloc *); 122 void txp_rxbuf_reclaim(struct txp_softc *); 123 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 124 struct txp_dma_alloc *); 125 126 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 127 NULL, NULL); 128 129 const struct txp_pci_match { 130 int vid, did, flags; 131 } txp_devices[] = { 132 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 133 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 140 }; 141 142 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 143 144 static const struct { 145 uint16_t mask, value; 146 int flags; 147 } txp_subsysinfo[] = { 148 {0xf000, 0x2000, TXP_SERVERVERSION}, 149 {0x0100, 0x0100, TXP_FIBER}, 150 #if 0 /* information from 3com header, unused */ 151 {0x0010, 0x0010, /* secured firmware */}, 152 {0x0003, 0x0000, /* variable DES */}, 153 {0x0003, 0x0001, /* single DES - "95" */}, 154 {0x0003, 0x0002, /* triple DES - "97" */}, 155 #endif 156 }; 157 158 static const struct txp_pci_match * 159 txp_pcilookup(pcireg_t id) 160 { 161 int i; 162 163 for (i = 0; i < __arraycount(txp_devices); i++) 164 if (PCI_VENDOR(id) == txp_devices[i].vid && 165 PCI_PRODUCT(id) == txp_devices[i].did) 166 return &txp_devices[i]; 167 return (0); 168 } 169 170 int 171 txp_probe(device_t parent, cfdata_t match, void *aux) 172 { 173 struct pci_attach_args *pa = aux; 174 175 if (txp_pcilookup(pa->pa_id)) 176 return (1); 177 return (0); 178 } 179 180 void 181 txp_attach(device_t parent, device_t self, void *aux) 182 { 183 struct txp_softc *sc = device_private(self); 184 struct pci_attach_args *pa = aux; 185 pci_chipset_tag_t pc = pa->pa_pc; 186 pci_intr_handle_t ih; 187 const char *intrstr = NULL; 188 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 189 uint32_t command; 190 uint16_t p1; 191 uint32_t p2; 192 u_char enaddr[6]; 193 const struct txp_pci_match *match; 194 uint16_t subsys; 195 int i, flags; 196 char devinfo[256]; 197 char intrbuf[PCI_INTRSTR_LEN]; 198 199 sc->sc_dev = self; 200 sc->sc_cold = 1; 201 202 match = txp_pcilookup(pa->pa_id); 203 flags = match->flags; 204 if (match->flags & TXP_USESUBSYSTEM) { 205 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 206 PCI_SUBSYS_ID_REG)); 207 for (i = 0; 208 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 209 i++) 210 if ((subsys & txp_subsysinfo[i].mask) == 211 txp_subsysinfo[i].value) 212 flags |= txp_subsysinfo[i].flags; 213 } 214 sc->sc_flags = flags; 215 216 aprint_naive("\n"); 217 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 218 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 219 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 220 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 221 device_xname(sc->sc_dev)); 222 223 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 224 225 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 226 aprint_error(": failed to enable bus mastering\n"); 227 return; 228 } 229 230 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 231 aprint_error(": failed to enable memory mapping\n"); 232 return; 233 } 234 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 235 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 236 aprint_error(": can't map mem space %d\n", 0); 237 return; 238 } 239 240 sc->sc_dmat = pa->pa_dmat; 241 242 /* 243 * Allocate our interrupt. 244 */ 245 if (pci_intr_map(pa, &ih)) { 246 aprint_error(": couldn't map interrupt\n"); 247 return; 248 } 249 250 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 251 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 252 device_xname(self)); 253 if (sc->sc_ih == NULL) { 254 aprint_error(": couldn't establish interrupt"); 255 if (intrstr != NULL) 256 aprint_normal(" at %s", intrstr); 257 aprint_normal("\n"); 258 return; 259 } 260 aprint_normal(": interrupting at %s\n", intrstr); 261 262 if (txp_chip_init(sc)) 263 goto cleanupintr; 264 265 if (txp_download_fw(sc)) 266 goto cleanupintr; 267 268 if (txp_alloc_rings(sc)) 269 goto cleanupintr; 270 271 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 272 NULL, NULL, NULL, 1)) 273 goto cleanupintr; 274 275 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 276 &p1, &p2, NULL, 1)) 277 goto cleanupintr; 278 279 txp_set_filter(sc); 280 281 p1 = htole16(p1); 282 enaddr[0] = ((uint8_t *)&p1)[1]; 283 enaddr[1] = ((uint8_t *)&p1)[0]; 284 p2 = htole32(p2); 285 enaddr[2] = ((uint8_t *)&p2)[3]; 286 enaddr[3] = ((uint8_t *)&p2)[2]; 287 enaddr[4] = ((uint8_t *)&p2)[1]; 288 enaddr[5] = ((uint8_t *)&p2)[0]; 289 290 aprint_normal_dev(self, "Ethernet address %s\n", 291 ether_sprintf(enaddr)); 292 sc->sc_cold = 0; 293 294 /* Initialize ifmedia structures. */ 295 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 297 if (flags & TXP_FIBER) { 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_HDX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 303 0, NULL); 304 } else { 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 316 0, NULL); 317 } 318 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 319 320 sc->sc_xcvr = TXP_XCVR_AUTO; 321 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 322 NULL, NULL, NULL, 0); 323 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 324 325 ifp->if_softc = sc; 326 ifp->if_mtu = ETHERMTU; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = txp_ioctl; 329 ifp->if_start = txp_start; 330 ifp->if_watchdog = txp_watchdog; 331 ifp->if_baudrate = 10000000; 332 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 333 IFQ_SET_READY(&ifp->if_snd); 334 ifp->if_capabilities = 0; 335 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 336 337 txp_capabilities(sc); 338 339 callout_init(&sc->sc_tick, 0); 340 callout_setfunc(&sc->sc_tick, txp_tick, sc); 341 342 /* 343 * Attach us everywhere 344 */ 345 if_attach(ifp); 346 if_deferred_start_init(ifp, NULL); 347 ether_ifattach(ifp, enaddr); 348 349 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 350 pmf_class_network_register(self, ifp); 351 else 352 aprint_error_dev(self, "couldn't establish power handler\n"); 353 354 return; 355 356 cleanupintr: 357 pci_intr_disestablish(pc, sc->sc_ih); 358 359 return; 360 361 } 362 363 int 364 txp_chip_init(struct txp_softc *sc) 365 { 366 /* disable interrupts */ 367 WRITE_REG(sc, TXP_IER, 0); 368 WRITE_REG(sc, TXP_IMR, 369 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 370 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 371 TXP_INT_LATCH); 372 373 /* ack all interrupts */ 374 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 375 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 376 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 377 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 378 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 379 380 if (txp_reset_adapter(sc)) 381 return (-1); 382 383 /* disable interrupts */ 384 WRITE_REG(sc, TXP_IER, 0); 385 WRITE_REG(sc, TXP_IMR, 386 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 387 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 388 TXP_INT_LATCH); 389 390 /* ack all interrupts */ 391 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 392 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 393 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 394 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 395 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 396 397 return (0); 398 } 399 400 int 401 txp_reset_adapter(struct txp_softc *sc) 402 { 403 uint32_t r; 404 int i; 405 406 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 407 DELAY(1000); 408 WRITE_REG(sc, TXP_SRR, 0); 409 410 /* Should wait max 6 seconds */ 411 for (i = 0; i < 6000; i++) { 412 r = READ_REG(sc, TXP_A2H_0); 413 if (r == STAT_WAITING_FOR_HOST_REQUEST) 414 break; 415 DELAY(1000); 416 } 417 418 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 419 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 420 return (-1); 421 } 422 423 return (0); 424 } 425 426 int 427 txp_download_fw(struct txp_softc *sc) 428 { 429 const struct txp_fw_file_header *fileheader; 430 const struct txp_fw_section_header *secthead; 431 int sect; 432 uint32_t r, i, ier, imr; 433 434 ier = READ_REG(sc, TXP_IER); 435 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 436 437 imr = READ_REG(sc, TXP_IMR); 438 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 439 440 for (i = 0; i < 10000; i++) { 441 r = READ_REG(sc, TXP_A2H_0); 442 if (r == STAT_WAITING_FOR_HOST_REQUEST) 443 break; 444 DELAY(50); 445 } 446 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 447 printf(": not waiting for host request\n"); 448 return (-1); 449 } 450 451 /* Ack the status */ 452 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 453 454 fileheader = (const struct txp_fw_file_header *)tc990image; 455 if (memcmp("TYPHOON", fileheader->magicid, 456 sizeof(fileheader->magicid))) { 457 printf(": fw invalid magic\n"); 458 return (-1); 459 } 460 461 /* Tell boot firmware to get ready for image */ 462 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 463 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 464 465 if (txp_download_fw_wait(sc)) { 466 printf("%s: fw wait failed, initial\n", 467 device_xname(sc->sc_dev)); 468 return (-1); 469 } 470 471 secthead = (const struct txp_fw_section_header *) 472 (((const uint8_t *)tc990image) + 473 sizeof(struct txp_fw_file_header)); 474 475 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 476 if (txp_download_fw_section(sc, secthead, sect)) 477 return (-1); 478 secthead = (const struct txp_fw_section_header *) 479 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 480 sizeof(*secthead)); 481 } 482 483 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 484 485 for (i = 0; i < 10000; i++) { 486 r = READ_REG(sc, TXP_A2H_0); 487 if (r == STAT_WAITING_FOR_BOOT) 488 break; 489 DELAY(50); 490 } 491 if (r != STAT_WAITING_FOR_BOOT) { 492 printf(": not waiting for boot\n"); 493 return (-1); 494 } 495 496 WRITE_REG(sc, TXP_IER, ier); 497 WRITE_REG(sc, TXP_IMR, imr); 498 499 return (0); 500 } 501 502 int 503 txp_download_fw_wait(struct txp_softc *sc) 504 { 505 uint32_t i, r; 506 507 for (i = 0; i < 10000; i++) { 508 r = READ_REG(sc, TXP_ISR); 509 if (r & TXP_INT_A2H_0) 510 break; 511 DELAY(50); 512 } 513 514 if (!(r & TXP_INT_A2H_0)) { 515 printf(": fw wait failed comm0\n"); 516 return (-1); 517 } 518 519 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 520 521 r = READ_REG(sc, TXP_A2H_0); 522 if (r != STAT_WAITING_FOR_SEGMENT) { 523 printf(": fw not waiting for segment\n"); 524 return (-1); 525 } 526 return (0); 527 } 528 529 int 530 txp_download_fw_section(struct txp_softc *sc, 531 const struct txp_fw_section_header *sect, int sectnum) 532 { 533 struct txp_dma_alloc dma; 534 int rseg, err = 0; 535 struct mbuf m; 536 #ifdef INET 537 uint16_t csum; 538 #endif 539 540 /* Skip zero length sections */ 541 if (sect->nbytes == 0) 542 return (0); 543 544 /* Make sure we aren't past the end of the image */ 545 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 546 if (rseg >= sizeof(tc990image)) { 547 printf(": fw invalid section address, section %d\n", sectnum); 548 return (-1); 549 } 550 551 /* Make sure this section doesn't go past the end */ 552 rseg += le32toh(sect->nbytes); 553 if (rseg >= sizeof(tc990image)) { 554 printf(": fw truncated section %d\n", sectnum); 555 return (-1); 556 } 557 558 /* map a buffer, copy segment to it, get physaddr */ 559 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 560 printf(": fw dma malloc failed, section %d\n", sectnum); 561 return (-1); 562 } 563 564 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 565 le32toh(sect->nbytes)); 566 567 /* 568 * dummy up mbuf and verify section checksum 569 */ 570 m.m_type = MT_DATA; 571 m.m_next = m.m_nextpkt = NULL; 572 m.m_owner = NULL; 573 m.m_len = le32toh(sect->nbytes); 574 m.m_data = dma.dma_vaddr; 575 m.m_flags = 0; 576 #ifdef INET 577 csum = in_cksum(&m, le32toh(sect->nbytes)); 578 if (csum != sect->cksum) { 579 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 580 sectnum, sect->cksum, csum); 581 txp_dma_free(sc, &dma); 582 return -1; 583 } 584 #endif 585 586 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 587 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 588 589 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 590 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 591 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 592 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 593 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 594 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 595 596 if (txp_download_fw_wait(sc)) { 597 printf("%s: fw wait failed, section %d\n", 598 device_xname(sc->sc_dev), sectnum); 599 err = -1; 600 } 601 602 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 603 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 604 605 txp_dma_free(sc, &dma); 606 return (err); 607 } 608 609 int 610 txp_intr(void *vsc) 611 { 612 struct txp_softc *sc = vsc; 613 struct txp_hostvar *hv = sc->sc_hostvar; 614 uint32_t isr; 615 int claimed = 0; 616 617 /* mask all interrupts */ 618 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 619 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 620 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 621 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 622 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 623 624 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 625 sizeof(struct txp_hostvar), 626 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 627 628 isr = READ_REG(sc, TXP_ISR); 629 while (isr) { 630 claimed = 1; 631 WRITE_REG(sc, TXP_ISR, isr); 632 633 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 635 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 636 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 637 638 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 639 txp_rxbuf_reclaim(sc); 640 641 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 642 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 643 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 644 645 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 646 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 647 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 648 649 isr = READ_REG(sc, TXP_ISR); 650 } 651 652 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 653 sizeof(struct txp_hostvar), 654 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 655 656 /* unmask all interrupts */ 657 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 658 659 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 660 661 return (claimed); 662 } 663 664 void 665 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 666 struct txp_dma_alloc *dma) 667 { 668 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 669 struct txp_rx_desc *rxd; 670 struct mbuf *m; 671 struct txp_swdesc *sd; 672 uint32_t roff, woff; 673 int sumflags = 0; 674 int idx; 675 676 roff = le32toh(*r->r_roff); 677 woff = le32toh(*r->r_woff); 678 idx = roff / sizeof(struct txp_rx_desc); 679 rxd = r->r_desc + idx; 680 681 while (roff != woff) { 682 683 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 684 idx * sizeof(struct txp_rx_desc), 685 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 686 687 if (rxd->rx_flags & RX_FLAGS_ERROR) { 688 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 689 le32toh(rxd->rx_stat)); 690 ifp->if_ierrors++; 691 goto next; 692 } 693 694 /* retrieve stashed pointer */ 695 memcpy(&sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 696 697 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 698 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 699 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 700 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 701 m = sd->sd_mbuf; 702 free(sd, M_DEVBUF); 703 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 704 705 #ifdef __STRICT_ALIGNMENT 706 { 707 /* 708 * XXX Nice chip, except it won't accept "off by 2" 709 * buffers, so we're force to copy. Supposedly 710 * this will be fixed in a newer firmware rev 711 * and this will be temporary. 712 */ 713 struct mbuf *mnew; 714 715 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 716 if (mnew == NULL) { 717 m_freem(m); 718 goto next; 719 } 720 if (m->m_len > (MHLEN - 2)) { 721 MCLGET(mnew, M_DONTWAIT); 722 if (!(mnew->m_flags & M_EXT)) { 723 m_freem(mnew); 724 m_freem(m); 725 goto next; 726 } 727 } 728 m_set_rcvif(mnew, ifp); 729 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 730 mnew->m_data += 2; 731 memcpy(mnew->m_data, m->m_data, m->m_len); 732 m_freem(m); 733 m = mnew; 734 } 735 #endif 736 737 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 738 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 739 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 740 sumflags |= M_CSUM_IPv4; 741 742 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 743 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 744 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 745 sumflags |= M_CSUM_TCPv4; 746 747 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 748 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 749 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 750 sumflags |= M_CSUM_UDPv4; 751 752 m->m_pkthdr.csum_flags = sumflags; 753 754 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 755 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 756 } 757 758 if_percpuq_enqueue(ifp->if_percpuq, m); 759 760 next: 761 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 762 idx * sizeof(struct txp_rx_desc), 763 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 764 765 roff += sizeof(struct txp_rx_desc); 766 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 767 idx = 0; 768 roff = 0; 769 rxd = r->r_desc; 770 } else { 771 idx++; 772 rxd++; 773 } 774 woff = le32toh(*r->r_woff); 775 } 776 777 *r->r_roff = htole32(woff); 778 } 779 780 void 781 txp_rxbuf_reclaim(struct txp_softc *sc) 782 { 783 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 784 struct txp_hostvar *hv = sc->sc_hostvar; 785 struct txp_rxbuf_desc *rbd; 786 struct txp_swdesc *sd; 787 uint32_t i, end; 788 789 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 790 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 791 792 if (++i == RXBUF_ENTRIES) 793 i = 0; 794 795 rbd = sc->sc_rxbufs + i; 796 797 while (i != end) { 798 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 799 M_DEVBUF, M_NOWAIT); 800 if (sd == NULL) 801 break; 802 803 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 804 if (sd->sd_mbuf == NULL) 805 goto err_sd; 806 807 MCLGET(sd->sd_mbuf, M_DONTWAIT); 808 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 809 goto err_mbuf; 810 m_set_rcvif(sd->sd_mbuf, ifp); 811 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 812 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 813 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 814 goto err_mbuf; 815 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 816 BUS_DMA_NOWAIT)) { 817 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 818 goto err_mbuf; 819 } 820 821 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 822 i * sizeof(struct txp_rxbuf_desc), 823 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 824 825 /* stash away pointer */ 826 memcpy(__UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 827 828 rbd->rb_paddrlo = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 829 & 0xffffffff; 830 rbd->rb_paddrhi = ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) 831 >> 32; 832 833 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 834 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 835 836 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 837 i * sizeof(struct txp_rxbuf_desc), 838 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 839 840 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 841 842 if (++i == RXBUF_ENTRIES) { 843 i = 0; 844 rbd = sc->sc_rxbufs; 845 } else 846 rbd++; 847 } 848 return; 849 850 err_mbuf: 851 m_freem(sd->sd_mbuf); 852 err_sd: 853 free(sd, M_DEVBUF); 854 } 855 856 /* 857 * Reclaim mbufs and entries from a transmit ring. 858 */ 859 void 860 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 861 struct txp_dma_alloc *dma) 862 { 863 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 864 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 865 uint32_t cons = r->r_cons, cnt = r->r_cnt; 866 struct txp_tx_desc *txd = r->r_desc + cons; 867 struct txp_swdesc *sd = sc->sc_txd + cons; 868 struct mbuf *m; 869 870 while (cons != idx) { 871 if (cnt == 0) 872 break; 873 874 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 875 cons * sizeof(struct txp_tx_desc), 876 sizeof(struct txp_tx_desc), 877 BUS_DMASYNC_POSTWRITE); 878 879 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 880 TX_FLAGS_TYPE_DATA) { 881 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 882 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 883 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 884 m = sd->sd_mbuf; 885 if (m != NULL) { 886 m_freem(m); 887 txd->tx_addrlo = 0; 888 txd->tx_addrhi = 0; 889 ifp->if_opackets++; 890 } 891 } 892 ifp->if_flags &= ~IFF_OACTIVE; 893 894 if (++cons == TX_ENTRIES) { 895 txd = r->r_desc; 896 cons = 0; 897 sd = sc->sc_txd; 898 } else { 899 txd++; 900 sd++; 901 } 902 903 cnt--; 904 } 905 906 r->r_cons = cons; 907 r->r_cnt = cnt; 908 if (cnt == 0) 909 ifp->if_timer = 0; 910 } 911 912 bool 913 txp_shutdown(device_t self, int howto) 914 { 915 struct txp_softc *sc; 916 917 sc = device_private(self); 918 919 /* mask all interrupts */ 920 WRITE_REG(sc, TXP_IMR, 921 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 922 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 923 TXP_INT_LATCH); 924 925 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 926 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 927 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 928 929 return true; 930 } 931 932 int 933 txp_alloc_rings(struct txp_softc *sc) 934 { 935 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 936 struct txp_boot_record *boot; 937 struct txp_swdesc *sd; 938 uint32_t r; 939 int i, j, nb; 940 941 /* boot record */ 942 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 943 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 944 printf(": can't allocate boot record\n"); 945 return (-1); 946 } 947 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 948 memset(boot, 0, sizeof(*boot)); 949 sc->sc_boot = boot; 950 951 /* host variables */ 952 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 953 BUS_DMA_COHERENT)) { 954 printf(": can't allocate host ring\n"); 955 goto bail_boot; 956 } 957 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 958 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 959 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 960 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 961 962 /* high priority tx ring */ 963 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 964 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 965 printf(": can't allocate high tx ring\n"); 966 goto bail_host; 967 } 968 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 969 sizeof(struct txp_tx_desc) * TX_ENTRIES); 970 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 971 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 972 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 973 sc->sc_txhir.r_reg = TXP_H2A_1; 974 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 975 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 976 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 977 for (i = 0; i < TX_ENTRIES; i++) { 978 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 979 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 980 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 981 for (j = 0; j < i; j++) { 982 bus_dmamap_destroy(sc->sc_dmat, 983 sc->sc_txd[j].sd_map); 984 sc->sc_txd[j].sd_map = NULL; 985 } 986 goto bail_txhiring; 987 } 988 } 989 990 /* low priority tx ring */ 991 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 992 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 993 printf(": can't allocate low tx ring\n"); 994 goto bail_txhiring; 995 } 996 memset(sc->sc_txloring_dma.dma_vaddr, 0, 997 sizeof(struct txp_tx_desc) * TX_ENTRIES); 998 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 999 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1000 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1001 sc->sc_txlor.r_reg = TXP_H2A_3; 1002 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1003 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1004 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1005 1006 /* high priority rx ring */ 1007 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1008 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1009 printf(": can't allocate high rx ring\n"); 1010 goto bail_txloring; 1011 } 1012 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1013 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1014 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1015 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1016 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1017 sc->sc_rxhir.r_desc = 1018 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1019 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1020 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1021 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1022 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1023 1024 /* low priority ring */ 1025 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1026 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1027 printf(": can't allocate low rx ring\n"); 1028 goto bail_rxhiring; 1029 } 1030 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1031 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1032 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1033 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1034 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1035 sc->sc_rxlor.r_desc = 1036 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1037 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1038 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1039 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1040 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1041 1042 /* command ring */ 1043 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1044 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1045 printf(": can't allocate command ring\n"); 1046 goto bail_rxloring; 1047 } 1048 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1049 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1050 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1051 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1052 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1053 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1054 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1055 sc->sc_cmdring.lastwrite = 0; 1056 1057 /* response ring */ 1058 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1059 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1060 printf(": can't allocate response ring\n"); 1061 goto bail_cmdring; 1062 } 1063 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1064 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1065 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1066 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1067 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1068 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1069 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1070 sc->sc_rspring.lastwrite = 0; 1071 1072 /* receive buffer ring */ 1073 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1074 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1075 printf(": can't allocate rx buffer ring\n"); 1076 goto bail_rspring; 1077 } 1078 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1079 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1080 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1081 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1082 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1083 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1084 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1085 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1086 M_DEVBUF, M_NOWAIT); 1087 /* stash away pointer */ 1088 memcpy(__UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, 1089 sizeof(sd)); 1090 if (sd == NULL) 1091 break; 1092 1093 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1094 if (sd->sd_mbuf == NULL) { 1095 goto bail_rxbufring; 1096 } 1097 1098 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1099 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1100 goto bail_rxbufring; 1101 } 1102 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1103 m_set_rcvif(sd->sd_mbuf, ifp); 1104 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1105 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1106 goto bail_rxbufring; 1107 } 1108 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1109 BUS_DMA_NOWAIT)) { 1110 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1111 goto bail_rxbufring; 1112 } 1113 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1114 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1115 1116 1117 sc->sc_rxbufs[nb].rb_paddrlo = 1118 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1119 sc->sc_rxbufs[nb].rb_paddrhi = 1120 ((uint64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1121 } 1122 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1123 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1124 BUS_DMASYNC_PREWRITE); 1125 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1126 sizeof(struct txp_rxbuf_desc)); 1127 1128 /* zero dma */ 1129 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1130 BUS_DMA_COHERENT)) { 1131 printf(": can't allocate response ring\n"); 1132 goto bail_rxbufring; 1133 } 1134 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1135 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1136 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1137 1138 /* See if it's waiting for boot, and try to boot it */ 1139 for (i = 0; i < 10000; i++) { 1140 r = READ_REG(sc, TXP_A2H_0); 1141 if (r == STAT_WAITING_FOR_BOOT) 1142 break; 1143 DELAY(50); 1144 } 1145 if (r != STAT_WAITING_FOR_BOOT) { 1146 printf(": not waiting for boot\n"); 1147 goto bail; 1148 } 1149 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1150 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1151 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1152 1153 /* See if it booted */ 1154 for (i = 0; i < 10000; i++) { 1155 r = READ_REG(sc, TXP_A2H_0); 1156 if (r == STAT_RUNNING) 1157 break; 1158 DELAY(50); 1159 } 1160 if (r != STAT_RUNNING) { 1161 printf(": fw not running\n"); 1162 goto bail; 1163 } 1164 1165 /* Clear TX and CMD ring write registers */ 1166 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1167 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1168 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1169 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1170 1171 return (0); 1172 1173 bail: 1174 txp_dma_free(sc, &sc->sc_zero_dma); 1175 bail_rxbufring: 1176 if (nb == RXBUF_ENTRIES) 1177 nb--; 1178 for (i = 0; i <= nb; i++) { 1179 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1180 sizeof(sd)); 1181 if (sd) 1182 free(sd, M_DEVBUF); 1183 } 1184 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1185 bail_rspring: 1186 txp_dma_free(sc, &sc->sc_rspring_dma); 1187 bail_cmdring: 1188 txp_dma_free(sc, &sc->sc_cmdring_dma); 1189 bail_rxloring: 1190 txp_dma_free(sc, &sc->sc_rxloring_dma); 1191 bail_rxhiring: 1192 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1193 bail_txloring: 1194 txp_dma_free(sc, &sc->sc_txloring_dma); 1195 bail_txhiring: 1196 txp_dma_free(sc, &sc->sc_txhiring_dma); 1197 bail_host: 1198 txp_dma_free(sc, &sc->sc_host_dma); 1199 bail_boot: 1200 txp_dma_free(sc, &sc->sc_boot_dma); 1201 return (-1); 1202 } 1203 1204 int 1205 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1206 struct txp_dma_alloc *dma, int mapflags) 1207 { 1208 int r; 1209 1210 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1211 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1212 goto fail_0; 1213 1214 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1215 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1216 goto fail_1; 1217 1218 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1219 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1220 goto fail_2; 1221 1222 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1223 size, NULL, BUS_DMA_NOWAIT)) != 0) 1224 goto fail_3; 1225 1226 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1227 return (0); 1228 1229 fail_3: 1230 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1231 fail_2: 1232 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1233 fail_1: 1234 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1235 fail_0: 1236 return (r); 1237 } 1238 1239 void 1240 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1241 { 1242 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1243 1244 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1245 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1246 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1247 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1248 } 1249 1250 int 1251 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1252 { 1253 struct txp_softc *sc = ifp->if_softc; 1254 struct ifaddr *ifa = (struct ifaddr *)data; 1255 int s, error = 0; 1256 1257 s = splnet(); 1258 1259 #if 0 1260 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1261 splx(s); 1262 return error; 1263 } 1264 #endif 1265 1266 switch (command) { 1267 case SIOCINITIFADDR: 1268 ifp->if_flags |= IFF_UP; 1269 txp_init(sc); 1270 switch (ifa->ifa_addr->sa_family) { 1271 #ifdef INET 1272 case AF_INET: 1273 arp_ifinit(ifp, ifa); 1274 break; 1275 #endif /* INET */ 1276 default: 1277 break; 1278 } 1279 break; 1280 case SIOCSIFFLAGS: 1281 if ((error = ifioctl_common(ifp, command, data)) != 0) 1282 break; 1283 if (ifp->if_flags & IFF_UP) { 1284 txp_init(sc); 1285 } else { 1286 if (ifp->if_flags & IFF_RUNNING) 1287 txp_stop(sc); 1288 } 1289 break; 1290 case SIOCADDMULTI: 1291 case SIOCDELMULTI: 1292 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1293 break; 1294 1295 error = 0; 1296 1297 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1298 ; 1299 else if (ifp->if_flags & IFF_RUNNING) { 1300 /* 1301 * Multicast list has changed; set the hardware 1302 * filter accordingly. 1303 */ 1304 txp_set_filter(sc); 1305 } 1306 break; 1307 default: 1308 error = ether_ioctl(ifp, command, data); 1309 break; 1310 } 1311 1312 splx(s); 1313 1314 return (error); 1315 } 1316 1317 void 1318 txp_init(struct txp_softc *sc) 1319 { 1320 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1321 int s; 1322 1323 txp_stop(sc); 1324 1325 s = splnet(); 1326 1327 txp_set_filter(sc); 1328 1329 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1330 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1331 1332 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1333 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1334 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1335 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1336 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1337 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1338 1339 ifp->if_flags |= IFF_RUNNING; 1340 ifp->if_flags &= ~IFF_OACTIVE; 1341 ifp->if_timer = 0; 1342 1343 if (!callout_pending(&sc->sc_tick)) 1344 callout_schedule(&sc->sc_tick, hz); 1345 1346 splx(s); 1347 } 1348 1349 void 1350 txp_tick(void *vsc) 1351 { 1352 struct txp_softc *sc = vsc; 1353 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1354 struct txp_rsp_desc *rsp = NULL; 1355 struct txp_ext_desc *ext; 1356 int s; 1357 1358 s = splnet(); 1359 txp_rxbuf_reclaim(sc); 1360 1361 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1362 &rsp, 1)) 1363 goto out; 1364 if (rsp->rsp_numdesc != 6) 1365 goto out; 1366 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1367 NULL, NULL, NULL, 1)) 1368 goto out; 1369 ext = (struct txp_ext_desc *)(rsp + 1); 1370 1371 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1372 ext[4].ext_1 + ext[4].ext_4; 1373 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1374 ext[2].ext_1; 1375 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1376 ext[1].ext_3; 1377 ifp->if_opackets += rsp->rsp_par2; 1378 ifp->if_ipackets += ext[2].ext_3; 1379 1380 out: 1381 if (rsp != NULL) 1382 free(rsp, M_DEVBUF); 1383 1384 splx(s); 1385 callout_schedule(&sc->sc_tick, hz); 1386 } 1387 1388 void 1389 txp_start(struct ifnet *ifp) 1390 { 1391 struct txp_softc *sc = ifp->if_softc; 1392 struct txp_tx_ring *r = &sc->sc_txhir; 1393 struct txp_tx_desc *txd; 1394 int txdidx; 1395 struct txp_frag_desc *fxd; 1396 struct mbuf *m, *mnew; 1397 struct txp_swdesc *sd; 1398 uint32_t firstprod, firstcnt, prod, cnt, i; 1399 1400 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1401 return; 1402 1403 prod = r->r_prod; 1404 cnt = r->r_cnt; 1405 1406 while (1) { 1407 IFQ_POLL(&ifp->if_snd, m); 1408 if (m == NULL) 1409 break; 1410 mnew = NULL; 1411 1412 firstprod = prod; 1413 firstcnt = cnt; 1414 1415 sd = sc->sc_txd + prod; 1416 sd->sd_mbuf = m; 1417 1418 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1419 BUS_DMA_NOWAIT)) { 1420 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1421 if (mnew == NULL) 1422 goto oactive1; 1423 if (m->m_pkthdr.len > MHLEN) { 1424 MCLGET(mnew, M_DONTWAIT); 1425 if ((mnew->m_flags & M_EXT) == 0) { 1426 m_freem(mnew); 1427 goto oactive1; 1428 } 1429 } 1430 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1431 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1432 IFQ_DEQUEUE(&ifp->if_snd, m); 1433 m_freem(m); 1434 m = mnew; 1435 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1436 BUS_DMA_NOWAIT)) 1437 goto oactive1; 1438 } 1439 1440 if ((TX_ENTRIES - cnt) < 4) 1441 goto oactive; 1442 1443 txd = r->r_desc + prod; 1444 txdidx = prod; 1445 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1446 txd->tx_numdesc = 0; 1447 txd->tx_addrlo = 0; 1448 txd->tx_addrhi = 0; 1449 txd->tx_totlen = m->m_pkthdr.len; 1450 txd->tx_pflags = 0; 1451 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1452 1453 if (++prod == TX_ENTRIES) 1454 prod = 0; 1455 1456 if (++cnt >= (TX_ENTRIES - 4)) 1457 goto oactive; 1458 1459 if (vlan_has_tag(m)) 1460 txd->tx_pflags = TX_PFLAGS_VLAN | 1461 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1462 1463 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1464 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1465 #ifdef TRY_TX_TCP_CSUM 1466 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1467 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1468 #endif 1469 #ifdef TRY_TX_UDP_CSUM 1470 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1471 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1472 #endif 1473 1474 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1475 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1476 1477 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1478 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1479 if (++cnt >= (TX_ENTRIES - 4)) { 1480 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1481 0, sd->sd_map->dm_mapsize, 1482 BUS_DMASYNC_POSTWRITE); 1483 goto oactive; 1484 } 1485 1486 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1487 FRAG_FLAGS_VALID; 1488 fxd->frag_rsvd1 = 0; 1489 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1490 fxd->frag_addrlo = 1491 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) & 1492 0xffffffff; 1493 fxd->frag_addrhi = 1494 ((uint64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1495 32; 1496 fxd->frag_rsvd2 = 0; 1497 1498 bus_dmamap_sync(sc->sc_dmat, 1499 sc->sc_txhiring_dma.dma_map, 1500 prod * sizeof(struct txp_frag_desc), 1501 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1502 1503 if (++prod == TX_ENTRIES) { 1504 fxd = (struct txp_frag_desc *)r->r_desc; 1505 prod = 0; 1506 } else 1507 fxd++; 1508 1509 } 1510 1511 /* 1512 * if mnew isn't NULL, we already dequeued and copied 1513 * the packet. 1514 */ 1515 if (mnew == NULL) 1516 IFQ_DEQUEUE(&ifp->if_snd, m); 1517 1518 ifp->if_timer = 5; 1519 1520 bpf_mtap(ifp, m, BPF_D_OUT); 1521 1522 txd->tx_flags |= TX_FLAGS_VALID; 1523 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1524 txdidx * sizeof(struct txp_tx_desc), 1525 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1526 1527 #if 0 1528 { 1529 struct mbuf *mx; 1530 int i; 1531 1532 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1533 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1534 txd->tx_pflags); 1535 for (mx = m; mx != NULL; mx = mx->m_next) { 1536 for (i = 0; i < mx->m_len; i++) { 1537 printf(":%02x", 1538 (uint8_t)m->m_data[i]); 1539 } 1540 } 1541 printf("\n"); 1542 } 1543 #endif 1544 1545 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1546 } 1547 1548 r->r_prod = prod; 1549 r->r_cnt = cnt; 1550 return; 1551 1552 oactive: 1553 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1554 oactive1: 1555 ifp->if_flags |= IFF_OACTIVE; 1556 r->r_prod = firstprod; 1557 r->r_cnt = firstcnt; 1558 } 1559 1560 /* 1561 * Handle simple commands sent to the typhoon 1562 */ 1563 int 1564 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1565 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1566 { 1567 struct txp_rsp_desc *rsp = NULL; 1568 1569 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1570 return (-1); 1571 1572 if (!wait) 1573 return (0); 1574 1575 if (out1 != NULL) 1576 *out1 = le16toh(rsp->rsp_par1); 1577 if (out2 != NULL) 1578 *out2 = le32toh(rsp->rsp_par2); 1579 if (out3 != NULL) 1580 *out3 = le32toh(rsp->rsp_par3); 1581 free(rsp, M_DEVBUF); 1582 return (0); 1583 } 1584 1585 int 1586 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1587 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1588 struct txp_rsp_desc **rspp, int wait) 1589 { 1590 struct txp_hostvar *hv = sc->sc_hostvar; 1591 struct txp_cmd_desc *cmd; 1592 struct txp_ext_desc *ext; 1593 uint32_t idx, i; 1594 uint16_t seq; 1595 1596 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1597 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1598 return (-1); 1599 } 1600 1601 idx = sc->sc_cmdring.lastwrite; 1602 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1603 memset(cmd, 0, sizeof(*cmd)); 1604 1605 cmd->cmd_numdesc = in_extn; 1606 seq = sc->sc_seq++; 1607 cmd->cmd_seq = htole16(seq); 1608 cmd->cmd_id = htole16(id); 1609 cmd->cmd_par1 = htole16(in1); 1610 cmd->cmd_par2 = htole32(in2); 1611 cmd->cmd_par3 = htole32(in3); 1612 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1613 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1614 1615 idx += sizeof(struct txp_cmd_desc); 1616 if (idx == sc->sc_cmdring.size) 1617 idx = 0; 1618 1619 for (i = 0; i < in_extn; i++) { 1620 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1621 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1622 in_extp++; 1623 idx += sizeof(struct txp_cmd_desc); 1624 if (idx == sc->sc_cmdring.size) 1625 idx = 0; 1626 } 1627 1628 sc->sc_cmdring.lastwrite = idx; 1629 1630 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1631 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1632 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1633 1634 if (!wait) 1635 return (0); 1636 1637 for (i = 0; i < 10000; i++) { 1638 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1639 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1640 idx = le32toh(hv->hv_resp_read_idx); 1641 if (idx != le32toh(hv->hv_resp_write_idx)) { 1642 *rspp = NULL; 1643 if (txp_response(sc, idx, id, seq, rspp)) 1644 return (-1); 1645 if (*rspp != NULL) 1646 break; 1647 } 1648 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1649 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1650 DELAY(50); 1651 } 1652 if (i == 1000 || (*rspp) == NULL) { 1653 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1654 return (-1); 1655 } 1656 1657 return (0); 1658 } 1659 1660 int 1661 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1662 struct txp_rsp_desc **rspp) 1663 { 1664 struct txp_hostvar *hv = sc->sc_hostvar; 1665 struct txp_rsp_desc *rsp; 1666 1667 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1668 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1669 1670 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1671 *rspp = (struct txp_rsp_desc *)malloc( 1672 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1673 M_DEVBUF, M_NOWAIT); 1674 if ((*rspp) == NULL) 1675 return (-1); 1676 txp_rsp_fixup(sc, rsp, *rspp); 1677 return (0); 1678 } 1679 1680 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1681 printf("%s: response error: id 0x%x\n", 1682 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1683 txp_rsp_fixup(sc, rsp, NULL); 1684 ridx = le32toh(hv->hv_resp_read_idx); 1685 continue; 1686 } 1687 1688 switch (le16toh(rsp->rsp_id)) { 1689 case TXP_CMD_CYCLE_STATISTICS: 1690 case TXP_CMD_MEDIA_STATUS_READ: 1691 break; 1692 case TXP_CMD_HELLO_RESPONSE: 1693 printf("%s: hello\n", TXP_DEVNAME(sc)); 1694 break; 1695 default: 1696 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1697 le16toh(rsp->rsp_id)); 1698 } 1699 1700 txp_rsp_fixup(sc, rsp, NULL); 1701 ridx = le32toh(hv->hv_resp_read_idx); 1702 hv->hv_resp_read_idx = le32toh(ridx); 1703 } 1704 1705 return (0); 1706 } 1707 1708 void 1709 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1710 struct txp_rsp_desc *dst) 1711 { 1712 struct txp_rsp_desc *src = rsp; 1713 struct txp_hostvar *hv = sc->sc_hostvar; 1714 uint32_t i, ridx; 1715 1716 ridx = le32toh(hv->hv_resp_read_idx); 1717 1718 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1719 if (dst != NULL) 1720 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1721 ridx += sizeof(struct txp_rsp_desc); 1722 if (ridx == sc->sc_rspring.size) { 1723 src = sc->sc_rspring.base; 1724 ridx = 0; 1725 } else 1726 src++; 1727 sc->sc_rspring.lastwrite = ridx; 1728 hv->hv_resp_read_idx = htole32(ridx); 1729 } 1730 1731 hv->hv_resp_read_idx = htole32(ridx); 1732 } 1733 1734 int 1735 txp_cmd_desc_numfree(struct txp_softc *sc) 1736 { 1737 struct txp_hostvar *hv = sc->sc_hostvar; 1738 struct txp_boot_record *br = sc->sc_boot; 1739 uint32_t widx, ridx, nfree; 1740 1741 widx = sc->sc_cmdring.lastwrite; 1742 ridx = le32toh(hv->hv_cmd_read_idx); 1743 1744 if (widx == ridx) { 1745 /* Ring is completely free */ 1746 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1747 } else { 1748 if (widx > ridx) 1749 nfree = le32toh(br->br_cmd_siz) - 1750 (widx - ridx + sizeof(struct txp_cmd_desc)); 1751 else 1752 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1753 } 1754 1755 return (nfree / sizeof(struct txp_cmd_desc)); 1756 } 1757 1758 void 1759 txp_stop(struct txp_softc *sc) 1760 { 1761 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1762 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1763 1764 if (callout_pending(&sc->sc_tick)) 1765 callout_stop(&sc->sc_tick); 1766 } 1767 1768 void 1769 txp_watchdog(struct ifnet *ifp) 1770 { 1771 } 1772 1773 int 1774 txp_ifmedia_upd(struct ifnet *ifp) 1775 { 1776 struct txp_softc *sc = ifp->if_softc; 1777 struct ifmedia *ifm = &sc->sc_ifmedia; 1778 uint16_t new_xcvr; 1779 1780 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1781 return (EINVAL); 1782 1783 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1784 if ((ifm->ifm_media & IFM_FDX) != 0) 1785 new_xcvr = TXP_XCVR_10_FDX; 1786 else 1787 new_xcvr = TXP_XCVR_10_HDX; 1788 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1789 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1790 if ((ifm->ifm_media & IFM_FDX) != 0) 1791 new_xcvr = TXP_XCVR_100_FDX; 1792 else 1793 new_xcvr = TXP_XCVR_100_HDX; 1794 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1795 new_xcvr = TXP_XCVR_AUTO; 1796 } else 1797 return (EINVAL); 1798 1799 /* nothing to do */ 1800 if (sc->sc_xcvr == new_xcvr) 1801 return (0); 1802 1803 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1804 NULL, NULL, NULL, 0); 1805 sc->sc_xcvr = new_xcvr; 1806 1807 return (0); 1808 } 1809 1810 void 1811 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1812 { 1813 struct txp_softc *sc = ifp->if_softc; 1814 struct ifmedia *ifm = &sc->sc_ifmedia; 1815 uint16_t bmsr, bmcr, anlpar; 1816 1817 ifmr->ifm_status = IFM_AVALID; 1818 ifmr->ifm_active = IFM_ETHER; 1819 1820 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1821 &bmsr, NULL, NULL, 1)) 1822 goto bail; 1823 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1824 &bmsr, NULL, NULL, 1)) 1825 goto bail; 1826 1827 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1828 &bmcr, NULL, NULL, 1)) 1829 goto bail; 1830 1831 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1832 &anlpar, NULL, NULL, 1)) 1833 goto bail; 1834 1835 if (bmsr & BMSR_LINK) 1836 ifmr->ifm_status |= IFM_ACTIVE; 1837 1838 if (bmcr & BMCR_ISO) { 1839 ifmr->ifm_active |= IFM_NONE; 1840 ifmr->ifm_status = 0; 1841 return; 1842 } 1843 1844 if (bmcr & BMCR_LOOP) 1845 ifmr->ifm_active |= IFM_LOOP; 1846 1847 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1848 if ((bmsr & BMSR_ACOMP) == 0) { 1849 ifmr->ifm_active |= IFM_NONE; 1850 return; 1851 } 1852 1853 if (anlpar & ANLPAR_TX_FD) 1854 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1855 else if (anlpar & ANLPAR_T4) 1856 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1857 else if (anlpar & ANLPAR_TX) 1858 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1859 else if (anlpar & ANLPAR_10_FD) 1860 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1861 else if (anlpar & ANLPAR_10) 1862 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1863 else 1864 ifmr->ifm_active |= IFM_NONE; 1865 } else 1866 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1867 return; 1868 1869 bail: 1870 ifmr->ifm_active |= IFM_NONE; 1871 ifmr->ifm_status &= ~IFM_AVALID; 1872 } 1873 1874 void 1875 txp_show_descriptor(void *d) 1876 { 1877 struct txp_cmd_desc *cmd = d; 1878 struct txp_rsp_desc *rsp = d; 1879 struct txp_tx_desc *txd = d; 1880 struct txp_frag_desc *frgd = d; 1881 1882 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1883 case CMD_FLAGS_TYPE_CMD: 1884 /* command descriptor */ 1885 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1886 "0x%x par3 0x%x]\n", 1887 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1888 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1889 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1890 break; 1891 case CMD_FLAGS_TYPE_RESP: 1892 /* response descriptor */ 1893 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1894 "0x%x par3 0x%x]\n", 1895 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1896 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1897 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1898 break; 1899 case CMD_FLAGS_TYPE_DATA: 1900 /* data header (assuming tx for now) */ 1901 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1902 "pflags 0x%x]", 1903 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1904 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1905 break; 1906 case CMD_FLAGS_TYPE_FRAG: 1907 /* fragment descriptor */ 1908 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1909 "rsvd2 0x%x]", 1910 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1911 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1912 break; 1913 default: 1914 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1915 "0x%x par2 0x%x par3 0x%x]\n", 1916 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1917 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1918 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1919 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1920 break; 1921 } 1922 } 1923 1924 void 1925 txp_set_filter(struct txp_softc *sc) 1926 { 1927 struct ethercom *ec = &sc->sc_arpcom; 1928 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1929 uint32_t crc, carry, hashbit, hash[2]; 1930 uint16_t filter; 1931 uint8_t octet; 1932 int i, j, mcnt = 0; 1933 struct ether_multi *enm; 1934 struct ether_multistep step; 1935 1936 if (ifp->if_flags & IFF_PROMISC) { 1937 filter = TXP_RXFILT_PROMISC; 1938 goto setit; 1939 } 1940 1941 again: 1942 filter = TXP_RXFILT_DIRECT; 1943 1944 if (ifp->if_flags & IFF_BROADCAST) 1945 filter |= TXP_RXFILT_BROADCAST; 1946 1947 if (ifp->if_flags & IFF_ALLMULTI) 1948 filter |= TXP_RXFILT_ALLMULTI; 1949 else { 1950 hash[0] = hash[1] = 0; 1951 1952 ETHER_LOCK(ec); 1953 ETHER_FIRST_MULTI(step, ec, enm); 1954 while (enm != NULL) { 1955 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1956 ETHER_ADDR_LEN)) { 1957 /* 1958 * We must listen to a range of multicast 1959 * addresses. For now, just accept all 1960 * multicasts, rather than trying to set only 1961 * those filter bits needed to match the range. 1962 * (At this time, the only use of address 1963 * ranges is for IP multicast routing, for 1964 * which the range is big enough to require 1965 * all bits set.) 1966 */ 1967 ifp->if_flags |= IFF_ALLMULTI; 1968 ETHER_UNLOCK(ec); 1969 goto again; 1970 } 1971 1972 mcnt++; 1973 crc = 0xffffffff; 1974 1975 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1976 octet = enm->enm_addrlo[i]; 1977 for (j = 0; j < 8; j++) { 1978 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1979 (octet & 1); 1980 crc <<= 1; 1981 octet >>= 1; 1982 if (carry) 1983 crc = (crc ^ TXP_POLYNOMIAL) | 1984 carry; 1985 } 1986 } 1987 hashbit = (uint16_t)(crc & (64 - 1)); 1988 hash[hashbit / 32] |= (1 << hashbit % 32); 1989 ETHER_NEXT_MULTI(step, enm); 1990 } 1991 ETHER_UNLOCK(ec); 1992 1993 if (mcnt > 0) { 1994 filter |= TXP_RXFILT_HASHMULTI; 1995 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1996 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1997 } 1998 } 1999 2000 setit: 2001 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2002 NULL, NULL, NULL, 1); 2003 } 2004 2005 void 2006 txp_capabilities(struct txp_softc *sc) 2007 { 2008 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2009 struct txp_rsp_desc *rsp = NULL; 2010 struct txp_ext_desc *ext; 2011 2012 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2013 goto out; 2014 2015 if (rsp->rsp_numdesc != 1) 2016 goto out; 2017 ext = (struct txp_ext_desc *)(rsp + 1); 2018 2019 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2020 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2021 2022 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2023 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2024 sc->sc_tx_capability |= OFFLOAD_VLAN; 2025 sc->sc_rx_capability |= OFFLOAD_VLAN; 2026 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2027 } 2028 2029 #if 0 2030 /* not ready yet */ 2031 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2032 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2033 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2034 ifp->if_capabilities |= IFCAP_IPSEC; 2035 } 2036 #endif 2037 2038 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2039 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2040 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2041 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2042 } 2043 2044 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2045 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2046 #ifdef TRY_TX_TCP_CSUM 2047 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2048 ifp->if_capabilities |= 2049 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2050 #endif 2051 } 2052 2053 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2054 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2055 #ifdef TRY_TX_UDP_CSUM 2056 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2057 ifp->if_capabilities |= 2058 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2059 #endif 2060 } 2061 2062 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2063 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2064 goto out; 2065 2066 out: 2067 if (rsp != NULL) 2068 free(rsp, M_DEVBUF); 2069 } 2070
Indexes created Tue Sep 30 20:09:53 GMT 2025