if_txp.c revision 1.49.2.2
1 /* $NetBSD: if_txp.c,v 1.49.2.2 2020/04/13 08:04:26 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason (at) thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron (at) monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.49.2.2 2020/04/13 08:04:26 martin Exp $"); 36 37 #include "opt_inet.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/device.h> 47 #include <sys/callout.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 #include <net/if_media.h> 56 #include <net/bpf.h> 57 58 #ifdef INET 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 #endif 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/pci/if_txpreg.h> 73 74 #include <dev/microcode/typhoon/3c990img.h> 75 76 /* 77 * These currently break the 3c990 firmware, hopefully will be resolved 78 * at some point. 79 */ 80 #undef TRY_TX_UDP_CSUM 81 #undef TRY_TX_TCP_CSUM 82 83 static int txp_probe(device_t, cfdata_t, void *); 84 static void txp_attach(device_t, device_t, void *); 85 static int txp_intr(void *); 86 static void txp_tick(void *); 87 static bool txp_shutdown(device_t, int); 88 static int txp_ioctl(struct ifnet *, u_long, void *); 89 static void txp_start(struct ifnet *); 90 static void txp_stop(struct txp_softc *); 91 static void txp_init(struct txp_softc *); 92 static void txp_watchdog(struct ifnet *); 93 94 static int txp_chip_init(struct txp_softc *); 95 static int txp_reset_adapter(struct txp_softc *); 96 static int txp_download_fw(struct txp_softc *); 97 static int txp_download_fw_wait(struct txp_softc *); 98 static int txp_download_fw_section(struct txp_softc *, 99 const struct txp_fw_section_header *, int); 100 static int txp_alloc_rings(struct txp_softc *); 101 static void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 102 static int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 103 static void txp_set_filter(struct txp_softc *); 104 105 static int txp_cmd_desc_numfree(struct txp_softc *); 106 static int txp_command(struct txp_softc *, uint16_t, uint16_t, uint32_t, 107 uint32_t, uint16_t *, uint32_t *, uint32_t *, int); 108 static int txp_command2(struct txp_softc *, uint16_t, uint16_t, 109 uint32_t, uint32_t, struct txp_ext_desc *, uint8_t, 110 struct txp_rsp_desc **, int); 111 static int txp_response(struct txp_softc *, uint32_t, uint16_t, uint16_t, 112 struct txp_rsp_desc **); 113 static void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 114 struct txp_rsp_desc *); 115 static void txp_capabilities(struct txp_softc *); 116 117 static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static int txp_ifmedia_upd(struct ifnet *); 119 static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 120 struct txp_dma_alloc *); 121 static void txp_rxbuf_reclaim(struct txp_softc *); 122 static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 123 struct txp_dma_alloc *); 124 125 static void txp_rxd_free(struct txp_softc *, struct txp_swdesc *); 126 static struct txp_swdesc *txp_rxd_alloc(struct txp_softc *); 127 128 CFATTACH_DECL_NEW(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 129 NULL, NULL); 130 131 static const struct txp_pci_match { 132 int vid, did, flags; 133 } txp_devices[] = { 134 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 136 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 138 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 142 }; 143 144 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 145 146 static const struct { 147 uint16_t mask, value; 148 int flags; 149 } txp_subsysinfo[] = { 150 {0xf000, 0x2000, TXP_SERVERVERSION}, 151 {0x0100, 0x0100, TXP_FIBER}, 152 #if 0 /* information from 3com header, unused */ 153 {0x0010, 0x0010, /* secured firmware */}, 154 {0x0003, 0x0000, /* variable DES */}, 155 {0x0003, 0x0001, /* single DES - "95" */}, 156 {0x0003, 0x0002, /* triple DES - "97" */}, 157 #endif 158 }; 159 160 static const struct txp_pci_match * 161 txp_pcilookup(pcireg_t id) 162 { 163 int i; 164 165 for (i = 0; i < __arraycount(txp_devices); i++) 166 if (PCI_VENDOR(id) == txp_devices[i].vid && 167 PCI_PRODUCT(id) == txp_devices[i].did) 168 return &txp_devices[i]; 169 return (0); 170 } 171 172 static int 173 txp_probe(device_t parent, cfdata_t match, void *aux) 174 { 175 struct pci_attach_args *pa = aux; 176 177 if (txp_pcilookup(pa->pa_id)) 178 return (1); 179 return (0); 180 } 181 182 static void 183 txp_attach(device_t parent, device_t self, void *aux) 184 { 185 struct txp_softc *sc = device_private(self); 186 struct pci_attach_args *pa = aux; 187 pci_chipset_tag_t pc = pa->pa_pc; 188 pci_intr_handle_t ih; 189 const char *intrstr = NULL; 190 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 191 uint32_t command; 192 uint16_t p1; 193 uint32_t p2; 194 u_char enaddr[6]; 195 const struct txp_pci_match *match; 196 uint16_t subsys; 197 int i, flags; 198 char devinfo[256]; 199 char intrbuf[PCI_INTRSTR_LEN]; 200 201 sc->sc_dev = self; 202 sc->sc_cold = 1; 203 204 match = txp_pcilookup(pa->pa_id); 205 flags = match->flags; 206 if (match->flags & TXP_USESUBSYSTEM) { 207 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 208 PCI_SUBSYS_ID_REG)); 209 for (i = 0; 210 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 211 i++) 212 if ((subsys & txp_subsysinfo[i].mask) == 213 txp_subsysinfo[i].value) 214 flags |= txp_subsysinfo[i].flags; 215 } 216 sc->sc_flags = flags; 217 218 aprint_naive("\n"); 219 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 220 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM | TXP_SERVERVERSION)) == \ 221 (TXP_USESUBSYSTEM | TXP_SERVERVERSION) ? " (SVR)" : "") 222 aprint_normal(": %s%s\n%s", devinfo, TXP_EXTRAINFO, 223 device_xname(sc->sc_dev)); 224 225 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 226 227 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 228 aprint_error(": failed to enable bus mastering\n"); 229 return; 230 } 231 232 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 233 aprint_error(": failed to enable memory mapping\n"); 234 return; 235 } 236 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 237 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 238 aprint_error(": can't map mem space %d\n", 0); 239 return; 240 } 241 242 if (pci_dma64_available(pa)) 243 sc->sc_dmat = pa->pa_dmat64; 244 else 245 sc->sc_dmat = pa->pa_dmat; 246 247 /* 248 * Allocate our interrupt. 249 */ 250 if (pci_intr_map(pa, &ih)) { 251 aprint_error(": couldn't map interrupt\n"); 252 return; 253 } 254 255 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 256 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, txp_intr, sc, 257 device_xname(self)); 258 if (sc->sc_ih == NULL) { 259 aprint_error(": couldn't establish interrupt"); 260 if (intrstr != NULL) 261 aprint_normal(" at %s", intrstr); 262 aprint_normal("\n"); 263 return; 264 } 265 aprint_normal(": interrupting at %s\n", intrstr); 266 267 if (txp_chip_init(sc)) 268 goto cleanupintr; 269 270 if (txp_download_fw(sc)) 271 goto cleanupintr; 272 273 if (txp_alloc_rings(sc)) 274 goto cleanupintr; 275 276 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 277 NULL, NULL, NULL, 1)) 278 goto cleanupintr; 279 280 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 281 &p1, &p2, NULL, 1)) 282 goto cleanupintr; 283 284 p1 = htole16(p1); 285 enaddr[0] = ((uint8_t *)&p1)[1]; 286 enaddr[1] = ((uint8_t *)&p1)[0]; 287 p2 = htole32(p2); 288 enaddr[2] = ((uint8_t *)&p2)[3]; 289 enaddr[3] = ((uint8_t *)&p2)[2]; 290 enaddr[4] = ((uint8_t *)&p2)[1]; 291 enaddr[5] = ((uint8_t *)&p2)[0]; 292 293 aprint_normal_dev(self, "Ethernet address %s\n", 294 ether_sprintf(enaddr)); 295 sc->sc_cold = 0; 296 297 /* Initialize ifmedia structures. */ 298 sc->sc_arpcom.ec_ifmedia = &sc->sc_ifmedia; 299 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 300 if (flags & TXP_FIBER) { 301 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX, 302 0, NULL); 303 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_FX | IFM_FDX, 304 0, NULL); 305 } else { 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 309 0, NULL); 310 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 311 0, NULL); 312 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 313 0, NULL); 314 } 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 316 317 sc->sc_xcvr = TXP_XCVR_AUTO; 318 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 319 NULL, NULL, NULL, 0); 320 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 321 322 ifp->if_softc = sc; 323 ifp->if_mtu = ETHERMTU; 324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 325 ifp->if_ioctl = txp_ioctl; 326 ifp->if_start = txp_start; 327 ifp->if_watchdog = txp_watchdog; 328 ifp->if_baudrate = 10000000; 329 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 330 IFQ_SET_READY(&ifp->if_snd); 331 ifp->if_capabilities = 0; 332 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 333 334 txp_capabilities(sc); 335 336 callout_init(&sc->sc_tick, 0); 337 callout_setfunc(&sc->sc_tick, txp_tick, sc); 338 339 /* 340 * Attach us everywhere 341 */ 342 if_attach(ifp); 343 if_deferred_start_init(ifp, NULL); 344 ether_ifattach(ifp, enaddr); 345 346 /* 347 * XXX Because we allocate Rx buffers in txp_alloc_rings(), 348 * XXX we have to go back and claim them now that our mowners 349 * XXX have been initialized (in ether_ifattach()). 350 * 351 * XXX FIXME by allocating Rx buffers only when interface is 352 * XXX running, like other drivers do. 353 */ 354 for (i = 0; i < RXBUF_ENTRIES; i++) { 355 KASSERT(sc->sc_rxd[i].sd_mbuf != NULL); 356 MCLAIM(sc->sc_rxd[i].sd_mbuf, &sc->sc_arpcom.ec_rx_mowner); 357 } 358 359 if (pmf_device_register1(self, NULL, NULL, txp_shutdown)) 360 pmf_class_network_register(self, ifp); 361 else 362 aprint_error_dev(self, "couldn't establish power handler\n"); 363 364 return; 365 366 cleanupintr: 367 pci_intr_disestablish(pc, sc->sc_ih); 368 369 return; 370 371 } 372 373 static int 374 txp_chip_init(struct txp_softc *sc) 375 { 376 /* disable interrupts */ 377 WRITE_REG(sc, TXP_IER, 0); 378 WRITE_REG(sc, TXP_IMR, 379 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 380 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 381 TXP_INT_LATCH); 382 383 /* ack all interrupts */ 384 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 385 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 386 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 387 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 388 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 389 390 if (txp_reset_adapter(sc)) 391 return (-1); 392 393 /* disable interrupts */ 394 WRITE_REG(sc, TXP_IER, 0); 395 WRITE_REG(sc, TXP_IMR, 396 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 397 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 398 TXP_INT_LATCH); 399 400 /* ack all interrupts */ 401 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 402 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 403 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 404 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 405 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 406 407 return (0); 408 } 409 410 static int 411 txp_reset_adapter(struct txp_softc *sc) 412 { 413 uint32_t r; 414 int i; 415 416 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 417 DELAY(1000); 418 WRITE_REG(sc, TXP_SRR, 0); 419 420 /* Should wait max 6 seconds */ 421 for (i = 0; i < 6000; i++) { 422 r = READ_REG(sc, TXP_A2H_0); 423 if (r == STAT_WAITING_FOR_HOST_REQUEST) 424 break; 425 DELAY(1000); 426 } 427 428 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 429 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 430 return (-1); 431 } 432 433 return (0); 434 } 435 436 static int 437 txp_download_fw(struct txp_softc *sc) 438 { 439 const struct txp_fw_file_header *fileheader; 440 const struct txp_fw_section_header *secthead; 441 int sect; 442 uint32_t r, i, ier, imr; 443 444 ier = READ_REG(sc, TXP_IER); 445 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 446 447 imr = READ_REG(sc, TXP_IMR); 448 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 449 450 for (i = 0; i < 10000; i++) { 451 r = READ_REG(sc, TXP_A2H_0); 452 if (r == STAT_WAITING_FOR_HOST_REQUEST) 453 break; 454 DELAY(50); 455 } 456 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 457 printf(": not waiting for host request\n"); 458 return (-1); 459 } 460 461 /* Ack the status */ 462 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 463 464 fileheader = (const struct txp_fw_file_header *)tc990image; 465 if (memcmp("TYPHOON", fileheader->magicid, 466 sizeof(fileheader->magicid))) { 467 printf(": fw invalid magic\n"); 468 return (-1); 469 } 470 471 /* Tell boot firmware to get ready for image */ 472 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 473 WRITE_REG(sc, TXP_H2A_2, le32toh(fileheader->hmac[0])); 474 WRITE_REG(sc, TXP_H2A_3, le32toh(fileheader->hmac[1])); 475 WRITE_REG(sc, TXP_H2A_4, le32toh(fileheader->hmac[2])); 476 WRITE_REG(sc, TXP_H2A_5, le32toh(fileheader->hmac[3])); 477 WRITE_REG(sc, TXP_H2A_6, le32toh(fileheader->hmac[4])); 478 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 479 480 if (txp_download_fw_wait(sc)) { 481 printf("%s: fw wait failed, initial\n", 482 device_xname(sc->sc_dev)); 483 return (-1); 484 } 485 486 secthead = (const struct txp_fw_section_header *) 487 (((const uint8_t *)tc990image) + 488 sizeof(struct txp_fw_file_header)); 489 490 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 491 if (txp_download_fw_section(sc, secthead, sect)) 492 return (-1); 493 secthead = (const struct txp_fw_section_header *) 494 (((const uint8_t *)secthead) + le32toh(secthead->nbytes) + 495 sizeof(*secthead)); 496 } 497 498 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 499 500 for (i = 0; i < 10000; i++) { 501 r = READ_REG(sc, TXP_A2H_0); 502 if (r == STAT_WAITING_FOR_BOOT) 503 break; 504 DELAY(50); 505 } 506 if (r != STAT_WAITING_FOR_BOOT) { 507 printf(": not waiting for boot\n"); 508 return (-1); 509 } 510 511 WRITE_REG(sc, TXP_IER, ier); 512 WRITE_REG(sc, TXP_IMR, imr); 513 514 return (0); 515 } 516 517 static int 518 txp_download_fw_wait(struct txp_softc *sc) 519 { 520 uint32_t i, r; 521 522 for (i = 0; i < 10000; i++) { 523 r = READ_REG(sc, TXP_ISR); 524 if (r & TXP_INT_A2H_0) 525 break; 526 DELAY(50); 527 } 528 529 if (!(r & TXP_INT_A2H_0)) { 530 printf(": fw wait failed comm0\n"); 531 return (-1); 532 } 533 534 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 535 536 r = READ_REG(sc, TXP_A2H_0); 537 if (r != STAT_WAITING_FOR_SEGMENT) { 538 printf(": fw not waiting for segment\n"); 539 return (-1); 540 } 541 return (0); 542 } 543 544 static int 545 txp_download_fw_section(struct txp_softc *sc, 546 const struct txp_fw_section_header *sect, int sectnum) 547 { 548 struct txp_dma_alloc dma; 549 int rseg, err = 0; 550 struct mbuf m; 551 #ifdef INET 552 uint16_t csum; 553 #endif 554 555 /* Skip zero length sections */ 556 if (sect->nbytes == 0) 557 return (0); 558 559 /* Make sure we aren't past the end of the image */ 560 rseg = ((const uint8_t *)sect) - ((const uint8_t *)tc990image); 561 if (rseg >= sizeof(tc990image)) { 562 printf(": fw invalid section address, section %d\n", sectnum); 563 return (-1); 564 } 565 566 /* Make sure this section doesn't go past the end */ 567 rseg += le32toh(sect->nbytes); 568 if (rseg >= sizeof(tc990image)) { 569 printf(": fw truncated section %d\n", sectnum); 570 return (-1); 571 } 572 573 /* map a buffer, copy segment to it, get physaddr */ 574 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 575 printf(": fw dma malloc failed, section %d\n", sectnum); 576 return (-1); 577 } 578 579 memcpy(dma.dma_vaddr, ((const uint8_t *)sect) + sizeof(*sect), 580 le32toh(sect->nbytes)); 581 582 /* 583 * dummy up mbuf and verify section checksum 584 */ 585 m.m_type = MT_DATA; 586 m.m_next = m.m_nextpkt = NULL; 587 m.m_owner = NULL; 588 m.m_len = le32toh(sect->nbytes); 589 m.m_data = dma.dma_vaddr; 590 m.m_flags = 0; 591 #ifdef INET 592 csum = in_cksum(&m, le32toh(sect->nbytes)); 593 if (csum != sect->cksum) { 594 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 595 sectnum, sect->cksum, csum); 596 txp_dma_free(sc, &dma); 597 return -1; 598 } 599 #endif 600 601 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 602 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 603 604 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 605 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 606 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 607 WRITE_REG(sc, TXP_H2A_4, BUS_ADDR_HI32(dma.dma_paddr)); 608 WRITE_REG(sc, TXP_H2A_5, BUS_ADDR_LO32(dma.dma_paddr)); 609 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 610 611 if (txp_download_fw_wait(sc)) { 612 printf("%s: fw wait failed, section %d\n", 613 device_xname(sc->sc_dev), sectnum); 614 err = -1; 615 } 616 617 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 618 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 619 620 txp_dma_free(sc, &dma); 621 return (err); 622 } 623 624 static int 625 txp_intr(void *vsc) 626 { 627 struct txp_softc *sc = vsc; 628 struct txp_hostvar *hv = sc->sc_hostvar; 629 uint32_t isr; 630 int claimed = 0; 631 632 /* mask all interrupts */ 633 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 634 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 635 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 636 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 637 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 638 639 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 640 sizeof(struct txp_hostvar), 641 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 642 643 isr = READ_REG(sc, TXP_ISR); 644 while (isr) { 645 claimed = 1; 646 WRITE_REG(sc, TXP_ISR, isr); 647 648 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 649 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 650 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 651 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 652 653 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 654 txp_rxbuf_reclaim(sc); 655 656 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 657 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 658 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 659 660 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 661 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 662 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 663 664 isr = READ_REG(sc, TXP_ISR); 665 } 666 667 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 668 sizeof(struct txp_hostvar), 669 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 670 671 /* unmask all interrupts */ 672 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 673 674 if_schedule_deferred_start(&sc->sc_arpcom.ec_if); 675 676 return (claimed); 677 } 678 679 static struct txp_swdesc * 680 txp_rxd_alloc(struct txp_softc *sc) 681 { 682 if (sc->sc_txd_pool_ptr == 0) 683 return NULL; 684 return sc->sc_rxd_pool[--sc->sc_txd_pool_ptr]; 685 } 686 687 static void 688 txp_rxd_free(struct txp_softc *sc, struct txp_swdesc *sd) 689 { 690 KASSERT(sc->sc_txd_pool_ptr < RXBUF_ENTRIES); 691 sc->sc_rxd_pool[sc->sc_txd_pool_ptr++] = sd; 692 } 693 694 static inline uint32_t 695 txp_rxd_idx(struct txp_softc *sc, struct txp_swdesc *sd) 696 { 697 KASSERT(sd >= &sc->sc_rxd[0] && sd < &sc->sc_rxd[RXBUF_ENTRIES]); 698 return (uint32_t)(sd - &sc->sc_rxd[0]); 699 } 700 701 static inline uint32_t 702 txp_txd_idx(struct txp_softc *sc, struct txp_swdesc *sd) 703 { 704 KASSERT(sd >= &sc->sc_txd[0] && sd < &sc->sc_txd[TX_ENTRIES]); 705 return (uint32_t)(sd - &sc->sc_txd[0]); 706 } 707 708 static void 709 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, 710 struct txp_dma_alloc *dma) 711 { 712 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 713 struct txp_rx_desc *rxd; 714 struct mbuf *m; 715 struct txp_swdesc *sd; 716 uint32_t roff, woff; 717 uint16_t len; 718 int sumflags = 0; 719 int idx; 720 721 roff = le32toh(*r->r_roff); 722 woff = le32toh(*r->r_woff); 723 idx = roff / sizeof(struct txp_rx_desc); 724 rxd = r->r_desc + idx; 725 726 while (roff != woff) { 727 728 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 729 idx * sizeof(struct txp_rx_desc), 730 sizeof(struct txp_rx_desc), BUS_DMASYNC_POSTREAD); 731 732 if (rxd->rx_flags & RX_FLAGS_ERROR) { 733 printf("%s: error 0x%x\n", device_xname(sc->sc_dev), 734 le32toh(rxd->rx_stat)); 735 if_statinc(ifp, if_ierrors); 736 goto next; 737 } 738 739 /* retrieve stashed pointer */ 740 KASSERT(rxd->rx_vaddrlo < RXBUF_ENTRIES); 741 sd = &sc->sc_rxd[rxd->rx_vaddrlo]; 742 743 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 744 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 745 746 len = le16toh(rxd->rx_len); 747 748 #ifdef __NO_STRICT_ALIGNMENT 749 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 750 m = sd->sd_mbuf; 751 sd->sd_mbuf = NULL; 752 txp_rxd_free(sc, sd); 753 #else 754 /* 755 * The Typhoon's receive buffers must be 4-byte aligned. 756 * But this means the data after the Ethernet header 757 * is misaligned. We must allocate a new buffer and 758 * copy the data, shifted forward 2 bytes. 759 */ 760 MGETHDR(m, M_DONTWAIT, MT_DATA); 761 if (m == NULL) { 762 dropit: 763 if_statinc(ifp, if_ierrors); 764 txp_rxd_free(sc, sd); 765 goto next; 766 } 767 MCLAIM(m, &sc->sc_arpcom.ec_rx_mowner); 768 if (len > (MHLEN - ETHER_ALIGN)) { 769 MCLGET(m, M_DONTWAIT); 770 if ((m->m_flags & M_EXT) == 0) { 771 m_freem(m); 772 goto dropit; 773 } 774 } 775 m_set_rcvif(m, ifp); 776 m->m_data += ETHER_ALIGN; 777 memcpy(mtod(m, void *), mtod(sd->sd_mbuf, void *), len); 778 txp_rxd_free(sc, sd); 779 #endif /* __NO_STRICT_ALIGNMENT */ 780 781 m->m_pkthdr.len = m->m_len = len; 782 783 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 784 sumflags |= (M_CSUM_IPv4 | M_CSUM_IPv4_BAD); 785 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 786 sumflags |= M_CSUM_IPv4; 787 788 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 789 sumflags |= (M_CSUM_TCPv4 | M_CSUM_TCP_UDP_BAD); 790 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 791 sumflags |= M_CSUM_TCPv4; 792 793 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 794 sumflags |= (M_CSUM_UDPv4 | M_CSUM_TCP_UDP_BAD); 795 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 796 sumflags |= M_CSUM_UDPv4; 797 798 m->m_pkthdr.csum_flags = sumflags; 799 800 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 801 vlan_set_tag(m, htons(rxd->rx_vlan >> 16)); 802 } 803 804 if_percpuq_enqueue(ifp->if_percpuq, m); 805 806 next: 807 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 808 idx * sizeof(struct txp_rx_desc), 809 sizeof(struct txp_rx_desc), BUS_DMASYNC_PREREAD); 810 811 roff += sizeof(struct txp_rx_desc); 812 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 813 idx = 0; 814 roff = 0; 815 rxd = r->r_desc; 816 } else { 817 idx++; 818 rxd++; 819 } 820 woff = le32toh(*r->r_woff); 821 } 822 823 *r->r_roff = htole32(woff); 824 } 825 826 static void 827 txp_rxbuf_reclaim(struct txp_softc *sc) 828 { 829 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 830 struct txp_hostvar *hv = sc->sc_hostvar; 831 struct txp_rxbuf_desc *rbd; 832 struct txp_swdesc *sd; 833 uint32_t i, end; 834 835 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 836 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 837 838 if (++i == RXBUF_ENTRIES) 839 i = 0; 840 841 rbd = sc->sc_rxbufs + i; 842 843 while (i != end) { 844 sd = txp_rxd_alloc(sc); 845 if (sd == NULL) 846 break; 847 848 /* We might already have a buffer allocated. */ 849 if (sd->sd_mbuf == NULL) { 850 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 851 if (sd->sd_mbuf == NULL) 852 goto err_sd; 853 MCLAIM(sd->sd_mbuf, &sc->sc_arpcom.ec_rx_mowner); 854 855 MCLGET(sd->sd_mbuf, M_DONTWAIT); 856 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 857 goto err_mbuf; 858 m_set_rcvif(sd->sd_mbuf, ifp); 859 sd->sd_mbuf->m_pkthdr.len = 860 sd->sd_mbuf->m_len = MCLBYTES; 861 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, 862 sd->sd_mbuf, BUS_DMA_NOWAIT)) { 863 goto err_mbuf; 864 } 865 } 866 867 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 868 i * sizeof(struct txp_rxbuf_desc), 869 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 870 871 /* stash away pointer */ 872 rbd->rb_vaddrlo = txp_rxd_idx(sc, sd); 873 874 rbd->rb_paddrlo = 875 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 876 rbd->rb_paddrhi = 877 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 878 879 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 880 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 881 882 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 883 i * sizeof(struct txp_rxbuf_desc), 884 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 885 886 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 887 888 if (++i == RXBUF_ENTRIES) { 889 i = 0; 890 rbd = sc->sc_rxbufs; 891 } else 892 rbd++; 893 } 894 return; 895 896 err_mbuf: 897 m_freem(sd->sd_mbuf); 898 sd->sd_mbuf = NULL; 899 err_sd: 900 txp_rxd_free(sc, sd); 901 } 902 903 /* 904 * Reclaim mbufs and entries from a transmit ring. 905 */ 906 static void 907 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, 908 struct txp_dma_alloc *dma) 909 { 910 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 911 uint32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 912 uint32_t cons = r->r_cons, cnt = r->r_cnt; 913 struct txp_tx_desc *txd = r->r_desc + cons; 914 struct txp_swdesc *sd; 915 struct mbuf *m; 916 917 while (cons != idx) { 918 if (cnt == 0) 919 break; 920 921 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 922 cons * sizeof(struct txp_tx_desc), 923 sizeof(struct txp_tx_desc), 924 BUS_DMASYNC_POSTWRITE); 925 926 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 927 TX_FLAGS_TYPE_DATA) { 928 KASSERT(txd->tx_addrlo < TX_ENTRIES); 929 sd = &sc->sc_txd[txd->tx_addrlo]; 930 m = sd->sd_mbuf; 931 sd->sd_mbuf = NULL; 932 if (m != NULL) { 933 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 934 sd->sd_map->dm_mapsize, 935 BUS_DMASYNC_POSTWRITE); 936 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 937 m_freem(m); 938 txd->tx_addrlo = 0; 939 txd->tx_addrhi = 0; 940 if_statinc(ifp, if_opackets); 941 } 942 } 943 ifp->if_flags &= ~IFF_OACTIVE; 944 945 if (++cons == TX_ENTRIES) { 946 txd = r->r_desc; 947 cons = 0; 948 } else 949 txd++; 950 951 cnt--; 952 } 953 954 r->r_cons = cons; 955 r->r_cnt = cnt; 956 if (cnt == 0) 957 ifp->if_timer = 0; 958 } 959 960 static bool 961 txp_shutdown(device_t self, int howto) 962 { 963 struct txp_softc *sc; 964 965 sc = device_private(self); 966 967 /* mask all interrupts */ 968 WRITE_REG(sc, TXP_IMR, 969 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 970 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 971 TXP_INT_LATCH); 972 973 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 974 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 975 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 976 977 return true; 978 } 979 980 static int 981 txp_alloc_rings(struct txp_softc *sc) 982 { 983 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 984 struct txp_boot_record *boot; 985 struct txp_swdesc *sd; 986 uint32_t r; 987 int i, j, nb; 988 989 /* boot record */ 990 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), 991 &sc->sc_boot_dma, BUS_DMA_COHERENT)) { 992 printf(": can't allocate boot record\n"); 993 return (-1); 994 } 995 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 996 memset(boot, 0, sizeof(*boot)); 997 sc->sc_boot = boot; 998 999 /* host variables */ 1000 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 1001 BUS_DMA_COHERENT)) { 1002 printf(": can't allocate host ring\n"); 1003 goto bail_boot; 1004 } 1005 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 1006 boot->br_hostvar_lo = htole32(BUS_ADDR_LO32(sc->sc_host_dma.dma_paddr)); 1007 boot->br_hostvar_hi = htole32(BUS_ADDR_HI32(sc->sc_host_dma.dma_paddr)); 1008 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 1009 1010 /* high priority tx ring */ 1011 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1012 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 1013 printf(": can't allocate high tx ring\n"); 1014 goto bail_host; 1015 } 1016 memset(sc->sc_txhiring_dma.dma_vaddr, 0, 1017 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1018 boot->br_txhipri_lo = 1019 htole32(BUS_ADDR_LO32(sc->sc_txhiring_dma.dma_paddr)); 1020 boot->br_txhipri_hi = 1021 htole32(BUS_ADDR_HI32(sc->sc_txhiring_dma.dma_paddr)); 1022 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1023 sc->sc_txhir.r_reg = TXP_H2A_1; 1024 sc->sc_txhir.r_desc = 1025 (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 1026 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 1027 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 1028 for (i = 0; i < TX_ENTRIES; i++) { 1029 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1030 TXP_MAXTXSEGS, TXP_MAX_SEGLEN, 0, BUS_DMA_NOWAIT, 1031 &sc->sc_txd[i].sd_map) != 0) { 1032 for (j = 0; j < i; j++) { 1033 bus_dmamap_destroy(sc->sc_dmat, 1034 sc->sc_txd[j].sd_map); 1035 sc->sc_txd[j].sd_map = NULL; 1036 } 1037 goto bail_txhiring; 1038 } 1039 } 1040 1041 /* low priority tx ring */ 1042 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1043 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1044 printf(": can't allocate low tx ring\n"); 1045 goto bail_txhiring; 1046 } 1047 memset(sc->sc_txloring_dma.dma_vaddr, 0, 1048 sizeof(struct txp_tx_desc) * TX_ENTRIES); 1049 boot->br_txlopri_lo = 1050 htole32(BUS_ADDR_LO32(sc->sc_txloring_dma.dma_paddr)); 1051 boot->br_txlopri_hi = 1052 htole32(BUS_ADDR_HI32(sc->sc_txloring_dma.dma_paddr)); 1053 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1054 sc->sc_txlor.r_reg = TXP_H2A_3; 1055 sc->sc_txlor.r_desc = 1056 (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1057 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1058 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1059 1060 /* high priority rx ring */ 1061 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1062 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1063 printf(": can't allocate high rx ring\n"); 1064 goto bail_txloring; 1065 } 1066 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, 1067 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1068 boot->br_rxhipri_lo = 1069 htole32(BUS_ADDR_LO32(sc->sc_rxhiring_dma.dma_paddr)); 1070 boot->br_rxhipri_hi = 1071 htole32(BUS_ADDR_HI32(sc->sc_rxhiring_dma.dma_paddr)); 1072 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1073 sc->sc_rxhir.r_desc = 1074 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1075 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1076 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1077 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1078 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1079 1080 /* low priority ring */ 1081 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1082 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1083 printf(": can't allocate low rx ring\n"); 1084 goto bail_rxhiring; 1085 } 1086 memset(sc->sc_rxloring_dma.dma_vaddr, 0, 1087 sizeof(struct txp_rx_desc) * RX_ENTRIES); 1088 boot->br_rxlopri_lo = 1089 htole32(BUS_ADDR_LO32(sc->sc_rxloring_dma.dma_paddr)); 1090 boot->br_rxlopri_hi = 1091 htole32(BUS_ADDR_HI32(sc->sc_rxloring_dma.dma_paddr)); 1092 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1093 sc->sc_rxlor.r_desc = 1094 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1095 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1096 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1097 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1098 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1099 1100 /* command ring */ 1101 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1102 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1103 printf(": can't allocate command ring\n"); 1104 goto bail_rxloring; 1105 } 1106 memset(sc->sc_cmdring_dma.dma_vaddr, 0, 1107 sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1108 boot->br_cmd_lo = htole32(BUS_ADDR_LO32(sc->sc_cmdring_dma.dma_paddr)); 1109 boot->br_cmd_hi = htole32(BUS_ADDR_HI32(sc->sc_cmdring_dma.dma_paddr)); 1110 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1111 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1112 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1113 sc->sc_cmdring.lastwrite = 0; 1114 1115 /* response ring */ 1116 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1117 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1118 printf(": can't allocate response ring\n"); 1119 goto bail_cmdring; 1120 } 1121 memset(sc->sc_rspring_dma.dma_vaddr, 0, 1122 sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1123 boot->br_resp_lo = htole32(BUS_ADDR_LO32(sc->sc_rspring_dma.dma_paddr)); 1124 boot->br_resp_hi = htole32(BUS_ADDR_HI32(sc->sc_rspring_dma.dma_paddr)); 1125 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1126 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1127 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1128 sc->sc_rspring.lastwrite = 0; 1129 1130 /* receive buffer ring */ 1131 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1132 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1133 printf(": can't allocate rx buffer ring\n"); 1134 goto bail_rspring; 1135 } 1136 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, 1137 sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1138 boot->br_rxbuf_lo = htole32(BUS_ADDR_LO32(sc->sc_rxbufring_dma.dma_paddr)); 1139 boot->br_rxbuf_hi = htole32(BUS_ADDR_HI32(sc->sc_rxbufring_dma.dma_paddr)); 1140 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1141 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1142 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1143 sd = &sc->sc_rxd[nb]; 1144 1145 /* stash away pointer */ 1146 sc->sc_rxbufs[nb].rb_vaddrlo = txp_rxd_idx(sc, sd); 1147 1148 MGETHDR(sd->sd_mbuf, M_WAIT, MT_DATA); 1149 if (sd->sd_mbuf == NULL) { 1150 goto bail_rxbufring; 1151 } 1152 1153 MCLGET(sd->sd_mbuf, M_WAIT); 1154 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1155 goto bail_rxbufring; 1156 } 1157 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1158 m_set_rcvif(sd->sd_mbuf, ifp); 1159 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1160 TXP_MAX_PKTLEN, 0, BUS_DMA_WAITOK, &sd->sd_map)) { 1161 goto bail_rxbufring; 1162 } 1163 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1164 BUS_DMA_WAITOK)) { 1165 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1166 goto bail_rxbufring; 1167 } 1168 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1169 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1170 1171 sc->sc_rxbufs[nb].rb_paddrlo = 1172 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[0].ds_addr)); 1173 sc->sc_rxbufs[nb].rb_paddrhi = 1174 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[0].ds_addr)); 1175 } 1176 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1177 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1178 BUS_DMASYNC_PREWRITE); 1179 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1180 sizeof(struct txp_rxbuf_desc)); 1181 1182 /* zero dma */ 1183 if (txp_dma_malloc(sc, sizeof(uint32_t), &sc->sc_zero_dma, 1184 BUS_DMA_COHERENT)) { 1185 printf(": can't allocate response ring\n"); 1186 goto bail_rxbufring; 1187 } 1188 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(uint32_t)); 1189 boot->br_zero_lo = htole32(BUS_ADDR_LO32(sc->sc_zero_dma.dma_paddr)); 1190 boot->br_zero_hi = htole32(BUS_ADDR_HI32(sc->sc_zero_dma.dma_paddr)); 1191 1192 /* See if it's waiting for boot, and try to boot it */ 1193 for (i = 0; i < 10000; i++) { 1194 r = READ_REG(sc, TXP_A2H_0); 1195 if (r == STAT_WAITING_FOR_BOOT) 1196 break; 1197 DELAY(50); 1198 } 1199 if (r != STAT_WAITING_FOR_BOOT) { 1200 printf(": not waiting for boot\n"); 1201 goto bail; 1202 } 1203 WRITE_REG(sc, TXP_H2A_2, BUS_ADDR_HI32(sc->sc_boot_dma.dma_paddr)); 1204 WRITE_REG(sc, TXP_H2A_1, BUS_ADDR_LO32(sc->sc_boot_dma.dma_paddr)); 1205 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1206 1207 /* See if it booted */ 1208 for (i = 0; i < 10000; i++) { 1209 r = READ_REG(sc, TXP_A2H_0); 1210 if (r == STAT_RUNNING) 1211 break; 1212 DELAY(50); 1213 } 1214 if (r != STAT_RUNNING) { 1215 printf(": fw not running\n"); 1216 goto bail; 1217 } 1218 1219 /* Clear TX and CMD ring write registers */ 1220 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1221 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1222 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1223 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1224 1225 return (0); 1226 1227 bail: 1228 txp_dma_free(sc, &sc->sc_zero_dma); 1229 bail_rxbufring: 1230 if (nb == RXBUF_ENTRIES) 1231 nb--; 1232 for (i = 0; i <= nb; i++) { 1233 memcpy(&sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1234 sizeof(sd)); 1235 /* XXXJRT */ 1236 } 1237 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1238 bail_rspring: 1239 txp_dma_free(sc, &sc->sc_rspring_dma); 1240 bail_cmdring: 1241 txp_dma_free(sc, &sc->sc_cmdring_dma); 1242 bail_rxloring: 1243 txp_dma_free(sc, &sc->sc_rxloring_dma); 1244 bail_rxhiring: 1245 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1246 bail_txloring: 1247 txp_dma_free(sc, &sc->sc_txloring_dma); 1248 bail_txhiring: 1249 txp_dma_free(sc, &sc->sc_txhiring_dma); 1250 bail_host: 1251 txp_dma_free(sc, &sc->sc_host_dma); 1252 bail_boot: 1253 txp_dma_free(sc, &sc->sc_boot_dma); 1254 return (-1); 1255 } 1256 1257 static int 1258 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, 1259 struct txp_dma_alloc *dma, int mapflags) 1260 { 1261 int r; 1262 1263 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1264 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1265 goto fail_0; 1266 1267 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1268 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1269 goto fail_1; 1270 1271 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1272 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1273 goto fail_2; 1274 1275 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1276 size, NULL, BUS_DMA_NOWAIT)) != 0) 1277 goto fail_3; 1278 1279 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1280 return (0); 1281 1282 fail_3: 1283 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1284 fail_2: 1285 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1286 fail_1: 1287 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1288 fail_0: 1289 return (r); 1290 } 1291 1292 static void 1293 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1294 { 1295 bus_size_t mapsize = dma->dma_map->dm_mapsize; 1296 1297 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1298 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, mapsize); 1299 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1300 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1301 } 1302 1303 static int 1304 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1305 { 1306 struct txp_softc *sc = ifp->if_softc; 1307 struct ifaddr *ifa = (struct ifaddr *)data; 1308 int s, error = 0; 1309 1310 s = splnet(); 1311 1312 #if 0 1313 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1314 splx(s); 1315 return error; 1316 } 1317 #endif 1318 1319 switch (command) { 1320 case SIOCINITIFADDR: 1321 ifp->if_flags |= IFF_UP; 1322 txp_init(sc); 1323 switch (ifa->ifa_addr->sa_family) { 1324 #ifdef INET 1325 case AF_INET: 1326 arp_ifinit(ifp, ifa); 1327 break; 1328 #endif /* INET */ 1329 default: 1330 break; 1331 } 1332 break; 1333 case SIOCSIFFLAGS: 1334 if ((error = ifioctl_common(ifp, command, data)) != 0) 1335 break; 1336 if (ifp->if_flags & IFF_UP) { 1337 txp_init(sc); 1338 } else { 1339 if (ifp->if_flags & IFF_RUNNING) 1340 txp_stop(sc); 1341 } 1342 break; 1343 case SIOCADDMULTI: 1344 case SIOCDELMULTI: 1345 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1346 break; 1347 1348 error = 0; 1349 1350 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1351 ; 1352 else if (ifp->if_flags & IFF_RUNNING) { 1353 /* 1354 * Multicast list has changed; set the hardware 1355 * filter accordingly. 1356 */ 1357 txp_set_filter(sc); 1358 } 1359 break; 1360 default: 1361 error = ether_ioctl(ifp, command, data); 1362 break; 1363 } 1364 1365 splx(s); 1366 1367 return (error); 1368 } 1369 1370 static void 1371 txp_init(struct txp_softc *sc) 1372 { 1373 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1374 int s; 1375 1376 txp_stop(sc); 1377 1378 s = splnet(); 1379 1380 txp_set_filter(sc); 1381 1382 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1383 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1384 1385 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1386 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1387 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1388 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1389 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1390 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1391 1392 ifp->if_flags |= IFF_RUNNING; 1393 ifp->if_flags &= ~IFF_OACTIVE; 1394 ifp->if_timer = 0; 1395 1396 if (!callout_pending(&sc->sc_tick)) 1397 callout_schedule(&sc->sc_tick, hz); 1398 1399 splx(s); 1400 } 1401 1402 static void 1403 txp_tick(void *vsc) 1404 { 1405 struct txp_softc *sc = vsc; 1406 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1407 struct txp_rsp_desc *rsp = NULL; 1408 struct txp_ext_desc *ext; 1409 int s; 1410 1411 s = splnet(); 1412 txp_rxbuf_reclaim(sc); 1413 1414 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1415 &rsp, 1)) 1416 goto out; 1417 if (rsp->rsp_numdesc != 6) 1418 goto out; 1419 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1420 NULL, NULL, NULL, 1)) 1421 goto out; 1422 ext = (struct txp_ext_desc *)(rsp + 1); 1423 1424 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1425 if_statadd_ref(nsr, if_ierrors, 1426 ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1427 ext[4].ext_1 + ext[4].ext_4); 1428 if_statadd_ref(nsr, if_oerrors, 1429 ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1); 1430 if_statadd_ref(nsr, if_collisions, 1431 ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3); 1432 if_statadd_ref(nsr, if_opackets, rsp->rsp_par2); 1433 IF_STAT_PUTREF(ifp); 1434 1435 out: 1436 if (rsp != NULL) 1437 free(rsp, M_DEVBUF); 1438 1439 splx(s); 1440 callout_schedule(&sc->sc_tick, hz); 1441 } 1442 1443 static void 1444 txp_start(struct ifnet *ifp) 1445 { 1446 struct txp_softc *sc = ifp->if_softc; 1447 struct txp_tx_ring *r = &sc->sc_txhir; 1448 struct txp_tx_desc *txd; 1449 int txdidx; 1450 struct txp_frag_desc *fxd; 1451 struct mbuf *m, *mnew; 1452 struct txp_swdesc *sd; 1453 uint32_t prod, cnt, i; 1454 int error; 1455 1456 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1457 return; 1458 1459 prod = r->r_prod; 1460 cnt = r->r_cnt; 1461 1462 while (1) { 1463 if (cnt >= TX_ENTRIES - TXP_MAXTXSEGS - 4) { 1464 ifp->if_flags |= IFF_OACTIVE; 1465 break; 1466 } 1467 1468 IFQ_POLL(&ifp->if_snd, m); 1469 if (m == NULL) 1470 break; 1471 mnew = NULL; 1472 1473 sd = sc->sc_txd + prod; 1474 1475 /* 1476 * Load the DMA map. If this fails, the packet either 1477 * didn't fit in the alloted number of segments, or we 1478 * were short on resources. In this case, we'll copy 1479 * and try again. 1480 */ 1481 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1482 BUS_DMA_NOWAIT) != 0) { 1483 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1484 if (mnew == NULL) { 1485 printf("%s: unable to allocate Tx mbuf\n", 1486 device_xname(sc->sc_dev)); 1487 break; 1488 } 1489 MCLAIM(mnew, &sc->sc_arpcom.ec_tx_mowner); 1490 if (m->m_pkthdr.len > MHLEN) { 1491 MCLGET(mnew, M_DONTWAIT); 1492 if ((mnew->m_flags & M_EXT) == 0) { 1493 printf("%s: unable to allocate Tx " 1494 "cluster\n", 1495 device_xname(sc->sc_dev)); 1496 m_freem(mnew); 1497 break; 1498 } 1499 } 1500 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1501 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1502 error = bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, 1503 mnew, BUS_DMA_NOWAIT); 1504 if (error) { 1505 printf("%s: unable to load Tx buffer, " 1506 "error = %d\n", device_xname(sc->sc_dev), 1507 error); 1508 m_freem(mnew); 1509 break; 1510 } 1511 } 1512 1513 IFQ_DEQUEUE(&ifp->if_snd, m); 1514 if (mnew != NULL) { 1515 m_freem(m); 1516 m = mnew; 1517 } 1518 1519 /* 1520 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1521 */ 1522 1523 sd->sd_mbuf = m; 1524 1525 txd = r->r_desc + prod; 1526 txdidx = prod; 1527 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1528 txd->tx_numdesc = 0; 1529 txd->tx_addrlo = txp_txd_idx(sc, sd); 1530 txd->tx_addrhi = 0; 1531 txd->tx_totlen = m->m_pkthdr.len; 1532 txd->tx_pflags = 0; 1533 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1534 1535 if (++prod == TX_ENTRIES) 1536 prod = 0; 1537 cnt++; 1538 1539 if (vlan_has_tag(m)) 1540 txd->tx_pflags = TX_PFLAGS_VLAN | 1541 (htons(vlan_get_tag(m)) << TX_PFLAGS_VLANTAG_S); 1542 1543 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1544 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1545 #ifdef TRY_TX_TCP_CSUM 1546 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1547 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1548 #endif 1549 #ifdef TRY_TX_UDP_CSUM 1550 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1551 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1552 #endif 1553 1554 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1555 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1556 1557 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1558 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1559 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1560 FRAG_FLAGS_VALID; 1561 fxd->frag_rsvd1 = 0; 1562 fxd->frag_len = htole16(sd->sd_map->dm_segs[i].ds_len); 1563 fxd->frag_addrlo = 1564 htole32(BUS_ADDR_LO32(sd->sd_map->dm_segs[i].ds_addr)); 1565 fxd->frag_addrhi = 1566 htole32(BUS_ADDR_HI32(sd->sd_map->dm_segs[i].ds_addr)); 1567 fxd->frag_rsvd2 = 0; 1568 1569 bus_dmamap_sync(sc->sc_dmat, 1570 sc->sc_txhiring_dma.dma_map, 1571 prod * sizeof(struct txp_frag_desc), 1572 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1573 1574 if (++prod == TX_ENTRIES) { 1575 fxd = (struct txp_frag_desc *)r->r_desc; 1576 prod = 0; 1577 } else 1578 fxd++; 1579 cnt++; 1580 } 1581 1582 ifp->if_timer = 5; 1583 1584 bpf_mtap(ifp, m, BPF_D_OUT); 1585 1586 txd->tx_flags |= TX_FLAGS_VALID; 1587 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1588 txdidx * sizeof(struct txp_tx_desc), 1589 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1590 1591 #if 0 1592 { 1593 struct mbuf *mx; 1594 int i; 1595 1596 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1597 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1598 txd->tx_pflags); 1599 for (mx = m; mx != NULL; mx = mx->m_next) { 1600 for (i = 0; i < mx->m_len; i++) { 1601 printf(":%02x", 1602 (uint8_t)m->m_data[i]); 1603 } 1604 } 1605 printf("\n"); 1606 } 1607 #endif 1608 1609 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1610 } 1611 1612 r->r_prod = prod; 1613 r->r_cnt = cnt; 1614 } 1615 1616 /* 1617 * Handle simple commands sent to the typhoon 1618 */ 1619 static int 1620 txp_command(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1621 uint32_t in3, uint16_t *out1, uint32_t *out2, uint32_t *out3, int wait) 1622 { 1623 struct txp_rsp_desc *rsp = NULL; 1624 1625 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1626 return (-1); 1627 1628 if (!wait) 1629 return (0); 1630 1631 if (out1 != NULL) 1632 *out1 = le16toh(rsp->rsp_par1); 1633 if (out2 != NULL) 1634 *out2 = le32toh(rsp->rsp_par2); 1635 if (out3 != NULL) 1636 *out3 = le32toh(rsp->rsp_par3); 1637 free(rsp, M_DEVBUF); 1638 return (0); 1639 } 1640 1641 static int 1642 txp_command2(struct txp_softc *sc, uint16_t id, uint16_t in1, uint32_t in2, 1643 uint32_t in3, struct txp_ext_desc *in_extp, uint8_t in_extn, 1644 struct txp_rsp_desc **rspp, int wait) 1645 { 1646 struct txp_hostvar *hv = sc->sc_hostvar; 1647 struct txp_cmd_desc *cmd; 1648 struct txp_ext_desc *ext; 1649 uint32_t idx, i; 1650 uint16_t seq; 1651 1652 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1653 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1654 return (-1); 1655 } 1656 1657 idx = sc->sc_cmdring.lastwrite; 1658 cmd = (struct txp_cmd_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1659 memset(cmd, 0, sizeof(*cmd)); 1660 1661 cmd->cmd_numdesc = in_extn; 1662 seq = sc->sc_seq++; 1663 cmd->cmd_seq = htole16(seq); 1664 cmd->cmd_id = htole16(id); 1665 cmd->cmd_par1 = htole16(in1); 1666 cmd->cmd_par2 = htole32(in2); 1667 cmd->cmd_par3 = htole32(in3); 1668 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1669 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1670 1671 idx += sizeof(struct txp_cmd_desc); 1672 if (idx == sc->sc_cmdring.size) 1673 idx = 0; 1674 1675 for (i = 0; i < in_extn; i++) { 1676 ext = (struct txp_ext_desc *)(((uint8_t *)sc->sc_cmdring.base) + idx); 1677 memcpy(ext, in_extp, sizeof(struct txp_ext_desc)); 1678 in_extp++; 1679 idx += sizeof(struct txp_cmd_desc); 1680 if (idx == sc->sc_cmdring.size) 1681 idx = 0; 1682 } 1683 1684 sc->sc_cmdring.lastwrite = idx; 1685 1686 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1687 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1688 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1689 1690 if (!wait) 1691 return (0); 1692 1693 for (i = 0; i < 10000; i++) { 1694 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1695 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1696 idx = le32toh(hv->hv_resp_read_idx); 1697 if (idx != le32toh(hv->hv_resp_write_idx)) { 1698 *rspp = NULL; 1699 if (txp_response(sc, idx, id, seq, rspp)) 1700 return (-1); 1701 if (*rspp != NULL) 1702 break; 1703 } 1704 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1705 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1706 DELAY(50); 1707 } 1708 if (i == 1000 || (*rspp) == NULL) { 1709 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1710 return (-1); 1711 } 1712 1713 return (0); 1714 } 1715 1716 static int 1717 txp_response(struct txp_softc *sc, uint32_t ridx, uint16_t id, uint16_t seq, 1718 struct txp_rsp_desc **rspp) 1719 { 1720 struct txp_hostvar *hv = sc->sc_hostvar; 1721 struct txp_rsp_desc *rsp; 1722 1723 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1724 rsp = (struct txp_rsp_desc *)(((uint8_t *)sc->sc_rspring.base) + ridx); 1725 1726 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1727 *rspp = (struct txp_rsp_desc *)malloc( 1728 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1729 M_DEVBUF, M_NOWAIT); 1730 if ((*rspp) == NULL) 1731 return (-1); 1732 txp_rsp_fixup(sc, rsp, *rspp); 1733 return (0); 1734 } 1735 1736 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1737 printf("%s: response error: id 0x%x\n", 1738 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1739 txp_rsp_fixup(sc, rsp, NULL); 1740 ridx = le32toh(hv->hv_resp_read_idx); 1741 continue; 1742 } 1743 1744 switch (le16toh(rsp->rsp_id)) { 1745 case TXP_CMD_CYCLE_STATISTICS: 1746 case TXP_CMD_MEDIA_STATUS_READ: 1747 break; 1748 case TXP_CMD_HELLO_RESPONSE: 1749 printf("%s: hello\n", TXP_DEVNAME(sc)); 1750 break; 1751 default: 1752 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1753 le16toh(rsp->rsp_id)); 1754 } 1755 1756 txp_rsp_fixup(sc, rsp, NULL); 1757 ridx = le32toh(hv->hv_resp_read_idx); 1758 hv->hv_resp_read_idx = le32toh(ridx); 1759 } 1760 1761 return (0); 1762 } 1763 1764 static void 1765 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, 1766 struct txp_rsp_desc *dst) 1767 { 1768 struct txp_rsp_desc *src = rsp; 1769 struct txp_hostvar *hv = sc->sc_hostvar; 1770 uint32_t i, ridx; 1771 1772 ridx = le32toh(hv->hv_resp_read_idx); 1773 1774 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1775 if (dst != NULL) 1776 memcpy(dst++, src, sizeof(struct txp_rsp_desc)); 1777 ridx += sizeof(struct txp_rsp_desc); 1778 if (ridx == sc->sc_rspring.size) { 1779 src = sc->sc_rspring.base; 1780 ridx = 0; 1781 } else 1782 src++; 1783 sc->sc_rspring.lastwrite = ridx; 1784 hv->hv_resp_read_idx = htole32(ridx); 1785 } 1786 1787 hv->hv_resp_read_idx = htole32(ridx); 1788 } 1789 1790 static int 1791 txp_cmd_desc_numfree(struct txp_softc *sc) 1792 { 1793 struct txp_hostvar *hv = sc->sc_hostvar; 1794 struct txp_boot_record *br = sc->sc_boot; 1795 uint32_t widx, ridx, nfree; 1796 1797 widx = sc->sc_cmdring.lastwrite; 1798 ridx = le32toh(hv->hv_cmd_read_idx); 1799 1800 if (widx == ridx) { 1801 /* Ring is completely free */ 1802 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1803 } else { 1804 if (widx > ridx) 1805 nfree = le32toh(br->br_cmd_siz) - 1806 (widx - ridx + sizeof(struct txp_cmd_desc)); 1807 else 1808 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1809 } 1810 1811 return (nfree / sizeof(struct txp_cmd_desc)); 1812 } 1813 1814 static void 1815 txp_stop(struct txp_softc *sc) 1816 { 1817 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1818 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1819 1820 if (callout_pending(&sc->sc_tick)) 1821 callout_stop(&sc->sc_tick); 1822 } 1823 1824 static void 1825 txp_watchdog(struct ifnet *ifp) 1826 { 1827 } 1828 1829 static int 1830 txp_ifmedia_upd(struct ifnet *ifp) 1831 { 1832 struct txp_softc *sc = ifp->if_softc; 1833 struct ifmedia *ifm = &sc->sc_ifmedia; 1834 uint16_t new_xcvr; 1835 1836 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1837 return (EINVAL); 1838 1839 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1840 if ((ifm->ifm_media & IFM_FDX) != 0) 1841 new_xcvr = TXP_XCVR_10_FDX; 1842 else 1843 new_xcvr = TXP_XCVR_10_HDX; 1844 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1845 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1846 if ((ifm->ifm_media & IFM_FDX) != 0) 1847 new_xcvr = TXP_XCVR_100_FDX; 1848 else 1849 new_xcvr = TXP_XCVR_100_HDX; 1850 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1851 new_xcvr = TXP_XCVR_AUTO; 1852 } else 1853 return (EINVAL); 1854 1855 /* nothing to do */ 1856 if (sc->sc_xcvr == new_xcvr) 1857 return (0); 1858 1859 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1860 NULL, NULL, NULL, 0); 1861 sc->sc_xcvr = new_xcvr; 1862 1863 return (0); 1864 } 1865 1866 static void 1867 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1868 { 1869 struct txp_softc *sc = ifp->if_softc; 1870 struct ifmedia *ifm = &sc->sc_ifmedia; 1871 uint16_t bmsr, bmcr, anlpar; 1872 1873 ifmr->ifm_status = IFM_AVALID; 1874 ifmr->ifm_active = IFM_ETHER; 1875 1876 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1877 &bmsr, NULL, NULL, 1)) 1878 goto bail; 1879 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1880 &bmsr, NULL, NULL, 1)) 1881 goto bail; 1882 1883 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1884 &bmcr, NULL, NULL, 1)) 1885 goto bail; 1886 1887 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1888 &anlpar, NULL, NULL, 1)) 1889 goto bail; 1890 1891 if (bmsr & BMSR_LINK) 1892 ifmr->ifm_status |= IFM_ACTIVE; 1893 1894 if (bmcr & BMCR_ISO) { 1895 ifmr->ifm_active |= IFM_NONE; 1896 ifmr->ifm_status = 0; 1897 return; 1898 } 1899 1900 if (bmcr & BMCR_LOOP) 1901 ifmr->ifm_active |= IFM_LOOP; 1902 1903 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1904 if ((bmsr & BMSR_ACOMP) == 0) { 1905 ifmr->ifm_active |= IFM_NONE; 1906 return; 1907 } 1908 1909 if (anlpar & ANLPAR_TX_FD) 1910 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 1911 else if (anlpar & ANLPAR_T4) 1912 ifmr->ifm_active |= IFM_100_T4 | IFM_HDX; 1913 else if (anlpar & ANLPAR_TX) 1914 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 1915 else if (anlpar & ANLPAR_10_FD) 1916 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 1917 else if (anlpar & ANLPAR_10) 1918 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 1919 else 1920 ifmr->ifm_active |= IFM_NONE; 1921 } else 1922 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1923 return; 1924 1925 bail: 1926 ifmr->ifm_active |= IFM_NONE; 1927 ifmr->ifm_status &= ~IFM_AVALID; 1928 } 1929 1930 #if 0 /* XXX XXX XXX UNUSED */ 1931 static void 1932 txp_show_descriptor(void *d) 1933 { 1934 struct txp_cmd_desc *cmd = d; 1935 struct txp_rsp_desc *rsp = d; 1936 struct txp_tx_desc *txd = d; 1937 struct txp_frag_desc *frgd = d; 1938 1939 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1940 case CMD_FLAGS_TYPE_CMD: 1941 /* command descriptor */ 1942 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1943 "0x%x par3 0x%x]\n", 1944 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1945 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1946 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1947 break; 1948 case CMD_FLAGS_TYPE_RESP: 1949 /* response descriptor */ 1950 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 " 1951 "0x%x par3 0x%x]\n", 1952 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1953 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1954 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1955 break; 1956 case CMD_FLAGS_TYPE_DATA: 1957 /* data header (assuming tx for now) */ 1958 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x " 1959 "pflags 0x%x]", 1960 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1961 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1962 break; 1963 case CMD_FLAGS_TYPE_FRAG: 1964 /* fragment descriptor */ 1965 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x " 1966 "rsvd2 0x%x]", 1967 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1968 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1969 break; 1970 default: 1971 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 " 1972 "0x%x par2 0x%x par3 0x%x]\n", 1973 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1974 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1975 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1976 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1977 break; 1978 } 1979 } 1980 #endif 1981 1982 static void 1983 txp_set_filter(struct txp_softc *sc) 1984 { 1985 struct ethercom *ec = &sc->sc_arpcom; 1986 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1987 uint32_t crc, carry, hashbit, hash[2]; 1988 uint16_t filter; 1989 uint8_t octet; 1990 int i, j, mcnt = 0; 1991 struct ether_multi *enm; 1992 struct ether_multistep step; 1993 1994 if (ifp->if_flags & IFF_PROMISC) { 1995 filter = TXP_RXFILT_PROMISC; 1996 goto setit; 1997 } 1998 1999 again: 2000 filter = TXP_RXFILT_DIRECT; 2001 2002 if (ifp->if_flags & IFF_BROADCAST) 2003 filter |= TXP_RXFILT_BROADCAST; 2004 2005 if (ifp->if_flags & IFF_ALLMULTI) 2006 filter |= TXP_RXFILT_ALLMULTI; 2007 else { 2008 hash[0] = hash[1] = 0; 2009 2010 ETHER_LOCK(ec); 2011 ETHER_FIRST_MULTI(step, ec, enm); 2012 while (enm != NULL) { 2013 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 2014 ETHER_ADDR_LEN)) { 2015 /* 2016 * We must listen to a range of multicast 2017 * addresses. For now, just accept all 2018 * multicasts, rather than trying to set only 2019 * those filter bits needed to match the range. 2020 * (At this time, the only use of address 2021 * ranges is for IP multicast routing, for 2022 * which the range is big enough to require 2023 * all bits set.) 2024 */ 2025 ifp->if_flags |= IFF_ALLMULTI; 2026 ETHER_UNLOCK(ec); 2027 goto again; 2028 } 2029 2030 mcnt++; 2031 crc = 0xffffffff; 2032 2033 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2034 octet = enm->enm_addrlo[i]; 2035 for (j = 0; j < 8; j++) { 2036 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2037 (octet & 1); 2038 crc <<= 1; 2039 octet >>= 1; 2040 if (carry) 2041 crc = (crc ^ TXP_POLYNOMIAL) | 2042 carry; 2043 } 2044 } 2045 hashbit = (uint16_t)(crc & (64 - 1)); 2046 hash[hashbit / 32] |= (1 << hashbit % 32); 2047 ETHER_NEXT_MULTI(step, enm); 2048 } 2049 ETHER_UNLOCK(ec); 2050 2051 if (mcnt > 0) { 2052 filter |= TXP_RXFILT_HASHMULTI; 2053 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2054 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2055 } 2056 } 2057 2058 setit: 2059 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2060 NULL, NULL, NULL, 1); 2061 } 2062 2063 static void 2064 txp_capabilities(struct txp_softc *sc) 2065 { 2066 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2067 struct txp_rsp_desc *rsp = NULL; 2068 struct txp_ext_desc *ext; 2069 2070 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2071 goto out; 2072 2073 if (rsp->rsp_numdesc != 1) 2074 goto out; 2075 ext = (struct txp_ext_desc *)(rsp + 1); 2076 2077 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2078 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2079 2080 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2081 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2082 sc->sc_tx_capability |= OFFLOAD_VLAN; 2083 sc->sc_rx_capability |= OFFLOAD_VLAN; 2084 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2085 sc->sc_arpcom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 2086 } 2087 2088 #if 0 2089 /* not ready yet */ 2090 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2091 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2092 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2093 ifp->if_capabilities |= IFCAP_IPSEC; 2094 } 2095 #endif 2096 2097 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2098 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2099 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2100 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2101 } 2102 2103 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2104 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2105 #ifdef TRY_TX_TCP_CSUM 2106 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2107 ifp->if_capabilities |= 2108 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2109 #endif 2110 } 2111 2112 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2113 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2114 #ifdef TRY_TX_UDP_CSUM 2115 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2116 ifp->if_capabilities |= 2117 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2118 #endif 2119 } 2120 2121 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2122 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2123 goto out; 2124 2125 out: 2126 if (rsp != NULL) 2127 free(rsp, M_DEVBUF); 2128 } 2129
Indexes created Tue Sep 30 20:09:53 GMT 2025